mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-30 06:10:56 +00:00
wifi: ath11k: initialize hw_ops for IPQ5018
The ipq5018_ops is initialized for IPQ5018. This is different from other platforms. Tested-on: IPQ5018 hw1.0 AHB WLAN.HK.2.6.0.1-00861-QCAHKSWPL_SILICONZ-1 Signed-off-by: Sriram R <quic_srirrama@quicinc.com> Co-developed-by: Karthikeyan Kathirvel <quic_kathirve@quicinc.com> Signed-off-by: Karthikeyan Kathirvel <quic_kathirve@quicinc.com> Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com> Link: https://lore.kernel.org/r/20221122132152.17771-7-quic_kathirve@quicinc.com
This commit is contained in:
parent
711b80acbd
commit
ba60f2793d
3 changed files with 42 additions and 0 deletions
|
@ -635,6 +635,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
|
|||
},
|
||||
.internal_sleep_clock = false,
|
||||
.regs = &ipq5018_regs,
|
||||
.hw_ops = &ipq5018_ops,
|
||||
.host_ce_config = ath11k_host_ce_config_qcn9074,
|
||||
.ce_count = CE_CNT_5018,
|
||||
.target_ce_config = ath11k_target_ce_config_wlan_ipq5018,
|
||||
|
|
|
@ -1084,6 +1084,46 @@ const struct ath11k_hw_ops wcn6750_ops = {
|
|||
.get_ring_selector = ath11k_hw_wcn6750_get_tcl_ring_selector,
|
||||
};
|
||||
|
||||
/* IPQ5018 hw ops is similar to QCN9074 except for the dest ring remap */
|
||||
const struct ath11k_hw_ops ipq5018_ops = {
|
||||
.get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id,
|
||||
.wmi_init_config = ath11k_init_wmi_config_ipq8074,
|
||||
.mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074,
|
||||
.mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074,
|
||||
.tx_mesh_enable = ath11k_hw_qcn9074_tx_mesh_enable,
|
||||
.rx_desc_get_first_msdu = ath11k_hw_qcn9074_rx_desc_get_first_msdu,
|
||||
.rx_desc_get_last_msdu = ath11k_hw_qcn9074_rx_desc_get_last_msdu,
|
||||
.rx_desc_get_l3_pad_bytes = ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes,
|
||||
.rx_desc_get_hdr_status = ath11k_hw_qcn9074_rx_desc_get_hdr_status,
|
||||
.rx_desc_encrypt_valid = ath11k_hw_qcn9074_rx_desc_encrypt_valid,
|
||||
.rx_desc_get_encrypt_type = ath11k_hw_qcn9074_rx_desc_get_encrypt_type,
|
||||
.rx_desc_get_decap_type = ath11k_hw_qcn9074_rx_desc_get_decap_type,
|
||||
.rx_desc_get_mesh_ctl = ath11k_hw_qcn9074_rx_desc_get_mesh_ctl,
|
||||
.rx_desc_get_ldpc_support = ath11k_hw_qcn9074_rx_desc_get_ldpc_support,
|
||||
.rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld,
|
||||
.rx_desc_get_mpdu_fc_valid = ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid,
|
||||
.rx_desc_get_mpdu_start_seq_no = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no,
|
||||
.rx_desc_get_msdu_len = ath11k_hw_qcn9074_rx_desc_get_msdu_len,
|
||||
.rx_desc_get_msdu_sgi = ath11k_hw_qcn9074_rx_desc_get_msdu_sgi,
|
||||
.rx_desc_get_msdu_rate_mcs = ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs,
|
||||
.rx_desc_get_msdu_rx_bw = ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw,
|
||||
.rx_desc_get_msdu_freq = ath11k_hw_qcn9074_rx_desc_get_msdu_freq,
|
||||
.rx_desc_get_msdu_pkt_type = ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type,
|
||||
.rx_desc_get_msdu_nss = ath11k_hw_qcn9074_rx_desc_get_msdu_nss,
|
||||
.rx_desc_get_mpdu_tid = ath11k_hw_qcn9074_rx_desc_get_mpdu_tid,
|
||||
.rx_desc_get_mpdu_peer_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id,
|
||||
.rx_desc_copy_attn_end_tlv = ath11k_hw_qcn9074_rx_desc_copy_attn_end,
|
||||
.rx_desc_get_mpdu_start_tag = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag,
|
||||
.rx_desc_get_mpdu_ppdu_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id,
|
||||
.rx_desc_set_msdu_len = ath11k_hw_qcn9074_rx_desc_set_msdu_len,
|
||||
.rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention,
|
||||
.rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload,
|
||||
.mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid,
|
||||
.rx_desc_mac_addr2_valid = ath11k_hw_ipq9074_rx_desc_mac_addr2_valid,
|
||||
.rx_desc_mpdu_start_addr2 = ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2,
|
||||
|
||||
};
|
||||
|
||||
#define ATH11K_TX_RING_MASK_0 BIT(0)
|
||||
#define ATH11K_TX_RING_MASK_1 BIT(1)
|
||||
#define ATH11K_TX_RING_MASK_2 BIT(2)
|
||||
|
|
|
@ -275,6 +275,7 @@ extern const struct ath11k_hw_ops qca6390_ops;
|
|||
extern const struct ath11k_hw_ops qcn9074_ops;
|
||||
extern const struct ath11k_hw_ops wcn6855_ops;
|
||||
extern const struct ath11k_hw_ops wcn6750_ops;
|
||||
extern const struct ath11k_hw_ops ipq5018_ops;
|
||||
|
||||
extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074;
|
||||
extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390;
|
||||
|
|
Loading…
Reference in a new issue