arm64: dts: qcom: sm8450: Add qup nodes for qup2
qup2 has 7 SEs, so add the SEs (i2c and spi) along with pinconf for these SEs Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220414101630.1189052-6-vkoul@kernel.org
This commit is contained in:
Vinod Koul
Bjorn Andersson
parent
1a380216fd
commit
ba640cd313
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@ -744,6 +744,299 @@
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status = "disabled";
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};
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qupv3_id_2: geniqup@8c0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0x0 0x008c0000 0x0 0x2000>;
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clock-names = "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
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iommus = <&apps_smmu 0x483 0x0>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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status = "disabled";
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i2c15: i2c@880000 {
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compatible = "qcom,geni-i2c";
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reg = <0x0 0x00880000 0x0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c15_data_clk>;
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interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
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<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
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<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
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<&gpi_dma2 1 0 QCOM_GPI_I2C>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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spi15: spi@880000 {
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compatible = "qcom,geni-spi";
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reg = <0x0 0x00880000 0x0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
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interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
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spi-max-frequency = <50000000>;
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interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
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<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
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interconnect-names = "qup-core", "qup-config";
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dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
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<&gpi_dma2 1 0 QCOM_GPI_SPI>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c16: i2c@884000 {
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compatible = "qcom,geni-i2c";
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reg = <0x0 0x00884000 0x0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c16_data_clk>;
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interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
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<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
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<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
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<&gpi_dma2 1 1 QCOM_GPI_I2C>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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spi16: spi@884000 {
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compatible = "qcom,geni-spi";
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reg = <0x0 0x00884000 0x0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
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interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
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spi-max-frequency = <50000000>;
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interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
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<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
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interconnect-names = "qup-core", "qup-config";
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dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
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<&gpi_dma2 1 1 QCOM_GPI_SPI>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c17: i2c@888000 {
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compatible = "qcom,geni-i2c";
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reg = <0x0 0x00888000 0x0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c17_data_clk>;
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interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
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<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
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<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
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<&gpi_dma2 1 2 QCOM_GPI_I2C>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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spi17: spi@888000 {
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compatible = "qcom,geni-spi";
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reg = <0x0 0x00888000 0x0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
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interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
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spi-max-frequency = <50000000>;
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interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
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<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
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interconnect-names = "qup-core", "qup-config";
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dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
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<&gpi_dma2 1 2 QCOM_GPI_SPI>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c18: i2c@88c000 {
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compatible = "qcom,geni-i2c";
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reg = <0x0 0x0088c000 0x0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c18_data_clk>;
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interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
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<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
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<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
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<&gpi_dma2 1 3 QCOM_GPI_I2C>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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spi18: spi@88c000 {
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compatible = "qcom,geni-spi";
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reg = <0 0x0088c000 0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
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interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
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spi-max-frequency = <50000000>;
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interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
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<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
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interconnect-names = "qup-core", "qup-config";
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dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
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<&gpi_dma2 1 3 QCOM_GPI_I2C>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c19: i2c@890000 {
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compatible = "qcom,geni-i2c";
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reg = <0x0 0x00890000 0x0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c19_data_clk>;
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interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
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<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
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<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
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<&gpi_dma2 1 4 QCOM_GPI_I2C>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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spi19: spi@890000 {
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compatible = "qcom,geni-spi";
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reg = <0 0x00890000 0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
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interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
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spi-max-frequency = <50000000>;
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interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
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<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
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interconnect-names = "qup-core", "qup-config";
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dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
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<&gpi_dma2 1 4 QCOM_GPI_I2C>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c20: i2c@894000 {
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compatible = "qcom,geni-i2c";
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reg = <0x0 0x00894000 0x0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c20_data_clk>;
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interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
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<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
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<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
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<&gpi_dma2 1 5 QCOM_GPI_I2C>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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spi20: spi@894000 {
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compatible = "qcom,geni-spi";
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reg = <0 0x00894000 0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
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interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
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spi-max-frequency = <50000000>;
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interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
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<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
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interconnect-names = "qup-core", "qup-config";
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dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
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<&gpi_dma2 1 5 QCOM_GPI_SPI>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c21: i2c@898000 {
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compatible = "qcom,geni-i2c";
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reg = <0x0 0x00898000 0x0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c21_data_clk>;
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interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
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<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
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<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
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<&gpi_dma2 1 6 QCOM_GPI_I2C>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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spi21: spi@898000 {
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compatible = "qcom,geni-spi";
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reg = <0 0x00898000 0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
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interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
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spi-max-frequency = <50000000>;
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interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
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<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
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interconnect-names = "qup-core", "qup-config";
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dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
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<&gpi_dma2 1 6 QCOM_GPI_SPI>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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gpi_dma0: dma-controller@900000 {
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compatible = "qcom,sm8450-gpi-dma";
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#dma-cells = <3>;
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@ -2174,6 +2467,41 @@
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bias-pull-up;
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};
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qup_i2c15_data_clk: qup-i2c15-data-clk {
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pins = "gpio56", "gpio57";
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function = "qup15";
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};
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qup_i2c16_data_clk: qup-i2c16-data-clk {
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pins = "gpio60", "gpio61";
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function = "qup16";
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};
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qup_i2c17_data_clk: qup-i2c17-data-clk {
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pins = "gpio64", "gpio65";
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function = "qup17";
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};
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qup_i2c18_data_clk: qup-i2c18-data-clk {
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pins = "gpio68", "gpio69";
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function = "qup18";
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};
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qup_i2c19_data_clk: qup-i2c19-data-clk {
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pins = "gpio72", "gpio73";
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function = "qup19";
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};
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qup_i2c20_data_clk: qup-i2c20-data-clk {
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pins = "gpio76", "gpio77";
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function = "qup20";
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};
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qup_i2c21_data_clk: qup-i2c21-data-clk {
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pins = "gpio80", "gpio81";
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function = "qup21";
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};
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qup_spi0_cs: qup-spi0-cs {
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pins = "gpio3";
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function = "qup0";
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@ -2326,6 +2654,74 @@
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function = "qup15";
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};
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qup_spi16_cs: qup-spi16-cs {
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pins = "gpio63";
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function = "qup16";
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};
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qup_spi16_data_clk: qup-spi16-data-clk {
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pins = "gpio60", "gpio61", "gpio62";
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function = "qup16";
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};
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qup_spi17_cs: qup-spi17-cs {
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pins = "gpio67";
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function = "qup17";
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};
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||||
|
||||
qup_spi17_data_clk: qup-spi17-data-clk {
|
||||
pins = "gpio64", "gpio65", "gpio66";
|
||||
function = "qup17";
|
||||
};
|
||||
|
||||
qup_spi18_cs: qup-spi18-cs {
|
||||
pins = "gpio71";
|
||||
function = "qup18";
|
||||
drive-strength = <6>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
qup_spi18_data_clk: qup-spi18-data-clk {
|
||||
pins = "gpio68", "gpio69", "gpio70";
|
||||
function = "qup18";
|
||||
drive-strength = <6>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
qup_spi19_cs: qup-spi19-cs {
|
||||
pins = "gpio75";
|
||||
function = "qup19";
|
||||
drive-strength = <6>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
qup_spi19_data_clk: qup-spi19-data-clk {
|
||||
pins = "gpio72", "gpio73", "gpio74";
|
||||
function = "qup19";
|
||||
drive-strength = <6>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
qup_spi20_cs: qup-spi20-cs {
|
||||
pins = "gpio79";
|
||||
function = "qup20";
|
||||
};
|
||||
|
||||
qup_spi20_data_clk: qup-spi20-data-clk {
|
||||
pins = "gpio76", "gpio77", "gpio78";
|
||||
function = "qup20";
|
||||
};
|
||||
|
||||
qup_spi21_cs: qup-spi21-cs {
|
||||
pins = "gpio83";
|
||||
function = "qup21";
|
||||
};
|
||||
|
||||
qup_spi21_data_clk: qup-spi21-data-clk {
|
||||
pins = "gpio80", "gpio81", "gpio82";
|
||||
function = "qup21";
|
||||
};
|
||||
|
||||
qup_uart7_rx: qup-uart7-rx {
|
||||
pins = "gpio26";
|
||||
function = "qup7";
|
||||
|
|
|
|||
Loading…
Reference in New Issue