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sata_mv: cosmetic renames
Add _OFS suffix to more of the register offset names, for consistency with the rest of the driver. Also tag the defines for LTMODE and PHY_MODE4 to note that read-after-write is necessary when updating those regs. No code changes here. [NOTE: this commit is undone a few commits later] Signed-off-by: Mark Lord <mlord@pobox.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
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parent
2009177329
commit
ba68460b8e
1 changed files with 18 additions and 17 deletions
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@ -272,17 +272,17 @@ enum {
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SATA_FIS_IRQ_CAUSE_OFS = 0x364,
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SATA_FIS_IRQ_AN = (1 << 9), /* async notification */
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LTMODE_OFS = 0x30c,
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LTMODE_OFS = 0x30c, /* requires read-after-write */
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LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
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PHY_MODE3 = 0x310,
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PHY_MODE4 = 0x314,
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PHY_MODE2_OFS = 0x330,
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PHY_MODE3_OFS = 0x310,
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PHY_MODE4_OFS = 0x314, /* requires read-after-write */
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PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */
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PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */
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PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */
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PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */
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PHY_MODE2 = 0x330,
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SATA_IFCTL_OFS = 0x344,
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SATA_TESTCTL_OFS = 0x348,
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SATA_IFSTAT_OFS = 0x34c,
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@ -3168,7 +3168,7 @@ static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
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}
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port_mmio = mv_port_base(mmio, idx);
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tmp = readl(port_mmio + PHY_MODE2);
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tmp = readl(port_mmio + PHY_MODE2_OFS);
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hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
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hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
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@ -3192,25 +3192,25 @@ static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
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u32 m2, m3;
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if (fix_phy_mode2) {
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m2 = readl(port_mmio + PHY_MODE2);
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m2 = readl(port_mmio + PHY_MODE2_OFS);
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m2 &= ~(1 << 16);
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m2 |= (1 << 31);
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writel(m2, port_mmio + PHY_MODE2);
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writel(m2, port_mmio + PHY_MODE2_OFS);
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udelay(200);
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m2 = readl(port_mmio + PHY_MODE2);
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m2 = readl(port_mmio + PHY_MODE2_OFS);
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m2 &= ~((1 << 16) | (1 << 31));
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writel(m2, port_mmio + PHY_MODE2);
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writel(m2, port_mmio + PHY_MODE2_OFS);
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udelay(200);
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}
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/*
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* Gen-II/IIe PHY_MODE3 errata RM#2:
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* Gen-II/IIe PHY_MODE3_OFS errata RM#2:
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* Achieves better receiver noise performance than the h/w default:
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*/
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m3 = readl(port_mmio + PHY_MODE3);
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m3 = readl(port_mmio + PHY_MODE3_OFS);
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m3 = (m3 & 0x1f) | (0x5555601 << 5);
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/* Guideline 88F5182 (GL# SATA-S11) */
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@ -3218,7 +3218,7 @@ static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
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m3 &= ~0x1c;
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if (fix_phy_mode4) {
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u32 m4 = readl(port_mmio + PHY_MODE4);
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u32 m4 = readl(port_mmio + PHY_MODE4_OFS);
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/*
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* Enforce reserved-bit restrictions on GenIIe devices only.
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* For earlier chipsets, force only the internal config field
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@ -3228,17 +3228,18 @@ static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
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m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES;
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else
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m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE;
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writel(m4, port_mmio + PHY_MODE4);
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writel(m4, port_mmio + PHY_MODE4_OFS);
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}
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/*
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* Workaround for 60x1-B2 errata SATA#13:
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* Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
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* so we must always rewrite PHY_MODE3 after PHY_MODE4.
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* Or ensure we use writelfl() when writing PHY_MODE4.
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*/
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writel(m3, port_mmio + PHY_MODE3);
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writel(m3, port_mmio + PHY_MODE3_OFS);
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/* Revert values of pre-emphasis and signal amps to the saved ones */
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m2 = readl(port_mmio + PHY_MODE2);
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m2 = readl(port_mmio + PHY_MODE2_OFS);
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m2 &= ~MV_M2_PREAMP_MASK;
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m2 |= hpriv->signal[port].amps;
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@ -3251,7 +3252,7 @@ static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
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m2 |= 0x0000900F;
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}
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writel(m2, port_mmio + PHY_MODE2);
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writel(m2, port_mmio + PHY_MODE2_OFS);
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}
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/* TODO: use the generic LED interface to configure the SATA Presence */
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@ -3269,7 +3270,7 @@ static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
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u32 tmp;
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port_mmio = mv_port_base(mmio, idx);
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tmp = readl(port_mmio + PHY_MODE2);
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tmp = readl(port_mmio + PHY_MODE2_OFS);
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hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
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hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
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