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platform/x86: mlx-platform: Use defines for bus assignment

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Add defines for the bus IDs, used for hotplug device topology to improve
code readability. Defines added for FAN and power units.

Signed-off-by: Vadim Pasternak <vadimp@mellanox.com>
Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
This commit is contained in:
Vadim Pasternak 2018-02-02 08:45:45 +00:00 committed by Darren Hart (VMware)
parent b81e830c9a
commit ba814fdd0e
1 changed files with 15 additions and 8 deletions
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23
drivers/platform/x86/mlx-platform.c
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@ -89,6 +89,13 @@
/* Number of LPC attached MUX platform devices */ /* Number of LPC attached MUX platform devices */
#define MLXPLAT_CPLD_LPC_MUX_DEVS 2 #define MLXPLAT_CPLD_LPC_MUX_DEVS 2
/* Hotplug devices adapter numbers */
#define MLXPLAT_CPLD_PSU_DEFAULT_NR 10
#define MLXPLAT_CPLD_FAN1_DEFAULT_NR 11
#define MLXPLAT_CPLD_FAN2_DEFAULT_NR 12
#define MLXPLAT_CPLD_FAN3_DEFAULT_NR 13
#define MLXPLAT_CPLD_FAN4_DEFAULT_NR 14
/* mlxplat_priv - platform private data /* mlxplat_priv - platform private data
* @pdev_i2c - i2c controller platform device * @pdev_i2c - i2c controller platform device
* @pdev_mux - array of mux platform devices * @pdev_mux - array of mux platform devices
@ -190,14 +197,14 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_psu_items_data[] = {
.reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
.mask = BIT(0), .mask = BIT(0),
.hpdev.brdinfo = &mlxplat_mlxcpld_psu[0], .hpdev.brdinfo = &mlxplat_mlxcpld_psu[0],
.hpdev.nr = 10, .hpdev.nr = MLXPLAT_CPLD_PSU_DEFAULT_NR,
}, },
{ {
.label = "psu2", .label = "psu2",
.reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
.mask = BIT(1), .mask = BIT(1),
.hpdev.brdinfo = &mlxplat_mlxcpld_psu[1], .hpdev.brdinfo = &mlxplat_mlxcpld_psu[1],
.hpdev.nr = 10, .hpdev.nr = MLXPLAT_CPLD_PSU_DEFAULT_NR,
}, },
}; };
@ -207,14 +214,14 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_items_data[] = {
.reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
.mask = BIT(0), .mask = BIT(0),
.hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0],
.hpdev.nr = 10, .hpdev.nr = MLXPLAT_CPLD_PSU_DEFAULT_NR,
}, },
{ {
.label = "pwr2", .label = "pwr2",
.reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
.mask = BIT(1), .mask = BIT(1),
.hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1],
.hpdev.nr = 10, .hpdev.nr = MLXPLAT_CPLD_PSU_DEFAULT_NR,
}, },
}; };
@ -224,28 +231,28 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_items_data[] = {
.reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
.mask = BIT(0), .mask = BIT(0),
.hpdev.brdinfo = &mlxplat_mlxcpld_fan[0], .hpdev.brdinfo = &mlxplat_mlxcpld_fan[0],
.hpdev.nr = 11, .hpdev.nr = MLXPLAT_CPLD_FAN1_DEFAULT_NR,
}, },
{ {
.label = "fan2", .label = "fan2",
.reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
.mask = BIT(1), .mask = BIT(1),
.hpdev.brdinfo = &mlxplat_mlxcpld_fan[1], .hpdev.brdinfo = &mlxplat_mlxcpld_fan[1],
.hpdev.nr = 12, .hpdev.nr = MLXPLAT_CPLD_FAN2_DEFAULT_NR,
}, },
{ {
.label = "fan3", .label = "fan3",
.reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
.mask = BIT(2), .mask = BIT(2),
.hpdev.brdinfo = &mlxplat_mlxcpld_fan[2], .hpdev.brdinfo = &mlxplat_mlxcpld_fan[2],
.hpdev.nr = 13, .hpdev.nr = MLXPLAT_CPLD_FAN3_DEFAULT_NR,
}, },
{ {
.label = "fan4", .label = "fan4",
.reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
.mask = BIT(3), .mask = BIT(3),
.hpdev.brdinfo = &mlxplat_mlxcpld_fan[3], .hpdev.brdinfo = &mlxplat_mlxcpld_fan[3],
.hpdev.nr = 14, .hpdev.nr = MLXPLAT_CPLD_FAN4_DEFAULT_NR,
}, },
}; };