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drm/gma500: Deprecate pci_get_bus_and_slot()
pci_get_bus_and_slot() is restrictive such that it assumes domain=0 as where a PCI device is present. This restricts the device drivers to be reused for other domain numbers. Getting ready to remove pci_get_bus_and_slot() function in favor of pci_get_domain_bus_and_slot(). Add domain parameter to CDV_MSG_READ32, CDV_MSG_WRITE32, MRST_MSG_READ32, MRST_MSG_WRITE32, MDFLD_MSG_READ32, MDFLD_MSG_WRITE32. Extract pci_dev from struct drm_device and use pdev to find the domain number while calling pci_get_domain_bus_and_slot(). Signed-off-by: Sinan Kaya <okaya@codeaurora.org> Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
This commit is contained in:
parent
cb5264be3c
commit
ba99d83488
5 changed files with 39 additions and 21 deletions
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@ -185,21 +185,22 @@ static int cdv_backlight_init(struct drm_device *dev)
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* for this and the MID devices.
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*/
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static inline u32 CDV_MSG_READ32(uint port, uint offset)
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static inline u32 CDV_MSG_READ32(int domain, uint port, uint offset)
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{
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int mcr = (0x10<<24) | (port << 16) | (offset << 8);
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uint32_t ret_val = 0;
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struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
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struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
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pci_write_config_dword(pci_root, 0xD0, mcr);
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pci_read_config_dword(pci_root, 0xD4, &ret_val);
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pci_dev_put(pci_root);
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return ret_val;
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}
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static inline void CDV_MSG_WRITE32(uint port, uint offset, u32 value)
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static inline void CDV_MSG_WRITE32(int domain, uint port, uint offset,
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u32 value)
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{
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int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
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struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
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struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
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pci_write_config_dword(pci_root, 0xD4, value);
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pci_write_config_dword(pci_root, 0xD0, mcr);
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pci_dev_put(pci_root);
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@ -216,11 +217,12 @@ static void cdv_init_pm(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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u32 pwr_cnt;
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int domain = pci_domain_nr(dev->pdev->bus);
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int i;
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dev_priv->apm_base = CDV_MSG_READ32(PSB_PUNIT_PORT,
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dev_priv->apm_base = CDV_MSG_READ32(domain, PSB_PUNIT_PORT,
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PSB_APMBA) & 0xFFFF;
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dev_priv->ospm_base = CDV_MSG_READ32(PSB_PUNIT_PORT,
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dev_priv->ospm_base = CDV_MSG_READ32(domain, PSB_PUNIT_PORT,
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PSB_OSPMBA) & 0xFFFF;
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/* Power status */
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@ -251,7 +253,7 @@ static void cdv_errata(struct drm_device *dev)
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* Bonus Launch to work around the issue, by degrading
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* performance.
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*/
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CDV_MSG_WRITE32(3, 0x30, 0x08027108);
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CDV_MSG_WRITE32(pci_domain_nr(dev->pdev->bus), 3, 0x30, 0x08027108);
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}
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/**
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@ -19,7 +19,9 @@
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void gma_get_core_freq(struct drm_device *dev)
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{
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uint32_t clock;
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struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
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struct pci_dev *pci_root =
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pci_get_domain_bus_and_slot(pci_domain_nr(dev->pdev->bus),
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0, 0);
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struct drm_psb_private *dev_priv = dev->dev_private;
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/*pci_write_config_dword(pci_root, 0xD4, 0x00C32004);*/
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@ -32,7 +32,9 @@
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static void mid_get_fuse_settings(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
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struct pci_dev *pci_root =
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pci_get_domain_bus_and_slot(pci_domain_nr(dev->pdev->bus),
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0, 0);
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uint32_t fuse_value = 0;
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uint32_t fuse_value_tmp = 0;
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@ -104,7 +106,9 @@ static void mid_get_fuse_settings(struct drm_device *dev)
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static void mid_get_pci_revID(struct drm_psb_private *dev_priv)
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{
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uint32_t platform_rev_id = 0;
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struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
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int domain = pci_domain_nr(dev_priv->dev->pdev->bus);
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struct pci_dev *pci_gfx_root =
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pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(2, 0));
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if (pci_gfx_root == NULL) {
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WARN_ON(1);
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@ -281,7 +285,9 @@ static void mid_get_vbt_data(struct drm_psb_private *dev_priv)
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u32 addr;
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u8 __iomem *vbt_virtual;
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struct mid_vbt_header vbt_header;
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struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
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struct pci_dev *pci_gfx_root =
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pci_get_domain_bus_and_slot(pci_domain_nr(dev->pdev->bus),
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0, PCI_DEVFN(2, 0));
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int ret = -1;
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/* Get the address of the platform config vbt */
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@ -261,7 +261,11 @@ static int psb_driver_load(struct drm_device *dev, unsigned long flags)
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goto out_err;
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if (IS_MRST(dev)) {
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dev_priv->aux_pdev = pci_get_bus_and_slot(0, PCI_DEVFN(3, 0));
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int domain = pci_domain_nr(dev->pdev->bus);
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dev_priv->aux_pdev =
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pci_get_domain_bus_and_slot(domain, 0,
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PCI_DEVFN(3, 0));
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if (dev_priv->aux_pdev) {
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resource_start = pci_resource_start(dev_priv->aux_pdev,
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@ -281,7 +285,9 @@ static int psb_driver_load(struct drm_device *dev, unsigned long flags)
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}
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dev_priv->gmbus_reg = dev_priv->aux_reg;
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dev_priv->lpc_pdev = pci_get_bus_and_slot(0, PCI_DEVFN(31, 0));
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dev_priv->lpc_pdev =
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pci_get_domain_bus_and_slot(domain, 0,
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PCI_DEVFN(31, 0));
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if (dev_priv->lpc_pdev) {
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pci_read_config_word(dev_priv->lpc_pdev, PSB_LPC_GBA,
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&dev_priv->lpc_gpio_base);
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@ -781,38 +781,40 @@ extern const struct psb_ops cdv_chip_ops;
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extern int drm_idle_check_interval;
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/* Utilities */
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static inline u32 MRST_MSG_READ32(uint port, uint offset)
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static inline u32 MRST_MSG_READ32(int domain, uint port, uint offset)
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{
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int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
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uint32_t ret_val = 0;
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struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
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struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
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pci_write_config_dword(pci_root, 0xD0, mcr);
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pci_read_config_dword(pci_root, 0xD4, &ret_val);
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pci_dev_put(pci_root);
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return ret_val;
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}
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static inline void MRST_MSG_WRITE32(uint port, uint offset, u32 value)
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static inline void MRST_MSG_WRITE32(int domain, uint port, uint offset,
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u32 value)
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{
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int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
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struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
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struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
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pci_write_config_dword(pci_root, 0xD4, value);
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pci_write_config_dword(pci_root, 0xD0, mcr);
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pci_dev_put(pci_root);
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}
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static inline u32 MDFLD_MSG_READ32(uint port, uint offset)
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static inline u32 MDFLD_MSG_READ32(int domain, uint port, uint offset)
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{
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int mcr = (0x10<<24) | (port << 16) | (offset << 8);
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uint32_t ret_val = 0;
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struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
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struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
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pci_write_config_dword(pci_root, 0xD0, mcr);
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pci_read_config_dword(pci_root, 0xD4, &ret_val);
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pci_dev_put(pci_root);
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return ret_val;
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}
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static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value)
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static inline void MDFLD_MSG_WRITE32(int domain, uint port, uint offset,
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u32 value)
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{
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int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
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struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
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struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
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pci_write_config_dword(pci_root, 0xD4, value);
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pci_write_config_dword(pci_root, 0xD0, mcr);
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pci_dev_put(pci_root);
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