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xtensa: fix xtensa_wsr always writing 0
commita3d0245c58
upstream. The commitcad6fade6e
("xtensa: clean up WSR*/RSR*/get_sr/set_sr") replaced 'WSR' macro in the function xtensa_wsr with 'xtensa_set_sr', but variable 'v' in the xtensa_set_sr body shadowed the argument 'v' passed to it, resulting in wrong value written to debug registers. Fix that by removing intermediate variable from the xtensa_set_sr macro body. Cc: stable@vger.kernel.org Fixes:cad6fade6e
("xtensa: clean up WSR*/RSR*/get_sr/set_sr") Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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1 changed files with 2 additions and 2 deletions
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@ -246,8 +246,8 @@ extern unsigned long __get_wchan(struct task_struct *p);
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#define xtensa_set_sr(x, sr) \
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({ \
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unsigned int v = (unsigned int)(x); \
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__asm__ __volatile__ ("wsr %0, "__stringify(sr) :: "a"(v)); \
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__asm__ __volatile__ ("wsr %0, "__stringify(sr) :: \
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"a"((unsigned int)(x))); \
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})
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#define xtensa_get_sr(sr) \
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