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powerpc/32s: Introduce _PAGE_READ and remove _PAGE_USER
On 603 MMU, TLB missed are handled by SW and there are separated DTLB and ITLB. It is therefore possible to implement execute-only protection by not loading DTLB when read access is not permitted. To do that, _PAGE_READ flag is needed but there is no bit available for it in PTE. On the other hand the only real use of _PAGE_USER is to implement PAGE_NONE by clearing _PAGE_USER. As _PAGE_NONE can also be implemented by clearing _PAGE_READ, remove _PAGE_USER and add _PAGE_READ. Then use the virtual address to know whether user rights or kernel rights are to be used. With that change, 603 MMU now honors execute-only protection. For hash (604) MMU it is more tricky because hash table is common to load/store and execute. Nevertheless it is still possible to check whether _PAGE_READ is set before loading hash table for a load/store access. At least it can't be read unless it is executed first. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/b7702dd5a041ec59055ed2880f4952e94c087a2e.1695659959.git.christophe.leroy@csgroup.eu
This commit is contained in:
Christophe Leroy
Michael Ellerman
parent
46ebef51fd
commit
bac4cffc7c
3 changed files with 60 additions and 71 deletions
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@ -20,7 +20,7 @@
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#define _PAGE_PRESENT 0x001 /* software: pte contains a translation */
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#define _PAGE_HASHPTE 0x002 /* hash_page has made an HPTE for this pte */
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#define _PAGE_USER 0x004 /* usermode access allowed */
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#define _PAGE_READ 0x004 /* software: read access allowed */
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#define _PAGE_GUARDED 0x008 /* G: prohibit speculative access */
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#define _PAGE_COHERENT 0x010 /* M: enforce memory coherence (SMP systems) */
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#define _PAGE_NO_CACHE 0x020 /* I: cache inhibit */
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@ -28,11 +28,9 @@
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#define _PAGE_DIRTY 0x080 /* C: page changed */
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#define _PAGE_ACCESSED 0x100 /* R: page referenced */
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#define _PAGE_EXEC 0x200 /* software: exec allowed */
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#define _PAGE_RW 0x400 /* software: user write access allowed */
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#define _PAGE_WRITE 0x400 /* software: user write access allowed */
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#define _PAGE_SPECIAL 0x800 /* software: Special page */
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#define _PAGE_WRITE _PAGE_RW
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#ifdef CONFIG_PTE_64BIT
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/* We never clear the high word of the pte */
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#define _PTE_NONE_MASK (0xffffffff00000000ULL | _PAGE_HASHPTE)
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@ -44,26 +42,13 @@
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#define _PMD_PRESENT_MASK (PAGE_MASK)
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#define _PMD_BAD (~PAGE_MASK)
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/* We borrow the _PAGE_USER bit to store the exclusive marker in swap PTEs. */
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#define _PAGE_SWP_EXCLUSIVE _PAGE_USER
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/* We borrow the _PAGE_READ bit to store the exclusive marker in swap PTEs. */
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#define _PAGE_SWP_EXCLUSIVE _PAGE_READ
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/* And here we include common definitions */
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#define _PAGE_KERNEL_RO 0
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#define _PAGE_KERNEL_ROX (_PAGE_EXEC)
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#define _PAGE_KERNEL_RW (_PAGE_DIRTY | _PAGE_RW)
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#define _PAGE_KERNEL_RWX (_PAGE_DIRTY | _PAGE_RW | _PAGE_EXEC)
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#define _PAGE_HPTEFLAGS _PAGE_HASHPTE
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#ifndef __ASSEMBLY__
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static inline bool pte_user(pte_t pte)
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{
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return pte_val(pte) & _PAGE_USER;
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}
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#endif /* __ASSEMBLY__ */
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/*
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* Location of the PFN in the PTE. Most 32-bit platforms use the same
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* as _PAGE_SHIFT here (ie, naturally aligned).
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@ -99,20 +84,7 @@ static inline bool pte_user(pte_t pte)
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#define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED)
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#define _PAGE_BASE (_PAGE_BASE_NC | _PAGE_COHERENT)
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/*
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* Permission masks used to generate the __P and __S table.
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*
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* Note:__pgprot is defined in arch/powerpc/include/asm/page.h
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*
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* Write permissions imply read permissions for now.
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*/
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#define PAGE_NONE __pgprot(_PAGE_BASE)
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#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
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#define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
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#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER)
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#define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
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#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER)
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#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
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#include <asm/pgtable-masks.h>
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/* Permission masks used for kernel mappings */
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#define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW)
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@ -408,12 +380,16 @@ static inline pte_t pte_swp_clear_exclusive(pte_t pte)
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}
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/* Generic accessors to PTE bits */
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static inline bool pte_read(pte_t pte)
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{
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return !!(pte_val(pte) & _PAGE_READ);
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}
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static inline bool pte_write(pte_t pte)
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{
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return !!(pte_val(pte) & _PAGE_WRITE);
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}
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static inline int pte_read(pte_t pte) { return 1; }
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static inline int pte_dirty(pte_t pte) { return !!(pte_val(pte) & _PAGE_DIRTY); }
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static inline int pte_young(pte_t pte) { return !!(pte_val(pte) & _PAGE_ACCESSED); }
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static inline int pte_special(pte_t pte) { return !!(pte_val(pte) & _PAGE_SPECIAL); }
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@ -448,10 +424,10 @@ static inline bool pte_ci(pte_t pte)
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static inline bool pte_access_permitted(pte_t pte, bool write)
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{
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/*
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* A read-only access is controlled by _PAGE_USER bit.
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* A read-only access is controlled by _PAGE_READ bit.
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* We have _PAGE_READ set for WRITE and EXECUTE
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*/
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if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte))
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if (!pte_present(pte) || !pte_read(pte))
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return false;
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if (write && !pte_write(pte))
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@ -412,10 +412,10 @@ END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
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. = INTERRUPT_INST_TLB_MISS_603
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InstructionTLBMiss:
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/*
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* r0: scratch
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* r0: userspace flag (later scratch)
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* r1: linux style pte ( later becomes ppc hardware pte )
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* r2: ptr to linux-style pte
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* r3: scratch
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* r3: fault address
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*/
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/* Get PTE (linux-style) and check access */
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mfspr r3,SPRN_IMISS
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@ -424,12 +424,13 @@ InstructionTLBMiss:
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cmplw 0,r1,r3
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#endif
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mfspr r2, SPRN_SDR1
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li r1,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC | _PAGE_USER
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li r1,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
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rlwinm r2, r2, 28, 0xfffff000
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#ifdef CONFIG_MODULES
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li r0, 3
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bgt- 112f
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lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
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li r1,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
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li r0, 0
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addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
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#endif
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112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
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@ -437,13 +438,15 @@ InstructionTLBMiss:
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rlwinm. r2,r2,0,0,19 /* extract address of pte page */
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beq- InstructionAddressInvalid /* return if no mapping */
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rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
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lwz r0,0(r2) /* get linux-style pte */
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andc. r1,r1,r0 /* check access & ~permission */
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lwz r2,0(r2) /* get linux-style pte */
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andc. r1,r1,r2 /* check access & ~permission */
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bne- InstructionAddressInvalid /* return if access not permitted */
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/* Convert linux-style PTE to low word of PPC-style PTE */
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rlwimi r0,r0,32-2,31,31 /* _PAGE_USER -> PP lsb */
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#ifdef CONFIG_MODULES
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rlwimi r2, r0, 0, 31, 31 /* userspace ? -> PP lsb */
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#endif
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ori r1, r1, 0xe06 /* clear out reserved bits */
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andc r1, r0, r1 /* PP = user? 1 : 0 */
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andc r1, r2, r1 /* PP = user? 1 : 0 */
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BEGIN_FTR_SECTION
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rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
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END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
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@ -478,38 +481,38 @@ InstructionAddressInvalid:
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. = INTERRUPT_DATA_LOAD_TLB_MISS_603
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DataLoadTLBMiss:
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/*
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* r0: scratch
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* r0: userspace flag (later scratch)
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* r1: linux style pte ( later becomes ppc hardware pte )
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* r2: ptr to linux-style pte
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* r3: scratch
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* r3: fault address
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*/
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/* Get PTE (linux-style) and check access */
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mfspr r3,SPRN_DMISS
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lis r1, TASK_SIZE@h /* check if kernel address */
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cmplw 0,r1,r3
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mfspr r2, SPRN_SDR1
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li r1, _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_USER
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li r1, _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_READ
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rlwinm r2, r2, 28, 0xfffff000
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li r0, 3
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bgt- 112f
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lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
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li r1, _PAGE_PRESENT | _PAGE_ACCESSED
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li r0, 0
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addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
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112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
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lwz r2,0(r2) /* get pmd entry */
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rlwinm. r2,r2,0,0,19 /* extract address of pte page */
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beq- DataAddressInvalid /* return if no mapping */
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rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
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lwz r0,0(r2) /* get linux-style pte */
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andc. r1,r1,r0 /* check access & ~permission */
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lwz r2,0(r2) /* get linux-style pte */
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andc. r1,r1,r2 /* check access & ~permission */
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bne- DataAddressInvalid /* return if access not permitted */
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/* Convert linux-style PTE to low word of PPC-style PTE */
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rlwinm r1,r0,32-9,30,30 /* _PAGE_WRITE -> PP msb */
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rlwimi r0,r0,32-1,30,30 /* _PAGE_USER -> PP msb */
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rlwimi r1,r0,32-3,24,24 /* _PAGE_WRITE -> _PAGE_DIRTY */
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rlwimi r0,r0,32-1,31,31 /* _PAGE_USER -> PP lsb */
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rlwinm r1,r2,32-9,30,30 /* _PAGE_WRITE -> PP msb */
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rlwimi r2,r0,0,30,31 /* userspace ? -> PP */
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rlwimi r1,r2,32-3,24,24 /* _PAGE_WRITE -> _PAGE_DIRTY */
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xori r1,r1,_PAGE_DIRTY /* clear dirty when not rw */
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ori r1,r1,0xe04 /* clear out reserved bits */
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andc r1,r0,r1 /* PP = user? rw? 1: 3: 0 */
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andc r1,r2,r1 /* PP = user? rw? 1: 3: 0 */
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BEGIN_FTR_SECTION
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rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
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END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
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@ -558,34 +561,35 @@ DataAddressInvalid:
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. = INTERRUPT_DATA_STORE_TLB_MISS_603
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DataStoreTLBMiss:
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/*
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* r0: scratch
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* r0: userspace flag (later scratch)
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* r1: linux style pte ( later becomes ppc hardware pte )
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* r2: ptr to linux-style pte
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* r3: scratch
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* r3: fault address
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*/
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/* Get PTE (linux-style) and check access */
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mfspr r3,SPRN_DMISS
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lis r1, TASK_SIZE@h /* check if kernel address */
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cmplw 0,r1,r3
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mfspr r2, SPRN_SDR1
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li r1, _PAGE_RW | _PAGE_DIRTY | _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_USER
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li r1, _PAGE_RW | _PAGE_DIRTY | _PAGE_PRESENT | _PAGE_ACCESSED
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rlwinm r2, r2, 28, 0xfffff000
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li r0, 3
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bgt- 112f
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lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
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li r1, _PAGE_RW | _PAGE_DIRTY | _PAGE_PRESENT | _PAGE_ACCESSED
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li r0, 0
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addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
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112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
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lwz r2,0(r2) /* get pmd entry */
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rlwinm. r2,r2,0,0,19 /* extract address of pte page */
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beq- DataAddressInvalid /* return if no mapping */
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rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
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lwz r0,0(r2) /* get linux-style pte */
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andc. r1,r1,r0 /* check access & ~permission */
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lwz r2,0(r2) /* get linux-style pte */
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andc. r1,r1,r2 /* check access & ~permission */
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bne- DataAddressInvalid /* return if access not permitted */
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/* Convert linux-style PTE to low word of PPC-style PTE */
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rlwimi r0,r0,32-2,31,31 /* _PAGE_USER -> PP lsb */
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rlwimi r2,r0,0,31,31 /* userspace ? -> PP lsb */
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li r1,0xe06 /* clear out reserved bits & PP msb */
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andc r1,r0,r1 /* PP = user? 1: 0 */
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andc r1,r2,r1 /* PP = user? 1: 0 */
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BEGIN_FTR_SECTION
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rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
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END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
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@ -690,6 +694,7 @@ hash_page_dsi:
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mfsrr0 r5
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mfsrr1 r9
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rlwinm r3, r3, 32 - 15, _PAGE_WRITE /* DSISR_STORE -> _PAGE_WRITE */
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ori r3, r3, _PAGE_PRESENT | _PAGE_READ
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bl hash_page
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mfspr r10, SPRN_SPRG_THREAD
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restore_regs_thread r10
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@ -699,7 +704,7 @@ hash_page_isi:
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mr r11, r10
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mfspr r10, SPRN_SPRG_THREAD
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save_regs_thread r10
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li r3, 0
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li r3, _PAGE_PRESENT | _PAGE_EXEC
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lwz r4, SRR0(r10)
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lwz r9, SRR1(r10)
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bl hash_page
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@ -36,8 +36,9 @@
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/*
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* Load a PTE into the hash table, if possible.
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* The address is in r4, and r3 contains an access flag:
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* _PAGE_WRITE (0x400) if a write.
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* The address is in r4, and r3 contains required access flags:
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* - For ISI: _PAGE_PRESENT | _PAGE_EXEC
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* - For DSI: _PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE if a write.
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* r9 contains the SRR1 value, from which we use the MSR_PR bit.
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* SPRG_THREAD contains the physical address of the current task's thread.
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*
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@ -67,12 +68,16 @@ _GLOBAL(hash_page)
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lis r0, TASK_SIZE@h /* check if kernel address */
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cmplw 0,r4,r0
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mfspr r8,SPRN_SPRG_THREAD /* current task's THREAD (phys) */
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ori r3,r3,_PAGE_USER|_PAGE_PRESENT /* test low addresses as user */
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lwz r5,PGDIR(r8) /* virt page-table root */
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blt+ 112f /* assume user more likely */
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lis r5,swapper_pg_dir@ha /* if kernel address, use */
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andi. r0,r9,MSR_PR /* Check usermode */
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addi r5,r5,swapper_pg_dir@l /* kernel page table */
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rlwimi r3,r9,32-12,29,29 /* MSR_PR -> _PAGE_USER */
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#ifdef CONFIG_SMP
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bne- .Lhash_page_out /* return if usermode */
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#else
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bnelr-
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#endif
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112: tophys(r5, r5)
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#ifndef CONFIG_PTE_64BIT
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rlwimi r5,r4,12,20,29 /* insert top 10 bits of address */
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@ -307,12 +312,15 @@ Hash_msk = (((1 << Hash_bits) - 1) * 64)
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__REF
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_GLOBAL(create_hpte)
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/* Convert linux-style PTE (r5) to low word of PPC-style PTE (r8) */
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lis r0, TASK_SIZE@h
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rlwinm r5,r5,0,~3 /* Clear PP bits */
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cmplw r4,r0
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rlwinm r8,r5,32-9,30,30 /* _PAGE_WRITE -> PP msb */
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rlwinm r0,r5,32-6,30,30 /* _PAGE_DIRTY -> PP msb */
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and r8,r8,r0 /* writable if _RW & _DIRTY */
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rlwimi r5,r5,32-1,30,30 /* _PAGE_USER -> PP msb */
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rlwimi r5,r5,32-2,31,31 /* _PAGE_USER -> PP lsb */
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ori r8,r8,0xe04 /* clear out reserved bits */
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bge- 1f /* Kernelspace ? Skip */
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ori r5,r5,3 /* Userspace ? PP = 3 */
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1: ori r8,r8,0xe04 /* clear out reserved bits */
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andc r8,r5,r8 /* PP = user? (rw&dirty? 1: 3): 0 */
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BEGIN_FTR_SECTION
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rlwinm r8,r8,0,~_PAGE_COHERENT /* clear M (coherence not required) */
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