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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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ixgbe: Provide unlocked I2C methods
Most I2C accesses take and release semaphores for each access. Now there is a reason to perform multiple I2C operations under the same holding of the semaphore, so provide unlocked I2C methods for that purpose. Signed-off-by: Mark Rustad <mark.d.rustad@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
Mark Rustad
Jeff Kirsher
parent
4f9e3a3de0
commit
bb5ce9a5cb
4 changed files with 186 additions and 28 deletions
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@ -100,16 +100,17 @@ static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
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}
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/**
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* ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
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* ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
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* @hw: pointer to the hardware structure
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* @addr: I2C bus address to read from
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* @reg: I2C device register to read from
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* @val: pointer to location to receive read value
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* @lock: true if to take and release semaphore
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*
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* Returns an error code on error.
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**/
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s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
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u16 reg, u16 *val)
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*/
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static s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
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u16 reg, u16 *val, bool lock)
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{
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u32 swfw_mask = hw->phy.phy_semaphore_mask;
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int max_retry = 10;
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@ -124,7 +125,7 @@ s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
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csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
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csum = ~csum;
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do {
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if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
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if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
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return IXGBE_ERR_SWFW_SYNC;
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ixgbe_i2c_start(hw);
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/* Device Address and write indication */
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@ -157,13 +158,15 @@ s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
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if (ixgbe_clock_out_i2c_bit(hw, false))
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goto fail;
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ixgbe_i2c_stop(hw);
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hw->mac.ops.release_swfw_sync(hw, swfw_mask);
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if (lock)
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hw->mac.ops.release_swfw_sync(hw, swfw_mask);
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*val = (high_bits << 8) | low_bits;
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return 0;
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fail:
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ixgbe_i2c_bus_clear(hw);
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hw->mac.ops.release_swfw_sync(hw, swfw_mask);
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if (lock)
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hw->mac.ops.release_swfw_sync(hw, swfw_mask);
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retry++;
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if (retry < max_retry)
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hw_dbg(hw, "I2C byte read combined error - Retry.\n");
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@ -175,17 +178,49 @@ s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
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}
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/**
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* ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
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* ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
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* @hw: pointer to the hardware structure
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* @addr: I2C bus address to read from
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* @reg: I2C device register to read from
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* @val: pointer to location to receive read value
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*
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* Returns an error code on error.
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*/
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s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
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u16 reg, u16 *val)
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{
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return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
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}
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/**
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* ixgbe_read_i2c_combined_generic_unlocked - Unlocked I2C read combined
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* @hw: pointer to the hardware structure
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* @addr: I2C bus address to read from
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* @reg: I2C device register to read from
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* @val: pointer to location to receive read value
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*
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* Returns an error code on error.
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*/
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s32 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
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u16 reg, u16 *val)
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{
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return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
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}
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/**
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* ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
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* @hw: pointer to the hardware structure
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* @addr: I2C bus address to write to
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* @reg: I2C device register to write to
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* @val: value to write
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* @lock: true if to take and release semaphore
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*
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* Returns an error code on error.
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**/
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s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
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u8 addr, u16 reg, u16 val)
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*/
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static s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
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u16 reg, u16 val, bool lock)
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{
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u32 swfw_mask = hw->phy.phy_semaphore_mask;
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int max_retry = 1;
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int retry = 0;
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u8 reg_high;
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@ -197,6 +232,8 @@ s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
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csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
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csum = ~csum;
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do {
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if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
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return IXGBE_ERR_SWFW_SYNC;
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ixgbe_i2c_start(hw);
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/* Device Address and write indication */
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if (ixgbe_out_i2c_byte_ack(hw, addr))
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@ -217,10 +254,14 @@ s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
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if (ixgbe_out_i2c_byte_ack(hw, csum))
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goto fail;
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ixgbe_i2c_stop(hw);
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if (lock)
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hw->mac.ops.release_swfw_sync(hw, swfw_mask);
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return 0;
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fail:
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ixgbe_i2c_bus_clear(hw);
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if (lock)
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hw->mac.ops.release_swfw_sync(hw, swfw_mask);
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retry++;
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if (retry < max_retry)
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hw_dbg(hw, "I2C byte write combined error - Retry.\n");
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@ -231,6 +272,36 @@ s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
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return IXGBE_ERR_I2C;
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}
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/**
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* ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
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* @hw: pointer to the hardware structure
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* @addr: I2C bus address to write to
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* @reg: I2C device register to write to
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* @val: value to write
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*
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* Returns an error code on error.
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*/
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s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
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u8 addr, u16 reg, u16 val)
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{
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return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
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}
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/**
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* ixgbe_write_i2c_combined_generic_unlocked - Unlocked I2C write combined
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* @hw: pointer to the hardware structure
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* @addr: I2C bus address to write to
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* @reg: I2C device register to write to
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* @val: value to write
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*
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* Returns an error code on error.
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*/
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s32 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
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u8 addr, u16 reg, u16 val)
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{
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return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
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}
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/**
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* ixgbe_identify_phy_generic - Get physical layer module
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* @hw: pointer to hardware structure
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@ -1660,26 +1731,28 @@ s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
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}
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/**
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* ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
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* ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
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* @hw: pointer to hardware structure
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* @byte_offset: byte offset to read
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* @data: value read
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* @lock: true if to take and release semaphore
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*
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* Performs byte read operation to SFP module's EEPROM over I2C interface at
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* a specified device address.
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**/
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s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
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u8 dev_addr, u8 *data)
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*/
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static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
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u8 dev_addr, u8 *data, bool lock)
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{
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s32 status;
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u32 max_retry = 10;
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u32 retry = 0;
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u32 swfw_mask = hw->phy.phy_semaphore_mask;
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bool nack = true;
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*data = 0;
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do {
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if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
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if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
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return IXGBE_ERR_SWFW_SYNC;
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ixgbe_i2c_start(hw);
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@ -1721,12 +1794,16 @@ s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
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goto fail;
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ixgbe_i2c_stop(hw);
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break;
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if (lock)
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hw->mac.ops.release_swfw_sync(hw, swfw_mask);
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return 0;
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fail:
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ixgbe_i2c_bus_clear(hw);
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hw->mac.ops.release_swfw_sync(hw, swfw_mask);
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msleep(100);
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if (lock) {
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hw->mac.ops.release_swfw_sync(hw, swfw_mask);
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msleep(100);
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}
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retry++;
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if (retry < max_retry)
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hw_dbg(hw, "I2C byte read error - Retrying.\n");
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@ -1735,29 +1812,60 @@ s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
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} while (retry < max_retry);
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hw->mac.ops.release_swfw_sync(hw, swfw_mask);
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return status;
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}
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/**
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* ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
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* ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
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* @hw: pointer to hardware structure
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* @byte_offset: byte offset to read
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* @data: value read
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*
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* Performs byte read operation to SFP module's EEPROM over I2C interface at
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* a specified device address.
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*/
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s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
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u8 dev_addr, u8 *data)
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{
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return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
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data, true);
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}
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/**
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* ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
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* @hw: pointer to hardware structure
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* @byte_offset: byte offset to read
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* @data: value read
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*
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* Performs byte read operation to SFP module's EEPROM over I2C interface at
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* a specified device address.
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*/
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s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
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u8 dev_addr, u8 *data)
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{
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return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
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data, false);
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}
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/**
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* ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
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* @hw: pointer to hardware structure
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* @byte_offset: byte offset to write
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* @data: value to write
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* @lock: true if to take and release semaphore
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*
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* Performs byte write operation to SFP module's EEPROM over I2C interface at
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* a specified device address.
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**/
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s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
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u8 dev_addr, u8 data)
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*/
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static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
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u8 dev_addr, u8 data, bool lock)
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{
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s32 status;
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u32 max_retry = 1;
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u32 retry = 0;
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u32 swfw_mask = hw->phy.phy_semaphore_mask;
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if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
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if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
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return IXGBE_ERR_SWFW_SYNC;
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do {
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@ -1788,7 +1896,9 @@ s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
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goto fail;
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ixgbe_i2c_stop(hw);
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break;
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if (lock)
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hw->mac.ops.release_swfw_sync(hw, swfw_mask);
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return 0;
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fail:
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ixgbe_i2c_bus_clear(hw);
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@ -1799,11 +1909,44 @@ s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
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hw_dbg(hw, "I2C byte write error.\n");
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} while (retry < max_retry);
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hw->mac.ops.release_swfw_sync(hw, swfw_mask);
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if (lock)
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hw->mac.ops.release_swfw_sync(hw, swfw_mask);
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return status;
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}
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/**
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* ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
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* @hw: pointer to hardware structure
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* @byte_offset: byte offset to write
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* @data: value to write
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*
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* Performs byte write operation to SFP module's EEPROM over I2C interface at
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* a specified device address.
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*/
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s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
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u8 dev_addr, u8 data)
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{
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return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
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data, true);
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}
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/**
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* ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
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* @hw: pointer to hardware structure
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* @byte_offset: byte offset to write
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* @data: value to write
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*
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* Performs byte write operation to SFP module's EEPROM over I2C interface at
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* a specified device address.
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*/
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s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
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u8 dev_addr, u8 data)
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{
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return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
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data, false);
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}
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/**
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* ixgbe_i2c_start - Sets I2C start condition
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* @hw: pointer to hardware structure
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@ -154,8 +154,12 @@ s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
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s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw);
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s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
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u8 dev_addr, u8 *data);
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s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
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u8 dev_addr, u8 *data);
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s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
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u8 dev_addr, u8 data);
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s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
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u8 dev_addr, u8 data);
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s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
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u8 *eeprom_data);
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s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
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@ -164,6 +168,10 @@ s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
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u8 eeprom_data);
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s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
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u16 reg, u16 *val);
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s32 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
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u16 reg, u16 *val);
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s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
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u16 reg, u16 val);
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s32 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
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u16 reg, u16 val);
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#endif /* _IXGBE_PHY_H_ */
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@ -3329,6 +3329,10 @@ struct ixgbe_phy_operations {
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s32 (*set_phy_power)(struct ixgbe_hw *, bool on);
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s32 (*enter_lplu)(struct ixgbe_hw *);
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s32 (*handle_lasi)(struct ixgbe_hw *hw);
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s32 (*read_i2c_combined_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,
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u16 *value);
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s32 (*write_i2c_combined_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,
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u16 value);
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};
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struct ixgbe_eeprom_info {
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@ -2047,6 +2047,9 @@ static struct ixgbe_phy_operations phy_ops_X550EM_x = {
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.identify = &ixgbe_identify_phy_x550em,
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.read_i2c_combined = &ixgbe_read_i2c_combined_generic,
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.write_i2c_combined = &ixgbe_write_i2c_combined_generic,
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.read_i2c_combined_unlocked = &ixgbe_read_i2c_combined_generic_unlocked,
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.write_i2c_combined_unlocked =
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&ixgbe_write_i2c_combined_generic_unlocked,
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};
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static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = {
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|
|
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Loading…
Reference in a new issue