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arm64: dts: qcom: rename AOSS QMP nodes

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The Always On Subsystem (AOSS) QMP is not a power domain controller
since commit 1357804562 ("arm64: dts: qcom: sc7180: Use QMP property
to control load state") and few others.  In fact, it was never a power
domain controller but rather control of power state of remote
processors.  This power state control is now handled differently, thus
the AOSS QMP nodes do not have power-domain-cells:

  sc7280-idp.dtb: power-controller@c300000: '#power-domain-cells' is a required property
  From schema: Documentation/devicetree/bindings/power/power-domain.yaml

AOSS QMP is an interface to the actuall AOSS subsystem responsible for
some of power management functions, thus let's call the nodes as
"power-management".

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221213101921.47924-4-krzysztof.kozlowski@linaro.org
This commit is contained in:
Krzysztof Kozlowski 2022-12-13 11:19:20 +01:00 committed by Bjorn Andersson
parent 76d9e8b4d5
commit bb99820dd2
9 changed files with 9 additions and 9 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
arch/arm64/boot/dts/qcom/sc7180.dtsi
View file

@ -3250,7 +3250,7 @@ aoss_reset: reset-controller@c2a0000 {
#reset-cells = <1>; #reset-cells = <1>;
}; };
aoss_qmp: power-controller@c300000 { aoss_qmp: power-management@c300000 {
compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp"; compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp";
reg = <0 0x0c300000 0 0x400>; reg = <0 0x0c300000 0 0x400>;
interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;

2
arch/arm64/boot/dts/qcom/sc7280.dtsi
View file

@ -4221,7 +4221,7 @@ aoss_reset: reset-controller@c2a0000 {
#reset-cells = <1>; #reset-cells = <1>;
}; };
aoss_qmp: power-controller@c300000 { aoss_qmp: power-management@c300000 {
compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp";
reg = <0 0x0c300000 0 0x400>; reg = <0 0x0c300000 0 0x400>;
interrupts-extended = <&ipcc IPCC_CLIENT_AOP interrupts-extended = <&ipcc IPCC_CLIENT_AOP

2
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
View file

@ -2421,7 +2421,7 @@ tsens1: thermal-sensor@c265000 {
#thermal-sensor-cells = <1>; #thermal-sensor-cells = <1>;
}; };
aoss_qmp: power-controller@c300000 { aoss_qmp: power-management@c300000 {
compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp"; compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp";
reg = <0 0x0c300000 0 0x400>; reg = <0 0x0c300000 0 0x400>;
interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>;

2
arch/arm64/boot/dts/qcom/sdm845.dtsi
View file

@ -4935,7 +4935,7 @@ aoss_reset: reset-controller@c2a0000 {
#reset-cells = <1>; #reset-cells = <1>;
}; };
aoss_qmp: power-controller@c300000 { aoss_qmp: power-management@c300000 {
compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp"; compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp";
reg = <0 0x0c300000 0 0x400>; reg = <0 0x0c300000 0 0x400>;
interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;

2
arch/arm64/boot/dts/qcom/sm6350.dtsi
View file

@ -1280,7 +1280,7 @@ tsens1: thermal-sensor@c265000 {
#thermal-sensor-cells = <1>; #thermal-sensor-cells = <1>;
}; };
aoss_qmp: power-controller@c300000 { aoss_qmp: power-management@c300000 {
compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp"; compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp";
reg = <0 0x0c300000 0 0x1000>; reg = <0 0x0c300000 0 0x1000>;
interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP

2
arch/arm64/boot/dts/qcom/sm8150.dtsi
View file

@ -3890,7 +3890,7 @@ pdc: interrupt-controller@b220000 {
interrupt-controller; interrupt-controller;
}; };
aoss_qmp: power-controller@c300000 { aoss_qmp: power-management@c300000 {
compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp"; compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp";
reg = <0x0 0x0c300000 0x0 0x400>; reg = <0x0 0x0c300000 0x0 0x400>;
interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;

2
arch/arm64/boot/dts/qcom/sm8250.dtsi
View file

@ -4294,7 +4294,7 @@ tsens1: thermal-sensor@c265000 {
#thermal-sensor-cells = <1>; #thermal-sensor-cells = <1>;
}; };
aoss_qmp: power-controller@c300000 { aoss_qmp: power-management@c300000 {
compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp"; compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp";
reg = <0 0x0c300000 0 0x400>; reg = <0 0x0c300000 0 0x400>;
interrupts-extended = <&ipcc IPCC_CLIENT_AOP interrupts-extended = <&ipcc IPCC_CLIENT_AOP

2
arch/arm64/boot/dts/qcom/sm8350.dtsi
View file

@ -1726,7 +1726,7 @@ tsens1: thermal-sensor@c265000 {
#thermal-sensor-cells = <1>; #thermal-sensor-cells = <1>;
}; };
aoss_qmp: power-controller@c300000 { aoss_qmp: power-management@c300000 {
compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp"; compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp";
reg = <0 0x0c300000 0 0x400>; reg = <0 0x0c300000 0 0x400>;
interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP

2
arch/arm64/boot/dts/qcom/sm8450.dtsi
View file

@ -2994,7 +2994,7 @@ tsens1: thermal-sensor@c265000 {
#thermal-sensor-cells = <1>; #thermal-sensor-cells = <1>;
}; };
aoss_qmp: power-controller@c300000 { aoss_qmp: power-management@c300000 {
compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp"; compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp";
reg = <0 0x0c300000 0 0x400>; reg = <0 0x0c300000 0 0x400>;
interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP