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clk: divider: Add re-usable determine_rate implementations

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These are useful when running on 32-bit systems to increase the upper
supported frequency limit. clk_ops.round_rate returns a signed long
which limits the maximum rate on 32-bit systems to 2^31 (or approx.
2.14GHz). clk_ops.determine_rate internally uses an unsigned long so
the maximum rate on 32-bit systems is 2^32 or approx. 4.29GHz.

To avoid code-duplication switch over divider_{ro_,}round_rate_parent
to use the new divider_{ro_,}determine_rate functions.

Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20210627223959.188139-2-martin.blumenstingl@googlemail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Martin Blumenstingl 2021-06-28 00:39:57 +02:00 committed by Stephen Boyd
parent faa0e30794
commit bbd7a6cc38
2 changed files with 67 additions and 14 deletions
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75
drivers/clk/clk-divider.c
View file

@ -343,16 +343,63 @@ static int clk_divider_bestdiv(struct clk_hw *hw, struct clk_hw *parent,
return bestdiv;
}
int divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
const struct clk_div_table *table, u8 width,
unsigned long flags)
{
int div;
div = clk_divider_bestdiv(hw, req->best_parent_hw, req->rate,
&req->best_parent_rate, table, width, flags);
req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div);
return 0;
}
EXPORT_SYMBOL_GPL(divider_determine_rate);
int divider_ro_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
const struct clk_div_table *table, u8 width,
unsigned long flags, unsigned int val)
{
int div;
div = _get_div(table, val, flags, width);
/* Even a read-only clock can propagate a rate change */
if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
if (!req->best_parent_hw)
return -EINVAL;
req->best_parent_rate = clk_hw_round_rate(req->best_parent_hw,
req->rate * div);
}
req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div);
return 0;
}
EXPORT_SYMBOL_GPL(divider_ro_determine_rate);
long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
unsigned long rate, unsigned long *prate,
const struct clk_div_table *table,
u8 width, unsigned long flags)
{
int div;
struct clk_rate_request req = {
.rate = rate,
.best_parent_rate = *prate,
.best_parent_hw = parent,
};
int ret;
div = clk_divider_bestdiv(hw, parent, rate, prate, table, width, flags);
ret = divider_determine_rate(hw, &req, table, width, flags);
if (ret)
return ret;
return DIV_ROUND_UP_ULL((u64)*prate, div);
*prate = req.best_parent_rate;
return req.rate;
}
EXPORT_SYMBOL_GPL(divider_round_rate_parent);
@ -361,23 +408,23 @@ long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
const struct clk_div_table *table, u8 width,
unsigned long flags, unsigned int val)
{
int div;
struct clk_rate_request req = {
.rate = rate,
.best_parent_rate = *prate,
.best_parent_hw = parent,
};
int ret;
div = _get_div(table, val, flags, width);
ret = divider_ro_determine_rate(hw, &req, table, width, flags, val);
if (ret)
return ret;
/* Even a read-only clock can propagate a rate change */
if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
if (!parent)
return -EINVAL;
*prate = req.best_parent_rate;
*prate = clk_hw_round_rate(parent, rate * div);
}
return DIV_ROUND_UP_ULL((u64)*prate, div);
return req.rate;
}
EXPORT_SYMBOL_GPL(divider_ro_round_rate_parent);
static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{

6
include/linux/clk-provider.h
View file

@ -629,6 +629,12 @@ long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
unsigned long rate, unsigned long *prate,
const struct clk_div_table *table, u8 width,
unsigned long flags, unsigned int val);
int divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
const struct clk_div_table *table, u8 width,
unsigned long flags);
int divider_ro_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
const struct clk_div_table *table, u8 width,
unsigned long flags, unsigned int val);
int divider_get_val(unsigned long rate, unsigned long parent_rate,
const struct clk_div_table *table, u8 width,
unsigned long flags);