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ARM: dts: uniphier: rename cache controller nodes to follow json-schema

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Follow the standard nodename pattern
"^(cache-controller|cpu)(@[0-9a-f,]+)*$" defined in
schemas/cache-controller.yaml of dt-schema.

Otherwise, after the dt-binding is converted to json-schema,
'make ARCH=arm dtbs_check' will show warnings like this:

  l2-cache@500c0000: $nodename:0: 'l2-cache@500c0000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$'

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Masahiro Yamada 2020-02-27 21:37:26 +09:00
parent f215c5ef7c
commit bc350d1073
5 changed files with 6 additions and 6 deletions
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2
arch/arm/boot/dts/uniphier-ld4.dtsi
View file

@ -51,7 +51,7 @@ soc {
ranges;
interrupt-parent = <&intc>;
l2: l2-cache@500c0000 {
l2: cache-controller@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
<0x506c0000 0x400>;

2
arch/arm/boot/dts/uniphier-pro4.dtsi
View file

@ -59,7 +59,7 @@ soc {
ranges;
interrupt-parent = <&intc>;
l2: l2-cache@500c0000 {
l2: cache-controller@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
<0x506c0000 0x400>;

4
arch/arm/boot/dts/uniphier-pro5.dtsi
View file

@ -131,7 +131,7 @@ soc {
ranges;
interrupt-parent = <&intc>;
l2: l2-cache@500c0000 {
l2: cache-controller@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
<0x506c0000 0x400>;
@ -144,7 +144,7 @@ l2: l2-cache@500c0000 {
next-level-cache = <&l3>;
};
l3: l3-cache@500c8000 {
l3: cache-controller@500c8000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
<0x506c8000 0x400>;

2
arch/arm/boot/dts/uniphier-pxs2.dtsi
View file

@ -157,7 +157,7 @@ soc {
ranges;
interrupt-parent = <&intc>;
l2: l2-cache@500c0000 {
l2: cache-controller@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
<0x506c0000 0x400>;

2
arch/arm/boot/dts/uniphier-sld8.dtsi
View file

@ -51,7 +51,7 @@ soc {
ranges;
interrupt-parent = <&intc>;
l2: l2-cache@500c0000 {
l2: cache-controller@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
<0x506c0000 0x400>;