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serial: stm32: fix clearing interrupt error flags
commit1250ed7114
upstream. The interrupt clear flag register is a "write 1 to clear" register. So, only writing ones allows to clear flags: - Replace buggy stm32_clr_bits() by a simple write to clear error flags - Replace useless read/modify/write stm32_set_bits() routine by a simple write to clear TC (transfer complete) flag. Fixes:4f01d833fd
("serial: stm32: fix rx error handling") Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Cc: stable <stable@vger.kernel.org> Link: https://lore.kernel.org/r/1574323849-1909-1-git-send-email-fabrice.gasnier@st.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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parent
6e728a5792
commit
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1 changed files with 3 additions and 3 deletions
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@ -240,8 +240,8 @@ static void stm32_receive_chars(struct uart_port *port, bool threaded)
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* cleared by the sequence [read SR - read DR].
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*/
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if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG)
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stm32_clr_bits(port, ofs->icr, USART_ICR_ORECF |
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USART_ICR_PECF | USART_ICR_FECF);
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writel_relaxed(sr & USART_SR_ERR_MASK,
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port->membase + ofs->icr);
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c = stm32_get_char(port, &sr, &stm32_port->last_res);
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port->icount.rx++;
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@ -435,7 +435,7 @@ static void stm32_transmit_chars(struct uart_port *port)
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if (ofs->icr == UNDEF_REG)
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stm32_clr_bits(port, ofs->isr, USART_SR_TC);
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else
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stm32_set_bits(port, ofs->icr, USART_ICR_TCCF);
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writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr);
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if (stm32_port->tx_ch)
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stm32_transmit_chars_dma(port);
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