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arm64: dts: qcom: sm8450: add PCIe1 root device
Add device tree node for the second PCIe host found on the Qualcomm SM8450 platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220301061500.2110569-5-dmitry.baryshkov@linaro.org
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@ -865,6 +865,79 @@ pcie0_lane: lanes@1c06200 {
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};
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};
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pcie1: pci@1c08000 {
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compatible = "qcom,pcie-sm8450-pcie1";
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reg = <0 0x01c08000 0 0x3000>,
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<0 0x40000000 0 0xf1d>,
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<0 0x40000f20 0 0xa8>,
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<0 0x40001000 0 0x1000>,
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<0 0x40100000 0 0x100000>;
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reg-names = "parf", "dbi", "elbi", "atu", "config";
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device_type = "pci";
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linux,pci-domain = <1>;
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bus-range = <0x00 0xff>;
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num-lanes = <2>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>,
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<0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>;
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interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
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<0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
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<0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
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<0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
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clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
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<&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
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<&pcie1_lane>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_PCIE_1_AUX_CLK>,
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<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
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<&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
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<&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
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clock-names = "pipe",
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"pipe_mux",
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"phy_pipe",
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"ref",
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"aux",
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"cfg",
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"bus_master",
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"bus_slave",
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"slave_q2a",
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"ddrss_sf_tbu",
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"aggre1";
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iommus = <&apps_smmu 0x1c80 0x7f>;
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iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
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<0x100 &apps_smmu 0x1c81 0x1>;
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resets = <&gcc GCC_PCIE_1_BCR>;
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reset-names = "pci";
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power-domains = <&gcc PCIE_1_GDSC>;
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power-domain-names = "gdsc";
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phys = <&pcie1_lane>;
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phy-names = "pciephy";
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perst-gpio = <&tlmm 97 GPIO_ACTIVE_LOW>;
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enable-gpio = <&tlmm 99 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie1_default_state>;
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status = "disabled";
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};
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pcie1_phy: phy@1c0f000 {
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compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy";
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reg = <0 0x01c0f000 0 0x200>;
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@ -1344,6 +1417,29 @@ wake {
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};
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};
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pcie1_default_state: pcie1-default-state {
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perst {
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pins = "gpio97";
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function = "gpio";
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drive-strength = <2>;
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bias-pull-down;
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};
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clkreq {
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pins = "gpio98";
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function = "pcie1_clkreqn";
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drive-strength = <2>;
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bias-pull-up;
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};
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wake {
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pins = "gpio99";
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function = "gpio";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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qup_i2c13_data_clk: qup-i2c13-data-clk {
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pins = "gpio48", "gpio49";
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function = "qup13";
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