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clk: renesas: r8a77965: Add FDP clock

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This patch adds FDP1-0 clock to the R8A77965 SoC.

Signed-off-by: Hoan Nguyen An <na-hoan@jinso.co.jp>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Hoan Nguyen An 2018-08-24 13:52:29 +09:00 committed by Geert Uytterhoeven
parent 331a53e05b
commit bc7133cef8
1 changed files with 1 additions and 0 deletions
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drivers/clk/renesas/r8a77965-cpg-mssr.c
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@ -112,6 +112,7 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = {
};
static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
DEF_MOD("fdp1-0", 119, R8A77965_CLK_S0D1),
DEF_MOD("scif5", 202, R8A77965_CLK_S3D4),
DEF_MOD("scif4", 203, R8A77965_CLK_S3D4),
DEF_MOD("scif3", 204, R8A77965_CLK_S3D4),