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habanalabs/gaudi2: update f/w files
Update gaudi2 firmware files with the latest version. There is no functional change. Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
This commit is contained in:
parent
2fd7db3c80
commit
bcace6f058
2 changed files with 23 additions and 16 deletions
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@ -20,22 +20,25 @@
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#define GAUDI2_NUM_MME 4
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#define NUM_OF_GPIOS_PER_PORT 16
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#define GAUDI2_WD_GPIO (62 % NUM_OF_GPIOS_PER_PORT)
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#define GAUDI2_ARCPID_TX_MB_SIZE 0x1000
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#define GAUDI2_ARCPID_RX_MB_SIZE 0x400
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#define GAUDI2_ARM_TX_MB_SIZE 0x400
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#define GAUDI2_ARM_RX_MB_SIZE 0x1800
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#define GAUDI2_DCCM_BASE_ADDR 0x27020000
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#define GAUDI2_ARCPID_TX_MB_ADDR GAUDI2_DCCM_BASE_ADDR
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#define GAUDI2_ARCPID_RX_MB_ADDR (GAUDI2_ARCPID_TX_MB_ADDR + \
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GAUDI2_ARCPID_TX_MB_SIZE)
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#define GAUDI2_ARM_TX_MB_ADDR GAUDI2_MAILBOX_BASE_ADDR
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#define GAUDI2_ARM_RX_MB_ADDR (GAUDI2_ARM_TX_MB_ADDR + \
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GAUDI2_ARM_TX_MB_SIZE)
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#define GAUDI2_ARCPID_TX_MB_ADDR (GAUDI2_ARM_RX_MB_ADDR + GAUDI2_ARM_RX_MB_SIZE)
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#define GAUDI2_ARCPID_RX_MB_ADDR (GAUDI2_ARCPID_TX_MB_ADDR + GAUDI2_ARCPID_TX_MB_SIZE)
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#define GAUDI2_ARM_TX_MB_OFFSET (GAUDI2_ARM_TX_MB_ADDR - \
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GAUDI2_SP_SRAM_BASE_ADDR)
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@ -58,7 +61,9 @@ struct gaudi2_cold_rst_data {
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u32 spsram_init_done : 1;
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u32 fake_security_enable : 1;
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u32 fake_sig_validation_en : 1;
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u32 reserved : 26;
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u32 bist_skip_enable : 1;
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u32 bist_need_iatu_config : 1;
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u32 reserved : 24;
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};
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__le32 data;
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};
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@ -77,10 +82,10 @@ enum gaudi2_rst_src {
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};
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struct gaudi2_redundancy_ctx {
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int redundant_hbm;
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int redundant_edma;
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int redundant_tpc;
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int redundant_vdec;
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__le32 redundant_hbm;
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__le32 redundant_edma;
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__le32 redundant_tpc;
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__le32 redundant_vdec;
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__le64 hbm_mask;
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__le64 edma_mask;
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__le64 tpc_mask;
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@ -24,14 +24,14 @@
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#define mmGIC_HOST_HALT_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_10
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#define mmGIC_HOST_INTS_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_11
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#define mmGIC_HOST_SOFT_RST_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_12
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#define mmEEPROM_COPY_LOCATION_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_13
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#define mmCPU_RST_STATUS_TO_HOST mmPSOC_GLOBAL_CONF_SCRATCHPAD_14
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/*
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* Single scratchpad register used for all ARCs to notify dccm queue full event to FW.
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* So a new event would overwrite any unhandled previous event. In other words, incase
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* of multiple events before previous ones are handled, last one would be considered.
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*/
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#define mmENGINE_ARC_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_15
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#define mmPID_CFG_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_18
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/*
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* TODO: mmGIC_RAZWI_STATUS_REG is temporary
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* macro and to be removed after GAUDI2 PO
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*/
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#define mmGIC_RAZWI_STATUS_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_19
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#define mmCPU_BOOT_DEV_STS0 mmPSOC_GLOBAL_CONF_SCRATCHPAD_20
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#define mmCPU_BOOT_DEV_STS1 mmPSOC_GLOBAL_CONF_SCRATCHPAD_21
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@ -40,11 +40,10 @@
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#define mmCPU_BOOT_ERR1 mmPSOC_GLOBAL_CONF_SCRATCHPAD_25
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#define mmUPD_STS mmPSOC_GLOBAL_CONF_SCRATCHPAD_26
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#define mmUPD_CMD mmPSOC_GLOBAL_CONF_SCRATCHPAD_27
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#define mmUBOOT_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_29
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#define mmPPBOOT_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_28
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#define mmRDWR_TEST mmPSOC_GLOBAL_CONF_SCRATCHPAD_30
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#define mmBTL_ID mmPSOC_GLOBAL_CONF_SCRATCHPAD_31
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#define mmRST_SRC mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_0
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#define mmPREBOOT_PCIE_EN mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_1
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#define mmCOLD_RST_DATA mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_2
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#define mmUPD_PENDING_STS mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_3
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#define mmPID_CMD_REQ_REG mmPSOC_PID_PID_CMD_0
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@ -55,5 +54,8 @@
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#define mmPID_CMD_TELEMETRY_REG_0_HI mmPSOC_PID_PID_CMD_5
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#define mmPID_CMD_TELEMETRY_REG_1 mmPSOC_PID_PID_CMD_6
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#define mmPID_CMD_TELEMETRY_REG_1_HI mmPSOC_PID_PID_CMD_7
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#define mmWD_GPIO_OUTSET_REG mmPSOC_GPIO3_OUTENSET
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#define mmWD_GPIO_DATAOUT_REG mmPSOC_GPIO3_DATAOUT
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#define mmSTM_PROFILER_SPE_REG mmPSOC_STM_STMSPER
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#endif /* GAUDI2_REG_MAP_H_ */
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