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spi: remove omap 100K driver
The OMAP7xx/OMAP8xx support was removed since all of its boards have no remaining users. Remove its spi driver as well. Cc: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: Janusz Krzysztofik <jmkrzyszt@gmail.com> Cc: linux-omap@vger.kernel.org Cc: Cory Maccarrone <darkstar6262@gmail.com> Cc: Fabrice Crohas <fcrohas@gmail.com> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
parent
4a8fda693b
commit
bcace9c4c9
3 changed files with 0 additions and 497 deletions
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@ -708,12 +708,6 @@ config SPI_TI_QSPI
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This device supports single, dual and quad read support, while
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This device supports single, dual and quad read support, while
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it only supports single write mode.
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it only supports single write mode.
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config SPI_OMAP_100K
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tristate "OMAP SPI 100K"
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depends on ARCH_OMAP850 || ARCH_OMAP730 || COMPILE_TEST
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help
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OMAP SPI 100K master controller for omap7xx boards.
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config SPI_ORION
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config SPI_ORION
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tristate "Orion SPI master"
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tristate "Orion SPI master"
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depends on PLAT_ORION || ARCH_MVEBU || COMPILE_TEST
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depends on PLAT_ORION || ARCH_MVEBU || COMPILE_TEST
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@ -91,7 +91,6 @@ obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o
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spi-octeon-objs := spi-cavium.o spi-cavium-octeon.o
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spi-octeon-objs := spi-cavium.o spi-cavium-octeon.o
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obj-$(CONFIG_SPI_OCTEON) += spi-octeon.o
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obj-$(CONFIG_SPI_OCTEON) += spi-octeon.o
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obj-$(CONFIG_SPI_OMAP_UWIRE) += spi-omap-uwire.o
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obj-$(CONFIG_SPI_OMAP_UWIRE) += spi-omap-uwire.o
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obj-$(CONFIG_SPI_OMAP_100K) += spi-omap-100k.o
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obj-$(CONFIG_SPI_OMAP24XX) += spi-omap2-mcspi.o
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obj-$(CONFIG_SPI_OMAP24XX) += spi-omap2-mcspi.o
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obj-$(CONFIG_SPI_TI_QSPI) += spi-ti-qspi.o
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obj-$(CONFIG_SPI_TI_QSPI) += spi-ti-qspi.o
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obj-$(CONFIG_SPI_ORION) += spi-orion.o
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obj-$(CONFIG_SPI_ORION) += spi-orion.o
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@ -1,490 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* OMAP7xx SPI 100k controller driver
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* Author: Fabrice Crohas <fcrohas@gmail.com>
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* from original omap1_mcspi driver
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*
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* Copyright (C) 2005, 2006 Nokia Corporation
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* Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
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* Juha Yrjola <juha.yrjola@nokia.com>
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/spi/spi.h>
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#define OMAP1_SPI100K_MAX_FREQ 48000000
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#define ICR_SPITAS (OMAP7XX_ICR_BASE + 0x12)
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#define SPI_SETUP1 0x00
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#define SPI_SETUP2 0x02
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#define SPI_CTRL 0x04
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#define SPI_STATUS 0x06
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#define SPI_TX_LSB 0x08
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#define SPI_TX_MSB 0x0a
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#define SPI_RX_LSB 0x0c
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#define SPI_RX_MSB 0x0e
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#define SPI_SETUP1_INT_READ_ENABLE (1UL << 5)
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#define SPI_SETUP1_INT_WRITE_ENABLE (1UL << 4)
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#define SPI_SETUP1_CLOCK_DIVISOR(x) ((x) << 1)
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#define SPI_SETUP1_CLOCK_ENABLE (1UL << 0)
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#define SPI_SETUP2_ACTIVE_EDGE_FALLING (0UL << 0)
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#define SPI_SETUP2_ACTIVE_EDGE_RISING (1UL << 0)
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#define SPI_SETUP2_NEGATIVE_LEVEL (0UL << 5)
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#define SPI_SETUP2_POSITIVE_LEVEL (1UL << 5)
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#define SPI_SETUP2_LEVEL_TRIGGER (0UL << 10)
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#define SPI_SETUP2_EDGE_TRIGGER (1UL << 10)
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#define SPI_CTRL_SEN(x) ((x) << 7)
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#define SPI_CTRL_WORD_SIZE(x) (((x) - 1) << 2)
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#define SPI_CTRL_WR (1UL << 1)
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#define SPI_CTRL_RD (1UL << 0)
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#define SPI_STATUS_WE (1UL << 1)
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#define SPI_STATUS_RD (1UL << 0)
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/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
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* cache operations; better heuristics consider wordsize and bitrate.
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*/
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#define DMA_MIN_BYTES 8
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#define SPI_RUNNING 0
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#define SPI_SHUTDOWN 1
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struct omap1_spi100k {
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struct clk *ick;
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struct clk *fck;
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/* Virtual base address of the controller */
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void __iomem *base;
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};
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struct omap1_spi100k_cs {
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void __iomem *base;
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int word_len;
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};
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static void spi100k_enable_clock(struct spi_master *master)
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{
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unsigned int val;
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struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
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/* enable SPI */
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val = readw(spi100k->base + SPI_SETUP1);
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val |= SPI_SETUP1_CLOCK_ENABLE;
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writew(val, spi100k->base + SPI_SETUP1);
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}
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static void spi100k_disable_clock(struct spi_master *master)
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{
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unsigned int val;
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struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
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/* disable SPI */
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val = readw(spi100k->base + SPI_SETUP1);
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val &= ~SPI_SETUP1_CLOCK_ENABLE;
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writew(val, spi100k->base + SPI_SETUP1);
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}
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static void spi100k_write_data(struct spi_master *master, int len, int data)
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{
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struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
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/* write 16-bit word, shifting 8-bit data if necessary */
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if (len <= 8) {
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data <<= 8;
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len = 16;
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}
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spi100k_enable_clock(master);
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writew(data, spi100k->base + SPI_TX_MSB);
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writew(SPI_CTRL_SEN(0) |
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SPI_CTRL_WORD_SIZE(len) |
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SPI_CTRL_WR,
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spi100k->base + SPI_CTRL);
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/* Wait for bit ack send change */
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while ((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_WE) != SPI_STATUS_WE)
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;
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udelay(1000);
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spi100k_disable_clock(master);
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}
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static int spi100k_read_data(struct spi_master *master, int len)
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{
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int dataL;
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struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
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/* Always do at least 16 bits */
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if (len <= 8)
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len = 16;
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spi100k_enable_clock(master);
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writew(SPI_CTRL_SEN(0) |
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SPI_CTRL_WORD_SIZE(len) |
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SPI_CTRL_RD,
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spi100k->base + SPI_CTRL);
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while ((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_RD) != SPI_STATUS_RD)
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;
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udelay(1000);
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dataL = readw(spi100k->base + SPI_RX_LSB);
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readw(spi100k->base + SPI_RX_MSB);
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spi100k_disable_clock(master);
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return dataL;
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}
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static void spi100k_open(struct spi_master *master)
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{
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/* get control of SPI */
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struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
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writew(SPI_SETUP1_INT_READ_ENABLE |
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SPI_SETUP1_INT_WRITE_ENABLE |
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SPI_SETUP1_CLOCK_DIVISOR(0), spi100k->base + SPI_SETUP1);
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/* configure clock and interrupts */
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writew(SPI_SETUP2_ACTIVE_EDGE_FALLING |
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SPI_SETUP2_NEGATIVE_LEVEL |
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SPI_SETUP2_LEVEL_TRIGGER, spi100k->base + SPI_SETUP2);
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}
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static void omap1_spi100k_force_cs(struct omap1_spi100k *spi100k, int enable)
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{
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if (enable)
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writew(0x05fc, spi100k->base + SPI_CTRL);
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else
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writew(0x05fd, spi100k->base + SPI_CTRL);
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}
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static unsigned
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omap1_spi100k_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
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{
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struct omap1_spi100k_cs *cs = spi->controller_state;
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unsigned int count, c;
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int word_len;
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count = xfer->len;
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c = count;
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word_len = cs->word_len;
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if (word_len <= 8) {
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u8 *rx;
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const u8 *tx;
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rx = xfer->rx_buf;
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tx = xfer->tx_buf;
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do {
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c -= 1;
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if (xfer->tx_buf != NULL)
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spi100k_write_data(spi->master, word_len, *tx++);
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if (xfer->rx_buf != NULL)
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*rx++ = spi100k_read_data(spi->master, word_len);
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} while (c);
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} else if (word_len <= 16) {
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u16 *rx;
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const u16 *tx;
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rx = xfer->rx_buf;
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tx = xfer->tx_buf;
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do {
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c -= 2;
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if (xfer->tx_buf != NULL)
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spi100k_write_data(spi->master, word_len, *tx++);
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if (xfer->rx_buf != NULL)
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*rx++ = spi100k_read_data(spi->master, word_len);
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} while (c);
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} else if (word_len <= 32) {
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u32 *rx;
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const u32 *tx;
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rx = xfer->rx_buf;
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tx = xfer->tx_buf;
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do {
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c -= 4;
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if (xfer->tx_buf != NULL)
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spi100k_write_data(spi->master, word_len, *tx);
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if (xfer->rx_buf != NULL)
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*rx = spi100k_read_data(spi->master, word_len);
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} while (c);
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}
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return count - c;
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}
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/* called only when no transfer is active to this device */
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static int omap1_spi100k_setup_transfer(struct spi_device *spi,
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struct spi_transfer *t)
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{
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struct omap1_spi100k *spi100k = spi_master_get_devdata(spi->master);
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struct omap1_spi100k_cs *cs = spi->controller_state;
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u8 word_len;
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if (t != NULL)
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word_len = t->bits_per_word;
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else
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word_len = spi->bits_per_word;
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if (word_len > 32)
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return -EINVAL;
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cs->word_len = word_len;
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/* SPI init before transfer */
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writew(0x3e, spi100k->base + SPI_SETUP1);
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writew(0x00, spi100k->base + SPI_STATUS);
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writew(0x3e, spi100k->base + SPI_CTRL);
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return 0;
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}
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/* the spi->mode bits understood by this driver: */
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#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
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static int omap1_spi100k_setup(struct spi_device *spi)
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{
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int ret;
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struct omap1_spi100k *spi100k;
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struct omap1_spi100k_cs *cs = spi->controller_state;
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spi100k = spi_master_get_devdata(spi->master);
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if (!cs) {
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cs = devm_kzalloc(&spi->dev, sizeof(*cs), GFP_KERNEL);
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if (!cs)
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return -ENOMEM;
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cs->base = spi100k->base + spi->chip_select * 0x14;
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spi->controller_state = cs;
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}
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spi100k_open(spi->master);
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clk_prepare_enable(spi100k->ick);
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clk_prepare_enable(spi100k->fck);
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ret = omap1_spi100k_setup_transfer(spi, NULL);
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clk_disable_unprepare(spi100k->ick);
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clk_disable_unprepare(spi100k->fck);
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return ret;
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}
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static int omap1_spi100k_transfer_one_message(struct spi_master *master,
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struct spi_message *m)
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{
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struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
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struct spi_device *spi = m->spi;
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struct spi_transfer *t = NULL;
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int cs_active = 0;
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int status = 0;
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list_for_each_entry(t, &m->transfers, transfer_list) {
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if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
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break;
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}
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status = omap1_spi100k_setup_transfer(spi, t);
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if (status < 0)
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break;
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if (!cs_active) {
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omap1_spi100k_force_cs(spi100k, 1);
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cs_active = 1;
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}
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if (t->len) {
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unsigned count;
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count = omap1_spi100k_txrx_pio(spi, t);
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m->actual_length += count;
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if (count != t->len) {
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break;
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}
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}
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spi_transfer_delay_exec(t);
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/* ignore the "leave it on after last xfer" hint */
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if (t->cs_change) {
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omap1_spi100k_force_cs(spi100k, 0);
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cs_active = 0;
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}
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}
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status = omap1_spi100k_setup_transfer(spi, NULL);
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||||||
if (cs_active)
|
|
||||||
omap1_spi100k_force_cs(spi100k, 0);
|
|
||||||
|
|
||||||
m->status = status;
|
|
||||||
|
|
||||||
spi_finalize_current_message(master);
|
|
||||||
|
|
||||||
return status;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int omap1_spi100k_probe(struct platform_device *pdev)
|
|
||||||
{
|
|
||||||
struct spi_master *master;
|
|
||||||
struct omap1_spi100k *spi100k;
|
|
||||||
int status = 0;
|
|
||||||
|
|
||||||
if (!pdev->id)
|
|
||||||
return -EINVAL;
|
|
||||||
|
|
||||||
master = spi_alloc_master(&pdev->dev, sizeof(*spi100k));
|
|
||||||
if (master == NULL) {
|
|
||||||
dev_dbg(&pdev->dev, "master allocation failed\n");
|
|
||||||
return -ENOMEM;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (pdev->id != -1)
|
|
||||||
master->bus_num = pdev->id;
|
|
||||||
|
|
||||||
master->setup = omap1_spi100k_setup;
|
|
||||||
master->transfer_one_message = omap1_spi100k_transfer_one_message;
|
|
||||||
master->num_chipselect = 2;
|
|
||||||
master->mode_bits = MODEBITS;
|
|
||||||
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
|
|
||||||
master->min_speed_hz = OMAP1_SPI100K_MAX_FREQ/(1<<16);
|
|
||||||
master->max_speed_hz = OMAP1_SPI100K_MAX_FREQ;
|
|
||||||
master->auto_runtime_pm = true;
|
|
||||||
|
|
||||||
spi100k = spi_master_get_devdata(master);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* The memory region base address is taken as the platform_data.
|
|
||||||
* You should allocate this with ioremap() before initializing
|
|
||||||
* the SPI.
|
|
||||||
*/
|
|
||||||
spi100k->base = (void __iomem *)dev_get_platdata(&pdev->dev);
|
|
||||||
|
|
||||||
spi100k->ick = devm_clk_get(&pdev->dev, "ick");
|
|
||||||
if (IS_ERR(spi100k->ick)) {
|
|
||||||
dev_dbg(&pdev->dev, "can't get spi100k_ick\n");
|
|
||||||
status = PTR_ERR(spi100k->ick);
|
|
||||||
goto err;
|
|
||||||
}
|
|
||||||
|
|
||||||
spi100k->fck = devm_clk_get(&pdev->dev, "fck");
|
|
||||||
if (IS_ERR(spi100k->fck)) {
|
|
||||||
dev_dbg(&pdev->dev, "can't get spi100k_fck\n");
|
|
||||||
status = PTR_ERR(spi100k->fck);
|
|
||||||
goto err;
|
|
||||||
}
|
|
||||||
|
|
||||||
status = clk_prepare_enable(spi100k->ick);
|
|
||||||
if (status != 0) {
|
|
||||||
dev_err(&pdev->dev, "failed to enable ick: %d\n", status);
|
|
||||||
goto err;
|
|
||||||
}
|
|
||||||
|
|
||||||
status = clk_prepare_enable(spi100k->fck);
|
|
||||||
if (status != 0) {
|
|
||||||
dev_err(&pdev->dev, "failed to enable fck: %d\n", status);
|
|
||||||
goto err_ick;
|
|
||||||
}
|
|
||||||
|
|
||||||
pm_runtime_enable(&pdev->dev);
|
|
||||||
pm_runtime_set_active(&pdev->dev);
|
|
||||||
|
|
||||||
status = devm_spi_register_master(&pdev->dev, master);
|
|
||||||
if (status < 0)
|
|
||||||
goto err_fck;
|
|
||||||
|
|
||||||
return status;
|
|
||||||
|
|
||||||
err_fck:
|
|
||||||
pm_runtime_disable(&pdev->dev);
|
|
||||||
clk_disable_unprepare(spi100k->fck);
|
|
||||||
err_ick:
|
|
||||||
clk_disable_unprepare(spi100k->ick);
|
|
||||||
err:
|
|
||||||
spi_master_put(master);
|
|
||||||
return status;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int omap1_spi100k_remove(struct platform_device *pdev)
|
|
||||||
{
|
|
||||||
struct spi_master *master = platform_get_drvdata(pdev);
|
|
||||||
struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
|
|
||||||
|
|
||||||
pm_runtime_disable(&pdev->dev);
|
|
||||||
|
|
||||||
clk_disable_unprepare(spi100k->fck);
|
|
||||||
clk_disable_unprepare(spi100k->ick);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
#ifdef CONFIG_PM
|
|
||||||
static int omap1_spi100k_runtime_suspend(struct device *dev)
|
|
||||||
{
|
|
||||||
struct spi_master *master = dev_get_drvdata(dev);
|
|
||||||
struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
|
|
||||||
|
|
||||||
clk_disable_unprepare(spi100k->ick);
|
|
||||||
clk_disable_unprepare(spi100k->fck);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int omap1_spi100k_runtime_resume(struct device *dev)
|
|
||||||
{
|
|
||||||
struct spi_master *master = dev_get_drvdata(dev);
|
|
||||||
struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
|
|
||||||
int ret;
|
|
||||||
|
|
||||||
ret = clk_prepare_enable(spi100k->ick);
|
|
||||||
if (ret != 0) {
|
|
||||||
dev_err(dev, "Failed to enable ick: %d\n", ret);
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
ret = clk_prepare_enable(spi100k->fck);
|
|
||||||
if (ret != 0) {
|
|
||||||
dev_err(dev, "Failed to enable fck: %d\n", ret);
|
|
||||||
clk_disable_unprepare(spi100k->ick);
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
static const struct dev_pm_ops omap1_spi100k_pm = {
|
|
||||||
SET_RUNTIME_PM_OPS(omap1_spi100k_runtime_suspend,
|
|
||||||
omap1_spi100k_runtime_resume, NULL)
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct platform_driver omap1_spi100k_driver = {
|
|
||||||
.driver = {
|
|
||||||
.name = "omap1_spi100k",
|
|
||||||
.pm = &omap1_spi100k_pm,
|
|
||||||
},
|
|
||||||
.probe = omap1_spi100k_probe,
|
|
||||||
.remove = omap1_spi100k_remove,
|
|
||||||
};
|
|
||||||
|
|
||||||
module_platform_driver(omap1_spi100k_driver);
|
|
||||||
|
|
||||||
MODULE_DESCRIPTION("OMAP7xx SPI 100k controller driver");
|
|
||||||
MODULE_AUTHOR("Fabrice Crohas <fcrohas@gmail.com>");
|
|
||||||
MODULE_LICENSE("GPL");
|
|
||||||
Loading…
Reference in a new issue