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[POWERPC] cell: PPU Oprofile cleanup patch
This is a clean up patch that includes the following changes: -Some comments were added to clarify the code based on feedback from the community. -The write_pm_cntrl() and set_count_mode() were passed a structure element from a global variable. The argument was removed so the functions now just operate on the global directly. -The set_pm_event() function call in the cell_virtual_cntr() routine was moved to a for-loop before the for_each_cpu loop Signed-off-by: Carl Love <carll@us.ibm.com> Signed-off-by: Maynard Johnson <mpjohn@us.ibm.com> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
This commit is contained in:
parent
128b8546a8
commit
bcb63e25ed
3 changed files with 73 additions and 60 deletions
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@ -41,8 +41,12 @@
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#define PPU_CYCLES_EVENT_NUM 1 /* event number for CYCLES */
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#define PPU_CYCLES_EVENT_NUM 1 /* event number for CYCLES */
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#define CBE_COUNT_ALL_CYCLES 0x42800000 /* PPU cycle event specifier */
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#define CBE_COUNT_ALL_CYCLES 0x42800000 /* PPU cycle event specifier */
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#define NUM_THREADS 2
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#define NUM_THREADS 2 /* number of physical threads in
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#define VIRT_CNTR_SW_TIME_NS 100000000 // 0.5 seconds
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* physical processor
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*/
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#define NUM_TRACE_BUS_WORDS 4
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#define NUM_INPUT_BUS_WORDS 2
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struct pmc_cntrl_data {
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struct pmc_cntrl_data {
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unsigned long vcntr;
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unsigned long vcntr;
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@ -93,7 +97,6 @@ static struct {
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u32 pm07_cntrl[NR_PHYS_CTRS];
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u32 pm07_cntrl[NR_PHYS_CTRS];
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} pm_regs;
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} pm_regs;
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#define GET_SUB_UNIT(x) ((x & 0x0000f000) >> 12)
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#define GET_SUB_UNIT(x) ((x & 0x0000f000) >> 12)
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#define GET_BUS_WORD(x) ((x & 0x000000f0) >> 4)
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#define GET_BUS_WORD(x) ((x & 0x000000f0) >> 4)
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#define GET_BUS_TYPE(x) ((x & 0x00000300) >> 8)
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#define GET_BUS_TYPE(x) ((x & 0x00000300) >> 8)
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@ -101,7 +104,6 @@ static struct {
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#define GET_COUNT_CYCLES(x) (x & 0x00000001)
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#define GET_COUNT_CYCLES(x) (x & 0x00000001)
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#define GET_INPUT_CONTROL(x) ((x & 0x00000004) >> 2)
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#define GET_INPUT_CONTROL(x) ((x & 0x00000004) >> 2)
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static DEFINE_PER_CPU(unsigned long[NR_PHYS_CTRS], pmc_values);
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static DEFINE_PER_CPU(unsigned long[NR_PHYS_CTRS], pmc_values);
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static struct pmc_cntrl_data pmc_cntrl[NUM_THREADS][NR_PHYS_CTRS];
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static struct pmc_cntrl_data pmc_cntrl[NUM_THREADS][NR_PHYS_CTRS];
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@ -129,8 +131,8 @@ static spinlock_t virt_cntr_lock = SPIN_LOCK_UNLOCKED;
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static u32 ctr_enabled;
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static u32 ctr_enabled;
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static unsigned char trace_bus[4];
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static unsigned char trace_bus[NUM_TRACE_BUS_WORDS];
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static unsigned char input_bus[2];
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static unsigned char input_bus[NUM_INPUT_BUS_WORDS];
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/*
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/*
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* Firmware interface functions
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* Firmware interface functions
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@ -183,7 +185,8 @@ static void pm_rtas_activate_signals(u32 node, u32 count)
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for (j = 0; j < count; j++) {
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for (j = 0; j < count; j++) {
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/* fw expects physical cpu # */
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/* fw expects physical cpu # */
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pm_signal_local[j].cpu = node;
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pm_signal_local[j].cpu = node;
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pm_signal_local[j].signal_group = pm_signal[j].signal_group;
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pm_signal_local[j].signal_group
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= pm_signal[j].signal_group;
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pm_signal_local[j].bus_word = pm_signal[j].bus_word;
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pm_signal_local[j].bus_word = pm_signal[j].bus_word;
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pm_signal_local[j].sub_unit = pm_signal[j].sub_unit;
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pm_signal_local[j].sub_unit = pm_signal[j].sub_unit;
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pm_signal_local[j].bit = pm_signal[j].bit;
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pm_signal_local[j].bit = pm_signal[j].bit;
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@ -232,13 +235,21 @@ static void set_pm_event(u32 ctr, int event, u32 unit_mask)
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p->signal_group = event / 100;
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p->signal_group = event / 100;
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p->bus_word = bus_word;
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p->bus_word = bus_word;
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p->sub_unit = unit_mask & 0x0000f000;
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p->sub_unit = (unit_mask & 0x0000f000) >> 12;
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pm_regs.pm07_cntrl[ctr] = 0;
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pm_regs.pm07_cntrl[ctr] = 0;
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pm_regs.pm07_cntrl[ctr] |= PM07_CTR_COUNT_CYCLES(count_cycles);
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pm_regs.pm07_cntrl[ctr] |= PM07_CTR_COUNT_CYCLES(count_cycles);
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pm_regs.pm07_cntrl[ctr] |= PM07_CTR_POLARITY(polarity);
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pm_regs.pm07_cntrl[ctr] |= PM07_CTR_POLARITY(polarity);
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pm_regs.pm07_cntrl[ctr] |= PM07_CTR_INPUT_CONTROL(input_control);
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pm_regs.pm07_cntrl[ctr] |= PM07_CTR_INPUT_CONTROL(input_control);
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/* Some of the islands signal selection is based on 64 bit words.
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* The debug bus words are 32 bits, the input words to the performance
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* counters are defined as 32 bits. Need to convert the 64 bit island
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* specification to the appropriate 32 input bit and bus word for the
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* performance counter event selection. See the CELL Performance
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* monitoring signals manual and the Perf cntr hardware descriptions
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* for the details.
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*/
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if (input_control == 0) {
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if (input_control == 0) {
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if (signal_bit > 31) {
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if (signal_bit > 31) {
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signal_bit -= 32;
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signal_bit -= 32;
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@ -259,12 +270,12 @@ static void set_pm_event(u32 ctr, int event, u32 unit_mask)
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p->bit = signal_bit;
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p->bit = signal_bit;
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}
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}
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for (i = 0; i < 4; i++) {
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for (i = 0; i < NUM_TRACE_BUS_WORDS; i++) {
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if (bus_word & (1 << i)) {
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if (bus_word & (1 << i)) {
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pm_regs.debug_bus_control |=
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pm_regs.debug_bus_control |=
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(bus_type << (31 - (2 * i) + 1));
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(bus_type << (31 - (2 * i) + 1));
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for (j = 0; j < 2; j++) {
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for (j = 0; j < NUM_INPUT_BUS_WORDS; j++) {
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if (input_bus[j] == 0xff) {
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if (input_bus[j] == 0xff) {
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input_bus[j] = i;
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input_bus[j] = i;
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pm_regs.group_control |=
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pm_regs.group_control |=
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@ -278,52 +289,58 @@ static void set_pm_event(u32 ctr, int event, u32 unit_mask)
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;
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;
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}
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}
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static void write_pm_cntrl(int cpu, struct pm_cntrl *pm_cntrl)
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static void write_pm_cntrl(int cpu)
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{
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{
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/* Oprofile will use 32 bit counters, set bits 7:10 to 0 */
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/* Oprofile will use 32 bit counters, set bits 7:10 to 0
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* pmregs.pm_cntrl is a global
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*/
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u32 val = 0;
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u32 val = 0;
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if (pm_cntrl->enable == 1)
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if (pm_regs.pm_cntrl.enable == 1)
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val |= CBE_PM_ENABLE_PERF_MON;
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val |= CBE_PM_ENABLE_PERF_MON;
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if (pm_cntrl->stop_at_max == 1)
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if (pm_regs.pm_cntrl.stop_at_max == 1)
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val |= CBE_PM_STOP_AT_MAX;
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val |= CBE_PM_STOP_AT_MAX;
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if (pm_cntrl->trace_mode == 1)
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if (pm_regs.pm_cntrl.trace_mode == 1)
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val |= CBE_PM_TRACE_MODE_SET(pm_cntrl->trace_mode);
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val |= CBE_PM_TRACE_MODE_SET(pm_regs.pm_cntrl.trace_mode);
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if (pm_cntrl->freeze == 1)
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if (pm_regs.pm_cntrl.freeze == 1)
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val |= CBE_PM_FREEZE_ALL_CTRS;
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val |= CBE_PM_FREEZE_ALL_CTRS;
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/* Routine set_count_mode must be called previously to set
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/* Routine set_count_mode must be called previously to set
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* the count mode based on the user selection of user and kernel.
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* the count mode based on the user selection of user and kernel.
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*/
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*/
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val |= CBE_PM_COUNT_MODE_SET(pm_cntrl->count_mode);
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val |= CBE_PM_COUNT_MODE_SET(pm_regs.pm_cntrl.count_mode);
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cbe_write_pm(cpu, pm_control, val);
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cbe_write_pm(cpu, pm_control, val);
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}
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}
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static inline void
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static inline void
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set_count_mode(u32 kernel, u32 user, struct pm_cntrl *pm_cntrl)
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set_count_mode(u32 kernel, u32 user)
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{
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{
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/* The user must specify user and kernel if they want them. If
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/* The user must specify user and kernel if they want them. If
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* neither is specified, OProfile will count in hypervisor mode
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* neither is specified, OProfile will count in hypervisor mode.
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* pm_regs.pm_cntrl is a global
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*/
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*/
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if (kernel) {
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if (kernel) {
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if (user)
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if (user)
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pm_cntrl->count_mode = CBE_COUNT_ALL_MODES;
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pm_regs.pm_cntrl.count_mode = CBE_COUNT_ALL_MODES;
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else
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else
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pm_cntrl->count_mode = CBE_COUNT_SUPERVISOR_MODE;
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pm_regs.pm_cntrl.count_mode =
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CBE_COUNT_SUPERVISOR_MODE;
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} else {
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} else {
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if (user)
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if (user)
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pm_cntrl->count_mode = CBE_COUNT_PROBLEM_MODE;
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pm_regs.pm_cntrl.count_mode = CBE_COUNT_PROBLEM_MODE;
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else
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else
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pm_cntrl->count_mode = CBE_COUNT_HYPERVISOR_MODE;
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pm_regs.pm_cntrl.count_mode =
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CBE_COUNT_HYPERVISOR_MODE;
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}
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}
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}
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}
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static inline void enable_ctr(u32 cpu, u32 ctr, u32 * pm07_cntrl)
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static inline void enable_ctr(u32 cpu, u32 ctr, u32 * pm07_cntrl)
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{
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{
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pm07_cntrl[ctr] |= PM07_CTR_ENABLE(1);
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pm07_cntrl[ctr] |= CBE_PM_CTR_ENABLE;
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cbe_write_pm07_control(cpu, ctr, pm07_cntrl[ctr]);
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cbe_write_pm07_control(cpu, ctr, pm07_cntrl[ctr]);
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}
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}
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@ -365,6 +382,14 @@ static void cell_virtual_cntr(unsigned long data)
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hdw_thread = 1 ^ hdw_thread;
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hdw_thread = 1 ^ hdw_thread;
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next_hdw_thread = hdw_thread;
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next_hdw_thread = hdw_thread;
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for (i = 0; i < num_counters; i++)
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/* There are some per thread events. Must do the
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* set event, for the thread that is being started
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*/
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set_pm_event(i,
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pmc_cntrl[next_hdw_thread][i].evnts,
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pmc_cntrl[next_hdw_thread][i].masks);
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/* The following is done only once per each node, but
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/* The following is done only once per each node, but
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* we need cpu #, not node #, to pass to the cbe_xxx functions.
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* we need cpu #, not node #, to pass to the cbe_xxx functions.
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*/
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*/
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== 0xFFFFFFFF)
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== 0xFFFFFFFF)
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/* If the cntr value is 0xffffffff, we must
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/* If the cntr value is 0xffffffff, we must
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* reset that to 0xfffffff0 when the current
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* reset that to 0xfffffff0 when the current
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* thread is restarted. This will generate a new
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* thread is restarted. This will generate a
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* interrupt and make sure that we never restore
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* new interrupt and make sure that we never
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* the counters to the max value. If the counters
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* restore the counters to the max value. If
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* were restored to the max value, they do not
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* the counters were restored to the max value,
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* increment and no interrupts are generated. Hence
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* they do not increment and no interrupts are
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* no more samples will be collected on that cpu.
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* generated. Hence no more samples will be
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* collected on that cpu.
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*/
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*/
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cbe_write_ctr(cpu, i, 0xFFFFFFF0);
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cbe_write_ctr(cpu, i, 0xFFFFFFF0);
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else
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else
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* Must do the set event, enable_cntr
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* Must do the set event, enable_cntr
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* for each cpu.
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* for each cpu.
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*/
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*/
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set_pm_event(i,
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pmc_cntrl[next_hdw_thread][i].evnts,
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pmc_cntrl[next_hdw_thread][i].masks);
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enable_ctr(cpu, i,
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enable_ctr(cpu, i,
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pm_regs.pm07_cntrl);
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pm_regs.pm07_cntrl);
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} else {
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} else {
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@ -465,8 +488,7 @@ cell_reg_setup(struct op_counter_config *ctr,
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pm_regs.pm_cntrl.trace_mode = 0;
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pm_regs.pm_cntrl.trace_mode = 0;
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pm_regs.pm_cntrl.freeze = 1;
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pm_regs.pm_cntrl.freeze = 1;
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set_count_mode(sys->enable_kernel, sys->enable_user,
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set_count_mode(sys->enable_kernel, sys->enable_user);
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&pm_regs.pm_cntrl);
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/* Setup the thread 0 events */
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/* Setup the thread 0 events */
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for (i = 0; i < num_ctrs; ++i) {
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for (i = 0; i < num_ctrs; ++i) {
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pmc_cntrl[1][i].vcntr = i;
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pmc_cntrl[1][i].vcntr = i;
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}
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}
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for (i = 0; i < 4; i++)
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for (i = 0; i < NUM_TRACE_BUS_WORDS; i++)
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trace_bus[i] = 0xff;
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trace_bus[i] = 0xff;
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for (i = 0; i < 2; i++)
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for (i = 0; i < NUM_INPUT_BUS_WORDS; i++)
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input_bus[i] = 0xff;
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input_bus[i] = 0xff;
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/* Our counters count up, and "count" refers to
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/* Our counters count up, and "count" refers to
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cbe_write_pm(cpu, pm_start_stop, 0);
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cbe_write_pm(cpu, pm_start_stop, 0);
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cbe_write_pm(cpu, group_control, pm_regs.group_control);
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cbe_write_pm(cpu, group_control, pm_regs.group_control);
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cbe_write_pm(cpu, debug_bus_control, pm_regs.debug_bus_control);
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cbe_write_pm(cpu, debug_bus_control, pm_regs.debug_bus_control);
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write_pm_cntrl(cpu, &pm_regs.pm_cntrl);
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write_pm_cntrl(cpu);
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for (i = 0; i < num_counters; ++i) {
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for (i = 0; i < num_counters; ++i) {
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if (ctr_enabled & (1 << i)) {
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if (ctr_enabled & (1 << i)) {
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@ -602,7 +624,7 @@ static void cell_global_start(struct op_counter_config *ctr)
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}
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}
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}
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}
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cbe_clear_pm_interrupts(cpu);
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cbe_get_and_clear_pm_interrupts(cpu);
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cbe_enable_pm_interrupts(cpu, hdw_thread, interrupt_mask);
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cbe_enable_pm_interrupts(cpu, hdw_thread, interrupt_mask);
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cbe_enable_pm(cpu);
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cbe_enable_pm(cpu);
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}
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}
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@ -672,7 +694,7 @@ cell_handle_interrupt(struct pt_regs *regs, struct op_counter_config *ctr)
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cbe_disable_pm(cpu);
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cbe_disable_pm(cpu);
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interrupt_mask = cbe_clear_pm_interrupts(cpu);
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interrupt_mask = cbe_get_and_clear_pm_interrupts(cpu);
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/* If the interrupt mask has been cleared, then the virt cntr
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/* If the interrupt mask has been cleared, then the virt cntr
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* has cleared the interrupt. When the thread that generated
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* has cleared the interrupt. When the thread that generated
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@ -345,18 +345,12 @@ EXPORT_SYMBOL_GPL(cbe_read_trace_buffer);
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* Enabling/disabling interrupts for the entire performance monitoring unit.
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* Enabling/disabling interrupts for the entire performance monitoring unit.
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*/
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*/
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u32 cbe_query_pm_interrupts(u32 cpu)
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u32 cbe_get_and_clear_pm_interrupts(u32 cpu)
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{
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return cbe_read_pm(cpu, pm_status);
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}
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EXPORT_SYMBOL_GPL(cbe_query_pm_interrupts);
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u32 cbe_clear_pm_interrupts(u32 cpu)
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{
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{
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/* Reading pm_status clears the interrupt bits. */
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/* Reading pm_status clears the interrupt bits. */
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return cbe_query_pm_interrupts(cpu);
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return cbe_read_pm(cpu, pm_status);
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}
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}
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EXPORT_SYMBOL_GPL(cbe_clear_pm_interrupts);
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EXPORT_SYMBOL_GPL(cbe_get_and_clear_pm_interrupts);
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void cbe_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask)
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void cbe_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask)
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{
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{
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@ -371,7 +365,7 @@ EXPORT_SYMBOL_GPL(cbe_enable_pm_interrupts);
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void cbe_disable_pm_interrupts(u32 cpu)
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void cbe_disable_pm_interrupts(u32 cpu)
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{
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{
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cbe_clear_pm_interrupts(cpu);
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cbe_get_and_clear_pm_interrupts(cpu);
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||||||
cbe_write_pm(cpu, pm_status, 0);
|
cbe_write_pm(cpu, pm_status, 0);
|
||||||
}
|
}
|
||||||
EXPORT_SYMBOL_GPL(cbe_disable_pm_interrupts);
|
EXPORT_SYMBOL_GPL(cbe_disable_pm_interrupts);
|
||||||
|
|
|
@ -53,6 +53,11 @@
|
||||||
#define CBE_PM_CTR_POLARITY 0x01000000
|
#define CBE_PM_CTR_POLARITY 0x01000000
|
||||||
#define CBE_PM_CTR_COUNT_CYCLES 0x00800000
|
#define CBE_PM_CTR_COUNT_CYCLES 0x00800000
|
||||||
#define CBE_PM_CTR_ENABLE 0x00400000
|
#define CBE_PM_CTR_ENABLE 0x00400000
|
||||||
|
#define PM07_CTR_INPUT_MUX(x) (((x) & 0x3F) << 26)
|
||||||
|
#define PM07_CTR_INPUT_CONTROL(x) (((x) & 1) << 25)
|
||||||
|
#define PM07_CTR_POLARITY(x) (((x) & 1) << 24)
|
||||||
|
#define PM07_CTR_COUNT_CYCLES(x) (((x) & 1) << 23)
|
||||||
|
#define PM07_CTR_ENABLE(x) (((x) & 1) << 22)
|
||||||
|
|
||||||
/* Macros for the pm_status register. */
|
/* Macros for the pm_status register. */
|
||||||
#define CBE_PM_CTR_OVERFLOW_INTR(ctr) (1 << (31 - ((ctr) & 7)))
|
#define CBE_PM_CTR_OVERFLOW_INTR(ctr) (1 << (31 - ((ctr) & 7)))
|
||||||
|
@ -89,8 +94,7 @@ extern void cbe_read_trace_buffer(u32 cpu, u64 *buf);
|
||||||
|
|
||||||
extern void cbe_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask);
|
extern void cbe_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask);
|
||||||
extern void cbe_disable_pm_interrupts(u32 cpu);
|
extern void cbe_disable_pm_interrupts(u32 cpu);
|
||||||
extern u32 cbe_query_pm_interrupts(u32 cpu);
|
extern u32 cbe_get_and_clear_pm_interrupts(u32 cpu);
|
||||||
extern u32 cbe_clear_pm_interrupts(u32 cpu);
|
|
||||||
extern void cbe_sync_irq(int node);
|
extern void cbe_sync_irq(int node);
|
||||||
|
|
||||||
/* Utility functions, macros */
|
/* Utility functions, macros */
|
||||||
|
@ -103,11 +107,4 @@ extern u32 cbe_get_hw_thread_id(int cpu);
|
||||||
#define CBE_COUNT_PROBLEM_MODE 2
|
#define CBE_COUNT_PROBLEM_MODE 2
|
||||||
#define CBE_COUNT_ALL_MODES 3
|
#define CBE_COUNT_ALL_MODES 3
|
||||||
|
|
||||||
/* Macros for the pm07_control registers. */
|
|
||||||
#define PM07_CTR_INPUT_MUX(x) (((x) & 0x3F) << 26)
|
|
||||||
#define PM07_CTR_INPUT_CONTROL(x) (((x) & 1) << 25)
|
|
||||||
#define PM07_CTR_POLARITY(x) (((x) & 1) << 24)
|
|
||||||
#define PM07_CTR_COUNT_CYCLES(x) (((x) & 1) << 23)
|
|
||||||
#define PM07_CTR_ENABLE(x) (((x) & 1) << 22)
|
|
||||||
|
|
||||||
#endif /* __ASM_CELL_PMU_H__ */
|
#endif /* __ASM_CELL_PMU_H__ */
|
||||||
|
|
Loading…
Reference in a new issue