From fe6d5b8de04780e7ec27037b836324b59fade45b Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Fri, 19 Aug 2022 00:06:28 +0200 Subject: [PATCH 001/261] arm64: dts: qcom: ipq8074: add A53 PLL node Add the required node for A53 PLL which will be used to provide the CPU clock via APCS for APSS scaling. Signed-off-by: Robert Marko Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220818220628.339366-9-robimarko@gmail.com --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index a47acf9bdf24..51815d0861d4 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -674,6 +674,14 @@ apcs_glb: mailbox@b111000 { #mbox-cells = <1>; }; + a53pll: clock@b116000 { + compatible = "qcom,ipq8074-a53pll"; + reg = <0x0b116000 0x40>; + #clock-cells = <0>; + clocks = <&xo>; + clock-names = "xo"; + }; + timer@b120000 { #address-cells = <1>; #size-cells = <1>; From 372698e8df2619bf76b047c9a600d1f659d7868b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 26 Sep 2022 11:21:03 +0200 Subject: [PATCH 002/261] arm64: dts: qcom: align RPM regulators node name with bindings Node names should be generic and new DT schema expects RPM regulators node to be just "regulators". Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220926092104.111449-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 4 ++-- arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts | 2 +- arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts | 4 ++-- arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts | 2 +- arch/arm64/boot/dts/qcom/msm8996-xiaomi-natrium.dts | 2 +- arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts | 2 +- arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts | 4 ++-- arch/arm64/boot/dts/qcom/msm8998-mtp.dts | 4 ++-- arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 2 +- arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts | 4 ++-- arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts | 2 +- arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts | 4 ++-- 22 files changed, 35 insertions(+), 35 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index 5cdc7ac1a9c0..7f10372178d6 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -751,7 +751,7 @@ vdd_gfx: s2@1700 { }; &rpm_requests { - pm8994-regulators { + regulators-0 { compatible = "qcom,rpm-pm8994-regulators"; vdd_s1-supply = <&vph_pwr>; @@ -963,7 +963,7 @@ vreg_lvs2a_1p8: lvs2 { }; }; - pmi8994-regulators { + regulators-1 { compatible = "qcom,rpm-pmi8994-regulators"; vdd_s1-supply = <&vph_pwr>; diff --git a/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts b/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts index 92f264891d84..3ea793b20e7f 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts @@ -162,7 +162,7 @@ cd { }; &rpm_requests { - pm8994-regulators { + regulators-0 { compatible = "qcom,rpm-pm8994-regulators"; vdd_s1-supply = <&vph_pwr>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi index 539823b2c36e..8cac23b5240c 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi @@ -47,7 +47,7 @@ &usb_hs_phy { }; &rpm_requests { - smd_rpm_regulators: pm8916-regulators { + smd_rpm_regulators: regulators { compatible = "qcom,rpm-pm8916-regulators"; /* pm8916_s1 is managed by rpmpd (MSM8916_VDDCX) */ diff --git a/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi index 71e373b11de9..aef92f3c49da 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi @@ -58,7 +58,7 @@ &blsp1_uart2 { }; &rpm_requests { - pm8994_regulators: pm8994-regulators { + pm8994_regulators: regulators-0 { compatible = "qcom,rpm-pm8994-regulators"; vdd_l1-supply = <&pm8994_s1>; @@ -281,7 +281,7 @@ pm8994_l32: l32 { }; }; - pmi8994_regulators: pmi8994-regulators { + pmi8994_regulators: regulators-1 { compatible = "qcom,rpm-pmi8994-regulators"; vdd_s1-supply = <&vph_pwr>; diff --git a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts index c4e87d0aec42..b242c272d2af 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts +++ b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts @@ -153,7 +153,7 @@ VDD_APC1: s11 { }; &rpm_requests { - pm8994-regulators { + regulators-0 { compatible = "qcom,rpm-pm8994-regulators"; vdd_l1-supply = <&pm8994_s7>; @@ -363,7 +363,7 @@ pm8994_l32: l32 { pm8994_lvs2: lvs2 {}; }; - pmi8994_regulators: pmi8994-regulators { + pmi8994_regulators: regulators-1 { compatible = "qcom,rpm-pmi8994-regulators"; vdd_s1-supply = <&vph_pwr>; vdd_bst_byp-supply = <&vph_pwr>; diff --git a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi index f9d8bd09e074..d8d732ec1b73 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi @@ -551,7 +551,7 @@ vdd_gfx: s2@1700 { &rpm_requests { /* These values were taken from the original firmware ACPI tables */ - pm8994_regulators: pm8994-regulators { + pm8994_regulators: regulators-0 { compatible = "qcom,rpm-pm8994-regulators"; vdd_s1-supply = <&vph_pwr>; @@ -835,7 +835,7 @@ vreg_l32a_1p8: l32 { vreg_lvs2a_1p8: lvs2 { }; }; - pmi8994_regulators: pmi8994-regulators { + pmi8994_regulators: regulators-1 { compatible = "qcom,rpm-pmi8994-regulators"; vdd_s1-supply = <&vph_pwr>; diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi index ff60b7004d26..0c2680ff22a4 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi @@ -186,7 +186,7 @@ vdd_gfx: s2@1700 { &rpm_requests { /* PMI8994 should probe first, because pmi8994_bby supplies some of PM8994's regulators */ - pmi8994_regulators: pmi8994-regulators { + pmi8994_regulators: regulators-0 { compatible = "qcom,rpm-pmi8994-regulators"; vdd_s1-supply = <&vph_pwr>; @@ -205,7 +205,7 @@ pmi8994_bby: boost-bypass { }; }; - pm8994_regulators: pm8994-regulators { + pm8994_regulators: regulators-1 { compatible = "qcom,rpm-pm8994-regulators"; vdd_s3-supply = <&vph_pwr>; diff --git a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi index ca7c8d2e1d3d..de61c3c94903 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi @@ -629,7 +629,7 @@ &pmi8994_wled { }; &rpm_requests { - pm8994-regulators { + regulators-0 { compatible = "qcom,rpm-pm8994-regulators"; vdd_s1-supply = <&vph_pwr>; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi index 77819186086a..78a1977d0593 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi @@ -413,7 +413,7 @@ &wcd9335 { }; &rpm_requests { - pm8994-regulators { + regulators-0 { compatible = "qcom,rpm-pm8994-regulators"; vdd_s1-supply = <&vph_pwr>; @@ -598,7 +598,7 @@ vreg_lvs2a_1p8: lvs2 { }; }; - pmi8994-regulators { + regulators-1 { compatible = "qcom,rpm-pmi8994-regulators"; vdd_s1-supply = <&vph_pwr>; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts index 4e5264f4116a..c8e84a934678 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts @@ -219,7 +219,7 @@ &venus { }; &rpm_requests { - pm8994-regulators { + regulators-0 { vreg_l17a_2p8: l17 { regulator-name = "vreg_l17a_2p8"; regulator-min-microvolt = <2500000>; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-natrium.dts b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-natrium.dts index ff4673ee9e81..7526f8f473b5 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-natrium.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-natrium.dts @@ -164,7 +164,7 @@ &venus { }; &rpm_requests { - pm8994-regulators { + regulators-0 { vreg_l3a_0p875: l3 { regulator-name = "vreg_l3a_0p875"; regulator-min-microvolt = <850000>; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts index 79be5fb1295b..b751cbbf1a23 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts @@ -216,7 +216,7 @@ &venus { }; &rpm_requests { - pm8994-regulators { + regulators-0 { vreg_l3a_0p875: l3 { regulator-name = "vreg_l3a_0p875"; regulator-min-microvolt = <850000>; diff --git a/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi b/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi index 7928b8197474..63413e39572c 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi @@ -137,7 +137,7 @@ &qusb2phy { }; &rpm_requests { - pm8998-regulators { + regulators-0 { compatible = "qcom,rpm-pm8998-regulators"; vdd_s1-supply = <&vph_pwr>; diff --git a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts index 429ba57e20f7..a7a79ddd3bea 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts @@ -390,7 +390,7 @@ &replicator1 { }; &rpm_requests { - pm8998-regulators { + regulators-0 { compatible = "qcom,rpm-pm8998-regulators"; vdd_s1-supply = <&vph_pwr>; @@ -588,7 +588,7 @@ vreg_lvs2a_1p8: lvs2 { }; - pmi8998-regulators { + regulators-1 { compatible = "qcom,rpm-pmi8998-regulators"; vdd_bob-supply = <&vph_pwr>; diff --git a/arch/arm64/boot/dts/qcom/msm8998-mtp.dts b/arch/arm64/boot/dts/qcom/msm8998-mtp.dts index a3ca58100aee..abea3ffa0094 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-mtp.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-mtp.dts @@ -168,7 +168,7 @@ &replicator1 { }; &rpm_requests { - pm8998-regulators { + regulators-0 { compatible = "qcom,rpm-pm8998-regulators"; vdd_s1-supply = <&vph_pwr>; @@ -366,7 +366,7 @@ vreg_lvs2a_1p8: lvs2 { }; - pmi8998-regulators { + regulators-1 { compatible = "qcom,rpm-pmi8998-regulators"; vdd_bob-supply = <&vph_pwr>; diff --git a/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi index 62bda23791bb..3af6deed2e86 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi @@ -288,7 +288,7 @@ &qusb2phy { }; &rpm_requests { - pm8998-regulators { + regulators-0 { compatible = "qcom,rpm-pm8998-regulators"; vdd_s1-supply = <&vph_pwr>; @@ -477,7 +477,7 @@ vreg_l28_3p0: l28 { vreg_lvs2a_1p8: lvs2 { }; }; - pmi8998-regulators { + regulators-1 { compatible = "qcom,rpm-pmi8998-regulators"; vdd_bob-supply = <&vph_pwr>; diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index d08639082247..47cd3caa6927 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -375,7 +375,7 @@ &qusb2phy { }; &rpm_requests { - pm8998-regulators { + regulators-0 { compatible = "qcom,rpm-pm8998-regulators"; vdd_s1-supply = <&vph_pwr>; @@ -538,7 +538,7 @@ vreg_l28_3p0: l28 { vreg_lvs2a_1p8: lvs2 { }; }; - pmi8998-regulators { + regulators-1 { compatible = "qcom,rpm-pmi8998-regulators"; vdd_bob-supply = <&vph_pwr>; diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index 1678ef0f8684..dbbe1653718b 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -125,7 +125,7 @@ &remoteproc_wcss { }; &rpm_requests { - pms405-regulators { + regulators { compatible = "qcom,rpm-pms405-regulators"; vdd_s1-supply = <&vph_pwr>; diff --git a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts index 28050bc5f081..f62a74f0e8f0 100644 --- a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts +++ b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts @@ -231,7 +231,7 @@ &qusb2phy1 { }; &rpm_requests { - pm660-regulators { + regulators-0 { compatible = "qcom,rpm-pm660-regulators"; vdd_s1-supply = <&vph_pwr>; @@ -313,7 +313,7 @@ vreg_l19a_3p3: l19 { }; }; - pm660l-regulators { + regulators-1 { compatible = "qcom,rpm-pm660l-regulators"; vdd_s1-supply = <&vph_pwr>; diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi index 09c07800793a..f9e1d599466a 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi @@ -260,7 +260,7 @@ &qusb2phy0 { }; &rpm_requests { - pm660l-regulators { + regulators-0 { compatible = "qcom,rpm-pm660l-regulators"; vdd_s1-supply = <&vph_pwr>; @@ -394,7 +394,7 @@ vreg_bob: bob { }; }; - pm660-regulators { + regulators-1 { compatible = "qcom,rpm-pm660-regulators"; vdd_s1-supply = <&vph_pwr>; diff --git a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts index 891e314bc782..c238fba2fe7c 100644 --- a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts +++ b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts @@ -69,7 +69,7 @@ &sdhc_2 { }; &rpm_requests { - pm8953-regulators { + regulators { compatible = "qcom,rpm-pm8953-regulators"; vdd_l1-supply = <&pm8953_s3>; diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index a3559f6e34a5..fea2c3e416e5 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -111,7 +111,7 @@ &qusb2phy0 { }; &rpm_requests { - pm660l-regulators { + regulators-0 { compatible = "qcom,rpm-pm660l-regulators"; vdd_s1-supply = <&vph_pwr>; @@ -206,7 +206,7 @@ vreg_bob: bob { }; }; - pm660-regulators { + regulators-1 { compatible = "qcom,rpm-pm660-regulators"; vdd_s1-supply = <&vph_pwr>; From aa27f316de7fbf3155ffde20a6daa4041d15ac5e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 10 Sep 2022 11:14:14 +0200 Subject: [PATCH 003/261] arm64: dts: qcom: sdm630: align APR services node names with dtschema DT schema expects APR services node names to be "service": qcom/sdm850-lenovo-yoga-c630.dtb: remoteproc-adsp: glink-edge:apr: 'apr-service@3', 'apr-service@4', 'apr-service@7', 'apr-service@8', 'qcom,glink-channels', 'qcom,intents' do not match any of the regexes: '^service@[1-9a-d]$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Srinivas Kandagatla Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220910091428.50418-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index b51b85f583e5..bff80e795dad 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -2224,12 +2224,12 @@ apr { #address-cells = <1>; #size-cells = <0>; - q6core { + service@3 { reg = ; compatible = "qcom,q6core"; }; - q6afe: apr-service@4 { + q6afe: service@4 { compatible = "qcom,q6afe"; reg = ; q6afedai: dais { @@ -2240,7 +2240,7 @@ q6afedai: dais { }; }; - q6asm: apr-service@7 { + q6asm: service@7 { compatible = "qcom,q6asm"; reg = ; q6asmdai: dais { @@ -2252,7 +2252,7 @@ q6asmdai: dais { }; }; - q6adm: apr-service@8 { + q6adm: service@8 { compatible = "qcom,q6adm"; reg = ; q6routing: routing { From a3692a5edc5681d47fede71efeeaa065ebcad8d9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 10 Sep 2022 11:14:15 +0200 Subject: [PATCH 004/261] arm64: dts: qcom: sdm845: align APR services node names with dtschema DT schema expects APR services node names to be "service": qcom/sdm630-sony-xperia-nile-voyager.dtb: remoteproc@15700000: glink-edge:apr:service@4: 'dais' does not match any of the regexes: '^.*@[0-9a-f]+$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Srinivas Kandagatla Tested-by: Steev Klimaszewski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220910091428.50418-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index d761da47220d..0387e9b86211 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -767,13 +767,13 @@ apr { #size-cells = <0>; qcom,intents = <512 20>; - apr-service@3 { + service@3 { reg = ; compatible = "qcom,q6core"; qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; }; - q6afe: apr-service@4 { + q6afe: service@4 { compatible = "qcom,q6afe"; reg = ; qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; @@ -785,7 +785,7 @@ q6afedai: dais { }; }; - q6asm: apr-service@7 { + q6asm: service@7 { compatible = "qcom,q6asm"; reg = ; qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; @@ -798,7 +798,7 @@ q6asmdai: dais { }; }; - q6adm: apr-service@8 { + q6adm: service@8 { compatible = "qcom,q6adm"; reg = ; qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; From a22609bf9fee17f9045b5b1847f2585200cd1920 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 10 Sep 2022 11:14:16 +0200 Subject: [PATCH 005/261] arm64: dts: qcom: sm8250: align APR services node names with dtschema DT schema expects APR services node names to be "service": qcom/sm8250-sony-xperia-edo-pdx203.dtb: remoteproc@17300000: glink-edge:apr:service@7: 'dais' does not match any of the regexes: '^.*@[0-9a-f]+$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Srinivas Kandagatla Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220910091428.50418-4-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index a5b62cadb129..c77247fe7575 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -4790,13 +4790,13 @@ apr { #address-cells = <1>; #size-cells = <0>; - apr-service@3 { + service@3 { reg = ; compatible = "qcom,q6core"; qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; }; - q6afe: apr-service@4 { + q6afe: service@4 { compatible = "qcom,q6afe"; reg = ; qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; @@ -4813,7 +4813,7 @@ q6afecc: cc { }; }; - q6asm: apr-service@7 { + q6asm: service@7 { compatible = "qcom,q6asm"; reg = ; qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; @@ -4826,7 +4826,7 @@ q6asmdai: dais { }; }; - q6adm: apr-service@8 { + q6adm: service@8 { compatible = "qcom,q6adm"; reg = ; qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; From c05b95d3286734c83e384240eb41d9867ce11027 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 10 Sep 2022 11:14:17 +0200 Subject: [PATCH 006/261] arm64: dts: qcom: msm8996: fix APR services nodes DT schema expects APR services node names to be "service" and to have an unit address (as it has a "reg" property): qcom/msm8996-xiaomi-gemini.dtb: apr: 'power-domains', 'q6adm', 'q6afe', 'q6asm', 'qcom,smd-channels' do not match any of the regexes: '^service@[1-9a-d]$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Srinivas Kandagatla Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220910091428.50418-5-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index c0a2baffa49d..add9c0077697 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -3393,12 +3393,12 @@ apr { #address-cells = <1>; #size-cells = <0>; - q6core { + service@3 { reg = ; compatible = "qcom,q6core"; }; - q6afe: q6afe { + q6afe: service@4 { compatible = "qcom,q6afe"; reg = ; q6afedai: dais { @@ -3412,7 +3412,7 @@ hdmi@1 { }; }; - q6asm: q6asm { + q6asm: service@7 { compatible = "qcom,q6asm"; reg = ; q6asmdai: dais { @@ -3424,7 +3424,7 @@ q6asmdai: dais { }; }; - q6adm: q6adm { + q6adm: service@8 { compatible = "qcom,q6adm"; reg = ; q6routing: routing { From 074240974e08a50faf434fa61c8bb7859871c774 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 10 Sep 2022 11:14:18 +0200 Subject: [PATCH 007/261] arm64: dts: qcom: sdm845: align dai node names with dtschema DT schema expects DAI node names to be "dai": qcom/sdm845-xiaomi-beryllium.dtb: dais: 'qi2s@22' does not match any of the regexes: '^dai@[0-9]+$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Srinivas Kandagatla Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220910091428.50418-6-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 2 +- arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts | 2 +- arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 132417e2d11e..2110a5893149 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -651,7 +651,7 @@ led@5 { /* QUAT I2S Uses 4 I2S SD Lines for audio on LT9611 HDMI Bridge */ &q6afedai { - qi2s@22 { + dai@22 { reg = ; qcom,sd-lines = <0 1 2 3>; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts index 0f470cf1ed1c..68e2a07a01dc 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts @@ -338,7 +338,7 @@ resin { /* QUAT I2S Uses 1 I2S SD Line for audio on TAS2559/60 amplifiers */ &q6afedai { - qi2s@22 { + dai@22 { reg = ; qcom,sd-lines = <0>; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts index afc17e4d403f..4f6f1ce7286c 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts @@ -544,8 +544,8 @@ resin { }; &q6afedai { - qi2s@22 { - reg = <22>; + dai@22 { + reg = ; qcom,sd-lines = <0>; }; }; From 6b401d49395c3fbb082e84c1df3ad77495876c18 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 10 Sep 2022 11:14:19 +0200 Subject: [PATCH 008/261] arm64: dts: qcom: msm8996: align dai node names with dtschema DT schema expects DAI node names to be "dai": qcom/msm8996-mtp.dtb: dais: 'hdmi@1' does not match any of the regexes: '^dai@[0-9]+$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Srinivas Kandagatla Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220910091428.50418-7-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index add9c0077697..ffa5177af7af 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -3406,7 +3406,7 @@ q6afedai: dais { #address-cells = <1>; #size-cells = <0>; #sound-dai-cells = <1>; - hdmi@1 { + dai@1 { reg = <1>; }; }; From cf4a15e409ff1287506fac51c343821d846fc1bc Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 10 Sep 2022 11:14:20 +0200 Subject: [PATCH 009/261] arm64: dts: qcom: qrb5165-rb5: align dai node names with dtschema DT schema expects DAI node names to be "dai": qcom/qrb5165-rb5.dtb: dais: 'qi2s@16', 'qi2s@20' do not match any of the regexes: '^dai@[0-9]+$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Srinivas Kandagatla Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220910091428.50418-8-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index bf8077a1cf9a..d39ca3671477 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -867,7 +867,7 @@ &qupv3_id_2 { }; &q6afedai { - qi2s@16 { + dai@16 { reg = ; qcom,sd-lines = <0 1 2 3>; }; @@ -875,7 +875,7 @@ qi2s@16 { /* TERT I2S Uses 1 I2S SD Lines for audio on LT9611 HDMI Bridge */ &q6afedai { - qi2s@20 { + dai@20 { reg = ; qcom,sd-lines = <0>; }; From e0b6c1ff512db643050e4a09020d7c0b69c82807 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 10 Sep 2022 11:14:21 +0200 Subject: [PATCH 010/261] arm64: dts: qcom: sm8250: use generic name for LPASS clock controller The node names should be generic according to Devicetree specification, so use "clock-controller" instead of "cc". The bindings so far did not define this name (as child of APR service). Signed-off-by: Krzysztof Kozlowski Reviewed-by: Srinivas Kandagatla Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220910091428.50418-9-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index c77247fe7575..8a5edcb9eca6 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -4807,7 +4807,7 @@ q6afedai: dais { #sound-dai-cells = <1>; }; - q6afecc: cc { + q6afecc: clock-controller { compatible = "qcom,q6afe-clocks"; #clock-cells = <2>; }; From 028fe09cda0a0d568e6a7d65b0336d32600b480c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 6 Oct 2022 16:45:17 +0200 Subject: [PATCH 011/261] arm64: dts: qcom: sm8150: align TLMM pin configuration with DT schema DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221006144518.256956-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 60 ++- .../dts/qcom/sm8150-microsoft-surface-duo.dts | 2 +- arch/arm64/boot/dts/qcom/sm8150.dtsi | 376 ++++++------------ 3 files changed, 157 insertions(+), 281 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts index 87ab0e1ecd16..06d0b6edd48a 100644 --- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts @@ -477,26 +477,26 @@ &pcie1_phy { &tlmm { gpio-reserved-ranges = <0 4>; - sdc2_on: sdc2_on { - clk { + sdc2_on: sdc2-on-state { + clk-pins { pins = "sdc2_clk"; bias-disable; /* No pull */ drive-strength = <16>; /* 16 MA */ }; - cmd { + cmd-pins { pins = "sdc2_cmd"; bias-pull-up; /* pull up */ drive-strength = <16>; /* 16 MA */ }; - data { + data-pins { pins = "sdc2_data"; bias-pull-up; /* pull up */ drive-strength = <16>; /* 16 MA */ }; - sd-cd { + sd-cd-pins { pins = "gpio96"; function = "gpio"; bias-pull-up; /* pull up */ @@ -504,26 +504,26 @@ sd-cd { }; }; - sdc2_off: sdc2_off { - clk { + sdc2_off: sdc2-off-state { + clk-pins { pins = "sdc2_clk"; bias-disable; /* No pull */ drive-strength = <2>; /* 2 MA */ }; - cmd { + cmd-pins { pins = "sdc2_cmd"; bias-pull-up; /* pull up */ drive-strength = <2>; /* 2 MA */ }; - data { + data-pins { pins = "sdc2_data"; bias-pull-up; /* pull up */ drive-strength = <2>; /* 2 MA */ }; - sd-cd { + sd-cd-pins { pins = "gpio96"; function = "gpio"; bias-pull-up; /* pull up */ @@ -531,66 +531,62 @@ sd-cd { }; }; - usb2phy_ac_en1_default: usb2phy_ac_en1_default { - mux { - pins = "gpio113"; - function = "usb2phy_ac"; - bias-disable; - drive-strength = <2>; - }; + usb2phy_ac_en1_default: usb2phy-ac-en1-default-state { + pins = "gpio113"; + function = "usb2phy_ac"; + bias-disable; + drive-strength = <2>; }; - usb2phy_ac_en2_default: usb2phy_ac_en2_default { - mux { - pins = "gpio123"; - function = "usb2phy_ac"; - bias-disable; - drive-strength = <2>; - }; + usb2phy_ac_en2_default: usb2phy-ac-en2-default-state { + pins = "gpio123"; + function = "usb2phy_ac"; + bias-disable; + drive-strength = <2>; }; - ethernet_defaults: ethernet-defaults { - mdc { + ethernet_defaults: ethernet-defaults-state { + mdc-pins { pins = "gpio7"; function = "rgmii"; bias-pull-up; }; - mdio { + mdio-pins { pins = "gpio59"; function = "rgmii"; bias-pull-up; }; - rgmii-rx { + rgmii-rx-pins { pins = "gpio117", "gpio118", "gpio119", "gpio120", "gpio115", "gpio116"; function = "rgmii"; bias-disable; drive-strength = <2>; }; - rgmii-tx { + rgmii-tx-pins { pins = "gpio122", "gpio4", "gpio5", "gpio6", "gpio114", "gpio121"; function = "rgmii"; bias-pull-up; drive-strength = <16>; }; - phy-intr { + phy-intr-pins { pins = "gpio124"; function = "emac_phy"; bias-disable; drive-strength = <8>; }; - pps { + pps-pins { pins = "gpio81"; function = "emac_pps"; bias-disable; drive-strength = <8>; }; - phy-reset { + phy-reset-pins { pins = "gpio79"; function = "gpio"; bias-pull-up; diff --git a/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts index bb278ecac3fa..5397fba9417b 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts @@ -475,7 +475,7 @@ &pon_resin { &tlmm { gpio-reserved-ranges = <126 4>; - da7280_intr_default: da7280-intr-default { + da7280_intr_default: da7280-intr-default-state { pins = "gpio42"; function = "gpio"; bias-pull-up; diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index cef8c4f4f0ff..18195ae2d021 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -2276,422 +2276,302 @@ tlmm: pinctrl@3100000 { #interrupt-cells = <2>; wakeup-parent = <&pdc>; - qup_i2c0_default: qup-i2c0-default { - mux { - pins = "gpio0", "gpio1"; - function = "qup0"; - }; - - config { - pins = "gpio0", "gpio1"; - drive-strength = <0x02>; - bias-disable; - }; + qup_i2c0_default: qup-i2c0-default-state { + pins = "gpio0", "gpio1"; + function = "qup0"; + drive-strength = <0x02>; + bias-disable; }; - qup_spi0_default: qup-spi0-default { + qup_spi0_default: qup-spi0-default-state { pins = "gpio0", "gpio1", "gpio2", "gpio3"; function = "qup0"; drive-strength = <6>; bias-disable; }; - qup_i2c1_default: qup-i2c1-default { - mux { - pins = "gpio114", "gpio115"; - function = "qup1"; - }; - - config { - pins = "gpio114", "gpio115"; - drive-strength = <0x02>; - bias-disable; - }; + qup_i2c1_default: qup-i2c1-default-state { + pins = "gpio114", "gpio115"; + function = "qup1"; + drive-strength = <2>; + bias-disable; }; - qup_spi1_default: qup-spi1-default { + qup_spi1_default: qup-spi1-default-state { pins = "gpio114", "gpio115", "gpio116", "gpio117"; function = "qup1"; drive-strength = <6>; bias-disable; }; - qup_i2c2_default: qup-i2c2-default { - mux { - pins = "gpio126", "gpio127"; - function = "qup2"; - }; - - config { - pins = "gpio126", "gpio127"; - drive-strength = <0x02>; - bias-disable; - }; + qup_i2c2_default: qup-i2c2-default-state { + pins = "gpio126", "gpio127"; + function = "qup2"; + drive-strength = <2>; + bias-disable; }; - qup_spi2_default: qup-spi2-default { + qup_spi2_default: qup-spi2-default-state { pins = "gpio126", "gpio127", "gpio128", "gpio129"; function = "qup2"; drive-strength = <6>; bias-disable; }; - qup_i2c3_default: qup-i2c3-default { - mux { - pins = "gpio144", "gpio145"; - function = "qup3"; - }; - - config { - pins = "gpio144", "gpio145"; - drive-strength = <0x02>; - bias-disable; - }; + qup_i2c3_default: qup-i2c3-default-state { + pins = "gpio144", "gpio145"; + function = "qup3"; + drive-strength = <2>; + bias-disable; }; - qup_spi3_default: qup-spi3-default { + qup_spi3_default: qup-spi3-default-state { pins = "gpio144", "gpio145", "gpio146", "gpio147"; function = "qup3"; drive-strength = <6>; bias-disable; }; - qup_i2c4_default: qup-i2c4-default { - mux { - pins = "gpio51", "gpio52"; - function = "qup4"; - }; - - config { - pins = "gpio51", "gpio52"; - drive-strength = <0x02>; - bias-disable; - }; + qup_i2c4_default: qup-i2c4-default-state { + pins = "gpio51", "gpio52"; + function = "qup4"; + drive-strength = <2>; + bias-disable; }; - qup_spi4_default: qup-spi4-default { + qup_spi4_default: qup-spi4-default-state { pins = "gpio51", "gpio52", "gpio53", "gpio54"; function = "qup4"; drive-strength = <6>; bias-disable; }; - qup_i2c5_default: qup-i2c5-default { - mux { - pins = "gpio121", "gpio122"; - function = "qup5"; - }; - - config { - pins = "gpio121", "gpio122"; - drive-strength = <0x02>; - bias-disable; - }; + qup_i2c5_default: qup-i2c5-default-state { + pins = "gpio121", "gpio122"; + function = "qup5"; + drive-strength = <2>; + bias-disable; }; - qup_spi5_default: qup-spi5-default { + qup_spi5_default: qup-spi5-default-state { pins = "gpio119", "gpio120", "gpio121", "gpio122"; function = "qup5"; drive-strength = <6>; bias-disable; }; - qup_i2c6_default: qup-i2c6-default { - mux { - pins = "gpio6", "gpio7"; - function = "qup6"; - }; - - config { - pins = "gpio6", "gpio7"; - drive-strength = <0x02>; - bias-disable; - }; + qup_i2c6_default: qup-i2c6-default-state { + pins = "gpio6", "gpio7"; + function = "qup6"; + drive-strength = <2>; + bias-disable; }; - qup_spi6_default: qup-spi6_default { + qup_spi6_default: qup-spi6_default-state { pins = "gpio4", "gpio5", "gpio6", "gpio7"; function = "qup6"; drive-strength = <6>; bias-disable; }; - qup_i2c7_default: qup-i2c7-default { - mux { - pins = "gpio98", "gpio99"; - function = "qup7"; - }; - - config { - pins = "gpio98", "gpio99"; - drive-strength = <0x02>; - bias-disable; - }; + qup_i2c7_default: qup-i2c7-default-state { + pins = "gpio98", "gpio99"; + function = "qup7"; + drive-strength = <2>; + bias-disable; }; - qup_spi7_default: qup-spi7_default { + qup_spi7_default: qup-spi7_default-state { pins = "gpio98", "gpio99", "gpio100", "gpio101"; function = "qup7"; drive-strength = <6>; bias-disable; }; - qup_i2c8_default: qup-i2c8-default { - mux { - pins = "gpio88", "gpio89"; - function = "qup8"; - }; - - config { - pins = "gpio88", "gpio89"; - drive-strength = <0x02>; - bias-disable; - }; + qup_i2c8_default: qup-i2c8-default-state { + pins = "gpio88", "gpio89"; + function = "qup8"; + drive-strength = <2>; + bias-disable; }; - qup_spi8_default: qup-spi8-default { + qup_spi8_default: qup-spi8-default-state { pins = "gpio88", "gpio89", "gpio90", "gpio91"; function = "qup8"; drive-strength = <6>; bias-disable; }; - qup_i2c9_default: qup-i2c9-default { - mux { - pins = "gpio39", "gpio40"; - function = "qup9"; - }; - - config { - pins = "gpio39", "gpio40"; - drive-strength = <0x02>; - bias-disable; - }; + qup_i2c9_default: qup-i2c9-default-state { + pins = "gpio39", "gpio40"; + function = "qup9"; + drive-strength = <2>; + bias-disable; }; - qup_spi9_default: qup-spi9-default { + qup_spi9_default: qup-spi9-default-state { pins = "gpio39", "gpio40", "gpio41", "gpio42"; function = "qup9"; drive-strength = <6>; bias-disable; }; - qup_i2c10_default: qup-i2c10-default { - mux { - pins = "gpio9", "gpio10"; - function = "qup10"; - }; - - config { - pins = "gpio9", "gpio10"; - drive-strength = <0x02>; - bias-disable; - }; + qup_i2c10_default: qup-i2c10-default-state { + pins = "gpio9", "gpio10"; + function = "qup10"; + drive-strength = <2>; + bias-disable; }; - qup_spi10_default: qup-spi10-default { + qup_spi10_default: qup-spi10-default-state { pins = "gpio9", "gpio10", "gpio11", "gpio12"; function = "qup10"; drive-strength = <6>; bias-disable; }; - qup_i2c11_default: qup-i2c11-default { - mux { - pins = "gpio94", "gpio95"; - function = "qup11"; - }; - - config { - pins = "gpio94", "gpio95"; - drive-strength = <0x02>; - bias-disable; - }; + qup_i2c11_default: qup-i2c11-default-state { + pins = "gpio94", "gpio95"; + function = "qup11"; + drive-strength = <2>; + bias-disable; }; - qup_spi11_default: qup-spi11-default { + qup_spi11_default: qup-spi11-default-state { pins = "gpio92", "gpio93", "gpio94", "gpio95"; function = "qup11"; drive-strength = <6>; bias-disable; }; - qup_i2c12_default: qup-i2c12-default { - mux { - pins = "gpio83", "gpio84"; - function = "qup12"; - }; - - config { - pins = "gpio83", "gpio84"; - drive-strength = <0x02>; - bias-disable; - }; + qup_i2c12_default: qup-i2c12-default-state { + pins = "gpio83", "gpio84"; + function = "qup12"; + drive-strength = <2>; + bias-disable; }; - qup_spi12_default: qup-spi12-default { + qup_spi12_default: qup-spi12-default-state { pins = "gpio83", "gpio84", "gpio85", "gpio86"; function = "qup12"; drive-strength = <6>; bias-disable; }; - qup_i2c13_default: qup-i2c13-default { - mux { - pins = "gpio43", "gpio44"; - function = "qup13"; - }; - - config { - pins = "gpio43", "gpio44"; - drive-strength = <0x02>; - bias-disable; - }; + qup_i2c13_default: qup-i2c13-default-state { + pins = "gpio43", "gpio44"; + function = "qup13"; + drive-strength = <2>; + bias-disable; }; - qup_spi13_default: qup-spi13-default { + qup_spi13_default: qup-spi13-default-state { pins = "gpio43", "gpio44", "gpio45", "gpio46"; function = "qup13"; drive-strength = <6>; bias-disable; }; - qup_i2c14_default: qup-i2c14-default { - mux { - pins = "gpio47", "gpio48"; - function = "qup14"; - }; - - config { - pins = "gpio47", "gpio48"; - drive-strength = <0x02>; - bias-disable; - }; + qup_i2c14_default: qup-i2c14-default-state { + pins = "gpio47", "gpio48"; + function = "qup14"; + drive-strength = <2>; + bias-disable; }; - qup_spi14_default: qup-spi14-default { + qup_spi14_default: qup-spi14-default-state { pins = "gpio47", "gpio48", "gpio49", "gpio50"; function = "qup14"; drive-strength = <6>; bias-disable; }; - qup_i2c15_default: qup-i2c15-default { - mux { - pins = "gpio27", "gpio28"; - function = "qup15"; - }; - - config { - pins = "gpio27", "gpio28"; - drive-strength = <0x02>; - bias-disable; - }; + qup_i2c15_default: qup-i2c15-default-state { + pins = "gpio27", "gpio28"; + function = "qup15"; + drive-strength = <2>; + bias-disable; }; - qup_spi15_default: qup-spi15-default { + qup_spi15_default: qup-spi15-default-state { pins = "gpio27", "gpio28", "gpio29", "gpio30"; function = "qup15"; drive-strength = <6>; bias-disable; }; - qup_i2c16_default: qup-i2c16-default { - mux { - pins = "gpio86", "gpio85"; - function = "qup16"; - }; - - config { - pins = "gpio86", "gpio85"; - drive-strength = <0x02>; - bias-disable; - }; + qup_i2c16_default: qup-i2c16-default-state { + pins = "gpio86", "gpio85"; + function = "qup16"; + drive-strength = <2>; + bias-disable; }; - qup_spi16_default: qup-spi16-default { + qup_spi16_default: qup-spi16-default-state { pins = "gpio83", "gpio84", "gpio85", "gpio86"; function = "qup16"; drive-strength = <6>; bias-disable; }; - qup_i2c17_default: qup-i2c17-default { - mux { - pins = "gpio55", "gpio56"; - function = "qup17"; - }; - - config { - pins = "gpio55", "gpio56"; - drive-strength = <0x02>; - bias-disable; - }; + qup_i2c17_default: qup-i2c17-default-state { + pins = "gpio55", "gpio56"; + function = "qup17"; + drive-strength = <2>; + bias-disable; }; - qup_spi17_default: qup-spi17-default { + qup_spi17_default: qup-spi17-default-state { pins = "gpio55", "gpio56", "gpio57", "gpio58"; function = "qup17"; drive-strength = <6>; bias-disable; }; - qup_i2c18_default: qup-i2c18-default { - mux { - pins = "gpio23", "gpio24"; - function = "qup18"; - }; - - config { - pins = "gpio23", "gpio24"; - drive-strength = <0x02>; - bias-disable; - }; + qup_i2c18_default: qup-i2c18-default-state { + pins = "gpio23", "gpio24"; + function = "qup18"; + drive-strength = <2>; + bias-disable; }; - qup_spi18_default: qup-spi18-default { + qup_spi18_default: qup-spi18-default-state { pins = "gpio23", "gpio24", "gpio25", "gpio26"; function = "qup18"; drive-strength = <6>; bias-disable; }; - qup_i2c19_default: qup-i2c19-default { - mux { - pins = "gpio57", "gpio58"; - function = "qup19"; - }; - - config { - pins = "gpio57", "gpio58"; - drive-strength = <0x02>; - bias-disable; - }; + qup_i2c19_default: qup-i2c19-default-state { + pins = "gpio57", "gpio58"; + function = "qup19"; + drive-strength = <2>; + bias-disable; }; - qup_spi19_default: qup-spi19-default { + qup_spi19_default: qup-spi19-default-state { pins = "gpio55", "gpio56", "gpio57", "gpio58"; function = "qup19"; drive-strength = <6>; bias-disable; }; - pcie0_default_state: pcie0-default { - perst { + pcie0_default_state: pcie0-default-state { + perst-pins { pins = "gpio35"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; - clkreq { + clkreq-pins { pins = "gpio36"; function = "pci_e0"; drive-strength = <2>; bias-pull-up; }; - wake { + wake-pins { pins = "gpio37"; function = "gpio"; drive-strength = <2>; @@ -2699,22 +2579,22 @@ wake { }; }; - pcie1_default_state: pcie1-default { - perst { + pcie1_default_state: pcie1-default-state { + perst-pins { pins = "gpio102"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; - clkreq { + clkreq-pins { pins = "gpio103"; function = "pci_e1"; drive-strength = <2>; bias-pull-up; }; - wake { + wake-pins { pins = "gpio104"; function = "gpio"; drive-strength = <2>; From 4871d3c38893c8a585e3e96364b7fb91cda8322e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 6 Oct 2022 14:46:26 +0200 Subject: [PATCH 012/261] arm64: dts: qcom: ipq6018-cp01-c1: use BLSPI1 pins When BLSPI1 (originally SPI0, later renamed in commit f82c48d46852 ("arm64: dts: qcom: ipq6018: correct QUP peripheral labels")) was added, the device node lacked respective pin configuration assignment. Fixes: 5bf635621245 ("arm64: dts: ipq6018: Add a few device nodes") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Bjorn Andersson Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221006124659.217540-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts index 1ba2eca33c7b..6a716c83e5f1 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts @@ -37,6 +37,8 @@ &blsp1_i2c3 { &blsp1_spi1 { cs-select = <0>; + pinctrl-0 = <&spi_0_pins>; + pinctrl-names = "default"; status = "okay"; flash@0 { From 20afb6751739264ea41993877de93923911dfdc3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 6 Oct 2022 14:46:27 +0200 Subject: [PATCH 013/261] arm64: dts: qcom: ipq6018: align TLMM pin configuration with DT schema DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Bjorn Andersson Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221006124659.217540-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 4 ++-- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts index 6a716c83e5f1..ec999f972360 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts @@ -51,13 +51,13 @@ flash@0 { }; &tlmm { - i2c_1_pins: i2c-1-pins { + i2c_1_pins: i2c-1-state { pins = "gpio42", "gpio43"; function = "blsp2_i2c"; drive-strength = <8>; }; - spi_0_pins: spi-0-pins { + spi_0_pins: spi-0-state { pins = "gpio38", "gpio39", "gpio40", "gpio41"; function = "blsp0_spi"; drive-strength = <8>; diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index a7c7ca980a71..9b9f778090e1 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -218,14 +218,14 @@ tlmm: pinctrl@1000000 { interrupt-controller; #interrupt-cells = <2>; - serial_3_pins: serial3-pinmux { + serial_3_pins: serial3-state { pins = "gpio44", "gpio45"; function = "blsp2_uart"; drive-strength = <8>; bias-pull-down; }; - qpic_pins: qpic-pins { + qpic_pins: qpic-state { pins = "gpio1", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", "gpio10", "gpio11", From e7e24786cf904e22e0472ac9a5ad35bcbd3fb7a3 Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Sat, 1 Oct 2022 17:19:33 -0400 Subject: [PATCH 014/261] arm64: dts: qcom: add gpi-dma fallback compatible The dt schema for gpi-dma has been updated with a new fallback compatible string. Add the compatible strings to existing device trees. Signed-off-by: Richard Acayan Reviewed-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221001211934.62511-4-mailingradian@gmail.com --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 6 +++--- arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 18195ae2d021..5fa575e4425a 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -887,7 +887,7 @@ gcc: clock-controller@100000 { }; gpi_dma0: dma-controller@800000 { - compatible = "qcom,sm8150-gpi-dma"; + compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; reg = <0 0x800000 0 0x60000>; interrupts = , , @@ -1222,7 +1222,7 @@ spi7: spi@89c000 { }; gpi_dma1: dma-controller@a00000 { - compatible = "qcom,sm8150-gpi-dma"; + compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; reg = <0 0xa00000 0 0x60000>; interrupts = , , @@ -1471,7 +1471,7 @@ spi16: spi@a94000 { }; gpi_dma2: dma-controller@c00000 { - compatible = "qcom,sm8150-gpi-dma"; + compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; reg = <0 0xc00000 0 0x60000>; interrupts = , , diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 8a5edcb9eca6..98e7ff0647b8 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -936,7 +936,7 @@ rng: rng@793000 { }; gpi_dma2: dma-controller@800000 { - compatible = "qcom,sm8250-gpi-dma"; + compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; reg = <0 0x00800000 0 0x70000>; interrupts = , , @@ -1187,7 +1187,7 @@ spi19: spi@894000 { }; gpi_dma0: dma-controller@900000 { - compatible = "qcom,sm8250-gpi-dma"; + compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; reg = <0 0x00900000 0 0x70000>; interrupts = , , @@ -1505,7 +1505,7 @@ spi7: spi@99c000 { }; gpi_dma1: dma-controller@a00000 { - compatible = "qcom,sm8250-gpi-dma"; + compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; reg = <0 0x00a00000 0 0x70000>; interrupts = , , From f76361749b607d52cb8eb9a7398999ee6cf17767 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 30 Sep 2022 21:29:39 +0200 Subject: [PATCH 015/261] arm64: dts: qcom: sm8250: align TLMM pin configuration with DT schema DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. Drop also unneeded split between mux and config. Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220930192954.242546-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 12 +- arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 34 +- .../boot/dts/qcom/sm8250-sony-xperia-edo.dtsi | 16 +- arch/arm64/boot/dts/qcom/sm8250.dtsi | 556 +++++++----------- 4 files changed, 237 insertions(+), 381 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index d39ca3671477..69dda5ed7692 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -1210,33 +1210,33 @@ &tlmm { "HST_WLAN_UART_TX", "HST_WLAN_UART_RX"; - lt9611_irq_pin: lt9611-irq { + lt9611_irq_pin: lt9611-irq-state { pins = "gpio63"; function = "gpio"; bias-disable; }; - sdc2_default_state: sdc2-default { - clk { + sdc2_default_state: sdc2-default-state { + clk-pins { pins = "sdc2_clk"; bias-disable; drive-strength = <16>; }; - cmd { + cmd-pins { pins = "sdc2_cmd"; bias-pull-up; drive-strength = <10>; }; - data { + data-pins { pins = "sdc2_data"; bias-pull-up; drive-strength = <10>; }; }; - sdc2_card_det_n: sd-card-det-n { + sdc2_card_det_n: sd-card-det-n-state { pins = "gpio77"; function = "gpio"; bias-pull-up; diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index a102aa5efa32..9db6136321b4 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -799,31 +799,19 @@ wcd_tx: wcd9380-tx@0,3 { &tlmm { gpio-reserved-ranges = <28 4>, <40 4>; - wcd938x_reset_default: wcd938x_reset_default { - mux { - pins = "gpio32"; - function = "gpio"; - }; - - config { - pins = "gpio32"; - drive-strength = <16>; - output-high; - }; + wcd938x_reset_default: wcd938x-reset-default-state { + pins = "gpio32"; + function = "gpio"; + drive-strength = <16>; + output-high; }; - wcd938x_reset_sleep: wcd938x_reset_sleep { - mux { - pins = "gpio32"; - function = "gpio"; - }; - - config { - pins = "gpio32"; - drive-strength = <16>; - bias-disable; - output-low; - }; + wcd938x_reset_sleep: wcd938x-reset-sleep-state { + pins = "gpio32"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi index 549e0a2aa9fe..72162852fae7 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -582,34 +582,34 @@ &slpi { &tlmm { gpio-reserved-ranges = <40 4>, <52 4>; - sdc2_default_state: sdc2-default { - clk { + sdc2_default_state: sdc2-default-state { + clk-pins { pins = "sdc2_clk"; drive-strength = <16>; bias-disable; }; - cmd { + cmd-pins { pins = "sdc2_cmd"; drive-strength = <16>; bias-pull-up; }; - data { + data-pins { pins = "sdc2_data"; drive-strength = <16>; bias-pull-up; }; }; - mdm2ap_default: mdm2ap-default { + mdm2ap_default: mdm2ap-default-state { pins = "gpio1", "gpio3"; function = "gpio"; drive-strength = <8>; bias-disable; }; - ts_int_default: ts-int-default { + ts_int_default: ts-int-default-state { pins = "gpio39"; function = "gpio"; drive-strength = <2>; @@ -617,14 +617,14 @@ ts_int_default: ts-int-default { input-enable; }; - ap2mdm_default: ap2mdm-default { + ap2mdm_default: ap2mdm-default-state { pins = "gpio56", "gpio57"; function = "gpio"; drive-strength = <16>; bias-disable; }; - sdc2_card_det_n: sd-card-det-n { + sdc2_card_det_n: sd-card-det-n-state { pins = "gpio77"; function = "gpio"; bias-pull-up; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 98e7ff0647b8..87b75846367f 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3798,8 +3798,8 @@ tlmm: pinctrl@f100000 { gpio-ranges = <&tlmm 0 0 181>; wakeup-parent = <&pdc>; - cci0_default: cci0-default { - cci0_i2c0_default: cci0-i2c0-default { + cci0_default: cci0-default-state { + cci0_i2c0_default: cci0-i2c0-default-pins { /* SDA, SCL */ pins = "gpio101", "gpio102"; function = "cci_i2c"; @@ -3808,7 +3808,7 @@ cci0_i2c0_default: cci0-i2c0-default { drive-strength = <2>; /* 2 mA */ }; - cci0_i2c1_default: cci0-i2c1-default { + cci0_i2c1_default: cci0-i2c1-default-pins { /* SDA, SCL */ pins = "gpio103", "gpio104"; function = "cci_i2c"; @@ -3818,8 +3818,8 @@ cci0_i2c1_default: cci0-i2c1-default { }; }; - cci0_sleep: cci0-sleep { - cci0_i2c0_sleep: cci0-i2c0-sleep { + cci0_sleep: cci0-sleep-state { + cci0_i2c0_sleep: cci0-i2c0-sleep-pins { /* SDA, SCL */ pins = "gpio101", "gpio102"; function = "cci_i2c"; @@ -3828,7 +3828,7 @@ cci0_i2c0_sleep: cci0-i2c0-sleep { bias-pull-down; }; - cci0_i2c1_sleep: cci0-i2c1-sleep { + cci0_i2c1_sleep: cci0-i2c1-sleep-pins { /* SDA, SCL */ pins = "gpio103", "gpio104"; function = "cci_i2c"; @@ -3838,8 +3838,8 @@ cci0_i2c1_sleep: cci0-i2c1-sleep { }; }; - cci1_default: cci1-default { - cci1_i2c0_default: cci1-i2c0-default { + cci1_default: cci1-default-state { + cci1_i2c0_default: cci1-i2c0-default-pins { /* SDA, SCL */ pins = "gpio105","gpio106"; function = "cci_i2c"; @@ -3848,7 +3848,7 @@ cci1_i2c0_default: cci1-i2c0-default { drive-strength = <2>; /* 2 mA */ }; - cci1_i2c1_default: cci1-i2c1-default { + cci1_i2c1_default: cci1-i2c1-default-pins { /* SDA, SCL */ pins = "gpio107","gpio108"; function = "cci_i2c"; @@ -3858,8 +3858,8 @@ cci1_i2c1_default: cci1-i2c1-default { }; }; - cci1_sleep: cci1-sleep { - cci1_i2c0_sleep: cci1-i2c0-sleep { + cci1_sleep: cci1-sleep-state { + cci1_i2c0_sleep: cci1-i2c0-sleep-pins { /* SDA, SCL */ pins = "gpio105","gpio106"; function = "cci_i2c"; @@ -3868,7 +3868,7 @@ cci1_i2c0_sleep: cci1-i2c0-sleep { drive-strength = <2>; /* 2 mA */ }; - cci1_i2c1_sleep: cci1-i2c1-sleep { + cci1_i2c1_sleep: cci1-i2c1-sleep-pins { /* SDA, SCL */ pins = "gpio107","gpio108"; function = "cci_i2c"; @@ -3878,22 +3878,22 @@ cci1_i2c1_sleep: cci1-i2c1-sleep { }; }; - pri_mi2s_active: pri-mi2s-active { - sclk { + pri_mi2s_active: pri-mi2s-active-state { + sclk-pins { pins = "gpio138"; function = "mi2s0_sck"; drive-strength = <8>; bias-disable; }; - ws { + ws-pins { pins = "gpio141"; function = "mi2s0_ws"; drive-strength = <8>; output-high; }; - data0 { + data0-pins { pins = "gpio139"; function = "mi2s0_data0"; drive-strength = <8>; @@ -3901,7 +3901,7 @@ data0 { output-high; }; - data1 { + data1-pins { pins = "gpio140"; function = "mi2s0_data1"; drive-strength = <8>; @@ -3909,632 +3909,500 @@ data1 { }; }; - qup_i2c0_default: qup-i2c0-default { - mux { - pins = "gpio28", "gpio29"; - function = "qup0"; - }; - - config { - pins = "gpio28", "gpio29"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c0_default: qup-i2c0-default-state { + pins = "gpio28", "gpio29"; + function = "qup0"; + drive-strength = <2>; + bias-disable; }; - qup_i2c1_default: qup-i2c1-default { - pinmux { - pins = "gpio4", "gpio5"; - function = "qup1"; - }; - - config { - pins = "gpio4", "gpio5"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c1_default: qup-i2c1-default-state { + pins = "gpio4", "gpio5"; + function = "qup1"; + drive-strength = <2>; + bias-disable; }; - qup_i2c2_default: qup-i2c2-default { - mux { - pins = "gpio115", "gpio116"; - function = "qup2"; - }; - - config { - pins = "gpio115", "gpio116"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c2_default: qup-i2c2-default-state { + pins = "gpio115", "gpio116"; + function = "qup2"; + drive-strength = <2>; + bias-disable; }; - qup_i2c3_default: qup-i2c3-default { - mux { - pins = "gpio119", "gpio120"; - function = "qup3"; - }; - - config { - pins = "gpio119", "gpio120"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c3_default: qup-i2c3-default-state { + pins = "gpio119", "gpio120"; + function = "qup3"; + drive-strength = <2>; + bias-disable; }; - qup_i2c4_default: qup-i2c4-default { - mux { - pins = "gpio8", "gpio9"; - function = "qup4"; - }; - - config { - pins = "gpio8", "gpio9"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c4_default: qup-i2c4-default-state { + pins = "gpio8", "gpio9"; + function = "qup4"; + drive-strength = <2>; + bias-disable; }; - qup_i2c5_default: qup-i2c5-default { - mux { - pins = "gpio12", "gpio13"; - function = "qup5"; - }; - - config { - pins = "gpio12", "gpio13"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c5_default: qup-i2c5-default-state { + pins = "gpio12", "gpio13"; + function = "qup5"; + drive-strength = <2>; + bias-disable; }; - qup_i2c6_default: qup-i2c6-default { - mux { - pins = "gpio16", "gpio17"; - function = "qup6"; - }; - - config { - pins = "gpio16", "gpio17"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c6_default: qup-i2c6-default-state { + pins = "gpio16", "gpio17"; + function = "qup6"; + drive-strength = <2>; + bias-disable; }; - qup_i2c7_default: qup-i2c7-default { - mux { - pins = "gpio20", "gpio21"; - function = "qup7"; - }; - - config { - pins = "gpio20", "gpio21"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c7_default: qup-i2c7-default-state { + pins = "gpio20", "gpio21"; + function = "qup7"; + drive-strength = <2>; + bias-disable; }; - qup_i2c8_default: qup-i2c8-default { - mux { - pins = "gpio24", "gpio25"; - function = "qup8"; - }; - - config { - pins = "gpio24", "gpio25"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c8_default: qup-i2c8-default-state { + pins = "gpio24", "gpio25"; + function = "qup8"; + drive-strength = <2>; + bias-disable; }; - qup_i2c9_default: qup-i2c9-default { - mux { - pins = "gpio125", "gpio126"; - function = "qup9"; - }; - - config { - pins = "gpio125", "gpio126"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c9_default: qup-i2c9-default-state { + pins = "gpio125", "gpio126"; + function = "qup9"; + drive-strength = <2>; + bias-disable; }; - qup_i2c10_default: qup-i2c10-default { - mux { - pins = "gpio129", "gpio130"; - function = "qup10"; - }; - - config { - pins = "gpio129", "gpio130"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c10_default: qup-i2c10-default-state { + pins = "gpio129", "gpio130"; + function = "qup10"; + drive-strength = <2>; + bias-disable; }; - qup_i2c11_default: qup-i2c11-default { - mux { - pins = "gpio60", "gpio61"; - function = "qup11"; - }; - - config { - pins = "gpio60", "gpio61"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c11_default: qup-i2c11-default-state { + pins = "gpio60", "gpio61"; + function = "qup11"; + drive-strength = <2>; + bias-disable; }; - qup_i2c12_default: qup-i2c12-default { - mux { - pins = "gpio32", "gpio33"; - function = "qup12"; - }; - - config { - pins = "gpio32", "gpio33"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c12_default: qup-i2c12-default-state { + pins = "gpio32", "gpio33"; + function = "qup12"; + drive-strength = <2>; + bias-disable; }; - qup_i2c13_default: qup-i2c13-default { - mux { - pins = "gpio36", "gpio37"; - function = "qup13"; - }; - - config { - pins = "gpio36", "gpio37"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c13_default: qup-i2c13-default-state { + pins = "gpio36", "gpio37"; + function = "qup13"; + drive-strength = <2>; + bias-disable; }; - qup_i2c14_default: qup-i2c14-default { - mux { - pins = "gpio40", "gpio41"; - function = "qup14"; - }; - - config { - pins = "gpio40", "gpio41"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c14_default: qup-i2c14-default-state { + pins = "gpio40", "gpio41"; + function = "qup14"; + drive-strength = <2>; + bias-disable; }; - qup_i2c15_default: qup-i2c15-default { - mux { - pins = "gpio44", "gpio45"; - function = "qup15"; - }; - - config { - pins = "gpio44", "gpio45"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c15_default: qup-i2c15-default-state { + pins = "gpio44", "gpio45"; + function = "qup15"; + drive-strength = <2>; + bias-disable; }; - qup_i2c16_default: qup-i2c16-default { - mux { - pins = "gpio48", "gpio49"; - function = "qup16"; - }; - - config { - pins = "gpio48", "gpio49"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c16_default: qup-i2c16-default-state { + pins = "gpio48", "gpio49"; + function = "qup16"; + drive-strength = <2>; + bias-disable; }; - qup_i2c17_default: qup-i2c17-default { - mux { - pins = "gpio52", "gpio53"; - function = "qup17"; - }; - - config { - pins = "gpio52", "gpio53"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c17_default: qup-i2c17-default-state { + pins = "gpio52", "gpio53"; + function = "qup17"; + drive-strength = <2>; + bias-disable; }; - qup_i2c18_default: qup-i2c18-default { - mux { - pins = "gpio56", "gpio57"; - function = "qup18"; - }; - - config { - pins = "gpio56", "gpio57"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c18_default: qup-i2c18-default-state { + pins = "gpio56", "gpio57"; + function = "qup18"; + drive-strength = <2>; + bias-disable; }; - qup_i2c19_default: qup-i2c19-default { - mux { - pins = "gpio0", "gpio1"; - function = "qup19"; - }; - - config { - pins = "gpio0", "gpio1"; - drive-strength = <2>; - bias-disable; - }; + qup_i2c19_default: qup-i2c19-default-state { + pins = "gpio0", "gpio1"; + function = "qup19"; + drive-strength = <2>; + bias-disable; }; - qup_spi0_cs: qup-spi0-cs { + qup_spi0_cs: qup-spi0-cs-state { pins = "gpio31"; function = "qup0"; }; - qup_spi0_cs_gpio: qup-spi0-cs-gpio { + qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { pins = "gpio31"; function = "gpio"; }; - qup_spi0_data_clk: qup-spi0-data-clk { + qup_spi0_data_clk: qup-spi0-data-clk-state { pins = "gpio28", "gpio29", "gpio30"; function = "qup0"; }; - qup_spi1_cs: qup-spi1-cs { + qup_spi1_cs: qup-spi1-cs-state { pins = "gpio7"; function = "qup1"; }; - qup_spi1_cs_gpio: qup-spi1-cs-gpio { + qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { pins = "gpio7"; function = "gpio"; }; - qup_spi1_data_clk: qup-spi1-data-clk { + qup_spi1_data_clk: qup-spi1-data-clk-state { pins = "gpio4", "gpio5", "gpio6"; function = "qup1"; }; - qup_spi2_cs: qup-spi2-cs { + qup_spi2_cs: qup-spi2-cs-state { pins = "gpio118"; function = "qup2"; }; - qup_spi2_cs_gpio: qup-spi2-cs-gpio { + qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { pins = "gpio118"; function = "gpio"; }; - qup_spi2_data_clk: qup-spi2-data-clk { + qup_spi2_data_clk: qup-spi2-data-clk-state { pins = "gpio115", "gpio116", "gpio117"; function = "qup2"; }; - qup_spi3_cs: qup-spi3-cs { + qup_spi3_cs: qup-spi3-cs-state { pins = "gpio122"; function = "qup3"; }; - qup_spi3_cs_gpio: qup-spi3-cs-gpio { + qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { pins = "gpio122"; function = "gpio"; }; - qup_spi3_data_clk: qup-spi3-data-clk { + qup_spi3_data_clk: qup-spi3-data-clk-state { pins = "gpio119", "gpio120", "gpio121"; function = "qup3"; }; - qup_spi4_cs: qup-spi4-cs { + qup_spi4_cs: qup-spi4-cs-state { pins = "gpio11"; function = "qup4"; }; - qup_spi4_cs_gpio: qup-spi4-cs-gpio { + qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { pins = "gpio11"; function = "gpio"; }; - qup_spi4_data_clk: qup-spi4-data-clk { + qup_spi4_data_clk: qup-spi4-data-clk-state { pins = "gpio8", "gpio9", "gpio10"; function = "qup4"; }; - qup_spi5_cs: qup-spi5-cs { + qup_spi5_cs: qup-spi5-cs-state { pins = "gpio15"; function = "qup5"; }; - qup_spi5_cs_gpio: qup-spi5-cs-gpio { + qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { pins = "gpio15"; function = "gpio"; }; - qup_spi5_data_clk: qup-spi5-data-clk { + qup_spi5_data_clk: qup-spi5-data-clk-state { pins = "gpio12", "gpio13", "gpio14"; function = "qup5"; }; - qup_spi6_cs: qup-spi6-cs { + qup_spi6_cs: qup-spi6-cs-state { pins = "gpio19"; function = "qup6"; }; - qup_spi6_cs_gpio: qup-spi6-cs-gpio { + qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { pins = "gpio19"; function = "gpio"; }; - qup_spi6_data_clk: qup-spi6-data-clk { + qup_spi6_data_clk: qup-spi6-data-clk-state { pins = "gpio16", "gpio17", "gpio18"; function = "qup6"; }; - qup_spi7_cs: qup-spi7-cs { + qup_spi7_cs: qup-spi7-cs-state { pins = "gpio23"; function = "qup7"; }; - qup_spi7_cs_gpio: qup-spi7-cs-gpio { + qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { pins = "gpio23"; function = "gpio"; }; - qup_spi7_data_clk: qup-spi7-data-clk { + qup_spi7_data_clk: qup-spi7-data-clk-state { pins = "gpio20", "gpio21", "gpio22"; function = "qup7"; }; - qup_spi8_cs: qup-spi8-cs { + qup_spi8_cs: qup-spi8-cs-state { pins = "gpio27"; function = "qup8"; }; - qup_spi8_cs_gpio: qup-spi8-cs-gpio { + qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { pins = "gpio27"; function = "gpio"; }; - qup_spi8_data_clk: qup-spi8-data-clk { + qup_spi8_data_clk: qup-spi8-data-clk-state { pins = "gpio24", "gpio25", "gpio26"; function = "qup8"; }; - qup_spi9_cs: qup-spi9-cs { + qup_spi9_cs: qup-spi9-cs-state { pins = "gpio128"; function = "qup9"; }; - qup_spi9_cs_gpio: qup-spi9-cs-gpio { + qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { pins = "gpio128"; function = "gpio"; }; - qup_spi9_data_clk: qup-spi9-data-clk { + qup_spi9_data_clk: qup-spi9-data-clk-state { pins = "gpio125", "gpio126", "gpio127"; function = "qup9"; }; - qup_spi10_cs: qup-spi10-cs { + qup_spi10_cs: qup-spi10-cs-state { pins = "gpio132"; function = "qup10"; }; - qup_spi10_cs_gpio: qup-spi10-cs-gpio { + qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { pins = "gpio132"; function = "gpio"; }; - qup_spi10_data_clk: qup-spi10-data-clk { + qup_spi10_data_clk: qup-spi10-data-clk-state { pins = "gpio129", "gpio130", "gpio131"; function = "qup10"; }; - qup_spi11_cs: qup-spi11-cs { + qup_spi11_cs: qup-spi11-cs-state { pins = "gpio63"; function = "qup11"; }; - qup_spi11_cs_gpio: qup-spi11-cs-gpio { + qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { pins = "gpio63"; function = "gpio"; }; - qup_spi11_data_clk: qup-spi11-data-clk { + qup_spi11_data_clk: qup-spi11-data-clk-state { pins = "gpio60", "gpio61", "gpio62"; function = "qup11"; }; - qup_spi12_cs: qup-spi12-cs { + qup_spi12_cs: qup-spi12-cs-state { pins = "gpio35"; function = "qup12"; }; - qup_spi12_cs_gpio: qup-spi12-cs-gpio { + qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { pins = "gpio35"; function = "gpio"; }; - qup_spi12_data_clk: qup-spi12-data-clk { + qup_spi12_data_clk: qup-spi12-data-clk-state { pins = "gpio32", "gpio33", "gpio34"; function = "qup12"; }; - qup_spi13_cs: qup-spi13-cs { + qup_spi13_cs: qup-spi13-cs-state { pins = "gpio39"; function = "qup13"; }; - qup_spi13_cs_gpio: qup-spi13-cs-gpio { + qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { pins = "gpio39"; function = "gpio"; }; - qup_spi13_data_clk: qup-spi13-data-clk { + qup_spi13_data_clk: qup-spi13-data-clk-state { pins = "gpio36", "gpio37", "gpio38"; function = "qup13"; }; - qup_spi14_cs: qup-spi14-cs { + qup_spi14_cs: qup-spi14-cs-state { pins = "gpio43"; function = "qup14"; }; - qup_spi14_cs_gpio: qup-spi14-cs-gpio { + qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { pins = "gpio43"; function = "gpio"; }; - qup_spi14_data_clk: qup-spi14-data-clk { + qup_spi14_data_clk: qup-spi14-data-clk-state { pins = "gpio40", "gpio41", "gpio42"; function = "qup14"; }; - qup_spi15_cs: qup-spi15-cs { + qup_spi15_cs: qup-spi15-cs-state { pins = "gpio47"; function = "qup15"; }; - qup_spi15_cs_gpio: qup-spi15-cs-gpio { + qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { pins = "gpio47"; function = "gpio"; }; - qup_spi15_data_clk: qup-spi15-data-clk { + qup_spi15_data_clk: qup-spi15-data-clk-state { pins = "gpio44", "gpio45", "gpio46"; function = "qup15"; }; - qup_spi16_cs: qup-spi16-cs { + qup_spi16_cs: qup-spi16-cs-state { pins = "gpio51"; function = "qup16"; }; - qup_spi16_cs_gpio: qup-spi16-cs-gpio { + qup_spi16_cs_gpio: qup-spi16-cs-gpio-state { pins = "gpio51"; function = "gpio"; }; - qup_spi16_data_clk: qup-spi16-data-clk { + qup_spi16_data_clk: qup-spi16-data-clk-state { pins = "gpio48", "gpio49", "gpio50"; function = "qup16"; }; - qup_spi17_cs: qup-spi17-cs { + qup_spi17_cs: qup-spi17-cs-state { pins = "gpio55"; function = "qup17"; }; - qup_spi17_cs_gpio: qup-spi17-cs-gpio { + qup_spi17_cs_gpio: qup-spi17-cs-gpio-state { pins = "gpio55"; function = "gpio"; }; - qup_spi17_data_clk: qup-spi17-data-clk { + qup_spi17_data_clk: qup-spi17-data-clk-state { pins = "gpio52", "gpio53", "gpio54"; function = "qup17"; }; - qup_spi18_cs: qup-spi18-cs { + qup_spi18_cs: qup-spi18-cs-state { pins = "gpio59"; function = "qup18"; }; - qup_spi18_cs_gpio: qup-spi18-cs-gpio { + qup_spi18_cs_gpio: qup-spi18-cs-gpio-state { pins = "gpio59"; function = "gpio"; }; - qup_spi18_data_clk: qup-spi18-data-clk { + qup_spi18_data_clk: qup-spi18-data-clk-state { pins = "gpio56", "gpio57", "gpio58"; function = "qup18"; }; - qup_spi19_cs: qup-spi19-cs { + qup_spi19_cs: qup-spi19-cs-state { pins = "gpio3"; function = "qup19"; }; - qup_spi19_cs_gpio: qup-spi19-cs-gpio { + qup_spi19_cs_gpio: qup-spi19-cs-gpio-state { pins = "gpio3"; function = "gpio"; }; - qup_spi19_data_clk: qup-spi19-data-clk { + qup_spi19_data_clk: qup-spi19-data-clk-state { pins = "gpio0", "gpio1", "gpio2"; function = "qup19"; }; - qup_uart2_default: qup-uart2-default { - mux { - pins = "gpio117", "gpio118"; - function = "qup2"; - }; + qup_uart2_default: qup-uart2-default-state { + pins = "gpio117", "gpio118"; + function = "qup2"; }; - qup_uart6_default: qup-uart6-default { - mux { - pins = "gpio16", "gpio17", - "gpio18", "gpio19"; - function = "qup6"; - }; + qup_uart6_default: qup-uart6-default-state { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + function = "qup6"; }; - qup_uart12_default: qup-uart12-default { - mux { - pins = "gpio34", "gpio35"; - function = "qup12"; - }; + qup_uart12_default: qup-uart12-default-state { + pins = "gpio34", "gpio35"; + function = "qup12"; }; - qup_uart17_default: qup-uart17-default { - mux { - pins = "gpio52", "gpio53", - "gpio54", "gpio55"; - function = "qup17"; - }; + qup_uart17_default: qup-uart17-default-state { + pins = "gpio52", "gpio53", "gpio54", "gpio55"; + function = "qup17"; }; - qup_uart18_default: qup-uart18-default { - mux { - pins = "gpio58", "gpio59"; - function = "qup18"; - }; + qup_uart18_default: qup-uart18-default-state { + pins = "gpio58", "gpio59"; + function = "qup18"; }; - tert_mi2s_active: tert-mi2s-active { - sck { + tert_mi2s_active: tert-mi2s-active-state { + sck-pins { pins = "gpio133"; function = "mi2s2_sck"; drive-strength = <8>; bias-disable; }; - data0 { + data0-pins { pins = "gpio134"; function = "mi2s2_data0"; drive-strength = <8>; @@ -4542,7 +4410,7 @@ data0 { output-high; }; - ws { + ws-pins { pins = "gpio135"; function = "mi2s2_ws"; drive-strength = <8>; @@ -4550,42 +4418,42 @@ ws { }; }; - sdc2_sleep_state: sdc2-sleep { - clk { + sdc2_sleep_state: sdc2-sleep-state { + clk-pins { pins = "sdc2_clk"; drive-strength = <2>; bias-disable; }; - cmd { + cmd-pins { pins = "sdc2_cmd"; drive-strength = <2>; bias-pull-up; }; - data { + data-pins { pins = "sdc2_data"; drive-strength = <2>; bias-pull-up; }; }; - pcie0_default_state: pcie0-default { - perst { + pcie0_default_state: pcie0-default-state { + perst-pins { pins = "gpio79"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; - clkreq { + clkreq-pins { pins = "gpio80"; function = "pci_e0"; drive-strength = <2>; bias-pull-up; }; - wake { + wake-pins { pins = "gpio81"; function = "gpio"; drive-strength = <2>; @@ -4593,22 +4461,22 @@ wake { }; }; - pcie1_default_state: pcie1-default { - perst { + pcie1_default_state: pcie1-default-state { + perst-pins { pins = "gpio82"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; - clkreq { + clkreq-pins { pins = "gpio83"; function = "pci_e1"; drive-strength = <2>; bias-pull-up; }; - wake { + wake-pins { pins = "gpio84"; function = "gpio"; drive-strength = <2>; @@ -4616,22 +4484,22 @@ wake { }; }; - pcie2_default_state: pcie2-default { - perst { + pcie2_default_state: pcie2-default-state { + perst-pins { pins = "gpio85"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; - clkreq { + clkreq-pins { pins = "gpio86"; function = "pci_e2"; drive-strength = <2>; bias-pull-up; }; - wake { + wake-pins { pins = "gpio87"; function = "gpio"; drive-strength = <2>; From 7ff4a646fae3697b039c6b684786a1e309e8445c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 30 Sep 2022 21:29:40 +0200 Subject: [PATCH 016/261] arm64: dts: qcom: sm8250-sony-xperia-edo: fix touchscreen bias-disable The property to disable bias is "bias-disable". Fixes: e76c7e1f15fe ("arm64: dts: qcom: sm8250-edo: Add Samsung touchscreen") Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220930192954.242546-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi index 72162852fae7..601a21c381f8 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -613,7 +613,7 @@ ts_int_default: ts-int-default-state { pins = "gpio39"; function = "gpio"; drive-strength = <2>; - bias-disabled; + bias-disable; input-enable; }; From 91c4431b0204d720bee3062fa8e6c6ac789100b4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 30 Sep 2022 21:29:41 +0200 Subject: [PATCH 017/261] arm64: dts: qcom: sc8280xp: align TLMM pin configuration with DT schema DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. qcom/sc8280xp-crd.dtb: pinctrl@f100000: kybd-default-state: 'oneOf' conditional failed, one must be fixed: 'pins' is a required property 'function' is a required property 'disable', 'int-n', 'reset' do not match any of the regexes: 'pinctrl-[0-9]+' 'disable', 'int-n', 'reset' do not match any of the regexes: '-pins$', 'pinctrl-[0-9]+' Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220930192954.242546-4-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 12 ++++++------ .../boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 12 ++++++------ 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index fea7d8273ccd..a2027f1d1d04 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -374,19 +374,19 @@ &tlmm { gpio-reserved-ranges = <74 6>, <83 4>, <125 2>, <128 2>, <154 7>; kybd_default: kybd-default-state { - disable { + disable-pins { pins = "gpio102"; function = "gpio"; output-low; }; - int-n { + int-n-pins { pins = "gpio104"; function = "gpio"; bias-disable; }; - reset { + reset-pins { pins = "gpio105"; function = "gpio"; bias-disable; @@ -410,7 +410,7 @@ qup2_i2c5_default: qup2-i2c5-default-state { }; tpad_default: tpad-default-state { - int-n { + int-n-pins { pins = "gpio182"; function = "gpio"; bias-disable; @@ -418,13 +418,13 @@ int-n { }; ts0_default: ts0-default-state { - int-n { + int-n-pins { pins = "gpio175"; function = "gpio"; bias-disable; }; - reset-n { + reset-n-pins { pins = "gpio99"; function = "gpio"; output-high; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index b2b744bb8a53..68b61e8d03c0 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -350,19 +350,19 @@ &tlmm { gpio-reserved-ranges = <70 2>, <74 6>, <83 4>, <125 2>, <128 2>, <154 7>; kybd_default: kybd-default-state { - disable { + disable-pins { pins = "gpio102"; function = "gpio"; output-low; }; - int-n { + int-n-pins { pins = "gpio104"; function = "gpio"; bias-disable; }; - reset { + reset-pins { pins = "gpio105"; function = "gpio"; bias-disable; @@ -384,7 +384,7 @@ qup2_i2c5_default: qup2-i2c5-default-state { }; tpad_default: tpad-default-state { - int-n { + int-n-pins { pins = "gpio182"; function = "gpio"; bias-disable; @@ -392,13 +392,13 @@ int-n { }; ts0_default: ts0-default-state { - int-n { + int-n-pins { pins = "gpio175"; function = "gpio"; bias-disable; }; - reset-n { + reset-n-pins { pins = "gpio99"; function = "gpio"; output-high; From ec0872a68dcf9fba109fd7ac51843a49984f7586 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 30 Sep 2022 21:29:42 +0200 Subject: [PATCH 018/261] arm64: dts: qcom: sc7280: align TLMM pin configuration with DT schema (really) DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. I already tried to do this in commit d801357a0573 ("arm64: dts: qcom: sc7280: align TLMM pin configuration with DT schema") and I missed the fact that these nodes were not part of "state" node. Bindings did not catch these errors due to its own issues. Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220930192954.242546-5-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts | 8 +- .../arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 44 +-- .../arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi | 8 +- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 26 +- arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi | 20 +- arch/arm64/boot/dts/qcom/sc7280.dtsi | 316 +++++++++--------- 6 files changed, 211 insertions(+), 211 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts b/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts index dddb505e220b..1185141f348e 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts @@ -118,25 +118,25 @@ &wcd9385 { }; &tlmm { - tp_int_odl: tp-int-odl { + tp_int_odl: tp-int-odl-state { pins = "gpio7"; function = "gpio"; bias-disable; }; - ts_int_l: ts-int-l { + ts_int_l: ts-int-l-state { pins = "gpio55"; function = "gpio"; bias-pull-up; }; - ts_reset_l: ts-reset-l { + ts_reset_l: ts-reset-l-state { pins = "gpio54"; function = "gpio"; bias-disable; }; - us_euro_hs_sel: us-euro-hs-sel { + us_euro_hs_sel: us-euro-hs-sel-state { pins = "gpio81"; function = "gpio"; bias-pull-down; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index c11e37160f34..6a9389c40159 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -744,27 +744,27 @@ &tlmm { pinctrl-names = "default"; pinctrl-0 = <&bios_flash_wp_od>; - amp_en: amp-en-pins { + amp_en: amp-en-state { pins = "gpio63"; function = "gpio"; bias-disable; drive-strength = <2>; }; - ap_ec_int_l: ap-ec-int-l-pins { + ap_ec_int_l: ap-ec-int-l-state { pins = "gpio18"; function = "gpio"; bias-pull-up; }; - bios_flash_wp_od: bios-flash-wp-od-pins { + bios_flash_wp_od: bios-flash-wp-od-state { pins = "gpio16"; function = "gpio"; /* Has external pull */ bias-disable; }; - en_fp_rails: en-fp-rails-pins { + en_fp_rails: en-fp-rails-state { pins = "gpio77"; function = "gpio"; bias-disable; @@ -772,60 +772,60 @@ en_fp_rails: en-fp-rails-pins { output-high; }; - en_pp3300_codec: en-pp3300-codec-pins { + en_pp3300_codec: en-pp3300-codec-state { pins = "gpio105"; function = "gpio"; bias-disable; drive-strength = <2>; }; - en_pp3300_dx_edp: en-pp3300-dx-edp-pins { + en_pp3300_dx_edp: en-pp3300-dx-edp-state { pins = "gpio80"; function = "gpio"; bias-disable; drive-strength = <2>; }; - fp_rst_l: fp-rst-l-pins { + fp_rst_l: fp-rst-l-state { pins = "gpio78"; function = "gpio"; bias-disable; drive-strength = <2>; }; - fp_to_ap_irq_l: fp-to-ap-irq-l-pins { + fp_to_ap_irq_l: fp-to-ap-irq-l-state { pins = "gpio61"; function = "gpio"; /* Has external pullup */ bias-disable; }; - fpmcu_boot0: fpmcu-boot0-pins { + fpmcu_boot0: fpmcu-boot0-state { pins = "gpio68"; function = "gpio"; bias-disable; }; - gsc_ap_int_odl: gsc-ap-int-odl-pins { + gsc_ap_int_odl: gsc-ap-int-odl-state { pins = "gpio104"; function = "gpio"; bias-pull-up; }; - hp_irq: hp-irq-pins { + hp_irq: hp-irq-state { pins = "gpio101"; function = "gpio"; bias-pull-up; }; - hub_en: hub-en-pins { + hub_en: hub-en-state { pins = "gpio157"; function = "gpio"; bias-disable; drive-strength = <2>; }; - pe_wake_odl: pe-wake-odl-pins { + pe_wake_odl: pe-wake-odl-state { pins = "gpio3"; function = "gpio"; /* Has external pull */ @@ -834,45 +834,45 @@ pe_wake_odl: pe-wake-odl-pins { }; /* For ap_spi_fp */ - qup_spi9_cs_gpio_init_high: qup-spi9-cs-gpio-init-high-pins { + qup_spi9_cs_gpio_init_high: qup-spi9-cs-gpio-init-high-state { pins = "gpio39"; function = "gpio"; output-high; }; /* For ap_ec_spi */ - qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high-pins { + qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high-state { pins = "gpio43"; function = "gpio"; output-high; }; - sar0_irq_odl: sar0-irq-odl-pins { + sar0_irq_odl: sar0-irq-odl-state { pins = "gpio141"; function = "gpio"; bias-pull-up; }; - sar1_irq_odl: sar1-irq-odl-pins { + sar1_irq_odl: sar1-irq-odl-state { pins = "gpio140"; function = "gpio"; bias-pull-up; }; - sd_cd_odl: sd-cd-odl-pins { + sd_cd_odl: sd-cd-odl-state { pins = "gpio91"; function = "gpio"; bias-pull-up; }; - ssd_en: ssd-en-pins { + ssd_en: ssd-en-state { pins = "gpio51"; function = "gpio"; bias-disable; drive-strength = <2>; }; - ssd_rst_l: ssd-rst-l-pins { + ssd_rst_l: ssd-rst-l-state { pins = "gpio2"; function = "gpio"; bias-disable; @@ -880,14 +880,14 @@ ssd_rst_l: ssd-rst-l-pins { output-low; }; - tp_int_odl: tp-int-odl-pins { + tp_int_odl: tp-int-odl-state { pins = "gpio7"; function = "gpio"; /* Has external pullup */ bias-disable; }; - wf_cam_en: wf-cam-en-pins { + wf_cam_en: wf-cam-en-state { pins = "gpio119"; function = "gpio"; /* Has external pulldown */ diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi index 7f5143e9bb80..b35f3738933c 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi @@ -79,26 +79,26 @@ cr50: tpm@0 { }; &tlmm { - ap_ec_int_l: ap-ec-int-l-pins { + ap_ec_int_l: ap-ec-int-l-state { pins = "gpio18"; function = "gpio"; input-enable; bias-pull-up; }; - h1_ap_int_odl: h1-ap-int-odl-pins { + h1_ap_int_odl: h1-ap-int-odl-state { pins = "gpio104"; function = "gpio"; input-enable; bias-pull-up; }; - qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high-pins { + qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high-state { pins = "gpio43"; output-high; }; - qup_spi14_cs_gpio_init_high: qup-spi14-cs-gpio-init-high-pins { + qup_spi14_cs_gpio_init_high: qup-spi14-cs-gpio-init-high-state { pins = "gpio59"; output-high; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index cd432a2856a7..11982c14b704 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -747,24 +747,24 @@ &sdc2_data { }; &tlmm { - amp_en: amp-en { + amp_en: amp-en-state { pins = "gpio63"; bias-pull-down; drive-strength = <2>; }; - bt_en: bt-en-pins { + bt_en: bt-en-state { pins = "gpio85"; function = "gpio"; output-low; bias-disable; }; - nvme_pwren: nvme-pwren-pins { + nvme_pwren: nvme-pwren-state { function = "gpio"; }; - pcie1_reset_n: pcie1-reset-n-pins { + pcie1_reset_n: pcie1-reset-n-state { pins = "gpio2"; function = "gpio"; @@ -773,7 +773,7 @@ pcie1_reset_n: pcie1-reset-n-pins { bias-disable; }; - pcie1_wake_n: pcie1-wake-n-pins { + pcie1_wake_n: pcie1-wake-n-state { pins = "gpio3"; function = "gpio"; @@ -781,7 +781,7 @@ pcie1_wake_n: pcie1-wake-n-pins { bias-pull-up; }; - qup_uart7_sleep_cts: qup-uart7-sleep-cts-pins { + qup_uart7_sleep_cts: qup-uart7-sleep-cts-state { pins = "gpio28"; function = "gpio"; /* @@ -794,7 +794,7 @@ qup_uart7_sleep_cts: qup-uart7-sleep-cts-pins { bias-bus-hold; }; - qup_uart7_sleep_rts: qup-uart7-sleep-rts-pins { + qup_uart7_sleep_rts: qup-uart7-sleep-rts-state { pins = "gpio29"; function = "gpio"; /* @@ -806,7 +806,7 @@ qup_uart7_sleep_rts: qup-uart7-sleep-rts-pins { bias-pull-down; }; - qup_uart7_sleep_tx: qup-uart7-sleep-tx-pins { + qup_uart7_sleep_tx: qup-uart7-sleep-tx-state { pins = "gpio30"; function = "gpio"; /* @@ -816,7 +816,7 @@ qup_uart7_sleep_tx: qup-uart7-sleep-tx-pins { bias-pull-up; }; - qup_uart7_sleep_rx: qup-uart7-sleep-rx-pins { + qup_uart7_sleep_rx: qup-uart7-sleep-rx-state { pins = "gpio31"; function = "gpio"; /* @@ -827,25 +827,25 @@ qup_uart7_sleep_rx: qup-uart7-sleep-rx-pins { bias-pull-up; }; - sd_cd: sd-cd-pins { + sd_cd: sd-cd-state { pins = "gpio91"; function = "gpio"; bias-pull-up; }; - sw_ctrl: sw-ctrl-pins { + sw_ctrl: sw-ctrl-state { pins = "gpio86"; function = "gpio"; bias-pull-down; }; - wcd_reset_n: wcd-reset-n { + wcd_reset_n: wcd-reset-n-state { pins = "gpio83"; function = "gpio"; drive-strength = <8>; }; - wcd_reset_n_sleep: wcd-reset-n-sleep { + wcd_reset_n_sleep: wcd-reset-n-sleep-state { pins = "gpio83"; function = "gpio"; drive-strength = <8>; diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi index 4b8c676b0bb1..a42b5878a75f 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi @@ -595,7 +595,7 @@ pmic_edp_bl_pwm: pmic-edp-bl-pwm-state { }; &tlmm { - mos_bt_en: mos-bt-en-pins { + mos_bt_en: mos-bt-en-state { pins = "gpio85"; function = "gpio"; drive-strength = <2>; @@ -603,7 +603,7 @@ mos_bt_en: mos-bt-en-pins { }; /* For mos_bt_uart */ - qup_uart7_sleep_cts: qup-uart7-sleep-cts-pins { + qup_uart7_sleep_cts: qup-uart7-sleep-cts-state { pins = "gpio28"; function = "gpio"; /* @@ -617,7 +617,7 @@ qup_uart7_sleep_cts: qup-uart7-sleep-cts-pins { }; /* For mos_bt_uart */ - qup_uart7_sleep_rts: qup-uart7-sleep-rts-pins { + qup_uart7_sleep_rts: qup-uart7-sleep-rts-state { pins = "gpio29"; function = "gpio"; /* @@ -630,7 +630,7 @@ qup_uart7_sleep_rts: qup-uart7-sleep-rts-pins { }; /* For mos_bt_uart */ - qup_uart7_sleep_rx: qup-uart7-sleep-rx-pins { + qup_uart7_sleep_rx: qup-uart7-sleep-rx-state { pins = "gpio31"; function = "gpio"; /* @@ -642,7 +642,7 @@ qup_uart7_sleep_rx: qup-uart7-sleep-rx-pins { }; /* For mos_bt_uart */ - qup_uart7_sleep_tx: qup-uart7-sleep-tx-pins { + qup_uart7_sleep_tx: qup-uart7-sleep-tx-state { pins = "gpio30"; function = "gpio"; /* @@ -652,32 +652,32 @@ qup_uart7_sleep_tx: qup-uart7-sleep-tx-pins { bias-pull-up; }; - ts_int_conn: ts-int-conn-pins { + ts_int_conn: ts-int-conn-state { pins = "gpio55"; function = "gpio"; bias-pull-up; }; - ts_rst_conn: ts-rst-conn-pins { + ts_rst_conn: ts-rst-conn-state { pins = "gpio54"; function = "gpio"; drive-strength = <2>; }; - us_euro_hs_sel: us-euro-hs-sel { + us_euro_hs_sel: us-euro-hs-sel-state { pins = "gpio81"; function = "gpio"; bias-pull-down; drive-strength = <2>; }; - wcd_reset_n: wcd-reset-n { + wcd_reset_n: wcd-reset-n-state { pins = "gpio83"; function = "gpio"; drive-strength = <8>; }; - wcd_reset_n_sleep: wcd-reset-n-sleep { + wcd_reset_n_sleep: wcd-reset-n-sleep-state { pins = "gpio83"; function = "gpio"; drive-strength = <8>; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 212580316d3e..63af16966d43 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -4258,791 +4258,791 @@ tlmm: pinctrl@f100000 { gpio-ranges = <&tlmm 0 0 175>; wakeup-parent = <&pdc>; - dp_hot_plug_det: dp-hot-plug-det-pins { + dp_hot_plug_det: dp-hot-plug-det-state { pins = "gpio47"; function = "dp_hot"; }; - edp_hot_plug_det: edp-hot-plug-det-pins { + edp_hot_plug_det: edp-hot-plug-det-state { pins = "gpio60"; function = "edp_hot"; }; - mi2s0_data0: mi2s0-data0-pins { + mi2s0_data0: mi2s0-data0-state { pins = "gpio98"; function = "mi2s0_data0"; }; - mi2s0_data1: mi2s0-data1-pins { + mi2s0_data1: mi2s0-data1-state { pins = "gpio99"; function = "mi2s0_data1"; }; - mi2s0_mclk: mi2s0-mclk-pins { + mi2s0_mclk: mi2s0-mclk-state { pins = "gpio96"; function = "pri_mi2s"; }; - mi2s0_sclk: mi2s0-sclk-pins { + mi2s0_sclk: mi2s0-sclk-state { pins = "gpio97"; function = "mi2s0_sck"; }; - mi2s0_ws: mi2s0-ws-pins { + mi2s0_ws: mi2s0-ws-state { pins = "gpio100"; function = "mi2s0_ws"; }; - mi2s1_data0: mi2s1-data0-pins { + mi2s1_data0: mi2s1-data0-state { pins = "gpio107"; function = "mi2s1_data0"; }; - mi2s1_sclk: mi2s1-sclk-pins { + mi2s1_sclk: mi2s1-sclk-state { pins = "gpio106"; function = "mi2s1_sck"; }; - mi2s1_ws: mi2s1-ws-pins { + mi2s1_ws: mi2s1-ws-state { pins = "gpio108"; function = "mi2s1_ws"; }; - pcie1_clkreq_n: pcie1-clkreq-n-pins { + pcie1_clkreq_n: pcie1-clkreq-n-state { pins = "gpio79"; function = "pcie1_clkreqn"; }; - qspi_clk: qspi-clk-pins { + qspi_clk: qspi-clk-state { pins = "gpio14"; function = "qspi_clk"; }; - qspi_cs0: qspi-cs0-pins { + qspi_cs0: qspi-cs0-state { pins = "gpio15"; function = "qspi_cs"; }; - qspi_cs1: qspi-cs1-pins { + qspi_cs1: qspi-cs1-state { pins = "gpio19"; function = "qspi_cs"; }; - qspi_data01: qspi-data01-pins { + qspi_data01: qspi-data01-state { pins = "gpio12", "gpio13"; function = "qspi_data"; }; - qspi_data12: qspi-data12-pins { + qspi_data12: qspi-data12-state { pins = "gpio16", "gpio17"; function = "qspi_data"; }; - qup_i2c0_data_clk: qup-i2c0-data-clk-pins { + qup_i2c0_data_clk: qup-i2c0-data-clk-state { pins = "gpio0", "gpio1"; function = "qup00"; }; - qup_i2c1_data_clk: qup-i2c1-data-clk-pins { + qup_i2c1_data_clk: qup-i2c1-data-clk-state { pins = "gpio4", "gpio5"; function = "qup01"; }; - qup_i2c2_data_clk: qup-i2c2-data-clk-pins { + qup_i2c2_data_clk: qup-i2c2-data-clk-state { pins = "gpio8", "gpio9"; function = "qup02"; }; - qup_i2c3_data_clk: qup-i2c3-data-clk-pins { + qup_i2c3_data_clk: qup-i2c3-data-clk-state { pins = "gpio12", "gpio13"; function = "qup03"; }; - qup_i2c4_data_clk: qup-i2c4-data-clk-pins { + qup_i2c4_data_clk: qup-i2c4-data-clk-state { pins = "gpio16", "gpio17"; function = "qup04"; }; - qup_i2c5_data_clk: qup-i2c5-data-clk-pins { + qup_i2c5_data_clk: qup-i2c5-data-clk-state { pins = "gpio20", "gpio21"; function = "qup05"; }; - qup_i2c6_data_clk: qup-i2c6-data-clk-pins { + qup_i2c6_data_clk: qup-i2c6-data-clk-state { pins = "gpio24", "gpio25"; function = "qup06"; }; - qup_i2c7_data_clk: qup-i2c7-data-clk-pins { + qup_i2c7_data_clk: qup-i2c7-data-clk-state { pins = "gpio28", "gpio29"; function = "qup07"; }; - qup_i2c8_data_clk: qup-i2c8-data-clk-pins { + qup_i2c8_data_clk: qup-i2c8-data-clk-state { pins = "gpio32", "gpio33"; function = "qup10"; }; - qup_i2c9_data_clk: qup-i2c9-data-clk-pins { + qup_i2c9_data_clk: qup-i2c9-data-clk-state { pins = "gpio36", "gpio37"; function = "qup11"; }; - qup_i2c10_data_clk: qup-i2c10-data-clk-pins { + qup_i2c10_data_clk: qup-i2c10-data-clk-state { pins = "gpio40", "gpio41"; function = "qup12"; }; - qup_i2c11_data_clk: qup-i2c11-data-clk-pins { + qup_i2c11_data_clk: qup-i2c11-data-clk-state { pins = "gpio44", "gpio45"; function = "qup13"; }; - qup_i2c12_data_clk: qup-i2c12-data-clk-pins { + qup_i2c12_data_clk: qup-i2c12-data-clk-state { pins = "gpio48", "gpio49"; function = "qup14"; }; - qup_i2c13_data_clk: qup-i2c13-data-clk-pins { + qup_i2c13_data_clk: qup-i2c13-data-clk-state { pins = "gpio52", "gpio53"; function = "qup15"; }; - qup_i2c14_data_clk: qup-i2c14-data-clk-pins { + qup_i2c14_data_clk: qup-i2c14-data-clk-state { pins = "gpio56", "gpio57"; function = "qup16"; }; - qup_i2c15_data_clk: qup-i2c15-data-clk-pins { + qup_i2c15_data_clk: qup-i2c15-data-clk-state { pins = "gpio60", "gpio61"; function = "qup17"; }; - qup_spi0_data_clk: qup-spi0-data-clk-pins { + qup_spi0_data_clk: qup-spi0-data-clk-state { pins = "gpio0", "gpio1", "gpio2"; function = "qup00"; }; - qup_spi0_cs: qup-spi0-cs-pins { + qup_spi0_cs: qup-spi0-cs-state { pins = "gpio3"; function = "qup00"; }; - qup_spi0_cs_gpio: qup-spi0-cs-gpio-pins { + qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { pins = "gpio3"; function = "gpio"; }; - qup_spi1_data_clk: qup-spi1-data-clk-pins { + qup_spi1_data_clk: qup-spi1-data-clk-state { pins = "gpio4", "gpio5", "gpio6"; function = "qup01"; }; - qup_spi1_cs: qup-spi1-cs-pins { + qup_spi1_cs: qup-spi1-cs-state { pins = "gpio7"; function = "qup01"; }; - qup_spi1_cs_gpio: qup-spi1-cs-gpio-pins { + qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { pins = "gpio7"; function = "gpio"; }; - qup_spi2_data_clk: qup-spi2-data-clk-pins { + qup_spi2_data_clk: qup-spi2-data-clk-state { pins = "gpio8", "gpio9", "gpio10"; function = "qup02"; }; - qup_spi2_cs: qup-spi2-cs-pins { + qup_spi2_cs: qup-spi2-cs-state { pins = "gpio11"; function = "qup02"; }; - qup_spi2_cs_gpio: qup-spi2-cs-gpio-pins { + qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { pins = "gpio11"; function = "gpio"; }; - qup_spi3_data_clk: qup-spi3-data-clk-pins { + qup_spi3_data_clk: qup-spi3-data-clk-state { pins = "gpio12", "gpio13", "gpio14"; function = "qup03"; }; - qup_spi3_cs: qup-spi3-cs-pins { + qup_spi3_cs: qup-spi3-cs-state { pins = "gpio15"; function = "qup03"; }; - qup_spi3_cs_gpio: qup-spi3-cs-gpio-pins { + qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { pins = "gpio15"; function = "gpio"; }; - qup_spi4_data_clk: qup-spi4-data-clk-pins { + qup_spi4_data_clk: qup-spi4-data-clk-state { pins = "gpio16", "gpio17", "gpio18"; function = "qup04"; }; - qup_spi4_cs: qup-spi4-cs-pins { + qup_spi4_cs: qup-spi4-cs-state { pins = "gpio19"; function = "qup04"; }; - qup_spi4_cs_gpio: qup-spi4-cs-gpio-pins { + qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { pins = "gpio19"; function = "gpio"; }; - qup_spi5_data_clk: qup-spi5-data-clk-pins { + qup_spi5_data_clk: qup-spi5-data-clk-state { pins = "gpio20", "gpio21", "gpio22"; function = "qup05"; }; - qup_spi5_cs: qup-spi5-cs-pins { + qup_spi5_cs: qup-spi5-cs-state { pins = "gpio23"; function = "qup05"; }; - qup_spi5_cs_gpio: qup-spi5-cs-gpio-pins { + qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { pins = "gpio23"; function = "gpio"; }; - qup_spi6_data_clk: qup-spi6-data-clk-pins { + qup_spi6_data_clk: qup-spi6-data-clk-state { pins = "gpio24", "gpio25", "gpio26"; function = "qup06"; }; - qup_spi6_cs: qup-spi6-cs-pins { + qup_spi6_cs: qup-spi6-cs-state { pins = "gpio27"; function = "qup06"; }; - qup_spi6_cs_gpio: qup-spi6-cs-gpio-pins { + qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { pins = "gpio27"; function = "gpio"; }; - qup_spi7_data_clk: qup-spi7-data-clk-pins { + qup_spi7_data_clk: qup-spi7-data-clk-state { pins = "gpio28", "gpio29", "gpio30"; function = "qup07"; }; - qup_spi7_cs: qup-spi7-cs-pins { + qup_spi7_cs: qup-spi7-cs-state { pins = "gpio31"; function = "qup07"; }; - qup_spi7_cs_gpio: qup-spi7-cs-gpio-pins { + qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { pins = "gpio31"; function = "gpio"; }; - qup_spi8_data_clk: qup-spi8-data-clk-pins { + qup_spi8_data_clk: qup-spi8-data-clk-state { pins = "gpio32", "gpio33", "gpio34"; function = "qup10"; }; - qup_spi8_cs: qup-spi8-cs-pins { + qup_spi8_cs: qup-spi8-cs-state { pins = "gpio35"; function = "qup10"; }; - qup_spi8_cs_gpio: qup-spi8-cs-gpio-pins { + qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { pins = "gpio35"; function = "gpio"; }; - qup_spi9_data_clk: qup-spi9-data-clk-pins { + qup_spi9_data_clk: qup-spi9-data-clk-state { pins = "gpio36", "gpio37", "gpio38"; function = "qup11"; }; - qup_spi9_cs: qup-spi9-cs-pins { + qup_spi9_cs: qup-spi9-cs-state { pins = "gpio39"; function = "qup11"; }; - qup_spi9_cs_gpio: qup-spi9-cs-gpio-pins { + qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { pins = "gpio39"; function = "gpio"; }; - qup_spi10_data_clk: qup-spi10-data-clk-pins { + qup_spi10_data_clk: qup-spi10-data-clk-state { pins = "gpio40", "gpio41", "gpio42"; function = "qup12"; }; - qup_spi10_cs: qup-spi10-cs-pins { + qup_spi10_cs: qup-spi10-cs-state { pins = "gpio43"; function = "qup12"; }; - qup_spi10_cs_gpio: qup-spi10-cs-gpio-pins { + qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { pins = "gpio43"; function = "gpio"; }; - qup_spi11_data_clk: qup-spi11-data-clk-pins { + qup_spi11_data_clk: qup-spi11-data-clk-state { pins = "gpio44", "gpio45", "gpio46"; function = "qup13"; }; - qup_spi11_cs: qup-spi11-cs-pins { + qup_spi11_cs: qup-spi11-cs-state { pins = "gpio47"; function = "qup13"; }; - qup_spi11_cs_gpio: qup-spi11-cs-gpio-pins { + qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { pins = "gpio47"; function = "gpio"; }; - qup_spi12_data_clk: qup-spi12-data-clk-pins { + qup_spi12_data_clk: qup-spi12-data-clk-state { pins = "gpio48", "gpio49", "gpio50"; function = "qup14"; }; - qup_spi12_cs: qup-spi12-cs-pins { + qup_spi12_cs: qup-spi12-cs-state { pins = "gpio51"; function = "qup14"; }; - qup_spi12_cs_gpio: qup-spi12-cs-gpio-pins { + qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { pins = "gpio51"; function = "gpio"; }; - qup_spi13_data_clk: qup-spi13-data-clk-pins { + qup_spi13_data_clk: qup-spi13-data-clk-state { pins = "gpio52", "gpio53", "gpio54"; function = "qup15"; }; - qup_spi13_cs: qup-spi13-cs-pins { + qup_spi13_cs: qup-spi13-cs-state { pins = "gpio55"; function = "qup15"; }; - qup_spi13_cs_gpio: qup-spi13-cs-gpio-pins { + qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { pins = "gpio55"; function = "gpio"; }; - qup_spi14_data_clk: qup-spi14-data-clk-pins { + qup_spi14_data_clk: qup-spi14-data-clk-state { pins = "gpio56", "gpio57", "gpio58"; function = "qup16"; }; - qup_spi14_cs: qup-spi14-cs-pins { + qup_spi14_cs: qup-spi14-cs-state { pins = "gpio59"; function = "qup16"; }; - qup_spi14_cs_gpio: qup-spi14-cs-gpio-pins { + qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { pins = "gpio59"; function = "gpio"; }; - qup_spi15_data_clk: qup-spi15-data-clk-pins { + qup_spi15_data_clk: qup-spi15-data-clk-state { pins = "gpio60", "gpio61", "gpio62"; function = "qup17"; }; - qup_spi15_cs: qup-spi15-cs-pins { + qup_spi15_cs: qup-spi15-cs-state { pins = "gpio63"; function = "qup17"; }; - qup_spi15_cs_gpio: qup-spi15-cs-gpio-pins { + qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { pins = "gpio63"; function = "gpio"; }; - qup_uart0_cts: qup-uart0-cts-pins { + qup_uart0_cts: qup-uart0-cts-state { pins = "gpio0"; function = "qup00"; }; - qup_uart0_rts: qup-uart0-rts-pins { + qup_uart0_rts: qup-uart0-rts-state { pins = "gpio1"; function = "qup00"; }; - qup_uart0_tx: qup-uart0-tx-pins { + qup_uart0_tx: qup-uart0-tx-state { pins = "gpio2"; function = "qup00"; }; - qup_uart0_rx: qup-uart0-rx-pins { + qup_uart0_rx: qup-uart0-rx-state { pins = "gpio3"; function = "qup00"; }; - qup_uart1_cts: qup-uart1-cts-pins { + qup_uart1_cts: qup-uart1-cts-state { pins = "gpio4"; function = "qup01"; }; - qup_uart1_rts: qup-uart1-rts-pins { + qup_uart1_rts: qup-uart1-rts-state { pins = "gpio5"; function = "qup01"; }; - qup_uart1_tx: qup-uart1-tx-pins { + qup_uart1_tx: qup-uart1-tx-state { pins = "gpio6"; function = "qup01"; }; - qup_uart1_rx: qup-uart1-rx-pins { + qup_uart1_rx: qup-uart1-rx-state { pins = "gpio7"; function = "qup01"; }; - qup_uart2_cts: qup-uart2-cts-pins { + qup_uart2_cts: qup-uart2-cts-state { pins = "gpio8"; function = "qup02"; }; - qup_uart2_rts: qup-uart2-rts-pins { + qup_uart2_rts: qup-uart2-rts-state { pins = "gpio9"; function = "qup02"; }; - qup_uart2_tx: qup-uart2-tx-pins { + qup_uart2_tx: qup-uart2-tx-state { pins = "gpio10"; function = "qup02"; }; - qup_uart2_rx: qup-uart2-rx-pins { + qup_uart2_rx: qup-uart2-rx-state { pins = "gpio11"; function = "qup02"; }; - qup_uart3_cts: qup-uart3-cts-pins { + qup_uart3_cts: qup-uart3-cts-state { pins = "gpio12"; function = "qup03"; }; - qup_uart3_rts: qup-uart3-rts-pins { + qup_uart3_rts: qup-uart3-rts-state { pins = "gpio13"; function = "qup03"; }; - qup_uart3_tx: qup-uart3-tx-pins { + qup_uart3_tx: qup-uart3-tx-state { pins = "gpio14"; function = "qup03"; }; - qup_uart3_rx: qup-uart3-rx-pins { + qup_uart3_rx: qup-uart3-rx-state { pins = "gpio15"; function = "qup03"; }; - qup_uart4_cts: qup-uart4-cts-pins { + qup_uart4_cts: qup-uart4-cts-state { pins = "gpio16"; function = "qup04"; }; - qup_uart4_rts: qup-uart4-rts-pins { + qup_uart4_rts: qup-uart4-rts-state { pins = "gpio17"; function = "qup04"; }; - qup_uart4_tx: qup-uart4-tx-pins { + qup_uart4_tx: qup-uart4-tx-state { pins = "gpio18"; function = "qup04"; }; - qup_uart4_rx: qup-uart4-rx-pins { + qup_uart4_rx: qup-uart4-rx-state { pins = "gpio19"; function = "qup04"; }; - qup_uart5_cts: qup-uart5-cts-pins { + qup_uart5_cts: qup-uart5-cts-state { pins = "gpio20"; function = "qup05"; }; - qup_uart5_rts: qup-uart5-rts-pins { + qup_uart5_rts: qup-uart5-rts-state { pins = "gpio21"; function = "qup05"; }; - qup_uart5_tx: qup-uart5-tx-pins { + qup_uart5_tx: qup-uart5-tx-state { pins = "gpio22"; function = "qup05"; }; - qup_uart5_rx: qup-uart5-rx-pins { + qup_uart5_rx: qup-uart5-rx-state { pins = "gpio23"; function = "qup05"; }; - qup_uart6_cts: qup-uart6-cts-pins { + qup_uart6_cts: qup-uart6-cts-state { pins = "gpio24"; function = "qup06"; }; - qup_uart6_rts: qup-uart6-rts-pins { + qup_uart6_rts: qup-uart6-rts-state { pins = "gpio25"; function = "qup06"; }; - qup_uart6_tx: qup-uart6-tx-pins { + qup_uart6_tx: qup-uart6-tx-state { pins = "gpio26"; function = "qup06"; }; - qup_uart6_rx: qup-uart6-rx-pins { + qup_uart6_rx: qup-uart6-rx-state { pins = "gpio27"; function = "qup06"; }; - qup_uart7_cts: qup-uart7-cts-pins { + qup_uart7_cts: qup-uart7-cts-state { pins = "gpio28"; function = "qup07"; }; - qup_uart7_rts: qup-uart7-rts-pins { + qup_uart7_rts: qup-uart7-rts-state { pins = "gpio29"; function = "qup07"; }; - qup_uart7_tx: qup-uart7-tx-pins { + qup_uart7_tx: qup-uart7-tx-state { pins = "gpio30"; function = "qup07"; }; - qup_uart7_rx: qup-uart7-rx-pins { + qup_uart7_rx: qup-uart7-rx-state { pins = "gpio31"; function = "qup07"; }; - qup_uart8_cts: qup-uart8-cts-pins { + qup_uart8_cts: qup-uart8-cts-state { pins = "gpio32"; function = "qup10"; }; - qup_uart8_rts: qup-uart8-rts-pins { + qup_uart8_rts: qup-uart8-rts-state { pins = "gpio33"; function = "qup10"; }; - qup_uart8_tx: qup-uart8-tx-pins { + qup_uart8_tx: qup-uart8-tx-state { pins = "gpio34"; function = "qup10"; }; - qup_uart8_rx: qup-uart8-rx-pins { + qup_uart8_rx: qup-uart8-rx-state { pins = "gpio35"; function = "qup10"; }; - qup_uart9_cts: qup-uart9-cts-pins { + qup_uart9_cts: qup-uart9-cts-state { pins = "gpio36"; function = "qup11"; }; - qup_uart9_rts: qup-uart9-rts-pins { + qup_uart9_rts: qup-uart9-rts-state { pins = "gpio37"; function = "qup11"; }; - qup_uart9_tx: qup-uart9-tx-pins { + qup_uart9_tx: qup-uart9-tx-state { pins = "gpio38"; function = "qup11"; }; - qup_uart9_rx: qup-uart9-rx-pins { + qup_uart9_rx: qup-uart9-rx-state { pins = "gpio39"; function = "qup11"; }; - qup_uart10_cts: qup-uart10-cts-pins { + qup_uart10_cts: qup-uart10-cts-state { pins = "gpio40"; function = "qup12"; }; - qup_uart10_rts: qup-uart10-rts-pins { + qup_uart10_rts: qup-uart10-rts-state { pins = "gpio41"; function = "qup12"; }; - qup_uart10_tx: qup-uart10-tx-pins { + qup_uart10_tx: qup-uart10-tx-state { pins = "gpio42"; function = "qup12"; }; - qup_uart10_rx: qup-uart10-rx-pins { + qup_uart10_rx: qup-uart10-rx-state { pins = "gpio43"; function = "qup12"; }; - qup_uart11_cts: qup-uart11-cts-pins { + qup_uart11_cts: qup-uart11-cts-state { pins = "gpio44"; function = "qup13"; }; - qup_uart11_rts: qup-uart11-rts-pins { + qup_uart11_rts: qup-uart11-rts-state { pins = "gpio45"; function = "qup13"; }; - qup_uart11_tx: qup-uart11-tx-pins { + qup_uart11_tx: qup-uart11-tx-state { pins = "gpio46"; function = "qup13"; }; - qup_uart11_rx: qup-uart11-rx-pins { + qup_uart11_rx: qup-uart11-rx-state { pins = "gpio47"; function = "qup13"; }; - qup_uart12_cts: qup-uart12-cts-pins { + qup_uart12_cts: qup-uart12-cts-state { pins = "gpio48"; function = "qup14"; }; - qup_uart12_rts: qup-uart12-rts-pins { + qup_uart12_rts: qup-uart12-rts-state { pins = "gpio49"; function = "qup14"; }; - qup_uart12_tx: qup-uart12-tx-pins { + qup_uart12_tx: qup-uart12-tx-state { pins = "gpio50"; function = "qup14"; }; - qup_uart12_rx: qup-uart12-rx-pins { + qup_uart12_rx: qup-uart12-rx-state { pins = "gpio51"; function = "qup14"; }; - qup_uart13_cts: qup-uart13-cts-pins { + qup_uart13_cts: qup-uart13-cts-state { pins = "gpio52"; function = "qup15"; }; - qup_uart13_rts: qup-uart13-rts-pins { + qup_uart13_rts: qup-uart13-rts-state { pins = "gpio53"; function = "qup15"; }; - qup_uart13_tx: qup-uart13-tx-pins { + qup_uart13_tx: qup-uart13-tx-state { pins = "gpio54"; function = "qup15"; }; - qup_uart13_rx: qup-uart13-rx-pins { + qup_uart13_rx: qup-uart13-rx-state { pins = "gpio55"; function = "qup15"; }; - qup_uart14_cts: qup-uart14-cts-pins { + qup_uart14_cts: qup-uart14-cts-state { pins = "gpio56"; function = "qup16"; }; - qup_uart14_rts: qup-uart14-rts-pins { + qup_uart14_rts: qup-uart14-rts-state { pins = "gpio57"; function = "qup16"; }; - qup_uart14_tx: qup-uart14-tx-pins { + qup_uart14_tx: qup-uart14-tx-state { pins = "gpio58"; function = "qup16"; }; - qup_uart14_rx: qup-uart14-rx-pins { + qup_uart14_rx: qup-uart14-rx-state { pins = "gpio59"; function = "qup16"; }; - qup_uart15_cts: qup-uart15-cts-pins { + qup_uart15_cts: qup-uart15-cts-state { pins = "gpio60"; function = "qup17"; }; - qup_uart15_rts: qup-uart15-rts-pins { + qup_uart15_rts: qup-uart15-rts-state { pins = "gpio61"; function = "qup17"; }; - qup_uart15_tx: qup-uart15-tx-pins { + qup_uart15_tx: qup-uart15-tx-state { pins = "gpio62"; function = "qup17"; }; - qup_uart15_rx: qup-uart15-rx-pins { + qup_uart15_rx: qup-uart15-rx-state { pins = "gpio63"; function = "qup17"; }; - sdc1_clk: sdc1-clk-pins { + sdc1_clk: sdc1-clk-state { pins = "sdc1_clk"; }; - sdc1_cmd: sdc1-cmd-pins { + sdc1_cmd: sdc1-cmd-state { pins = "sdc1_cmd"; }; - sdc1_data: sdc1-data-pins { + sdc1_data: sdc1-data-state { pins = "sdc1_data"; }; - sdc1_rclk: sdc1-rclk-pins { + sdc1_rclk: sdc1-rclk-state { pins = "sdc1_rclk"; }; - sdc1_clk_sleep: sdc1-clk-sleep-pins { + sdc1_clk_sleep: sdc1-clk-sleep-state { pins = "sdc1_clk"; drive-strength = <2>; bias-bus-hold; }; - sdc1_cmd_sleep: sdc1-cmd-sleep-pins { + sdc1_cmd_sleep: sdc1-cmd-sleep-state { pins = "sdc1_cmd"; drive-strength = <2>; bias-bus-hold; }; - sdc1_data_sleep: sdc1-data-sleep-pins { + sdc1_data_sleep: sdc1-data-sleep-state { pins = "sdc1_data"; drive-strength = <2>; bias-bus-hold; }; - sdc1_rclk_sleep: sdc1-rclk-sleep-pins { + sdc1_rclk_sleep: sdc1-rclk-sleep-state { pins = "sdc1_rclk"; drive-strength = <2>; bias-bus-hold; }; - sdc2_clk: sdc2-clk-pins { + sdc2_clk: sdc2-clk-state { pins = "sdc2_clk"; }; - sdc2_cmd: sdc2-cmd-pins { + sdc2_cmd: sdc2-cmd-state { pins = "sdc2_cmd"; }; - sdc2_data: sdc2-data-pins { + sdc2_data: sdc2-data-state { pins = "sdc2_data"; }; - sdc2_clk_sleep: sdc2-clk-sleep-pins { + sdc2_clk_sleep: sdc2-clk-sleep-state { pins = "sdc2_clk"; drive-strength = <2>; bias-bus-hold; }; - sdc2_cmd_sleep: sdc2-cmd-sleep-pins { + sdc2_cmd_sleep: sdc2-cmd-sleep-state { pins = "sdc2_cmd"; drive-strength = <2>; bias-bus-hold; }; - sdc2_data_sleep: sdc2-data-sleep-pins { + sdc2_data_sleep: sdc2-data-sleep-state { pins = "sdc2_data"; drive-strength = <2>; bias-bus-hold; From 442b13a72a20e30b1883e425a49b337e9fa85069 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 30 Sep 2022 21:29:43 +0200 Subject: [PATCH 019/261] arm64: dts: qcom: sc7280-herobrine: correct number of gpio-line-names There are 175 GPIOs (gpio0-174). Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220930192954.242546-6-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts | 1 + arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker-r0.dts | 1 - arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts | 1 - arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi | 1 - 4 files changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts index f0f26af1e421..4e0b013e25f4 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts @@ -372,5 +372,6 @@ &tlmm { "", /* 170 */ "MOS_BLE_UART_TX", "MOS_BLE_UART_RX", + "", ""; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker-r0.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker-r0.dts index ccbe50b6249a..739e81bd6d68 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker-r0.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker-r0.dts @@ -328,6 +328,5 @@ &tlmm { "MOS_BLE_UART_TX", "MOS_BLE_UART_RX", "", - "", ""; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts index c1a671968725..c8ff13db30b9 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts @@ -358,6 +358,5 @@ &tlmm { "MOS_BLE_UART_TX", "MOS_BLE_UART_RX", "", - "", ""; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi index 4566722bf4dd..3dff610fb946 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi @@ -321,6 +321,5 @@ &tlmm { "MOS_BLE_UART_TX", "MOS_BLE_UART_RX", "", - "", ""; }; From d0ca0de64537d129d7f4f7e878a8c20eea751a7c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 30 Sep 2022 21:29:44 +0200 Subject: [PATCH 020/261] arm64: dts: qcom: sc7280-idp-ec-h1: add missing QUP GPIO functions Add default GPIO function to SPI10 and SPI14 chip-select pins on SC7280 IDP, as required by bindings. Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220930192954.242546-7-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi index b35f3738933c..3cfeb118d379 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi @@ -95,11 +95,13 @@ h1_ap_int_odl: h1-ap-int-odl-state { qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high-state { pins = "gpio43"; + function = "gpio"; output-high; }; qup_spi14_cs_gpio_init_high: qup-spi14-cs-gpio-init-high-state { pins = "gpio59"; + function = "gpio"; output-high; }; }; From 305dd3f89b492de7672bf53e016e7dcf14ba9e85 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 30 Sep 2022 21:29:45 +0200 Subject: [PATCH 021/261] arm64: dts: qcom: msm8953: align TLMM pin configuration with DT schema DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. qcom/sdm632-fairphone-fp3.dtb: pinctrl@1000000: 'cd-off-pins', 'cd-on-pins', 'gpio-key-default-pins', .... do not match any of the regexes: '-state$', 'pinctrl-[0-9]+' Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220930192954.242546-8-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 70 +++++++++++++-------------- 1 file changed, 35 insertions(+), 35 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 6b992a6d56c1..db94e6fd18f5 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -460,229 +460,229 @@ tlmm: pinctrl@1000000 { interrupt-controller; #interrupt-cells = <2>; - uart_console_active: uart-console-active-pins { + uart_console_active: uart-console-active-state { pins = "gpio4", "gpio5"; function = "blsp_uart2"; drive-strength = <2>; bias-disable; }; - uart_console_sleep: uart-console-sleep-pins { + uart_console_sleep: uart-console-sleep-state { pins = "gpio4", "gpio5"; function = "blsp_uart2"; drive-strength = <2>; bias-pull-down; }; - sdc1_clk_on: sdc1-clk-on-pins { + sdc1_clk_on: sdc1-clk-on-state { pins = "sdc1_clk"; bias-disable; drive-strength = <16>; }; - sdc1_clk_off: sdc1-clk-off-pins { + sdc1_clk_off: sdc1-clk-off-state { pins = "sdc1_clk"; bias-disable; drive-strength = <2>; }; - sdc1_cmd_on: sdc1-cmd-on-pins { + sdc1_cmd_on: sdc1-cmd-on-state { pins = "sdc1_cmd"; bias-disable; drive-strength = <10>; }; - sdc1_cmd_off: sdc1-cmd-off-pins { + sdc1_cmd_off: sdc1-cmd-off-state { pins = "sdc1_cmd"; bias-disable; drive-strength = <2>; }; - sdc1_data_on: sdc1-data-on-pins { + sdc1_data_on: sdc1-data-on-state { pins = "sdc1_data"; bias-pull-up; drive-strength = <10>; }; - sdc1_data_off: sdc1-data-off-pins { + sdc1_data_off: sdc1-data-off-state { pins = "sdc1_data"; bias-pull-up; drive-strength = <2>; }; - sdc1_rclk_on: sdc1-rclk-on-pins { + sdc1_rclk_on: sdc1-rclk-on-state { pins = "sdc1_rclk"; bias-pull-down; }; - sdc1_rclk_off: sdc1-rclk-off-pins { + sdc1_rclk_off: sdc1-rclk-off-state { pins = "sdc1_rclk"; bias-pull-down; }; - sdc2_clk_on: sdc2-clk-on-pins { + sdc2_clk_on: sdc2-clk-on-state { pins = "sdc2_clk"; drive-strength = <16>; bias-disable; }; - sdc2_clk_off: sdc2-clk-off-pins { + sdc2_clk_off: sdc2-clk-off-state { pins = "sdc2_clk"; bias-disable; drive-strength = <2>; }; - sdc2_cmd_on: sdc2-cmd-on-pins { + sdc2_cmd_on: sdc2-cmd-on-state { pins = "sdc2_cmd"; bias-pull-up; drive-strength = <10>; }; - sdc2_cmd_off: sdc2-cmd-off-pins { + sdc2_cmd_off: sdc2-cmd-off-state { pins = "sdc2_cmd"; bias-pull-up; drive-strength = <2>; }; - sdc2_data_on: sdc2-data-on-pins { + sdc2_data_on: sdc2-data-on-state { pins = "sdc2_data"; bias-pull-up; drive-strength = <10>; }; - sdc2_data_off: sdc2-data-off-pins { + sdc2_data_off: sdc2-data-off-state { pins = "sdc2_data"; bias-pull-up; drive-strength = <2>; }; - sdc2_cd_on: cd-on-pins { + sdc2_cd_on: cd-on-state { pins = "gpio133"; function = "gpio"; drive-strength = <2>; bias-pull-up; }; - sdc2_cd_off: cd-off-pins { + sdc2_cd_off: cd-off-state { pins = "gpio133"; function = "gpio"; drive-strength = <2>; bias-disable; }; - gpio_key_default: gpio-key-default-pins { + gpio_key_default: gpio-key-default-state { pins = "gpio85"; function = "gpio"; drive-strength = <2>; bias-pull-up; }; - i2c_1_default: i2c-1-default-pins { + i2c_1_default: i2c-1-default-state { pins = "gpio2", "gpio3"; function = "blsp_i2c1"; drive-strength = <2>; bias-disable; }; - i2c_1_sleep: i2c-1-sleep-pins { + i2c_1_sleep: i2c-1-sleep-state { pins = "gpio2", "gpio3"; function = "gpio"; drive-strength = <2>; bias-disable; }; - i2c_2_default: i2c-2-default-pins { + i2c_2_default: i2c-2-default-state { pins = "gpio6", "gpio7"; function = "blsp_i2c2"; drive-strength = <2>; bias-disable; }; - i2c_2_sleep: i2c-2-sleep-pins { + i2c_2_sleep: i2c-2-sleep-state { pins = "gpio6", "gpio7"; function = "gpio"; drive-strength = <2>; bias-disable; }; - i2c_3_default: i2c-3-default-pins { + i2c_3_default: i2c-3-default-state { pins = "gpio10", "gpio11"; function = "blsp_i2c3"; drive-strength = <2>; bias-disable; }; - i2c_3_sleep: i2c-3-sleep-pins { + i2c_3_sleep: i2c-3-sleep-state { pins = "gpio10", "gpio11"; function = "gpio"; drive-strength = <2>; bias-disable; }; - i2c_4_default: i2c-4-default-pins { + i2c_4_default: i2c-4-default-state { pins = "gpio14", "gpio15"; function = "blsp_i2c4"; drive-strength = <2>; bias-disable; }; - i2c_4_sleep: i2c-4-sleep-pins { + i2c_4_sleep: i2c-4-sleep-state { pins = "gpio14", "gpio15"; function = "gpio"; drive-strength = <2>; bias-disable; }; - i2c_5_default: i2c-5-default-pins { + i2c_5_default: i2c-5-default-state { pins = "gpio18", "gpio19"; function = "blsp_i2c5"; drive-strength = <2>; bias-disable; }; - i2c_5_sleep: i2c-5-sleep-pins { + i2c_5_sleep: i2c-5-sleep-state { pins = "gpio18", "gpio19"; function = "gpio"; drive-strength = <2>; bias-disable; }; - i2c_6_default: i2c-6-default-pins { + i2c_6_default: i2c-6-default-state { pins = "gpio22", "gpio23"; function = "blsp_i2c6"; drive-strength = <2>; bias-disable; }; - i2c_6_sleep: i2c-6-sleep-pins { + i2c_6_sleep: i2c-6-sleep-state { pins = "gpio22", "gpio23"; function = "gpio"; drive-strength = <2>; bias-disable; }; - i2c_7_default: i2c-7-default-pins { + i2c_7_default: i2c-7-default-state { pins = "gpio135", "gpio136"; function = "blsp_i2c7"; drive-strength = <2>; bias-disable; }; - i2c_7_sleep: i2c-7-sleep-pins { + i2c_7_sleep: i2c-7-sleep-state { pins = "gpio135", "gpio136"; function = "gpio"; drive-strength = <2>; bias-disable; }; - i2c_8_default: i2c-8-default-pins { + i2c_8_default: i2c-8-default-state { pins = "gpio98", "gpio99"; function = "blsp_i2c8"; drive-strength = <2>; bias-disable; }; - i2c_8_sleep: i2c-8-sleep-pins { + i2c_8_sleep: i2c-8-sleep-state { pins = "gpio98", "gpio99"; function = "gpio"; drive-strength = <2>; From 72e69d4d8d3e460806311f2b53b1807e3ca1112a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 30 Sep 2022 21:29:46 +0200 Subject: [PATCH 022/261] arm64: dts: qcom: sdm845: align TLMM pin configuration with DT schema DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. qcom/sdm845-lg-judyln.dtb: gpios@c000: 'vol-up-active-pins' does not match any of the regexes: '-state$', 'pinctrl-[0-9]+' Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220930192954.242546-9-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi index 20f275f8694d..1eb423e4be24 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi @@ -604,7 +604,7 @@ pinconf { }; &pm8998_gpio { - vol_up_pin_a: vol-up-active-pins { + vol_up_pin_a: vol-up-active-state { pins = "gpio6"; function = "normal"; input-enable; From f20a687fddf42f7d55a4992b9ecc3a663c34a6b7 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 30 Sep 2022 21:29:47 +0200 Subject: [PATCH 023/261] arm64: dts: qcom: sm6125-sony-xperia: add missing SD CD GPIO functions Add default GPIO function to SD card detect pins on SM6125 Sony Xperia, as required by bindings: qcom/sm6125-sony-xperia-seine-pdx201.dtb: pinctrl@500000: sdc2-off-state: 'oneOf' conditional failed, one must be fixed: 'pins' is a required property 'function' is a required property 'clk-pins', 'cmd-pins', 'data-pins', 'sd-cd-pins' do not match any of the regexes: 'pinctrl-[0-9]+' Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220930192954.242546-10-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts index 6a8b88cc4385..9af4b76fa6d7 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts +++ b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts @@ -89,6 +89,7 @@ &hsusb_phy1 { &sdc2_off_state { sd-cd-pins { pins = "gpio98"; + function = "gpio"; drive-strength = <2>; bias-disable; }; @@ -97,6 +98,7 @@ sd-cd-pins { &sdc2_on_state { sd-cd-pins { pins = "gpio98"; + function = "gpio"; drive-strength = <2>; bias-pull-up; }; From 179baddcc6905e6e657c35c3a380afe55b67c98d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 30 Sep 2022 21:29:48 +0200 Subject: [PATCH 024/261] arm64: dts: qcom: sm6125: align TLMM pin configuration with DT schema DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220930192954.242546-11-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 1fe3fa3ad877..af49a748e511 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -407,13 +407,13 @@ data-pins { }; sdc2_on_state: sdc2-on-state { - clk { + clk-pins { pins = "sdc2_clk"; drive-strength = <16>; bias-disable; }; - cmd-pins-pins { + cmd-pins { pins = "sdc2_cmd"; drive-strength = <10>; bias-pull-up; From fd49776d8f458bba5499384131eddc0b8bcaf50c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 30 Sep 2022 21:20:37 +0200 Subject: [PATCH 025/261] arm64: dts: qcom: sdm850-lenovo-yoga-c630: correct I2C12 pins drive strength The pin configuration (done with generic pin controller helpers and as expressed by bindings) requires children nodes with either: 1. "pins" property and the actual configuration, 2. another set of nodes with above point. The qup_i2c12_default pin configuration used second method - with a "pinmux" child. Fixes: 44acee207844 ("arm64: dts: qcom: Add Lenovo Yoga C630") Cc: Signed-off-by: Krzysztof Kozlowski Tested-by: Steev Klimaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220930192039.240486-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index be59a8ba9c1f..74f43da51fa5 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -487,8 +487,10 @@ pinconf { }; &qup_i2c12_default { - drive-strength = <2>; - bias-disable; + pinmux { + drive-strength = <2>; + bias-disable; + }; }; &qup_uart6_default { From 3638ea010c37e1e6d93474c4b3368f403600413f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 30 Sep 2022 21:20:38 +0200 Subject: [PATCH 026/261] arm64: dts: qcom: sdm850-samsung-w737: correct I2C12 pins drive strength The pin configuration (done with generic pin controller helpers and as expressed by bindings) requires children nodes with either: 1. "pins" property and the actual configuration, 2. another set of nodes with above point. The qup_i2c12_default pin configuration used second method - with a "pinmux" child. Fixes: d4b341269efb ("arm64: dts: qcom: Add support for Samsung Galaxy Book2") Cc: Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220930192039.240486-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts index f954fe5cb61a..d028a7eb364a 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts @@ -415,8 +415,10 @@ pinconf { }; &qup_i2c12_default { - drive-strength = <2>; - bias-disable; + pinmux { + drive-strength = <2>; + bias-disable; + }; }; &qup_uart6_default { From 58c4a0b6f4bdf8c3c2b4aad7f980e4019cc0fc83 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 30 Sep 2022 21:20:39 +0200 Subject: [PATCH 027/261] arm64: dts: qcom: sdm845-xiaomi-polaris: fix codec pin conf name Fix typo in the codec's pin name to be configured. Mismatched name caused the pin configuration to be ignored. Fixes: be497abe19bf ("arm64: dts: qcom: Add support for Xiaomi Mi Mix2s") Signed-off-by: Krzysztof Kozlowski Tested-by: Molly Sophia Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220930192039.240486-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts index 4f6f1ce7286c..4081822e0686 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts @@ -628,7 +628,7 @@ sde_dsi_suspend: sde-dsi-suspend { }; wcd_intr_default: wcd-intr-default { - pins = "goui54"; + pins = "gpio54"; function = "gpio"; input-enable; bias-pull-down; From 9c2eb59712cc21a183772e9837dec2305b14a423 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Thu, 29 Sep 2022 20:08:10 +0530 Subject: [PATCH 028/261] arm64: dts: qcom: sc7280: Update SNPS Phy params for SC7280 Add SNPS HS Phy tuning parameters for herobrine variant of SC7280 devices. Signed-off-by: Krishna Kurapati Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1664462290-29869-1-git-send-email-quic_kriskura@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index 6a9389c40159..fcd07ff0c6f6 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -627,6 +627,13 @@ usb_hub_3_x: hub@2 { &usb_1_hsphy { status = "okay"; + + qcom,hs-rise-fall-time-bp = <0>; + qcom,squelch-detector-bp = <(-2090)>; + qcom,hs-disconnect-bp = <1743>; + qcom,hs-amplitude-bp = <1780>; + qcom,hs-crossover-voltage-microvolt = <(-31000)>; + qcom,hs-output-impedance-micro-ohms = <2600000>; }; &usb_1_qmpphy { From 5d6fc6321db1b0ea4df0c4654ccb0432f740fcf4 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Tue, 27 Sep 2022 15:56:46 +0530 Subject: [PATCH 029/261] arm64: dts: qcom: sc7180: Add required-opps for USB USB has a requirement to put a performance state vote on 'cx' while active. Use 'required-opps' to pass this information from device tree, and since all the GDSCs in GCC (including USB) are sub-domains of cx, we also add cx as a power-domain for GCC. Now when any of the consumers of the GDSCs (in this case USB) votes on a perforamance state, genpd framework can identify that the GDSC itself does not support a performance state and it then propogates the vote to the parent, which in this case is cx. This change would also mean that any GDSC in GCC thats left enabled during low power state (perhaps because its marked with a ALWAYS_ON flag) can prevent the system from entering low power since that would prevent cx from transitioning to low power. Ideally any consumers that would need to have their devices (partially) powered to support wakeups should look at making the resp. GDSCs transtion to a Retention (PWRSTS_RET) state instead of leaving them ALWAYS_ON. Signed-off-by: Rajendra Nayak Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220927102646.14785-1-quic_rjendra@quicinc.com --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 58976a1ba06b..f59692213745 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -662,6 +662,7 @@ gcc: clock-controller@100000 { #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + power-domains = <&rpmhpd SC7180_CX>; }; qfprom: efuse@784000 { @@ -2775,6 +2776,7 @@ usb_1: usb@a6f8800 { "dm_hs_phy_irq", "dp_hs_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; resets = <&gcc GCC_USB30_PRIM_BCR>; From e3e9a5803807302221060e80880feee1b0be5765 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Tue, 27 Sep 2022 16:12:33 +0530 Subject: [PATCH 030/261] arm64: dts: qcom: sc7280: Add required-opps for i2c qup-i2c devices on sc7280 are clocked with a fixed clock (19.2 MHz) Though qup-i2c does not support DVFS, it still needs to vote for a performance state on 'CX' to satisfy the 19.2 Mhz clock frequency requirement. Use 'required-opps' to pass this information from device tree, and also add the power-domains property to specify the CX power-domain. Signed-off-by: Rajendra Nayak Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220927104233.29376-1-quic_rjendra@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 32 ++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 63af16966d43..909706ee86f5 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -967,6 +967,8 @@ i2c0: i2c@980000 { <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd SC7280_CX>; + required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, <&gpi_dma0 1 0 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1025,6 +1027,8 @@ i2c1: i2c@984000 { <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd SC7280_CX>; + required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, <&gpi_dma0 1 1 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1083,6 +1087,8 @@ i2c2: i2c@988000 { <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd SC7280_CX>; + required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, <&gpi_dma0 1 2 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1141,6 +1147,8 @@ i2c3: i2c@98c000 { <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd SC7280_CX>; + required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, <&gpi_dma0 1 3 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1199,6 +1207,8 @@ i2c4: i2c@990000 { <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd SC7280_CX>; + required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, <&gpi_dma0 1 4 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1257,6 +1267,8 @@ i2c5: i2c@994000 { <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd SC7280_CX>; + required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, <&gpi_dma0 1 5 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1315,6 +1327,8 @@ i2c6: i2c@998000 { <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd SC7280_CX>; + required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, <&gpi_dma0 1 6 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1373,6 +1387,8 @@ i2c7: i2c@99c000 { <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd SC7280_CX>; + required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, <&gpi_dma0 1 7 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1466,6 +1482,8 @@ i2c8: i2c@a80000 { <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd SC7280_CX>; + required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, <&gpi_dma1 1 0 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1524,6 +1542,8 @@ i2c9: i2c@a84000 { <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd SC7280_CX>; + required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, <&gpi_dma1 1 1 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1582,6 +1602,8 @@ i2c10: i2c@a88000 { <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd SC7280_CX>; + required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, <&gpi_dma1 1 2 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1640,6 +1662,8 @@ i2c11: i2c@a8c000 { <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd SC7280_CX>; + required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, <&gpi_dma1 1 3 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1698,6 +1722,8 @@ i2c12: i2c@a90000 { <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd SC7280_CX>; + required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, <&gpi_dma1 1 4 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1756,6 +1782,8 @@ i2c13: i2c@a94000 { <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd SC7280_CX>; + required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, <&gpi_dma1 1 5 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1814,6 +1842,8 @@ i2c14: i2c@a98000 { <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd SC7280_CX>; + required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, <&gpi_dma1 1 6 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1872,6 +1902,8 @@ i2c15: i2c@a9c000 { <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd SC7280_CX>; + required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, <&gpi_dma1 1 7 QCOM_GPI_I2C>; dma-names = "tx", "rx"; From 40b21d466a86bd5b10d24f59746ed41283a9b3f6 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Fri, 19 Aug 2022 00:06:27 +0200 Subject: [PATCH 031/261] arm64: dts: qcom: ipq8074: correct APCS register space size APCS DTS addition that was merged, was not supposed to get merged as it was part of patch series that was superseded by 2 more patch series that resolved issues with this one and greatly simplified things. Since it already got merged, start by correcting the register space size as APCS will not be providing regmap for PLL and it will conflict with the standalone A53 PLL node. Fixes: 50ed9fffec3a ("arm64: dts: qcom: ipq8074: add APCS node") Signed-off-by: Robert Marko Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220818220628.339366-8-robimarko@gmail.com --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index a47acf9bdf24..a721cdd80489 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -668,7 +668,7 @@ watchdog: watchdog@b017000 { apcs_glb: mailbox@b111000 { compatible = "qcom,ipq8074-apcs-apps-global"; - reg = <0x0b111000 0x6000>; + reg = <0x0b111000 0x1000>; #clock-cells = <1>; #mbox-cells = <1>; From a1afae1ac6e71f9995fd87fea3a116859fd64fe1 Mon Sep 17 00:00:00 2001 From: Judy Hsiao Date: Thu, 21 Jul 2022 08:38:47 +0000 Subject: [PATCH 032/261] arm64: dts: qcom: sc7280: herobrine: Add pinconf settings for mi2s1 1. Add drive strength property for mi2s1 on sc7280 based platforms. 2. Disable the pull-up for mi2s1 lines. Signed-off-by: Judy Hsiao Reviewed-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220721083849.1571744-2-judyhsiao@chromium.org --- arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index fcd07ff0c6f6..ca02ef26f161 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -646,6 +646,21 @@ &dp_hot_plug_det { bias-disable; }; +&mi2s1_data0 { + drive-strength = <6>; + bias-disable; +}; + +&mi2s1_sclk { + drive-strength = <6>; + bias-disable; +}; + +&mi2s1_ws { + drive-strength = <6>; + bias-disable; +}; + &pcie1_clkreq_n { bias-pull-up; drive-strength = <2>; From 1c5b7afeaf5b6568dc2f36d444d70ad9f6632582 Mon Sep 17 00:00:00 2001 From: Judy Hsiao Date: Thu, 21 Jul 2022 08:38:48 +0000 Subject: [PATCH 033/261] arm64: dts: qcom: sc7280: Add sc7280-herobrine-audio-rt5682.dtsi Audio dtsi for sc7280 boards that using rt5682 headset codec: 1. Add dt nodes for sound card which use I2S playback and record through rt5682s and I2S playback through max98357a. 2. Enable lpass cpu node and add pin control and dai-links. Signed-off-by: Judy Hsiao Reviewed-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220721083849.1571744-3-judyhsiao@chromium.org --- .../qcom/sc7280-herobrine-audio-rt5682.dtsi | 122 ++++++++++++++++++ 1 file changed, 122 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682.dtsi diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682.dtsi new file mode 100644 index 000000000000..2dbdeeb29ece --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682.dtsi @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * + * This file defines the common audio settings for the child boards + * using rt5682 codec. + * + * Copyright 2022 Google LLC. + */ + +/ { + /* BOARD-SPECIFIC TOP LEVEL NODES */ + sound: sound { + compatible = "google,sc7280-herobrine"; + model = "sc7280-rt5682-max98360a-1mic"; + + status = "okay"; + audio-routing = + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR"; + + #address-cells = <1>; + #size-cells = <0>; + + dai-link@0 { + link-name = "MAX98360"; + reg = <0>; + + cpu { + sound-dai = <&lpass_cpu MI2S_SECONDARY>; + }; + + codec { + sound-dai = <&max98360a>; + }; + }; + + dai-link@1 { + link-name = "ALC5682"; + reg = <1>; + + cpu { + sound-dai = <&lpass_cpu MI2S_PRIMARY>; + }; + + codec { + sound-dai = <&alc5682 0 /* aif1 */>; + }; + }; + }; +}; + +hp_i2c: &i2c2 { + status = "okay"; + clock-frequency = <400000>; + + alc5682: codec@1a { + compatible = "realtek,rt5682s"; + reg = <0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_irq>; + + #sound-dai-cells = <1>; + + interrupt-parent = <&tlmm>; + interrupts = <101 IRQ_TYPE_EDGE_BOTH>; + + AVDD-supply = <&pp1800_alc5682>; + MICVDD-supply = <&pp3300_codec>; + + realtek,dmic1-data-pin = <1>; + realtek,dmic1-clk-pin = <2>; + realtek,jd-src = <1>; + realtek,dmic-clk-rate-hz = <2048000>; + }; +}; + +&lpass_cpu { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&mi2s0_data0>, <&mi2s0_data1>, <&mi2s0_mclk>, <&mi2s0_sclk>, <&mi2s0_ws>, + <&mi2s1_data0>, <&mi2s1_sclk>, <&mi2s1_ws>; + + #address-cells = <1>; + #size-cells = <0>; + + dai-link@0 { + reg = ; + qcom,playback-sd-lines = <1>; + qcom,capture-sd-lines = <0>; + }; + + dai-link@1 { + reg = ; + qcom,playback-sd-lines = <0>; + }; +}; + +&mi2s0_data0 { + drive-strength = <6>; + bias-disable; +}; + +&mi2s0_data1 { + drive-strength = <6>; + bias-disable; +}; + +&mi2s0_mclk { + drive-strength = <6>; + bias-disable; +}; + +&mi2s0_sclk { + drive-strength = <6>; + bias-disable; +}; + +&mi2s0_ws { + drive-strength = <6>; + bias-disable; +}; From dd1651572165ffbe52e3d1aa184c04a9c11d3a03 Mon Sep 17 00:00:00 2001 From: Judy Hsiao Date: Thu, 21 Jul 2022 08:38:49 +0000 Subject: [PATCH 034/261] arm64: dts: qcom: sc7280: Include sc7280-herobrine-audio-rt5682.dtsi in herobrine-r1 Include sc7280-herobrine-audio-rt5682.dtsi in herobrine-r1 as it uses rt5682 codec. Signed-off-by: Judy Hsiao Reviewed-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220721083849.1571744-4-judyhsiao@chromium.org --- arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts index c8ff13db30b9..977dfcd9814f 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "sc7280-herobrine.dtsi" +#include "sc7280-herobrine-audio-rt5682.dtsi" #include "sc7280-herobrine-lte-sku.dtsi" / { From 358ef0c03e7ce62ab197af02e91b843b92ef4717 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 24 Jul 2022 17:04:15 +0300 Subject: [PATCH 035/261] dt-bindings: arm: qcom: separate msm8996pro bindings Xiaomi Mi 5s Plus (natrium) and Xiaomi Mi Note 2 (scorpio) use MSM8996Pro rather than plain MSM8996. Describe this in the arm/qcom.yaml bindings. Since MSM8996Pro is largely compatible with MSM8996, keep old compatible too rather than insiting on qcom,msm8996pro only. This allows the code that doesn't yet know about msm8996pro to continue supporting these devices. Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220724140421.1933004-2-dmitry.baryshkov@linaro.org --- Documentation/devicetree/bindings/arm/qcom.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 1b5ac6b02bc5..3514cd30718c 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -226,8 +226,13 @@ properties: - sony,kagura-row - sony,keyaki-row - xiaomi,gemini + - const: qcom,msm8996 + + - items: + - enum: - xiaomi,natrium - xiaomi,scorpio + - const: qcom,msm8996pro - const: qcom,msm8996 - items: From 8898c9748a872866f8c2973e719b26bf7c6ab64e Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Sun, 24 Jul 2022 17:04:16 +0300 Subject: [PATCH 036/261] arm64: dts: qcom: msm8996: Add MSM8996 Pro support Qualcomm MSM8996 Pro is a variant of MSM8996 with higher frequencies supported both on CPU and GPU. There are other minor hardware differencies in the CPU and GPU regulators and bus fabrics. However this results in significant differences between 8996 and 8996 Pro CPU OPP tables. Judging from msm-3.18 there are only few common frequencies supported by both msm8996 and msm8996pro. Rather than hacking the tables for msm8996, split msm8996pro support into a separate file. Later this would allow having additional customizations for the CBF, CPR, retulators, etc. [DB: dropped all non-CPU-OPP changes] Fixes: 90173a954a22 ("arm64: dts: qcom: msm8996: Add CPU opps") Signed-off-by: Yassine Oudjana [DB: Realigned supported-hw to keep compat with current cpufreq driver] Signed-off-by: Dmitry Baryshkov Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220724140421.1933004-3-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 82 +++---- arch/arm64/boot/dts/qcom/msm8996pro.dtsi | 266 +++++++++++++++++++++++ 2 files changed, 307 insertions(+), 41 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/msm8996pro.dtsi diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index ffa5177af7af..c6c074a9ed32 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -144,82 +144,82 @@ cluster0_opp: opp-table-cluster0 { /* Nominal fmax for now */ opp-307200000 { opp-hz = /bits/ 64 <307200000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-422400000 { opp-hz = /bits/ 64 <422400000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-480000000 { opp-hz = /bits/ 64 <480000000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-556800000 { opp-hz = /bits/ 64 <556800000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-652800000 { opp-hz = /bits/ 64 <652800000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-729600000 { opp-hz = /bits/ 64 <729600000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-844800000 { opp-hz = /bits/ 64 <844800000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-960000000 { opp-hz = /bits/ 64 <960000000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1036800000 { opp-hz = /bits/ 64 <1036800000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1113600000 { opp-hz = /bits/ 64 <1113600000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1190400000 { opp-hz = /bits/ 64 <1190400000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1228800000 { opp-hz = /bits/ 64 <1228800000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1324800000 { opp-hz = /bits/ 64 <1324800000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1401600000 { opp-hz = /bits/ 64 <1401600000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1478400000 { opp-hz = /bits/ 64 <1478400000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1593600000 { opp-hz = /bits/ 64 <1593600000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; }; @@ -232,127 +232,127 @@ cluster1_opp: opp-table-cluster1 { /* Nominal fmax for now */ opp-307200000 { opp-hz = /bits/ 64 <307200000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-403200000 { opp-hz = /bits/ 64 <403200000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-480000000 { opp-hz = /bits/ 64 <480000000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-556800000 { opp-hz = /bits/ 64 <556800000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-652800000 { opp-hz = /bits/ 64 <652800000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-729600000 { opp-hz = /bits/ 64 <729600000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-806400000 { opp-hz = /bits/ 64 <806400000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-883200000 { opp-hz = /bits/ 64 <883200000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-940800000 { opp-hz = /bits/ 64 <940800000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1036800000 { opp-hz = /bits/ 64 <1036800000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1113600000 { opp-hz = /bits/ 64 <1113600000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1190400000 { opp-hz = /bits/ 64 <1190400000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1248000000 { opp-hz = /bits/ 64 <1248000000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1324800000 { opp-hz = /bits/ 64 <1324800000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1401600000 { opp-hz = /bits/ 64 <1401600000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1478400000 { opp-hz = /bits/ 64 <1478400000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1555200000 { opp-hz = /bits/ 64 <1555200000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1632000000 { opp-hz = /bits/ 64 <1632000000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1708800000 { opp-hz = /bits/ 64 <1708800000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1785600000 { opp-hz = /bits/ 64 <1785600000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1824000000 { opp-hz = /bits/ 64 <1824000000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1920000000 { opp-hz = /bits/ 64 <1920000000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1996800000 { opp-hz = /bits/ 64 <1996800000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-2073600000 { opp-hz = /bits/ 64 <2073600000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-2150400000 { opp-hz = /bits/ 64 <2150400000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996pro.dtsi b/arch/arm64/boot/dts/qcom/msm8996pro.dtsi new file mode 100644 index 000000000000..63e1b4ec7a36 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8996pro.dtsi @@ -0,0 +1,266 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include "msm8996.dtsi" + +/ { + /delete-node/ opp-table-cluster0; + /delete-node/ opp-table-cluster1; + + /* + * On MSM8996 Pro the cpufreq driver shifts speed bins into the high + * nibble of supported hw, so speed bin 0 becomes 0x10, speed bin 1 + * becomes 0x20, speed 2 becomes 0x40. + */ + + cluster0_opp: opp-table-cluster0 { + compatible = "operating-points-v2-kryo-cpu"; + nvmem-cells = <&speedbin_efuse>; + opp-shared; + + opp-307200000 { + opp-hz = /bits/ 64 <307200000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-460800000 { + opp-hz = /bits/ 64 <460800000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-537600000 { + opp-hz = /bits/ 64 <537600000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-614400000 { + opp-hz = /bits/ 64 <614400000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-691200000 { + opp-hz = /bits/ 64 <691200000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-768000000 { + opp-hz = /bits/ 64 <768000000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-844800000 { + opp-hz = /bits/ 64 <844800000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-902400000 { + opp-hz = /bits/ 64 <902400000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-979200000 { + opp-hz = /bits/ 64 <979200000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1132800000 { + opp-hz = /bits/ 64 <1132800000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1209600000 { + opp-hz = /bits/ 64 <1209600000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1286400000 { + opp-hz = /bits/ 64 <1286400000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1363200000 { + opp-hz = /bits/ 64 <1363200000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1440000000 { + opp-hz = /bits/ 64 <1440000000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1593600000 { + opp-hz = /bits/ 64 <1593600000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1996800000 { + opp-hz = /bits/ 64 <1996800000>; + opp-supported-hw = <0x20>; + clock-latency-ns = <200000>; + }; + opp-2188800000 { + opp-hz = /bits/ 64 <2188800000>; + opp-supported-hw = <0x10>; + clock-latency-ns = <200000>; + }; + }; + + cluster1_opp: opp-table-cluster1 { + compatible = "operating-points-v2-kryo-cpu"; + nvmem-cells = <&speedbin_efuse>; + opp-shared; + + opp-307200000 { + opp-hz = /bits/ 64 <307200000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-460800000 { + opp-hz = /bits/ 64 <460800000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-537600000 { + opp-hz = /bits/ 64 <537600000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-614400000 { + opp-hz = /bits/ 64 <614400000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-691200000 { + opp-hz = /bits/ 64 <691200000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-748800000 { + opp-hz = /bits/ 64 <748800000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-825600000 { + opp-hz = /bits/ 64 <825600000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-902400000 { + opp-hz = /bits/ 64 <902400000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-979200000 { + opp-hz = /bits/ 64 <979200000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1132800000 { + opp-hz = /bits/ 64 <1132800000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1209600000 { + opp-hz = /bits/ 64 <1209600000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1286400000 { + opp-hz = /bits/ 64 <1286400000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1363200000 { + opp-hz = /bits/ 64 <1363200000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1440000000 { + opp-hz = /bits/ 64 <1440000000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1593600000 { + opp-hz = /bits/ 64 <1593600000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1670400000 { + opp-hz = /bits/ 64 <1670400000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1747200000 { + opp-hz = /bits/ 64 <1747200000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1824000000 { + opp-hz = /bits/ 64 <1824000000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1900800000 { + opp-hz = /bits/ 64 <1900800000>; + opp-supported-hw = <0x70>; + clock-latency-ns = <200000>; + }; + opp-1977600000 { + opp-hz = /bits/ 64 <1977600000>; + opp-supported-hw = <0x30>; + clock-latency-ns = <200000>; + }; + opp-2054400000 { + opp-hz = /bits/ 64 <2054400000>; + opp-supported-hw = <0x30>; + clock-latency-ns = <200000>; + }; + opp-2150400000 { + opp-hz = /bits/ 64 <2150400000>; + opp-supported-hw = <0x30>; + clock-latency-ns = <200000>; + }; + opp-2246400000 { + opp-hz = /bits/ 64 <2246400000>; + opp-supported-hw = <0x10>; + clock-latency-ns = <200000>; + }; + opp-2342400000 { + opp-hz = /bits/ 64 <2342400000>; + opp-supported-hw = <0x10>; + clock-latency-ns = <200000>; + }; + }; +}; From cea41be7ca66f0cdd0fa8e76ca799eed149d91c3 Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Sun, 24 Jul 2022 17:04:17 +0300 Subject: [PATCH 037/261] arm64: dts: qcom: msm8996-xiaomi-scorpio, natrium: Use MSM8996 Pro The Xiaomi Mi Note 2 has the MSM8996 Pro SoC. Rename the dts to match, include msm8996pro.dtsi, and add the qcom,msm8996pro compatible. To do that, the msm8996.dtsi include in msm8996-xiaomi-common has to be moved to msm8996-xiaomi-gemini, the only device that needs it included after this change. Since MSM8996Pro is largely compatible with MSM8996, keep old compatible too rather than insiting on qcom,msm8996pro only. This allows the code that doesn't yet know about msm8996pro to continue supporting these devices. [DB: Dropped msm-id changes.] Signed-off-by: Yassine Oudjana [DB: Applied the same change to Xiaomi Mi 5s Plus (natrium).] Signed-off-by: Dmitry Baryshkov Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220724140421.1933004-4-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/Makefile | 4 ++-- arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi | 3 --- arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts | 1 + ...m8996-xiaomi-natrium.dts => msm8996pro-xiaomi-natrium.dts} | 3 ++- ...m8996-xiaomi-scorpio.dts => msm8996pro-xiaomi-scorpio.dts} | 3 ++- 5 files changed, 7 insertions(+), 7 deletions(-) rename arch/arm64/boot/dts/qcom/{msm8996-xiaomi-natrium.dts => msm8996pro-xiaomi-natrium.dts} (99%) rename arch/arm64/boot/dts/qcom/{msm8996-xiaomi-scorpio.dts => msm8996pro-xiaomi-scorpio.dts} (99%) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index d7669a7cee9f..e984dba8575a 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -37,8 +37,8 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-dora.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-kagura.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-keyaki.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-xiaomi-gemini.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8996-xiaomi-natrium.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8996-xiaomi-scorpio.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8996pro-xiaomi-natrium.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8996pro-xiaomi-scorpio.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-asus-novago-tp370ql.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-fxtec-pro1.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-hp-envy-x2.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi index 78a1977d0593..d2637909a356 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi @@ -3,9 +3,6 @@ * Copyright (c) 2020, Yassine Oudjana */ -/dts-v1/; - -#include "msm8996.dtsi" #include "pm8994.dtsi" #include "pmi8994.dtsi" #include diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts index c8e84a934678..40f964ae80db 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include "msm8996.dtsi" #include "msm8996-xiaomi-common.dtsi" #include #include diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-natrium.dts b/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts similarity index 99% rename from arch/arm64/boot/dts/qcom/msm8996-xiaomi-natrium.dts rename to arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts index 7526f8f473b5..b18ee5c1f678 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-natrium.dts +++ b/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include "msm8996pro.dtsi" #include "msm8996-xiaomi-common.dtsi" #include "pmi8996.dtsi" #include @@ -12,7 +13,7 @@ / { model = "Xiaomi Mi 5s Plus"; - compatible = "xiaomi,natrium", "qcom,msm8996"; + compatible = "xiaomi,natrium", "qcom,msm8996pro", "qcom,msm8996"; chassis-type = "handset"; qcom,msm-id = <305 0x10000>; qcom,board-id = <47 0>; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts b/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-scorpio.dts similarity index 99% rename from arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts rename to arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-scorpio.dts index b751cbbf1a23..7bf6ad1a214b 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts +++ b/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-scorpio.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include "msm8996pro.dtsi" #include "msm8996-xiaomi-common.dtsi" #include "pmi8996.dtsi" #include @@ -13,7 +14,7 @@ / { model = "Xiaomi Mi Note 2"; - compatible = "xiaomi,scorpio", "qcom,msm8996"; + compatible = "xiaomi,scorpio", "qcom,msm8996pro", "qcom,msm8996"; chassis-type = "handset"; qcom,msm-id = <305 0x10000>; qcom,board-id = <34 0>; From 0154caaa2b748e7414a4ec3c6ee60e8f483b2d4f Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 24 Jul 2022 17:04:18 +0300 Subject: [PATCH 038/261] arm64: dts: qcom: msm8996: fix supported-hw in cpufreq OPP tables Adjust MSM8996 cpufreq tables according to tables in msm-3.18. Some of the frequencies are not supported on speed bins other than 0. Also other speed bins support intermediate topmost frequencies, not supported on speed bin 0. Implement all these differencies. Fixes: 90173a954a22 ("arm64: dts: qcom: msm8996: Add CPU opps") Signed-off-by: Dmitry Baryshkov Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220724140421.1933004-5-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 38 ++++++++++++++++++++------- 1 file changed, 29 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index c6c074a9ed32..cb5d461e482d 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -204,22 +204,32 @@ opp-1228800000 { }; opp-1324800000 { opp-hz = /bits/ 64 <1324800000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0x5>; + clock-latency-ns = <200000>; + }; + opp-1363200000 { + opp-hz = /bits/ 64 <1363200000>; + opp-supported-hw = <0x2>; clock-latency-ns = <200000>; }; opp-1401600000 { opp-hz = /bits/ 64 <1401600000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0x5>; clock-latency-ns = <200000>; }; opp-1478400000 { opp-hz = /bits/ 64 <1478400000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0x1>; + clock-latency-ns = <200000>; + }; + opp-1497600000 { + opp-hz = /bits/ 64 <1497600000>; + opp-supported-hw = <0x04>; clock-latency-ns = <200000>; }; opp-1593600000 { opp-hz = /bits/ 64 <1593600000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0x1>; clock-latency-ns = <200000>; }; }; @@ -330,29 +340,39 @@ opp-1785600000 { opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; + opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; + opp-supported-hw = <0x6>; + clock-latency-ns = <200000>; + }; opp-1824000000 { opp-hz = /bits/ 64 <1824000000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0x1>; + clock-latency-ns = <200000>; + }; + opp-1900800000 { + opp-hz = /bits/ 64 <1900800000>; + opp-supported-hw = <0x4>; clock-latency-ns = <200000>; }; opp-1920000000 { opp-hz = /bits/ 64 <1920000000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0x1>; clock-latency-ns = <200000>; }; opp-1996800000 { opp-hz = /bits/ 64 <1996800000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0x1>; clock-latency-ns = <200000>; }; opp-2073600000 { opp-hz = /bits/ 64 <2073600000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0x1>; clock-latency-ns = <200000>; }; opp-2150400000 { opp-hz = /bits/ 64 <2150400000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0x1>; clock-latency-ns = <200000>; }; }; From f1646de452ae8a9b858cefc2087c0ab93ac5c0ad Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 24 Jul 2022 17:04:19 +0300 Subject: [PATCH 039/261] arm64: dts: qcom: msm8996: add support for speed bin 3 Add support for msm8996, speed bin 3. It supports full range of frequencies on the power cluster, but is limited to 1.8 GHz on performance cluster. Signed-off-by: Dmitry Baryshkov Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220724140421.1933004-6-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 74 +++++++++++++-------------- 1 file changed, 37 insertions(+), 37 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index cb5d461e482d..8344e6b0493f 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -144,67 +144,67 @@ cluster0_opp: opp-table-cluster0 { /* Nominal fmax for now */ opp-307200000 { opp-hz = /bits/ 64 <307200000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0xf>; clock-latency-ns = <200000>; }; opp-422400000 { opp-hz = /bits/ 64 <422400000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0xf>; clock-latency-ns = <200000>; }; opp-480000000 { opp-hz = /bits/ 64 <480000000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0xf>; clock-latency-ns = <200000>; }; opp-556800000 { opp-hz = /bits/ 64 <556800000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0xf>; clock-latency-ns = <200000>; }; opp-652800000 { opp-hz = /bits/ 64 <652800000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0xf>; clock-latency-ns = <200000>; }; opp-729600000 { opp-hz = /bits/ 64 <729600000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0xf>; clock-latency-ns = <200000>; }; opp-844800000 { opp-hz = /bits/ 64 <844800000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0xf>; clock-latency-ns = <200000>; }; opp-960000000 { opp-hz = /bits/ 64 <960000000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0xf>; clock-latency-ns = <200000>; }; opp-1036800000 { opp-hz = /bits/ 64 <1036800000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0xf>; clock-latency-ns = <200000>; }; opp-1113600000 { opp-hz = /bits/ 64 <1113600000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0xf>; clock-latency-ns = <200000>; }; opp-1190400000 { opp-hz = /bits/ 64 <1190400000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0xf>; clock-latency-ns = <200000>; }; opp-1228800000 { opp-hz = /bits/ 64 <1228800000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0xf>; clock-latency-ns = <200000>; }; opp-1324800000 { opp-hz = /bits/ 64 <1324800000>; - opp-supported-hw = <0x5>; + opp-supported-hw = <0xd>; clock-latency-ns = <200000>; }; opp-1363200000 { @@ -214,12 +214,12 @@ opp-1363200000 { }; opp-1401600000 { opp-hz = /bits/ 64 <1401600000>; - opp-supported-hw = <0x5>; + opp-supported-hw = <0xd>; clock-latency-ns = <200000>; }; opp-1478400000 { opp-hz = /bits/ 64 <1478400000>; - opp-supported-hw = <0x1>; + opp-supported-hw = <0x9>; clock-latency-ns = <200000>; }; opp-1497600000 { @@ -229,7 +229,7 @@ opp-1497600000 { }; opp-1593600000 { opp-hz = /bits/ 64 <1593600000>; - opp-supported-hw = <0x1>; + opp-supported-hw = <0x9>; clock-latency-ns = <200000>; }; }; @@ -242,107 +242,107 @@ cluster1_opp: opp-table-cluster1 { /* Nominal fmax for now */ opp-307200000 { opp-hz = /bits/ 64 <307200000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0xf>; clock-latency-ns = <200000>; }; opp-403200000 { opp-hz = /bits/ 64 <403200000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0xf>; clock-latency-ns = <200000>; }; opp-480000000 { opp-hz = /bits/ 64 <480000000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0xf>; clock-latency-ns = <200000>; }; opp-556800000 { opp-hz = /bits/ 64 <556800000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0xf>; clock-latency-ns = <200000>; }; opp-652800000 { opp-hz = /bits/ 64 <652800000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0xf>; clock-latency-ns = <200000>; }; opp-729600000 { opp-hz = /bits/ 64 <729600000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0xf>; clock-latency-ns = <200000>; }; opp-806400000 { opp-hz = /bits/ 64 <806400000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0xf>; clock-latency-ns = <200000>; }; opp-883200000 { opp-hz = /bits/ 64 <883200000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0xf>; clock-latency-ns = <200000>; }; opp-940800000 { opp-hz = /bits/ 64 <940800000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0xf>; clock-latency-ns = <200000>; }; opp-1036800000 { opp-hz = /bits/ 64 <1036800000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0xf>; clock-latency-ns = <200000>; }; opp-1113600000 { opp-hz = /bits/ 64 <1113600000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0xf>; clock-latency-ns = <200000>; }; opp-1190400000 { opp-hz = /bits/ 64 <1190400000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0xf>; clock-latency-ns = <200000>; }; opp-1248000000 { opp-hz = /bits/ 64 <1248000000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0xf>; clock-latency-ns = <200000>; }; opp-1324800000 { opp-hz = /bits/ 64 <1324800000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0xf>; clock-latency-ns = <200000>; }; opp-1401600000 { opp-hz = /bits/ 64 <1401600000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0xf>; clock-latency-ns = <200000>; }; opp-1478400000 { opp-hz = /bits/ 64 <1478400000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0xf>; clock-latency-ns = <200000>; }; opp-1555200000 { opp-hz = /bits/ 64 <1555200000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0xf>; clock-latency-ns = <200000>; }; opp-1632000000 { opp-hz = /bits/ 64 <1632000000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0xf>; clock-latency-ns = <200000>; }; opp-1708800000 { opp-hz = /bits/ 64 <1708800000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0xf>; clock-latency-ns = <200000>; }; opp-1785600000 { opp-hz = /bits/ 64 <1785600000>; - opp-supported-hw = <0x7>; + opp-supported-hw = <0xf>; clock-latency-ns = <200000>; }; opp-1804800000 { opp-hz = /bits/ 64 <1804800000>; - opp-supported-hw = <0x6>; + opp-supported-hw = <0xe>; clock-latency-ns = <200000>; }; opp-1824000000 { From 0d440d811e6e2f37093e54db55bc27fe66678170 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 24 Jul 2022 17:04:20 +0300 Subject: [PATCH 040/261] arm64: dts: qcom: msm8996: fix GPU OPP table Fix Adreno OPP table according to the msm-3.18. Enable 624 MHz for the speed bin 3 and 560 MHz for bins 2 and 3. Fixes: 69cc3114ab0f ("arm64: dts: Add Adreno GPU definitions") Signed-off-by: Dmitry Baryshkov Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220724140421.1933004-7-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 8344e6b0493f..f7f55368fa28 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1233,17 +1233,17 @@ gpu_opp_table: opp-table { compatible = "operating-points-v2"; /* - * 624Mhz and 560Mhz are only available on speed - * bin (1 << 0). All the rest are available on - * all bins of the hardware + * 624Mhz is only available on speed bins 0 and 3. + * 560Mhz is only available on speed bins 0, 2 and 3. + * All the rest are available on all bins of the hardware. */ opp-624000000 { opp-hz = /bits/ 64 <624000000>; - opp-supported-hw = <0x01>; + opp-supported-hw = <0x09>; }; opp-560000000 { opp-hz = /bits/ 64 <560000000>; - opp-supported-hw = <0x01>; + opp-supported-hw = <0x0d>; }; opp-510000000 { opp-hz = /bits/ 64 <510000000>; From 1ae55caf9e93b9b24aab6bc81524bc33f11b3dd9 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 24 Jul 2022 17:04:21 +0300 Subject: [PATCH 041/261] arm64: dts: qcom: msm8996pro: expand Adreno OPP table There are minor differeces between msm8996 and msm8996pro in terms of GPU frequencies support. For example msm8996pro supports 652.8 MHz frequency for the Adreno. Reclect these differences in msm8996pro.dtsi. Signed-off-by: Dmitry Baryshkov Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220724140421.1933004-8-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/msm8996pro.dtsi | 25 ++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996pro.dtsi b/arch/arm64/boot/dts/qcom/msm8996pro.dtsi index 63e1b4ec7a36..a679a9c0cf99 100644 --- a/arch/arm64/boot/dts/qcom/msm8996pro.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996pro.dtsi @@ -264,3 +264,28 @@ opp-2342400000 { }; }; }; + +&gpu_opp_table { + /* + * Unlike CPU opp tables, the GPU driver does not shift speed bins. + * + * 652.8 Mhz is available on speed bin 0 only. + * 624 Mhz and 560 Mhz are available on speed bins 0 and 1. + * All the rest are available on all bins of the hardware (like on + * plain 8996). + */ + + opp-652800000 { + opp-hz = /bits/ 64 <652800000>; + opp-supported-hw = <0x01>; + }; + opp-624000000 { + opp-hz = /bits/ 64 <624000000>; + opp-supported-hw = <0x03>; + }; + opp-560000000 { + opp-hz = /bits/ 64 <560000000>; + opp-supported-hw = <0x03>; + }; + /* The rest is inherited from msm8996 */ +}; From 887ac08946cc0f2a2b915140fcf8d4365ca9393d Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Fri, 19 Aug 2022 00:02:45 +0200 Subject: [PATCH 042/261] arm64: dts: qcom: ipq8074: add thermal nodes IPQ8074 has a tsens v2.3.0 peripheral which monitors temperatures around the various subsystems on the die. So lets add the tsens and thermal zone nodes, passive CPU cooling will come in later patches after CPU frequency scaling is supported. Signed-off-by: Robert Marko Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220818220245.338396-5-robimarko@gmail.com --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 96 +++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 51815d0861d4..a425850eb00b 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -273,6 +273,16 @@ prng: rng@e3000 { status = "disabled"; }; + tsens: thermal-sensor@4a9000 { + compatible = "qcom,ipq8074-tsens"; + reg = <0x4a9000 0x1000>, /* TM */ + <0x4a8000 0x1000>; /* SROT */ + interrupts = ; + interrupt-names = "combined"; + #qcom,sensors = <16>; + #thermal-sensor-cells = <1>; + }; + cryptobam: dma-controller@704000 { compatible = "qcom,bam-v1.7.0"; reg = <0x00704000 0x20000>; @@ -873,4 +883,90 @@ timer { , ; }; + + thermal-zones { + nss-top-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 4>; + }; + + nss0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 5>; + }; + + nss1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 6>; + }; + + wcss-phya0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 7>; + }; + + wcss-phya1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 8>; + }; + + cpu0_thermal: cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 9>; + }; + + cpu1_thermal: cpu1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 10>; + }; + + cpu2_thermal: cpu2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 11>; + }; + + cpu3_thermal: cpu3-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 12>; + }; + + cluster_thermal: cluster-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 13>; + }; + + wcss-phyb0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 14>; + }; + + wcss-phyb1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 15>; + }; + }; }; From fd8bdb451c6541b40e5977defcfebfe51713a538 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Fri, 19 Aug 2022 00:08:49 +0200 Subject: [PATCH 043/261] arm64: dts: qcom: ipq8074: add clocks to APCS APCS now has support for providing the APSS clocks as the child device for IPQ8074. So, add the A53 PLL and XO clocks in order to use APCS as the CPU clocksource for APSS scaling. Signed-off-by: Robert Marko Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220818220849.339732-4-robimarko@gmail.com --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index ab9e7a46d566..d3d9e7eb5837 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -679,6 +679,8 @@ watchdog: watchdog@b017000 { apcs_glb: mailbox@b111000 { compatible = "qcom,ipq8074-apcs-apps-global"; reg = <0x0b111000 0x1000>; + clocks = <&a53pll>, <&xo>; + clock-names = "pll", "xo"; #clock-cells = <1>; #mbox-cells = <1>; From 01da7baf018c4977a260b40e7e6978133c9ef824 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Fri, 19 Aug 2022 00:18:14 +0200 Subject: [PATCH 044/261] arm64: dts: qcom: add PMP8074 DTSI PMP8074 is a companion PMIC to the Qualcomm IPQ8074 series that is controlled via SPMI. Add DTSI for it providing GPIO, regulator, RTC and VADC support. RTC is disabled by default as there is no built-in battery so it will loose time unless board vendor added a battery, so make it optional. Signed-off-by: Robert Marko Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220818221815.346233-4-robimarko@gmail.com --- arch/arm64/boot/dts/qcom/pmp8074.dtsi | 125 ++++++++++++++++++++++++++ 1 file changed, 125 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pmp8074.dtsi diff --git a/arch/arm64/boot/dts/qcom/pmp8074.dtsi b/arch/arm64/boot/dts/qcom/pmp8074.dtsi new file mode 100644 index 000000000000..ceb2e6358b3d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmp8074.dtsi @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause + +#include +#include + +&spmi_bus { + pmic@0 { + compatible = "qcom,pmp8074", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmp8074_adc: adc@3100 { + compatible = "qcom,spmi-adc-rev2"; + reg = <0x3100>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + ref-gnd@0 { + reg = ; + qcom,pre-scaling = <1 1>; + }; + + vref-1p25@1 { + reg = ; + qcom,pre-scaling = <1 1>; + }; + + vref-vadc@2 { + reg = ; + qcom,pre-scaling = <1 1>; + }; + + pmic_die: die-temp@6 { + reg = ; + qcom,pre-scaling = <1 1>; + }; + + xo_therm: xo-temp@76 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm1: thermistor1@77 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm2: thermistor2@78 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm3: thermistor3@79 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + vph-pwr@131 { + reg = ; + qcom,pre-scaling = <1 3>; + }; + }; + + pmp8074_rtc: rtc@6000 { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + allow-set-time; + status = "disabled"; + }; + + pmp8074_gpios: gpio@c000 { + compatible = "qcom,pmp8074-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmp8074_gpios 0 0 12>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmic@1 { + compatible = "qcom,pmp8074", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + + regulators { + compatible = "qcom,pmp8074-regulators"; + + s3: s3 { + regulator-name = "vdd_s3"; + regulator-min-microvolt = <592000>; + regulator-max-microvolt = <1064000>; + regulator-always-on; + regulator-boot-on; + }; + + s4: s4 { + regulator-name = "vdd_s4"; + regulator-min-microvolt = <712000>; + regulator-max-microvolt = <992000>; + regulator-always-on; + regulator-boot-on; + }; + + l11: l11 { + regulator-name = "l11"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; From 378c2064264e18b61922c388c09faba544ce7a15 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Fri, 19 Aug 2022 00:18:15 +0200 Subject: [PATCH 045/261] arm64: dts: qcom: ipq8074-hk01: add VQMMC supply Since now we have control over the PMP8074 PMIC providing various system voltages including L11 which provides the SDIO/eMMC I/O voltage set it as the SDHCI VQMMC supply. This allows SDHCI controller to switch to 1.8V I/O mode and support high speed modes like HS200 and HS400. Signed-off-by: Robert Marko Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220818221815.346233-5-robimarko@gmail.com --- arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts index 7143c936de61..b60b2d4c2ea5 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts @@ -3,6 +3,7 @@ /* Copyright (c) 2017, The Linux Foundation. All rights reserved. */ #include "ipq8074.dtsi" +#include "pmp8074.dtsi" / { model = "Qualcomm Technologies, Inc. IPQ8074-HK01"; @@ -84,6 +85,7 @@ nand@0 { &sdhc_1 { status = "okay"; + vqmmc-supply = <&l11>; }; &qusb_phy_0 { From 780f836fe071a9e8703fe6a05ae00129acf83391 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 10 Oct 2022 07:44:12 -0400 Subject: [PATCH 046/261] arm64: dts: qcom: sdm630: fix UART1 pin bias There is no "bias-no-pull" property. Assume intentions were disabling bias. Fixes: b190fb010664 ("arm64: dts: qcom: sdm630: Add sdm630 dts file") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221010114417.29859-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index bff80e795dad..2d3fdbfef8a6 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -779,7 +779,7 @@ rx-cts-rts { pins = "gpio17", "gpio18", "gpio19"; function = "gpio"; drive-strength = <2>; - bias-no-pull; + bias-disable; }; }; From 9905370560d9c29adc15f4937c5a0c0dac05f0b4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 10 Oct 2022 07:44:13 -0400 Subject: [PATCH 047/261] arm64: dts: qcom: sdm845-db845c: correct SPI2 pins drive strength The pin configuration (done with generic pin controller helpers and as expressed by bindings) requires children nodes with either: 1. "pins" property and the actual configuration, 2. another set of nodes with above point. The qup_spi2_default pin configuration uses alreaady the second method with a "pinmux" child, so configure drive-strength similarly in "pinconf". Otherwise the PIN drive strength would not be applied. Fixes: 8d23a0040475 ("arm64: dts: qcom: db845c: add Low speed expansion i2c and spi nodes") Cc: Signed-off-by: Krzysztof Kozlowski Reviewed-by: Douglas Anderson Reviewed-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221010114417.29859-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 2110a5893149..8ee512056da6 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -1123,7 +1123,10 @@ &wifi { /* PINCTRL - additions to nodes defined in sdm845.dtsi */ &qup_spi2_default { - drive-strength = <16>; + pinconf { + pins = "gpio27", "gpio28", "gpio29", "gpio30"; + drive-strength = <16>; + }; }; &qup_uart3_default{ From 9bce41fab14da8f21027dc9847535ef5e22cbe8b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 10 Oct 2022 07:44:14 -0400 Subject: [PATCH 048/261] arm64: dts: qcom: sdm845-cheza: fix AP suspend pin bias There is no "bias-no-pull" property. Assume intentions were disabling bias. Fixes: 79e7739f7b87 ("arm64: dts: qcom: sdm845-cheza: add initial cheza dt") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221010114417.29859-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi index b5eb8f7eca1d..b5f11fbcc300 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -1436,7 +1436,7 @@ ap_suspend_l_assert: ap_suspend_l_assert { config { pins = "gpio126"; function = "gpio"; - bias-no-pull; + bias-disable; drive-strength = <2>; output-low; }; @@ -1446,7 +1446,7 @@ ap_suspend_l_deassert: ap_suspend_l_deassert { config { pins = "gpio126"; function = "gpio"; - bias-no-pull; + bias-disable; drive-strength = <2>; output-high; }; From 37eac5a5fe27b1ab189d12064ffdd7db42f26900 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 8 Oct 2022 20:17:13 +0200 Subject: [PATCH 049/261] arm64: dts: qcom: sm8250-edo: Add NXP PN553 NFC Add a node for NXP PN553 NFC, using the nxp-nci driver. Signed-off-by: Konrad Dybcio Tested-by: Marijn Suijten Reviewed-by: Marijn Suijten Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221008181714.253634-1-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi index 601a21c381f8..4f9cf5401e2e 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -434,7 +434,16 @@ &i2c1 { status = "okay"; clock-frequency = <400000>; - /* NXP PN553 NFC @ 28 */ + nfc@28 { + compatible = "nxp,nxp-nci-i2c"; + reg = <0x28>; + + interrupt-parent = <&tlmm>; + interrupts = <111 IRQ_TYPE_EDGE_RISING>; + + enable-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; + firmware-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; + }; }; &i2c2 { From c24c9d53e001a38ac1637674304987ab061a38eb Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 19 Sep 2022 18:33:33 +0200 Subject: [PATCH 050/261] arm64: dts: qcom: correct white-space before { Add missing space or remove redundant one before opening {. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220919163333.129989-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8998.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 4 ++-- arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 6 +++--- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 8 ++++---- arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 4 ++-- arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts | 6 +++--- 10 files changed, 25 insertions(+), 25 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index f7f55368fa28..efba641f3d67 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1522,7 +1522,7 @@ blsp2_i2c3_sleep: blsp2-i2c3-sleep { bias-disable; }; - wcd_intr_default: wcd-intr-default{ + wcd_intr_default: wcd-intr-default { pins = "gpio54"; function = "gpio"; drive-strength = <2>; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index f05f16ac5cc1..f150bae67b74 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -1903,7 +1903,7 @@ etm5: etm@7c40000 { cpu = <&CPU4>; - port{ + port { etm4_out: endpoint { remote-endpoint = <&apss_funnel_in4>; }; @@ -1920,7 +1920,7 @@ etm6: etm@7d40000 { cpu = <&CPU5>; - port{ + port { etm5_out: endpoint { remote-endpoint = <&apss_funnel_in5>; }; @@ -1937,7 +1937,7 @@ etm7: etm@7e40000 { cpu = <&CPU6>; - port{ + port { etm6_out: endpoint { remote-endpoint = <&apss_funnel_in6>; }; @@ -1954,7 +1954,7 @@ etm8: etm@7f40000 { cpu = <&CPU7>; - port{ + port { etm7_out: endpoint { remote-endpoint = <&apss_funnel_in7>; }; diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 69dda5ed7692..2c0850016cc4 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -1007,7 +1007,7 @@ can@0 { }; &swr0 { - left_spkr: wsa8810-left{ + left_spkr: wsa8810-left { compatible = "sdw10217211000"; reg = <0 3>; powerdown-gpios = <&tlmm 130 GPIO_ACTIVE_HIGH>; @@ -1016,7 +1016,7 @@ left_spkr: wsa8810-left{ #sound-dai-cells = <0>; }; - right_spkr: wsa8810-right{ + right_spkr: wsa8810-right { compatible = "sdw10217211000"; reg = <0 4>; powerdown-gpios = <&tlmm 130 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi index 7ee407f7b6bb..1ce73187a562 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi @@ -181,7 +181,7 @@ &sound_multimedia0_codec { /* PINCTRL - modifications to sc7180-trogdor.dtsi */ &en_pp3300_dx_edp { - pinmux { + pinmux { pins = "gpio67"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi index 1bd6c7dcd9e9..7fcff4eddd3a 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi @@ -189,7 +189,7 @@ pinconf { }; }; -&sec_mi2s_active{ +&sec_mi2s_active { pinmux { pins = "gpio49", "gpio50", "gpio51", "gpio52"; function = "mi2s_1"; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index eae22e6e97c1..1a1c346d619c 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -1238,7 +1238,7 @@ pinconf { }; ap_suspend_l_neuter: ap-suspend-l-neuter { - pinmux { + pinmux { pins = "gpio27"; function = "gpio"; }; @@ -1383,7 +1383,7 @@ pinconf { }; pen_rst_odl: pen-rst-odl { - pinmux { + pinmux { pins = "gpio18"; function = "gpio"; }; @@ -1507,7 +1507,7 @@ pinconf { }; ts_int_l: ts-int-l { - pinmux { + pinmux { pins = "gpio9"; function = "gpio"; }; @@ -1519,7 +1519,7 @@ pinconf { }; ts_reset_l: ts-reset-l { - pinmux { + pinmux { pins = "gpio8"; function = "gpio"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi index b5f11fbcc300..5eafb556cc0c 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -1341,7 +1341,7 @@ pinconf { }; pen_rst_l: pen-rst-l { - pinmux { + pinmux { pins = "gpio23"; function = "gpio"; }; @@ -1408,7 +1408,7 @@ pinconf { }; ts_int_l: ts-int-l { - pinmux { + pinmux { pins = "gpio125"; function = "gpio"; }; @@ -1420,7 +1420,7 @@ pinconf { }; ts_reset_l: ts-reset-l { - pinmux { + pinmux { pins = "gpio118"; function = "gpio"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 8ee512056da6..72d26ceb4baf 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -1076,7 +1076,7 @@ &venus { status = "okay"; }; -&wcd9340{ +&wcd9340 { pinctrl-0 = <&wcd_intr_default>; pinctrl-names = "default"; clock-names = "extclk"; @@ -1089,7 +1089,7 @@ &wcd9340{ vdd-io-supply = <&vreg_s4a_1p8>; swm: swm@c85 { - left_spkr: wsa8810-left{ + left_spkr: wsa8810-left { compatible = "sdw10217201000"; reg = <0 1>; powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>; @@ -1098,7 +1098,7 @@ left_spkr: wsa8810-left{ #sound-dai-cells = <0>; }; - right_spkr: wsa8810-right{ + right_spkr: wsa8810-right { compatible = "sdw10217201000"; powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>; reg = <0 2>; @@ -1129,7 +1129,7 @@ pinconf { }; }; -&qup_uart3_default{ +&qup_uart3_default { pinmux { pins = "gpio41", "gpio42", "gpio43", "gpio44"; function = "qup3"; diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index 74f43da51fa5..0c375ec795b8 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -785,7 +785,7 @@ &wcd9340{ qcom,mbhc-headphone-vthreshold-microvolt = <50000>; swm: swm@c85 { - left_spkr: wsa8810-left{ + left_spkr: wsa8810-left { compatible = "sdw10217211000"; reg = <0 3>; powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>; @@ -794,7 +794,7 @@ left_spkr: wsa8810-left{ #sound-dai-cells = <0>; }; - right_spkr: wsa8810-right{ + right_spkr: wsa8810-right { compatible = "sdw10217211000"; powerdown-gpios = <&wcdgpio 2 GPIO_ACTIVE_HIGH>; reg = <0 4>; diff --git a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts index d028a7eb364a..dfa4857d705c 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts @@ -576,7 +576,7 @@ pinconf { }; pen_rst_l: pen-rst-l { - pinmux { + pinmux { pins = "gpio21"; function = "gpio"; }; @@ -717,7 +717,7 @@ &wcd9340{ qcom,mbhc-headphone-vthreshold-microvolt = <50000>; swm: swm@c85 { - left_spkr: wsa8810-left{ + left_spkr: wsa8810-left { compatible = "sdw10217211000"; reg = <0 3>; powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>; @@ -726,7 +726,7 @@ left_spkr: wsa8810-left{ #sound-dai-cells = <0>; }; - right_spkr: wsa8810-right{ + right_spkr: wsa8810-right { compatible = "sdw10217211000"; powerdown-gpios = <&wcdgpio 2 GPIO_ACTIVE_HIGH>; reg = <0 4>; From ff02ac621634e82c0c34d02a79d402ae700cdfd0 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 18 Jul 2022 16:03:40 +0200 Subject: [PATCH 051/261] arm64: dts: qcom: msm8916: Drop MSS fallback compatible MSM8916 was originally using the "qcom,q6v5-pil" compatible for the MSS remoteproc. Later it was decided to use SoC-specific compatibles instead, so "qcom,msm8916-mss-pil" is now the preferred compatible. Commit 60a05ed059a0 ("arm64: dts: qcom: msm8916: Add MSM8916-specific compatibles to SCM/MSS") updated the MSM8916 device tree to make use of the new compatible but still kept the old "qcom,q6v5-pil" as fallback. This is inconsistent with other SoCs and conflicts with the description in the binding documentation (which says that only one compatible should be present). Also, it has no functional advantage since older kernels could not handle this DT anyway (e.g. "power-domains" in the MSS node is only supported by kernels that also support "qcom,msm8916-mss-pil"). Make this consistent with other SoCs by using only the "qcom,msm8916-mss-pil" compatible. Fixes: 60a05ed059a0 ("arm64: dts: qcom: msm8916: Add MSM8916-specific compatibles to SCM/MSS") Signed-off-by: Stephan Gerhold Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220718140344.1831731-2-stephan.gerhold@kernkonzept.com --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index a831064700ee..9743cb270639 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1345,7 +1345,7 @@ bam_dmux_dma: dma-controller@4044000 { }; mpss: remoteproc@4080000 { - compatible = "qcom,msm8916-mss-pil", "qcom,q6v5-pil"; + compatible = "qcom,msm8916-mss-pil"; reg = <0x04080000 0x100>, <0x04020000 0x040>; From d6838f267f16189a8c1954a7a6bfa36fb79896f7 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 9 Aug 2022 22:54:21 -0500 Subject: [PATCH 052/261] arm64: dts: qcom: sdm845: switch usb_1 phy to use combo usb+dp phy Change sdm845's usb_1_qmpphy to use combo usb+dp phy bindings, rather than just usb phy. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220810035424.2796777-2-bjorn.andersson@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 0387e9b86211..54d920b70385 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -3959,9 +3959,10 @@ usb_2_hsphy: phy@88e3000 { }; usb_1_qmpphy: phy@88e9000 { - compatible = "qcom,sdm845-qmp-usb3-phy"; + compatible = "qcom,sdm845-qmp-usb3-dp-phy"; reg = <0 0x088e9000 0 0x18c>, - <0 0x088e8000 0 0x10>; + <0 0x088e8000 0 0x38>, + <0 0x088ea000 0 0x40>; status = "disabled"; #address-cells = <2>; #size-cells = <2>; @@ -3973,11 +3974,11 @@ usb_1_qmpphy: phy@88e9000 { <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; clock-names = "aux", "cfg_ahb", "ref", "com_aux"; - resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, - <&gcc GCC_USB3_PHY_PRIM_BCR>; + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; reset-names = "phy", "common"; - usb_1_ssphy: phy@88e9200 { + usb_1_ssphy: usb3-phy@88e9200 { reg = <0 0x088e9200 0 0x128>, <0 0x088e9400 0 0x200>, <0 0x088e9c00 0 0x218>, @@ -3990,6 +3991,16 @@ usb_1_ssphy: phy@88e9200 { clock-names = "pipe0"; clock-output-names = "usb3_phy_pipe_clk_src"; }; + + dp_phy: dp-phy@88ea200 { + reg = <0 0x088ea200 0 0x200>, + <0 0x088ea400 0 0x200>, + <0 0x088eaa00 0 0x200>, + <0 0x088ea600 0 0x200>, + <0 0x088ea800 0 0x200>; + #clock-cells = <1>; + #phy-cells = <0>; + }; }; usb_2_qmpphy: phy@88eb000 { @@ -4812,8 +4823,8 @@ dispcc: clock-controller@af00000 { <&dsi0_phy 1>, <&dsi1_phy 0>, <&dsi1_phy 1>, - <0>, - <0>; + <&dp_phy 0>, + <&dp_phy 1>; clock-names = "bi_tcxo", "gcc_disp_gpll0_clk_src", "gcc_disp_gpll0_div_clk_src", From eaac4e55a6f419541da4983cd6d36f5d5de658ec Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 9 Aug 2022 22:54:22 -0500 Subject: [PATCH 053/261] arm64: dts: qcom: sdm845: add displayport node Add displayport controller device node, describing DisplayPort hardware block on SDM845. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220810035424.2796777-3-bjorn.andersson@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 82 +++++++++++++++++++++++++++- 1 file changed, 80 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 54d920b70385..5a907b2819f0 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4494,13 +4494,20 @@ ports { port@0 { reg = <0>; - dpu_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; + dpu_intf0_out: endpoint { + remote-endpoint = <&dp_in>; }; }; port@1 { reg = <1>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@2 { + reg = <2>; dpu_intf2_out: endpoint { remote-endpoint = <&dsi1_in>; }; @@ -4532,6 +4539,77 @@ opp-430000000 { }; }; + mdss_dp: displayport-controller@ae90000 { + status = "disabled"; + compatible = "qcom,sdm845-dp"; + + reg = <0 0xae90000 0 0x200>, + <0 0xae90200 0 0x200>, + <0 0xae90400 0 0x600>, + <0 0xae90a00 0 0x600>, + <0 0xae91000 0 0x600>; + + interrupt-parent = <&mdss>; + interrupts = <12>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + clock-names = "core_iface", "core_aux", "ctrl_link", + "ctrl_link_iface", "stream_pixel"; + #clock-cells = <1>; + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; + phys = <&dp_phy>; + phy-names = "dp"; + + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd SDM845_CX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + dp_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + dp_out: endpoint { }; + }; + }; + + dp_opp_table: dp-opp-table { + compatible = "operating-points-v2"; + + opp-162000000 { + opp-hz = /bits/ 64 <162000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + dsi0: dsi@ae94000 { compatible = "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae94000 0 0x400>; From 185d192d0a7b565a24b3f7456a2f84f169ab087a Mon Sep 17 00:00:00 2001 From: Yunlong Jia Date: Thu, 1 Sep 2022 02:49:57 +0000 Subject: [PATCH 054/261] dt-bindings: arm: qcom: Document additional skus for sc7180 pazquel360 pazquel360 is an extension project based on pazquel. We create 3 sku on pazquel360: sku 20 for LTE with physical SIM _and_ eSIM and WiFi sku 21 for WiFi only sku 22 for LTE with only a physical SIM Both sku20 and sku22 are LTE SKUs. One has the eSIM stuffed and one doesn't. There is a single shared device tree for the two. Signed-off-by: Yunlong Jia Acked-by: Krzysztof Kozlowski Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220901024827.v3.1.I3aa360986c0e7377ea5e96c116f014ff1ab8c968@changeid --- Documentation/devicetree/bindings/arm/qcom.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 3514cd30718c..2c217478836c 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -468,6 +468,17 @@ properties: - const: google,pazquel-sku2 - const: qcom,sc7180 + - description: Google Pazquel360 with LTE (newest rev) + items: + - const: google,pazquel-sku22 + - const: google,pazquel-sku20 + - const: qcom,sc7180 + + - description: Google Pazquel360 with WiFi (newest rev) + items: + - const: google,pazquel-sku21 + - const: qcom,sc7180 + - description: Sharp Dynabook Chromebook C1 (rev1) items: - const: google,pompom-rev1 From 2f72a4f54cdb4fd0ebea9a2dea65756d3e676be2 Mon Sep 17 00:00:00 2001 From: Yunlong Jia Date: Thu, 1 Sep 2022 02:49:58 +0000 Subject: [PATCH 055/261] arm64: dts: qcom: Add sc7180-pazquel360 Create first version device tree for pazquel360 pazquel360 is convertible and the pazquel it is based on is clamshell. sku 20 for lte & wifi sku 21 for wifi only sku 22 for lte w/o esim & wifi Signed-off-by: Yunlong Jia Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220901024827.v3.2.Iea2d2918adfff2825b87d428b5732717425c196f@changeid --- arch/arm64/boot/dts/qcom/Makefile | 2 + .../qcom/sc7180-trogdor-pazquel360-lte.dts | 22 ++++++++ .../qcom/sc7180-trogdor-pazquel360-wifi.dts | 17 +++++++ .../dts/qcom/sc7180-trogdor-pazquel360.dtsi | 50 +++++++++++++++++++ 4 files changed, 91 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360-lte.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360-wifi.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index e984dba8575a..04f4fa66f966 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -87,6 +87,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-lte-parade.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-lte-ti.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-parade.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-ti.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel360-lte.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel360-wifi.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r2.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360-lte.dts new file mode 100644 index 000000000000..021bcafcf815 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360-lte.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Pazquel board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180-trogdor.dtsi" +#include "sc7180-trogdor-parade-ps8640.dtsi" +#include "sc7180-trogdor-pazquel360.dtsi" +#include "sc7180-trogdor-lte-sku.dtsi" + +/ { + model = "Google Pazquel (Parade,LTE)"; + compatible = "google,pazquel-sku22", "google,pazquel-sku20", "qcom,sc7180"; +}; + +&ap_sar_sensor_i2c { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360-wifi.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360-wifi.dts new file mode 100644 index 000000000000..defd84c5354a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360-wifi.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Pazquel board device tree source + * + * Copyright 2022 Google LLC. + */ + +/dts-v1/; + +#include "sc7180-trogdor.dtsi" +#include "sc7180-trogdor-parade-ps8640.dtsi" +#include "sc7180-trogdor-pazquel360.dtsi" + +/ { + model = "Google Pazquel (Parade,WIFI-only)"; + compatible = "google,pazquel-sku21", "qcom,sc7180"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360.dtsi new file mode 100644 index 000000000000..5702325d0c7b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360.dtsi @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Pazquel board device tree source + * + * Copyright 2021 Google LLC. + */ + +/* This file must be included after sc7180-trogdor.dtsi */ +#include "sc7180-trogdor-pazquel.dtsi" + +&alc5682 { + compatible = "realtek,rt5682s"; + realtek,dmic1-clk-pin = <2>; + realtek,dmic-clk-rate-hz = <2048000>; +}; + +&keyboard_controller { + function-row-physmap = < + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + MATRIX_KEY(0x03, 0x09, 0) /* T11 */ + >; + linux,keymap = < + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) + MATRIX_KEY(0x01, 0x02, KEY_SCALE) + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x02, 0x09, KEY_MUTE) + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) + MATRIX_KEY(0x03, 0x09, KEY_SLEEP) + CROS_STD_MAIN_KEYMAP + >; +}; + +&sound { + compatible = "google,sc7180-trogdor"; + model = "sc7180-rt5682s-max98357a-1mic"; +}; From b318c53e9c383b26d7972175e8ca60dc3552b4d2 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Thu, 1 Sep 2022 10:35:04 +0300 Subject: [PATCH 056/261] arm64: dts: qcom: sm8450: Add description of camera control interfaces Add description of two CCI controllers found on QCOM SM8450. Signed-off-by: Vladimir Zapolskiy Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220901073504.3077363-1-vladimir.zapolskiy@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 142 +++++++++++++++++++++++++++ 1 file changed, 142 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index d32f08df743d..7569ef1339a9 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2307,6 +2307,84 @@ IPCC_MPROC_SIGNAL_GLINK_QMP }; }; + cci0: cci@ac15000 { + compatible = "qcom,sm8450-cci"; + reg = <0 0xac15000 0 0x1000>; + interrupts = ; + power-domains = <&camcc TITAN_TOP_GDSC>; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_0_CLK>, + <&camcc CAM_CC_CCI_0_CLK_SRC>; + clock-names = "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci", + "cci_src"; + pinctrl-0 = <&cci0_default &cci1_default>; + pinctrl-1 = <&cci0_sleep &cci1_sleep>; + pinctrl-names = "default", "sleep"; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + + cci0_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci1: cci@ac16000 { + compatible = "qcom,sm8450-cci"; + reg = <0 0xac16000 0 0x1000>; + interrupts = ; + power-domains = <&camcc TITAN_TOP_GDSC>; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_1_CLK>, + <&camcc CAM_CC_CCI_1_CLK_SRC>; + clock-names = "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci", + "cci_src"; + pinctrl-0 = <&cci2_default &cci3_default>; + pinctrl-1 = <&cci2_sleep &cci3_sleep>; + pinctrl-names = "default", "sleep"; + + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + + cci1_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci1_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + camcc: clock-controller@ade0000 { compatible = "qcom,sm8450-camcc"; reg = <0 0x0ade0000 0 0x20000>; @@ -2404,6 +2482,70 @@ data-pins { }; }; + cci0_default: cci0-default-state { + /* SDA, SCL */ + pins = "gpio110", "gpio111"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci0_sleep: cci0-sleep-state { + /* SDA, SCL */ + pins = "gpio110", "gpio111"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci1_default: cci1-default-state { + /* SDA, SCL */ + pins = "gpio112", "gpio113"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci1_sleep: cci1-sleep-state { + /* SDA, SCL */ + pins = "gpio112", "gpio113"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci2_default: cci2-default-state { + /* SDA, SCL */ + pins = "gpio114", "gpio115"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci2_sleep: cci2-sleep-state { + /* SDA, SCL */ + pins = "gpio114", "gpio115"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci3_default: cci3-default-state { + /* SDA, SCL */ + pins = "gpio208", "gpio209"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci3_sleep: cci3-sleep-state { + /* SDA, SCL */ + pins = "gpio208", "gpio209"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + pcie0_default_state: pcie0-default-state { perst-pins { pins = "gpio94"; From c50e30b7e2614d140929280377337ec01bdbdc84 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Thu, 1 Sep 2022 10:29:50 -0700 Subject: [PATCH 057/261] arm64: dts: qcom: sc7180: Configure USB as wakeup source The dwc3 USB controller of the sc7180 supports USB remote wakeup, configure it as a wakeup source. Signed-off-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220901102946.v2.1.I347ea409ee3134bd32a29e33fecd1a6ef32085a0@changeid --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index f59692213745..78afbf4096cf 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2784,6 +2784,8 @@ usb_1: usb@a6f8800 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>; interconnect-names = "usb-ddr", "apps-usb"; + wakeup-source; + usb_1_dwc3: usb@a600000 { compatible = "snps,dwc3"; reg = <0 0x0a600000 0 0xe000>; From 3b08e3fdf056cf30ecb1413d2bcb1353a333024b Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Tue, 6 Sep 2022 21:45:33 +0530 Subject: [PATCH 058/261] arm64: dts: qcom: sc7280: Update SNPS Phy params for SC7280 IDP device Overriding the SNPS Phy tuning parameters for SC7280 IDP device. Signed-off-by: Krishna Kurapati Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1662480933-12326-4-git-send-email-quic_kriskura@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 11982c14b704..4884647a8a95 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -522,6 +522,12 @@ &usb_1_hsphy { vdda-pll-supply = <&vreg_l10c_0p8>; vdda33-supply = <&vreg_l2b_3p0>; vdda18-supply = <&vreg_l1c_1p8>; + qcom,hs-rise-fall-time-bp = <0>; + qcom,squelch-detector-bp = <(-2090)>; + qcom,hs-disconnect-bp = <1743>; + qcom,hs-amplitude-bp = <1780>; + qcom,hs-crossover-voltage-microvolt = <(-31000)>; + qcom,hs-output-impedance-micro-ohms = <2600000>; }; &usb_1_qmpphy { From da4a7c1431d656889c265d7fafaf3d6beaa05c1a Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Wed, 7 Sep 2022 01:00:58 +0100 Subject: [PATCH 059/261] arm64: dts: qcom: msm8916: Drop redundant phy-names from DSI controller phy-names has been marked deprecated. Remove it from the msm8916 DSI controller block. Signed-off-by: Bryan O'Donoghue Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220907000105.786265-5-bryan.odonoghue@linaro.org --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 9743cb270639..fca66e2beda3 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1046,7 +1046,6 @@ dsi0: dsi@1a98000 { "pixel", "core"; phys = <&dsi_phy0>; - phy-names = "dsi-phy"; #address-cells = <1>; #size-cells = <0>; From 02875b55fb451390d5bf95c59e85912c6933eabe Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Wed, 7 Sep 2022 01:00:59 +0100 Subject: [PATCH 060/261] arm64: dts: qcom: msm8996: Drop redundant phy-names from DSI controller phy-names has been marked deprecated. Remove it from the msm8996 DSI controller block. Signed-off-by: Bryan O'Donoghue Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220907000105.786265-6-bryan.odonoghue@linaro.org --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index efba641f3d67..8acb282a77a9 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1013,7 +1013,6 @@ dsi0: dsi@994000 { assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; phys = <&dsi0_phy>; - phy-names = "dsi"; status = "disabled"; #address-cells = <1>; @@ -1081,7 +1080,6 @@ dsi1: dsi@996000 { assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; phys = <&dsi1_phy>; - phy-names = "dsi"; status = "disabled"; #address-cells = <1>; From 95dc5fd99972fd0535ee82639ebbbcacf5175521 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Wed, 7 Sep 2022 01:01:00 +0100 Subject: [PATCH 061/261] arm64: dts: qcom: sc7180: Drop redundant phy-names from DSI controller phy-names has been marked deprecated. Remove it from the sc7180 DSI controller block. Signed-off-by: Bryan O'Donoghue Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220907000105.786265-7-bryan.odonoghue@linaro.org --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 78afbf4096cf..82ca6c17cb5a 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -3016,7 +3016,6 @@ dsi0: dsi@ae94000 { power-domains = <&rpmhpd SC7180_CX>; phys = <&dsi_phy>; - phy-names = "dsi"; #address-cells = <1>; #size-cells = <0>; From c427b8e28d7d040a092adaacf4d2b5905c226242 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Wed, 7 Sep 2022 01:01:01 +0100 Subject: [PATCH 062/261] arm64: dts: qcom: sc7280: Drop redundant phy-names from DSI controller phy-names has been marked deprecated. Remove it from the sc7280 DSI controller block. Signed-off-by: Bryan O'Donoghue Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220907000105.786265-8-bryan.odonoghue@linaro.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 909706ee86f5..16b3b1a4d2c8 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3959,7 +3959,6 @@ mdss_dsi: dsi@ae94000 { power-domains = <&rpmhpd SC7280_CX>; phys = <&mdss_dsi_phy>; - phy-names = "dsi"; #address-cells = <1>; #size-cells = <0>; From 99a4d3d8204d7ecb6c70afa50c9e23ecebbf7f20 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Wed, 7 Sep 2022 01:01:02 +0100 Subject: [PATCH 063/261] arm64: dts: qcom: sdm660: Drop redundant phy-names from DSI controller phy-names has been marked deprecated. Remove it from the sdm660 DSI controller block. Signed-off-by: Bryan O'Donoghue Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220907000105.786265-9-bryan.odonoghue@linaro.org --- arch/arm64/boot/dts/qcom/sdm660.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm660.dtsi b/arch/arm64/boot/dts/qcom/sdm660.dtsi index 43220af1b685..10bf1c45cf6e 100644 --- a/arch/arm64/boot/dts/qcom/sdm660.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm660.dtsi @@ -190,7 +190,6 @@ dsi1: dsi@c996000 { "core"; phys = <&dsi1_phy>; - phy-names = "dsi"; status = "disabled"; From 325821c74b2d04b6683f5d5bd4dbaa4e3fbbbb40 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Wed, 7 Sep 2022 01:01:03 +0100 Subject: [PATCH 064/261] arm64: dts: qcom: sdm630: Drop redundant phy-names from DSI controller phy-names has been marked deprecated. Remove it from the sdm630 DSI controller block. Signed-off-by: Bryan O'Donoghue Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220907000105.786265-10-bryan.odonoghue@linaro.org --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 2d3fdbfef8a6..62f94b9bd986 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1616,7 +1616,6 @@ dsi0: dsi@c994000 { "core"; phys = <&dsi0_phy>; - phy-names = "dsi"; status = "disabled"; From 4c182dff8e4556f6872e9834ed279cd2955305f2 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Wed, 7 Sep 2022 01:01:04 +0100 Subject: [PATCH 065/261] arm64: dts: qcom: sdm845: Drop redundant phy-names from DSI controller phy-names has been marked deprecated. Remove it from the sdm845 DSI controller block. Signed-off-by: Bryan O'Donoghue Reviewed-by: Krzysztof Kozlowski Tested-by: Steev Klimaszewski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220907000105.786265-11-bryan.odonoghue@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 5a907b2819f0..24ecf9be4495 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4637,7 +4637,6 @@ dsi0: dsi@ae94000 { power-domains = <&rpmhpd SDM845_CX>; phys = <&dsi0_phy>; - phy-names = "dsi"; status = "disabled"; @@ -4709,7 +4708,6 @@ dsi1: dsi@ae96000 { power-domains = <&rpmhpd SDM845_CX>; phys = <&dsi1_phy>; - phy-names = "dsi"; status = "disabled"; From 4ce9c4ebe26c2bc5ad39738f94a873bee150707d Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Wed, 7 Sep 2022 01:01:05 +0100 Subject: [PATCH 066/261] arm64: dts: qcom: sm8250: Drop redundant phy-names from DSI controller phy-names has been marked deprecated. Remove it from the sm8250 DSI controller block. Signed-off-by: Bryan O'Donoghue Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220907000105.786265-12-bryan.odonoghue@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 87b75846367f..1c4c720d4c7f 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3555,7 +3555,6 @@ dsi0: dsi@ae94000 { power-domains = <&rpmhpd SM8250_MMCX>; phys = <&dsi0_phy>; - phy-names = "dsi"; status = "disabled"; @@ -3647,7 +3646,6 @@ dsi1: dsi@ae96000 { power-domains = <&rpmhpd SM8250_MMCX>; phys = <&dsi1_phy>; - phy-names = "dsi"; status = "disabled"; From 80edac18ac173f0f0130c2164f75ddadcd68fa7f Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Wed, 7 Sep 2022 17:05:53 +0530 Subject: [PATCH 067/261] arm64: dts: qcom: sc7280: assign DSI clock source parents Assign DSI clock source parents to DSI PHY clocks. Signed-off-by: Rajeev Nandan Cc: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1662550553-28933-1-git-send-email-quic_rajeevny@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 16b3b1a4d2c8..5f4142ab85b8 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3955,6 +3955,9 @@ mdss_dsi: dsi@ae94000 { "iface", "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>; + operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SC7280_CX>; From c95243eeae587c0fbcaaf53bec9233400005c973 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 8 Sep 2022 10:09:37 +0200 Subject: [PATCH 068/261] arm64: dts: qcom: use generic node name "gpio" in SPMI PMIC GPIO controller nodes are named by convention just "gpio", not "gpios". Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220908080938.29199-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/pm6150.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm6150l.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm6350.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm660.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm660l.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm7325.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm8005.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm8916.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm8994.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm8998.dtsi | 2 +- arch/arm64/boot/dts/qcom/pmi8994.dtsi | 2 +- arch/arm64/boot/dts/qcom/pmi8998.dtsi | 2 +- 12 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm6150.dtsi b/arch/arm64/boot/dts/qcom/pm6150.dtsi index 8a4972e6a24c..3cfd3eadccbf 100644 --- a/arch/arm64/boot/dts/qcom/pm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150.dtsi @@ -86,7 +86,7 @@ pm6150_adc_tm: adc-tm@3500 { status = "disabled"; }; - pm6150_gpio: gpios@c000 { + pm6150_gpio: gpio@c000 { compatible = "qcom,pm6150-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; diff --git a/arch/arm64/boot/dts/qcom/pm6150l.dtsi b/arch/arm64/boot/dts/qcom/pm6150l.dtsi index f02c223ef448..8a7c18b134c7 100644 --- a/arch/arm64/boot/dts/qcom/pm6150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150l.dtsi @@ -55,7 +55,7 @@ pm6150l_adc_tm: adc-tm@3500 { status = "disabled"; }; - pm6150l_gpio: gpios@c000 { + pm6150l_gpio: gpio@c000 { compatible = "qcom,pm6150l-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; diff --git a/arch/arm64/boot/dts/qcom/pm6350.dtsi b/arch/arm64/boot/dts/qcom/pm6350.dtsi index ecf9b9919182..18c14257e2c1 100644 --- a/arch/arm64/boot/dts/qcom/pm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6350.dtsi @@ -35,7 +35,7 @@ pm6350_resin: resin { }; }; - pm6350_gpios: gpios@c000 { + pm6350_gpios: gpio@c000 { compatible = "qcom,pm6350-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; diff --git a/arch/arm64/boot/dts/qcom/pm660.dtsi b/arch/arm64/boot/dts/qcom/pm660.dtsi index e1622b16c08b..ab934ff51f6d 100644 --- a/arch/arm64/boot/dts/qcom/pm660.dtsi +++ b/arch/arm64/boot/dts/qcom/pm660.dtsi @@ -170,7 +170,7 @@ vcoin: vcoin@83 { }; }; - pm660_gpios: gpios@c000 { + pm660_gpios: gpio@c000 { compatible = "qcom,pm660-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; diff --git a/arch/arm64/boot/dts/qcom/pm660l.dtsi b/arch/arm64/boot/dts/qcom/pm660l.dtsi index 8aa0a5078772..f9b3864bd3b9 100644 --- a/arch/arm64/boot/dts/qcom/pm660l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm660l.dtsi @@ -48,7 +48,7 @@ pm660l_temp: temp-alarm@2400 { #thermal-sensor-cells = <0>; }; - pm660l_gpios: gpios@c000 { + pm660l_gpios: gpio@c000 { compatible = "qcom,pm660l-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; diff --git a/arch/arm64/boot/dts/qcom/pm7325.dtsi b/arch/arm64/boot/dts/qcom/pm7325.dtsi index e7f64a9ddc9c..cfd4b80c6e35 100644 --- a/arch/arm64/boot/dts/qcom/pm7325.dtsi +++ b/arch/arm64/boot/dts/qcom/pm7325.dtsi @@ -18,7 +18,7 @@ pm7325_temp_alarm: temp-alarm@a00 { #thermal-sensor-cells = <0>; }; - pm7325_gpios: gpios@8800 { + pm7325_gpios: gpio@8800 { compatible = "qcom,pm7325-gpio", "qcom,spmi-gpio"; reg = <0x8800>; gpio-controller; diff --git a/arch/arm64/boot/dts/qcom/pm8005.dtsi b/arch/arm64/boot/dts/qcom/pm8005.dtsi index 50fb6c753bf8..8d4b081b4e9d 100644 --- a/arch/arm64/boot/dts/qcom/pm8005.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8005.dtsi @@ -11,7 +11,7 @@ pm8005_lsid0: pmic@4 { #address-cells = <1>; #size-cells = <0>; - pm8005_gpio: gpios@c000 { + pm8005_gpio: gpio@c000 { compatible = "qcom,pm8005-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi index 606c2a6d1f0f..08f9ca006e72 100644 --- a/arch/arm64/boot/dts/qcom/pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi @@ -107,7 +107,7 @@ pm8916_mpps: mpps@a000 { #interrupt-cells = <2>; }; - pm8916_gpios: gpios@c000 { + pm8916_gpios: gpio@c000 { compatible = "qcom,pm8916-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; diff --git a/arch/arm64/boot/dts/qcom/pm8994.dtsi b/arch/arm64/boot/dts/qcom/pm8994.dtsi index e92e5ac414d3..672094c8ca58 100644 --- a/arch/arm64/boot/dts/qcom/pm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8994.dtsi @@ -108,7 +108,7 @@ adc-chan@f { }; }; - pm8994_gpios: gpios@c000 { + pm8994_gpios: gpio@c000 { compatible = "qcom,pm8994-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; diff --git a/arch/arm64/boot/dts/qcom/pm8998.dtsi b/arch/arm64/boot/dts/qcom/pm8998.dtsi index d09f2954b6f9..0d5163c720b7 100644 --- a/arch/arm64/boot/dts/qcom/pm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8998.dtsi @@ -101,7 +101,7 @@ rtc@6000 { interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; }; - pm8998_gpio: gpios@c000 { + pm8998_gpio: gpio@c000 { compatible = "qcom,pm8998-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; diff --git a/arch/arm64/boot/dts/qcom/pmi8994.dtsi b/arch/arm64/boot/dts/qcom/pmi8994.dtsi index 542c215dde10..a0af91698d49 100644 --- a/arch/arm64/boot/dts/qcom/pmi8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8994.dtsi @@ -10,7 +10,7 @@ pmic@2 { #address-cells = <1>; #size-cells = <0>; - pmi8994_gpios: gpios@c000 { + pmi8994_gpios: gpio@c000 { compatible = "qcom,pmi8994-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; diff --git a/arch/arm64/boot/dts/qcom/pmi8998.dtsi b/arch/arm64/boot/dts/qcom/pmi8998.dtsi index 3852a012bb0f..485bebb685f0 100644 --- a/arch/arm64/boot/dts/qcom/pmi8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8998.dtsi @@ -9,7 +9,7 @@ pmi8998_lsid0: pmic@2 { #address-cells = <1>; #size-cells = <0>; - pmi8998_gpio: gpios@c000 { + pmi8998_gpio: gpio@c000 { compatible = "qcom,pmi8998-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; From 65b35e04d2656305320c453df2824c8413fe7150 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 9 Sep 2022 01:28:50 +0300 Subject: [PATCH 069/261] arm64: dts: qcom: sm8450: add display clock controller Add device node for display clock controller on Qualcomm SM8450 platform Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220908222850.3552050-5-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 7569ef1339a9..eeff62d0954b 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -2400,6 +2401,33 @@ camcc: clock-controller@ade0000 { status = "disabled"; }; + dispcc: clock-controller@af00000 { + compatible = "qcom,sm8450-dispcc"; + reg = <0 0x0af00000 0 0x20000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&gcc GCC_DISP_AHB_CLK>, + <&sleep_clk>, + <0>, /* dsi0 */ + <0>, + <0>, /* dsi1 */ + <0>, + <0>, /* dp0 */ + <0>, + <0>, /* dp1 */ + <0>, + <0>, /* dp2 */ + <0>, + <0>, /* dp3 */ + <0>; + power-domains = <&rpmhpd SM8450_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + status = "disabled"; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8450-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; From dd6459a0890a17e136c539abda07f8b671615c29 Mon Sep 17 00:00:00 2001 From: Joel Selvaraj Date: Thu, 8 Sep 2022 22:54:45 -0500 Subject: [PATCH 070/261] arm64: dts: qcom: split beryllium dts into common dtsi and tianma dts There are two panel variants of Xiaomi Poco F1. Tianma and EBBG panel. The previous beryllium dts supported the Tianma variant. In order to add support for EBBG variant, the common nodes from beryllium dts are moved to a new common dtsi and to make the variants distinguishable, sdm845-xiaomi-beryllium.dts is now named as sdm845-xiaomi-beryllium-tianma.dts. The model property is updated to distinguish between the variants. The compatibility property is moved to the tianma variant, but it is not updated to avoid any further conflict with other projects/users that might depend on it. Signed-off-by: Joel Selvaraj Reviewed-by: Marijn Suijten Reviewed-by: Caleb Connolly Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220909035447.36674-2-joelselvaraj.oss@gmail.com --- arch/arm64/boot/dts/qcom/Makefile | 2 +- ...um.dts => sdm845-xiaomi-beryllium-common.dtsi} | 11 +++++------ .../dts/qcom/sdm845-xiaomi-beryllium-tianma.dts | 15 +++++++++++++++ 3 files changed, 21 insertions(+), 7 deletions(-) rename arch/arm64/boot/dts/qcom/{sdm845-xiaomi-beryllium.dts => sdm845-xiaomi-beryllium-common.dtsi} (98%) create mode 100644 arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-tianma.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 04f4fa66f966..3bb6f5113489 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -136,7 +136,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-oneplus-fajita.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-akari.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-akatsuki.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-apollo.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium-tianma.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-polaris.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-shift-axolotl.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi similarity index 98% rename from arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts rename to arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index 68e2a07a01dc..163bf9c1a1d8 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -26,8 +26,6 @@ /delete-node/ &rmtfs_mem; / { - model = "Xiaomi Pocophone F1"; - compatible = "xiaomi,beryllium", "qcom,sdm845"; chassis-type = "handset"; /* required for bootloader to select correct board */ @@ -221,8 +219,7 @@ &dsi0 { status = "okay"; vdda-supply = <&vreg_l26a_1p2>; - panel@0 { - compatible = "tianma,fhd-video"; + display_panel: panel@0 { reg = <0>; vddio-supply = <&vreg_l14a_1p8>; vddpos-supply = <&lab>; @@ -234,8 +231,10 @@ panel@0 { backlight = <&pmi8998_wled>; reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + status = "disabled"; + port { - tianma_nt36672a_in_0: endpoint { + panel_in_0: endpoint { remote-endpoint = <&dsi0_out>; }; }; @@ -243,7 +242,7 @@ tianma_nt36672a_in_0: endpoint { }; &dsi0_out { - remote-endpoint = <&tianma_nt36672a_in_0>; + remote-endpoint = <&panel_in_0>; data-lanes = <0 1 2 3>; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-tianma.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-tianma.dts new file mode 100644 index 000000000000..8e176111e599 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-tianma.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "sdm845-xiaomi-beryllium-common.dtsi" + +/ { + model = "Xiaomi Pocophone F1 (Tianma)"; + compatible = "xiaomi,beryllium", "qcom,sdm845"; +}; + +&display_panel { + compatible = "tianma,fhd-video"; + status = "okay"; +}; From 341fdef8ea49448a0c44a17ab442a1d25e4481fa Mon Sep 17 00:00:00 2001 From: Joel Selvaraj Date: Thu, 8 Sep 2022 22:54:46 -0500 Subject: [PATCH 071/261] dt-bindings: arm: qcom: Add Xiaomi Poco F1 EBBG variant bindings Add documentation for "xiaomi,beryllium-ebbg" device. Signed-off-by: Joel Selvaraj Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220909035447.36674-3-joelselvaraj.oss@gmail.com --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 2c217478836c..6a4df5833024 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -703,6 +703,7 @@ properties: - sony,apollo-row - thundercomm,db845c - xiaomi,beryllium + - xiaomi,beryllium-ebbg - xiaomi,polaris - const: qcom,sdm845 From bcf429831ecb4810caf1454f6692352401616ad4 Mon Sep 17 00:00:00 2001 From: Joel Selvaraj Date: Thu, 8 Sep 2022 22:54:47 -0500 Subject: [PATCH 072/261] arm64: dts: qcom: sdm845-xiaomi-beryllium-ebbg: introduce Xiaomi Poco F1 EBBG variant Introduce support for the Xiaomi Poco F1 EBBG variant. The EBBG variant uses EBBG FT8719 panel manufactured by EBBG. Signed-off-by: Joel Selvaraj Reviewed-by: Marijn Suijten Reviewed-by: Krzysztof Kozlowski Reviewed-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220909035447.36674-4-joelselvaraj.oss@gmail.com --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../dts/qcom/sdm845-xiaomi-beryllium-ebbg.dts | 15 +++++++++++++++ 2 files changed, 16 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-ebbg.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 3bb6f5113489..b0558d3389e5 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -136,6 +136,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-oneplus-fajita.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-akari.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-akatsuki.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-apollo.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium-ebbg.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium-tianma.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-polaris.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-shift-axolotl.dtb diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-ebbg.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-ebbg.dts new file mode 100644 index 000000000000..76931ebad065 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-ebbg.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "sdm845-xiaomi-beryllium-common.dtsi" + +/ { + model = "Xiaomi Pocophone F1 (EBBG)"; + compatible = "xiaomi,beryllium-ebbg", "qcom,sdm845"; +}; + +&display_panel { + compatible = "ebbg,ft8719"; + status = "okay"; +}; From 7d1473d7ba78ed15cfe7e08c1d8b5f2b21d60bbd Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 19 Sep 2022 22:00:32 +0300 Subject: [PATCH 073/261] arm64: dts: qcom: w737: correct firmware paths Correct firmware paths for the Samsung Galaxy Book2 to include the SoC name. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220919190037.2122284-2-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts index dfa4857d705c..f93d748e2c94 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts @@ -124,7 +124,7 @@ spss_mem: memory@98f00000 { }; &adsp_pas { - firmware-name = "qcom/samsung/w737/qcadsp850.mbn"; + firmware-name = "qcom/sdm850/samsung/w737/qcadsp850.mbn"; status = "okay"; }; @@ -336,7 +336,7 @@ vreg_lvs2a_1p8: lvs2 { }; &cdsp_pas { - firmware-name = "qcom/samsung/w737/qccdsp850.mbn"; + firmware-name = "qcom/sdm850/samsung/w737/qccdsp850.mbn"; status = "okay"; }; @@ -385,7 +385,7 @@ digitizer@9 { &ipa { status = "okay"; memory-region = <&ipa_fw_mem>; - firmware-name = "qcom/samsung/w737/ipa_fws.elf"; + firmware-name = "qcom/sdm850/samsung/w737/ipa_fws.elf"; }; /* No idea why it causes an SError when enabled */ @@ -395,7 +395,7 @@ &llcc { &mss_pil { status = "okay"; - firmware-name = "qcom/samsung/w737/qcdsp1v2850.mbn", "qcom/samsung/w737/qcdsp2850.mbn"; + firmware-name = "qcom/sdm850/samsung/w737/qcdsp1v2850.mbn", "qcom/sdm850/samsung/w737/qcdsp2850.mbn"; }; &qup_i2c10_default { @@ -698,7 +698,7 @@ &usb_2_qmpphy { &venus { status = "okay"; - firmware-name = "qcom/samsung/w737/qcvss850.mbn"; + firmware-name = "qcom/sdm850/samsung/w737/qcvss850.mbn"; }; &wcd9340{ From 6fa1fb7814f556a630b219033cd5de72e978537c Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 19 Sep 2022 22:00:33 +0300 Subject: [PATCH 074/261] arm64: dts: qcom: miix-630: correct firmware paths Correct firmware paths for the Lenovo Miix 630 to include the SoC name. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220919190037.2122284-3-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dts b/arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dts index cf81c33a9d7e..a105143bee4a 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dts @@ -28,8 +28,8 @@ keyboard@3a { }; &remoteproc_mss { - firmware-name = "qcom/LENOVO/81F1/qcdsp1v28998.mbn", - "qcom/LENOVO/81F1/qcdsp28998.mbn"; + firmware-name = "qcom/msm8998/LENOVO/81F1/qcdsp1v28998.mbn", + "qcom/msm8998/LENOVO/81F1/qcdsp28998.mbn"; }; &sdhc2 { From 6dae44d91e42da017d12b3dfeb546cbe2b9c9306 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 19 Sep 2022 22:00:34 +0300 Subject: [PATCH 075/261] arm64: dts: qcom: ifc6560: correct firmware paths Correct firmware paths for the Inforce IFC6560 to include the SoC name. Do not include the platform name, since the board uses test-signed firmware. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220919190037.2122284-4-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts index f62a74f0e8f0..f49f18843f42 100644 --- a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts +++ b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts @@ -99,7 +99,7 @@ v5p0_boost: v5p0-boost-regulator { }; &adsp_pil { - firmware-name = "qcom/ifc6560/adsp.mbn"; + firmware-name = "qcom/sda660/adsp.mbn"; }; &blsp_i2c6 { From f0a577c3a80790f4249be76a6b9712003deb93a5 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 19 Sep 2022 22:00:35 +0300 Subject: [PATCH 076/261] arm64: dts: qcom: sagami: correct firmware paths Correct firmware paths for the Sony Xperia Sagami devices to include the SoC name, vendor and platform names. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220919190037.2122284-5-dmitry.baryshkov@linaro.org --- .../arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi index b3c9952ac173..e73ea22bd142 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi @@ -77,12 +77,12 @@ ramoops@ffc00000 { &adsp { status = "okay"; - firmware-name = "qcom/adsp.mbn"; + firmware-name = "qcom/sm8350/Sony/sagami/adsp.mbn"; }; &cdsp { status = "okay"; - firmware-name = "qcom/cdsp.mbn"; + firmware-name = "qcom/sm8350/Sony/sagami/cdsp.mbn"; }; &i2c1 { @@ -175,12 +175,12 @@ &i2c17 { &ipa { status = "okay"; memory-region = <&pil_ipa_fw_mem>; - firmware-name = "qcom/ipa_fws.mbn"; + firmware-name = "qcom/sm8350/Sony/sagami/ipa_fws.mbn"; }; &mpss { status = "okay"; - firmware-name = "qcom/modem.mbn"; + firmware-name = "qcom/sm8350/Sony/sagami/modem.mbn"; }; &pmk8350_rtc { @@ -210,7 +210,7 @@ &qupv3_id_2 { &slpi { status = "okay"; - firmware-name = "qcom/slpi.mbn"; + firmware-name = "qcom/sm8350/Sony/sagami/slpi.mbn"; }; &spi14 { From c53532f7825c98ede6f80f9549e33443465aaf6a Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 19 Sep 2022 22:00:36 +0300 Subject: [PATCH 077/261] arm64: dts: qcom: pdx223: correct firmware paths Correct firmware paths for the Sony Xperia 1 IV to include the SoC name. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220919190037.2122284-6-dmitry.baryshkov@linaro.org --- .../boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts index d68765eb6d4f..82918c2d956f 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts @@ -523,17 +523,17 @@ &pcie0_phy { }; &remoteproc_adsp { - firmware-name = "qcom/adsp.mbn"; + firmware-name = "qcom/sm8350/Sony/nagara/adsp.mbn"; status = "okay"; }; &remoteproc_cdsp { - firmware-name = "qcom/cdsp.mbn"; + firmware-name = "qcom/sm8350/Sony/nagara/cdsp.mbn"; status = "okay"; }; &remoteproc_slpi { - firmware-name = "qcom/slpi.mbn"; + firmware-name = "qcom/sm8350/Sony/nagara/slpi.mbn"; status = "okay"; }; From 151d6e9cc22a8a5e9bd47a99723aa4ab60821faf Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 19 Sep 2022 22:00:37 +0300 Subject: [PATCH 078/261] arm64: dts: qcom: nile: correct firmware paths Correct firmware paths for the Sony Xperia Nile devices to include the SoC name. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220919190037.2122284-7-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi index f9e1d599466a..fe09628daf03 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi @@ -155,7 +155,7 @@ extcon_usb: extcon-usb { }; &adsp_pil { - firmware-name = "adsp.mdt"; + firmware-name = "qcom/sdm630/Sony/nile/adsp.mdt"; }; &blsp_i2c1 { From 732479bda06e1dfe5f46bfc682d94f40dff0af1f Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 21 Sep 2022 02:47:41 +0200 Subject: [PATCH 079/261] arm64: dts: qcom: msm8998-yoshino: Fix up SMD regulators formatting Add a new line between each subnode and make the { } consistent. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220921004741.152765-1-konrad.dybcio@somainline.org --- .../dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 33 ++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index 47cd3caa6927..332eda4ae50f 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -410,131 +410,162 @@ vreg_s3a_1p35: s3 { regulator-min-microvolt = <1352000>; regulator-max-microvolt = <1352000>; }; + vreg_s4a_1p8: s4 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-system-load = <100000>; regulator-allow-set-load; }; + vreg_s5a_2p04: s5 { regulator-min-microvolt = <1904000>; regulator-max-microvolt = <2032000>; }; + vreg_s7a_1p025: s7 { regulator-min-microvolt = <900000>; regulator-max-microvolt = <1028000>; }; + vreg_l1a_0p875: l1 { regulator-min-microvolt = <880000>; regulator-max-microvolt = <880000>; regulator-system-load = <73400>; regulator-allow-set-load; }; + vreg_l2a_1p2: l2 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-system-load = <12560>; regulator-allow-set-load; }; + vreg_l3a_1p0: l3 { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; }; + vreg_l5a_0p8: l5 { regulator-min-microvolt = <800000>; regulator-max-microvolt = <800000>; }; + vreg_l6a_1p8: l6 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + vreg_l7a_1p8: l7 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + vreg_l8a_1p2: l8 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; }; + vreg_l9a_1p8: l9 { regulator-min-microvolt = <1808000>; regulator-max-microvolt = <2960000>; }; + vreg_l10a_1p8: l10 { regulator-min-microvolt = <1808000>; regulator-max-microvolt = <2960000>; }; + vreg_l11a_1p0: l11 { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; }; + vreg_l12a_1p8: l12 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + vreg_l13a_2p95: l13 { regulator-min-microvolt = <1808000>; regulator-max-microvolt = <2960000>; regulator-allow-set-load; }; + vreg_l14a_1p85: l14 { regulator-min-microvolt = <1848000>; regulator-max-microvolt = <1856000>; regulator-system-load = <32000>; regulator-allow-set-load; }; + vreg_l15a_1p8: l15 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + vreg_l16a_2p7: l16 { regulator-min-microvolt = <2704000>; regulator-max-microvolt = <2704000>; }; + vreg_l17a_1p3: l17 { regulator-min-microvolt = <1304000>; regulator-max-microvolt = <1304000>; }; - vreg_l18a_2p85: l18 {}; + + vreg_l18a_2p85: l18 { }; + vreg_l19a_2p7: l19 { regulator-min-microvolt = <2696000>; regulator-max-microvolt = <2704000>; }; + vreg_l20a_2p95: l20 { regulator-min-microvolt = <2960000>; regulator-max-microvolt = <2960000>; regulator-system-load = <10000>; regulator-allow-set-load; }; + vreg_l21a_2p95: l21 { regulator-min-microvolt = <2960000>; regulator-max-microvolt = <2960000>; regulator-system-load = <800000>; regulator-allow-set-load; }; + vreg_l22a_2p85: l22 { }; + vreg_l23a_3p3: l23 { regulator-min-microvolt = <3312000>; regulator-max-microvolt = <3312000>; }; + vreg_l24a_3p075: l24 { regulator-min-microvolt = <3088000>; regulator-max-microvolt = <3088000>; }; + vreg_l25a_3p3: l25 { regulator-min-microvolt = <3104000>; regulator-max-microvolt = <3312000>; }; + vreg_l26a_1p2: l26 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-allow-set-load; }; + vreg_l28_3p0: l28 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; }; + vreg_lvs1a_1p8: lvs1 { }; + vreg_lvs2a_1p8: lvs2 { }; }; From b7e2ce42f61bd72e903952427538e2411b3a1429 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 21 Sep 2022 10:00:50 +0200 Subject: [PATCH 080/261] arm64: dts: qcom: sc8280xp: add rpmh-stats node Add a node describing the RPMh shared memory that can be used to retrieve statistics for the SoC low-power modes. Signed-off-by: Johan Hovold Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220921080050.21383-1-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index c32bcded2aef..9fad81bd22d2 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1476,6 +1476,11 @@ aoss_qmp: power-controller@c300000 { #clock-cells = <0>; }; + sram@c3f0000 { + compatible = "qcom,rpmh-stats"; + reg = <0 0x0c3f0000 0 0x400>; + }; + spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0 0x0c440000 0 0x1100>, From b03852c244baaf931c0e3908ff81d68206e10fd7 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 24 Sep 2022 12:01:02 +0300 Subject: [PATCH 081/261] arm64: dts: qcom: msm8916: change DSI PHY node name to generic one Change DSI PHY node names from custom 'dsi-phy' to the generic 'phy'. Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220924090108.166934-4-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index fca66e2beda3..a60eb8a59dca 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1069,7 +1069,7 @@ dsi0_out: endpoint { }; }; - dsi_phy0: dsi-phy@1a98300 { + dsi_phy0: phy@1a98300 { compatible = "qcom,dsi-phy-28nm-lp"; reg = <0x01a98300 0xd4>, <0x01a98500 0x280>, From 649119dbbdcccda5b29fd618d1d0546890c59bed Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 24 Sep 2022 12:01:03 +0300 Subject: [PATCH 082/261] arm64: dts: qcom: msm8996: change DSI PHY node name to generic one Change DSI PHY node names from custom 'dsi-phy' to the generic 'phy'. Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220924090108.166934-5-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 8acb282a77a9..8357633bca83 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1037,7 +1037,7 @@ dsi0_out: endpoint { }; }; - dsi0_phy: dsi-phy@994400 { + dsi0_phy: phy@994400 { compatible = "qcom,dsi-phy-14nm"; reg = <0x00994400 0x100>, <0x00994500 0x300>, @@ -1104,7 +1104,7 @@ dsi1_out: endpoint { }; }; - dsi1_phy: dsi-phy@996400 { + dsi1_phy: phy@996400 { compatible = "qcom,dsi-phy-14nm"; reg = <0x00996400 0x100>, <0x00996500 0x300>, From 2372bd2d5be6afd945f83b7980c1ca7254a3b66d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 24 Sep 2022 12:01:04 +0300 Subject: [PATCH 083/261] arm64: dts: qcom: sc7180: change DSI PHY node name to generic one Change DSI PHY node names from custom 'dsi-phy' to the generic 'phy'. Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220924090108.166934-6-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 82ca6c17cb5a..f1482675610a 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -3060,7 +3060,7 @@ opp-358000000 { }; }; - dsi_phy: dsi-phy@ae94400 { + dsi_phy: phy@ae94400 { compatible = "qcom,dsi-phy-10nm"; reg = <0 0x0ae94400 0 0x200>, <0 0x0ae94600 0 0x280>, From e922200b5733b363afa21c9e198963d882470c32 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 24 Sep 2022 12:01:05 +0300 Subject: [PATCH 084/261] arm64: dts: qcom: sdm630: change DSI PHY node name to generic one Change DSI PHY node names from custom 'dsi-phy' to the generic 'phy'. Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220924090108.166934-7-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 62f94b9bd986..a6de40f06bac 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1638,7 +1638,7 @@ dsi0_out: endpoint { }; }; - dsi0_phy: dsi-phy@c994400 { + dsi0_phy: phy@c994400 { compatible = "qcom,dsi-phy-14nm-660"; reg = <0x0c994400 0x100>, <0x0c994500 0x300>, From b76c00443e06ef7e45297b0c71b6bb62d830dd2b Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 24 Sep 2022 12:01:06 +0300 Subject: [PATCH 085/261] arm64: dts: qcom: sdm660: change DSI PHY node name to generic one Change DSI PHY node names from custom 'dsi-phy' to the generic 'phy'. Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220924090108.166934-8-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sdm660.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm660.dtsi b/arch/arm64/boot/dts/qcom/sdm660.dtsi index 10bf1c45cf6e..d52123cb5cd3 100644 --- a/arch/arm64/boot/dts/qcom/sdm660.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm660.dtsi @@ -212,7 +212,7 @@ dsi1_out: endpoint { }; }; - dsi1_phy: dsi-phy@c996400 { + dsi1_phy: phy@c996400 { compatible = "qcom,dsi-phy-14nm-660"; reg = <0x0c996400 0x100>, <0x0c996500 0x300>, From 2e176b550b34a1be6674867fb97d12dce2ad9bdb Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 24 Sep 2022 12:01:07 +0300 Subject: [PATCH 086/261] arm64: dts: qcom: sdm845: change DSI PHY node name to generic one Change DSI PHY node names from custom 'dsi-phy' to the generic 'phy'. Signed-off-by: Dmitry Baryshkov Tested-by: Steev Klimaszewski Reviewed-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220924090108.166934-9-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 24ecf9be4495..d1ec38593294 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4662,7 +4662,7 @@ dsi0_out: endpoint { }; }; - dsi0_phy: dsi-phy@ae94400 { + dsi0_phy: phy@ae94400 { compatible = "qcom,dsi-phy-10nm"; reg = <0 0x0ae94400 0 0x200>, <0 0x0ae94600 0 0x280>, @@ -4733,7 +4733,7 @@ dsi1_out: endpoint { }; }; - dsi1_phy: dsi-phy@ae96400 { + dsi1_phy: phy@ae96400 { compatible = "qcom,dsi-phy-10nm"; reg = <0 0x0ae96400 0 0x200>, <0 0x0ae96600 0 0x280>, From d455f20402a0a31ae77a3fb924106c46a7898a46 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 24 Sep 2022 12:01:08 +0300 Subject: [PATCH 087/261] arm64: dts: qcom: sm8250: change DSI PHY node name to generic one Change DSI PHY node names from custom 'dsi-phy' to the generic 'phy'. Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220924090108.166934-10-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 1c4c720d4c7f..eb5a10cbcd71 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3599,7 +3599,7 @@ opp-358000000 { }; }; - dsi0_phy: dsi-phy@ae94400 { + dsi0_phy: phy@ae94400 { compatible = "qcom,dsi-phy-7nm"; reg = <0 0x0ae94400 0 0x200>, <0 0x0ae94600 0 0x280>, @@ -3671,7 +3671,7 @@ dsi1_out: endpoint { }; }; - dsi1_phy: dsi-phy@ae96400 { + dsi1_phy: phy@ae96400 { compatible = "qcom,dsi-phy-7nm"; reg = <0 0x0ae96400 0 0x200>, <0 0x0ae96600 0 0x280>, From 8857b0ab6a562c473c5bded0efda9390b82a84d4 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 27 Sep 2022 22:12:17 +0200 Subject: [PATCH 088/261] arm64: dts: qcom: ipq6018: fix NAND node name Per schema it should be nand-controller@79b0000 instead of nand@79b0000. Fix it to match nand-controller.yaml requirements. Signed-off-by: Robert Marko Reviewed-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220927201218.1264506-1-robimarko@gmail.com --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 9b9f778090e1..8132118dc77d 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -348,7 +348,7 @@ qpic_bam: dma-controller@7984000 { status = "disabled"; }; - qpic_nand: nand@79b0000 { + qpic_nand: nand-controller@79b0000 { compatible = "qcom,ipq6018-nand"; reg = <0x0 0x079b0000 0x0 0x10000>; #address-cells = <1>; From feeef118fda562cf9081edef8ad464d89db070f4 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 27 Sep 2022 22:12:18 +0200 Subject: [PATCH 089/261] arm64: dts: qcom: ipq6018: move ARMv8 timer out of SoC node The ARM timer is usually considered not part of SoC node, just like other ARM designed blocks (PMU, PSCI). This fixes dtbs_check warning: arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dtb: soc: timer: {'compatible': ['arm,armv8-timer'], 'interrupts': [[1, 2, 3848], [1, 3, 3848], [1, 4, 3848], [1, 1, 3848]]} should not be valid under {'type': 'object'} From schema: dtschema/schemas/simple-bus.yaml Signed-off-by: Robert Marko Reviewed-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220927201218.1264506-2-robimarko@gmail.com --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 8132118dc77d..9ebb9e2371b1 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -511,14 +511,6 @@ a53pll: clock@b116000 { clock-names = "xo"; }; - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - timer@b120000 { #address-cells = <1>; #size-cells = <1>; @@ -770,6 +762,14 @@ dwc_0: usb@8a00000 { }; }; + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + wcss: wcss-smp2p { compatible = "qcom,smp2p"; qcom,smem = <435>, <428>; From f493bf2e70c6540f79fda3b28d636f1dd486d17a Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 27 Sep 2022 22:14:14 +0200 Subject: [PATCH 090/261] arm64: dts: qcom: cp01-c1: remove bootargs-append bootargs-append is a leftover from the vendor SDK, and does not exist in the mainline kernel at all, so remove it. Signed-off-by: Robert Marko Reviewed-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220927201415.1265191-1-robimarko@gmail.com --- arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts index ec999f972360..c973a4ed65f6 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts @@ -19,7 +19,6 @@ aliases { chosen { stdout-path = "serial0:115200n8"; - bootargs-append = " swiotlb=1"; }; }; From 4d29e016eb72d14fa4fb4e5c90c880d260b8b281 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 27 Sep 2022 22:14:15 +0200 Subject: [PATCH 091/261] arm64: dts: qcom: cp01-c1: use "okay" instead of "ok" Use "okay" instead of "ok" in USB nodes as "ok" is deprecated. Signed-off-by: Robert Marko Reviewed-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220927201415.1265191-2-robimarko@gmail.com --- arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts index c973a4ed65f6..2aee8594b280 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts @@ -81,9 +81,9 @@ nand@0 { }; &qusb_phy_1 { - status = "ok"; + status = "okay"; }; &usb2 { - status = "ok"; + status = "okay"; }; From 0a4594886dd904b73541188c875bf378c463cbbc Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 28 Sep 2022 17:20:17 +0200 Subject: [PATCH 092/261] arm64: dts: qcom: sdm845: drop unused slimbus properties Drop properties from slimbus node: unneeded status and downstream-related qcom,apps-ch-pipes/qcom,ea-pc (not documented, not used). Signed-off-by: Krzysztof Kozlowski Tested-by: Steev Klimaszewski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220928152027.489543-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index d1ec38593294..8b0de8be9515 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -3828,9 +3828,6 @@ slim: slim@171c0000 { reg = <0 0x171c0000 0 0x2c000>; interrupts = ; - qcom,apps-ch-pipes = <0x780000>; - qcom,ea-pc = <0x270>; - status = "okay"; dmas = <&slimbam 3>, <&slimbam 4>, <&slimbam 5>, <&slimbam 6>; dma-names = "rx", "tx", "tx2", "rx2"; From 9eae83f9ec9cee5cbc615fd6bc4221c7d62c07d5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 28 Sep 2022 17:20:18 +0200 Subject: [PATCH 093/261] arm64: dts: qcom: msm8996: drop unused slimbus reg-mames Drop undocumented reg-names from slimbus node - there is only one address range and Linux implementation does not use it. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220928152027.489543-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 8357633bca83..cc136b99716a 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -3330,7 +3330,6 @@ slimbam: dma-controller@9184000 { slim_msm: slim@91c0000 { compatible = "qcom,slim-ngd-v1.5.0"; reg = <0x091c0000 0x2C000>; - reg-names = "ctrl"; interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; dmas = <&slimbam 3>, <&slimbam 4>, <&slimbam 5>, <&slimbam 6>; From 251ba7ee1674cb7608fa2c5da6c188e976e83481 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 28 Sep 2022 17:20:19 +0200 Subject: [PATCH 094/261] arm64: dts: qcom: sdm845: correct slimbus children unit addresses slimbus uses address-cells=2, so correct children unit addresses. Signed-off-by: Krzysztof Kozlowski Tested-by: Steev Klimaszewski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220928152027.489543-4-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 8b0de8be9515..002928e507f0 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -3841,12 +3841,12 @@ ngd@1 { #address-cells = <2>; #size-cells = <0>; - wcd9340_ifd: ifd@0{ + wcd9340_ifd: ifd@0,0 { compatible = "slim217,250"; reg = <0 0>; }; - wcd9340: codec@1{ + wcd9340: codec@1,0 { compatible = "slim217,250"; reg = <1 0>; slim-ifc-dev = <&wcd9340_ifd>; From e92a949e436e9956a2f99a07f9f4f640f42d8f99 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 28 Sep 2022 17:20:20 +0200 Subject: [PATCH 095/261] arm64: dts: qcom: mms8996: correct slimbus children unit addresses Correct slimbus address/size cells to match bindings. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220928152027.489543-5-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index cc136b99716a..bc3cf3f3c897 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -3338,15 +3338,15 @@ slim_msm: slim@91c0000 { #size-cells = <0>; ngd@1 { reg = <1>; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <0>; - tasha_ifd: tas-ifd { + tasha_ifd: tas-ifd@0,0 { compatible = "slim217,1a0"; reg = <0 0>; }; - wcd9335: codec@1{ + wcd9335: codec@1,0 { pinctrl-0 = <&cdc_reset_active &wcd_intr_default>; pinctrl-names = "default"; From 7b027503c3620bcc8f60f3cef30ee3bc7f7aeede Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 28 Sep 2022 17:20:21 +0200 Subject: [PATCH 096/261] arm64: dts: qcom: sdm845: drop unused slimbus dmas Bindings document only two DMA channels. Linux driver also does not use remaining rx2/tx2. Signed-off-by: Krzysztof Kozlowski Tested-by: Steev Klimaszewski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220928152027.489543-6-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 002928e507f0..17e7cd1d9c02 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -3828,9 +3828,8 @@ slim: slim@171c0000 { reg = <0 0x171c0000 0 0x2c000>; interrupts = ; - dmas = <&slimbam 3>, <&slimbam 4>, - <&slimbam 5>, <&slimbam 6>; - dma-names = "rx", "tx", "tx2", "rx2"; + dmas = <&slimbam 3>, <&slimbam 4>; + dma-names = "rx", "tx"; iommus = <&apps_smmu 0x1806 0x0>; #address-cells = <1>; From 3cc63b981bab83e8e439629e94ea96c1b3ae5888 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 28 Sep 2022 17:20:22 +0200 Subject: [PATCH 097/261] arm64: dts: qcom: msm8996: drop unused slimbus dmas Bindings document only two DMA channels. Linux driver also does not use remaining rx2/tx2. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220928152027.489543-7-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index bc3cf3f3c897..c4c5287ab1b4 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -3331,9 +3331,8 @@ slim_msm: slim@91c0000 { compatible = "qcom,slim-ngd-v1.5.0"; reg = <0x091c0000 0x2C000>; interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&slimbam 3>, <&slimbam 4>, - <&slimbam 5>, <&slimbam 6>; - dma-names = "rx", "tx", "tx2", "rx2"; + dmas = <&slimbam 3>, <&slimbam 4>; + dma-names = "rx", "tx"; #address-cells = <1>; #size-cells = <0>; ngd@1 { From 880d93355135515d842a41b7ff50f27daaeb3bec Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 28 Sep 2022 17:20:23 +0200 Subject: [PATCH 098/261] arm64: dts: qcom: sdm845: align node names with DT schema New slimbus DT schema expect only SLIMbus bus nodes to be named "slimbus". In case of Qualcomm SLIMbus NGD, the bus node is what was called "ngd". Signed-off-by: Krzysztof Kozlowski Tested-by: Steev Klimaszewski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220928152027.489543-8-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 17e7cd1d9c02..5f867b1a2df0 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -3823,7 +3823,7 @@ qspi: spi@88df000 { status = "disabled"; }; - slim: slim@171c0000 { + slim: slim-ngd@171c0000 { compatible = "qcom,slim-ngd-v2.1.0"; reg = <0 0x171c0000 0 0x2c000>; interrupts = ; @@ -3835,7 +3835,7 @@ slim: slim@171c0000 { #address-cells = <1>; #size-cells = <0>; - ngd@1 { + slim@1 { reg = <1>; #address-cells = <2>; #size-cells = <0>; From 6414b1177e2e4f229b7807009f17ccf9491c6a44 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 28 Sep 2022 17:20:24 +0200 Subject: [PATCH 099/261] arm64: dts: qcom: msm8996: align node names with DT schema New slimbus DT schema expect only SLIMbus bus nodes to be named "slimbus". In case of Qualcomm SLIMbus NGD, the bus node is what was called "ngd". Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220928152027.489543-9-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index c4c5287ab1b4..a35fba4c0758 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -3327,7 +3327,7 @@ slimbam: dma-controller@9184000 { qcom,num-ees = <2>; }; - slim_msm: slim@91c0000 { + slim_msm: slim-ngd@91c0000 { compatible = "qcom,slim-ngd-v1.5.0"; reg = <0x091c0000 0x2C000>; interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; @@ -3335,7 +3335,7 @@ slim_msm: slim@91c0000 { dma-names = "rx", "tx"; #address-cells = <1>; #size-cells = <0>; - ngd@1 { + slim@1 { reg = <1>; #address-cells = <2>; #size-cells = <0>; From 5aa332c5e7ca2469c9ff55cf294eddb33a2c8e4b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 28 Sep 2022 17:25:01 +0200 Subject: [PATCH 100/261] dt-bindings: qcom: document preferred compatible naming Compatibles can come in two formats. Either "vendor,ip-soc" or "vendor,soc-ip". Qualcomm bindings were mixing both of usages, so add a DT schema file documenting preferred policy and enforcing it for all new compatibles, except few existing patterns. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Reviewed-by: Dmitry Baryshkov Reviewed-by: Bhupesh Sharma Reviewed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220928152501.490840-1-krzysztof.kozlowski@linaro.org --- .../devicetree/bindings/arm/qcom-soc.yaml | 65 +++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/qcom-soc.yaml diff --git a/Documentation/devicetree/bindings/arm/qcom-soc.yaml b/Documentation/devicetree/bindings/arm/qcom-soc.yaml new file mode 100644 index 000000000000..889fbfacf226 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/qcom-soc.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/qcom-soc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SoC compatibles naming convention + +maintainers: + - Bjorn Andersson + +description: | + Guidelines for new compatibles for SoC blocks/components. + When adding new compatibles in new bindings, use the format:: + qcom,SoC-IP + + For example:: + qcom,sdm845-llcc-bwmon + + When adding new compatibles to existing bindings, use the format in the + existing binding, even if it contradicts the above. + +select: + properties: + compatible: + pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$" + required: + - compatible + +properties: + compatible: + oneOf: + # Preferred naming style for compatibles of SoC components: + - pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+-.*$" + - pattern: "^qcom,(sa|sc)8[0-9]+[a-z][a-z]?-.*$" + + # Legacy namings - variations of existing patterns/compatibles are OK, + # but do not add completely new entries to these: + - pattern: "^qcom,[ak]pss-wdt-(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$" + - pattern: "^qcom,gcc-(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$" + - pattern: "^qcom,mmcc-(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$" + - pattern: "^qcom,pcie-(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$" + - pattern: "^qcom,rpm-(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$" + - pattern: "^qcom,scm-(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$" + - enum: + - qcom,gpucc-sdm630 + - qcom,gpucc-sdm660 + - qcom,lcc-apq8064 + - qcom,lcc-ipq8064 + - qcom,lcc-mdm9615 + - qcom,lcc-msm8960 + - qcom,lpass-cpu-apq8016 + - qcom,usb-ss-ipq4019-phy + - qcom,usb-hs-ipq4019-phy + - qcom,vqmmc-ipq4019-regulator + + # Legacy compatibles with wild-cards - list cannot grow with new bindings: + - enum: + - qcom,ipq806x-gmac + - qcom,ipq806x-nand + - qcom,ipq806x-sata-phy + - qcom,ipq806x-usb-phy-ss + - qcom,ipq806x-usb-phy-hs + +additionalProperties: true From 978bc4c578a6d7baffc5646b0f327da036b3051b Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Wed, 28 Sep 2022 18:15:56 -0700 Subject: [PATCH 101/261] arm64: dts: qcom: msm8916-samsung-a2015: fix polarity of "enable" line of NFC chip According to s3fwrn5 driver code the "enable" GPIO line is driven "high" when chip is not in use (mode is S3FWRN5_MODE_COLD), and is driven "low" when chip is in use. s3fwrn5_phy_power_ctrl(): ... gpio_set_value(phy->gpio_en, 1); ... if (mode != S3FWRN5_MODE_COLD) { msleep(S3FWRN5_EN_WAIT_TIME); gpio_set_value(phy->gpio_en, 0); msleep(S3FWRN5_EN_WAIT_TIME); } Therefore the line described by "en-gpios" property should be annotated as "active low". The wakeup gpio appears to have correct polarity (active high). Signed-off-by: Dmitry Torokhov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220929011557.4165216-2-dmitry.torokhov@gmail.com --- arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index 3255bd3fcb55..5f7cec347a4f 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -144,7 +144,7 @@ nfc@27 { interrupt-parent = <&msmgpio>; interrupts = <21 IRQ_TYPE_EDGE_RISING>; - en-gpios = <&msmgpio 20 GPIO_ACTIVE_HIGH>; + en-gpios = <&msmgpio 20 GPIO_ACTIVE_LOW>; wake-gpios = <&msmgpio 49 GPIO_ACTIVE_HIGH>; clocks = <&rpmcc RPM_SMD_BB_CLK2_PIN>; From 804ec4dad48c4fc7844c66b5febe9dbc6198f8b5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 11 Oct 2022 15:02:28 -0400 Subject: [PATCH 102/261] arm64: dts: qcom: sdm630: add UART pin functions Configure UART1 and UART2 pins to respective functions in default state, otherwise the pins might stay as GPIOs. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221011190231.76784-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index a6de40f06bac..ef48eb12a384 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -723,6 +723,7 @@ tlmm: pinctrl@3100000 { blsp1_uart1_default: blsp1-uart1-default { pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "blsp_uart1"; drive-strength = <2>; bias-disable; }; @@ -735,6 +736,7 @@ blsp1_uart1_sleep: blsp1-uart1-sleep { blsp1_uart2_default: blsp1-uart2-default { pins = "gpio4", "gpio5"; + function = "blsp_uart2"; drive-strength = <2>; bias-disable; }; From 06783c3ae8899aa71abc795d3d6490a4afa9ed99 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 11 Oct 2022 15:02:29 -0400 Subject: [PATCH 103/261] arm64: dts: qcom: sdm630: correct I2C8 pin functions The I2C8 pins are split into i2c8_a (GPIO30 and GPIO31) and i2c8_b (GPIO44 and GPIO52). Correct the name of function for I2C8 pins. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221011190231.76784-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index ef48eb12a384..6fb52c050397 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -885,14 +885,14 @@ i2c7_sleep: i2c7-sleep { i2c8_default: i2c8-default { pins = "gpio30", "gpio31"; - function = "blsp_i2c8"; + function = "blsp_i2c8_a"; drive-strength = <2>; bias-disable; }; i2c8_sleep: i2c8-sleep { pins = "gpio30", "gpio31"; - function = "blsp_i2c8"; + function = "blsp_i2c8_a"; drive-strength = <2>; bias-pull-up; }; From 048a765ac5712397cb58e374a7e1087c34875b5f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 11 Oct 2022 15:02:30 -0400 Subject: [PATCH 104/261] arm64: dts: qcom: sdm630: align TLMM pin configuration with DT schema DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. All nodes for GPIOs must also define the function property. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221011190231.76784-3-krzysztof.kozlowski@linaro.org --- .../boot/dts/qcom/sda660-inforce-ifc6560.dts | 6 +- .../dts/qcom/sdm630-sony-xperia-nile.dtsi | 18 ++- arch/arm64/boot/dts/qcom/sdm630.dtsi | 121 ++++++++---------- .../sdm636-sony-xperia-ganges-mermaid.dts | 2 +- .../boot/dts/qcom/sdm660-xiaomi-lavender.dts | 6 +- 5 files changed, 75 insertions(+), 78 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts index f49f18843f42..cddbeade1ffc 100644 --- a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts +++ b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts @@ -401,16 +401,18 @@ vreg_bob: bob { }; &sdc2_state_on { - sd-cd { + sd-cd-pins { pins = "gpio54"; + function = "gpio"; bias-pull-up; drive-strength = <2>; }; }; &sdc2_state_off { - sd-cd { + sd-cd-pins { pins = "gpio54"; + function = "gpio"; bias-disable; drive-strength = <2>; }; diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi index fe09628daf03..3d2b08d551d0 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi @@ -577,16 +577,18 @@ vreg_l19a_3p3: l19 { }; &sdc2_state_on { - sd-cd { + sd-cd-pins { pins = "gpio54"; + function = "gpio"; bias-pull-up; drive-strength = <2>; }; }; &sdc2_state_off { - sd-cd { + sd-cd-pins { pins = "gpio54"; + function = "gpio"; bias-disable; drive-strength = <2>; }; @@ -615,33 +617,35 @@ &sdhc_2 { &tlmm { gpio-reserved-ranges = <8 4>; - ts_int_active: ts-int-active { + ts_int_active: ts-int-active-state { pins = "gpio45"; + function = "gpio"; drive-strength = <8>; bias-pull-up; }; - ts_lcd_id_active: ts-lcd-id-active { + ts_lcd_id_active: ts-lcd-id-active-state { pins = "gpio56"; + function = "gpio"; drive-strength = <8>; bias-disable; }; - imx300_vana_default: imx300-vana-default { + imx300_vana_default: imx300-vana-default-state { pins = "gpio50"; function = "gpio"; bias-disable; drive-strength = <2>; }; - imx219_vana_default: imx219-vana-default { + imx219_vana_default: imx219-vana-default-state { pins = "gpio51"; function = "gpio"; bias-disable; drive-strength = <2>; }; - cam_vdig_default: cam-vdig-default { + cam_vdig_default: cam-vdig-default-state { pins = "gpio52"; function = "gpio"; bias-disable; diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 6fb52c050397..13e6a4fbba27 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -721,35 +721,36 @@ tlmm: pinctrl@3100000 { interrupt-controller; #interrupt-cells = <2>; - blsp1_uart1_default: blsp1-uart1-default { + blsp1_uart1_default: blsp1-uart1-default-state { pins = "gpio0", "gpio1", "gpio2", "gpio3"; function = "blsp_uart1"; drive-strength = <2>; bias-disable; }; - blsp1_uart1_sleep: blsp1-uart1-sleep { + blsp1_uart1_sleep: blsp1-uart1-sleep-state { pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "gpio"; drive-strength = <2>; bias-disable; }; - blsp1_uart2_default: blsp1-uart2-default { + blsp1_uart2_default: blsp1-uart2-default-state { pins = "gpio4", "gpio5"; function = "blsp_uart2"; drive-strength = <2>; bias-disable; }; - blsp2_uart1_default: blsp2-uart1-active { - tx-rts { + blsp2_uart1_default: blsp2-uart1-active-state { + tx-rts-pins { pins = "gpio16", "gpio19"; function = "blsp_uart5"; drive-strength = <2>; bias-disable; }; - rx { + rx-pins { /* * Avoid garbage data while BT module * is powered off or not driving signal @@ -760,7 +761,7 @@ rx { bias-pull-up; }; - cts { + cts-pins { /* Match the pull of the BT module */ pins = "gpio18"; function = "blsp_uart5"; @@ -769,15 +770,15 @@ cts { }; }; - blsp2_uart1_sleep: blsp2-uart1-sleep { - tx { + blsp2_uart1_sleep: blsp2-uart1-sleep-state { + tx-pins { pins = "gpio16"; function = "gpio"; drive-strength = <2>; bias-pull-up; }; - rx-cts-rts { + rx-cts-rts-pins { pins = "gpio17", "gpio18", "gpio19"; function = "gpio"; drive-strength = <2>; @@ -785,228 +786,216 @@ rx-cts-rts { }; }; - i2c1_default: i2c1-default { + i2c1_default: i2c1-default-state { pins = "gpio2", "gpio3"; function = "blsp_i2c1"; drive-strength = <2>; bias-disable; }; - i2c1_sleep: i2c1-sleep { + i2c1_sleep: i2c1-sleep-state { pins = "gpio2", "gpio3"; function = "blsp_i2c1"; drive-strength = <2>; bias-pull-up; }; - i2c2_default: i2c2-default { + i2c2_default: i2c2-default-state { pins = "gpio6", "gpio7"; function = "blsp_i2c2"; drive-strength = <2>; bias-disable; }; - i2c2_sleep: i2c2-sleep { + i2c2_sleep: i2c2-sleep-state { pins = "gpio6", "gpio7"; function = "blsp_i2c2"; drive-strength = <2>; bias-pull-up; }; - i2c3_default: i2c3-default { + i2c3_default: i2c3-default-state { pins = "gpio10", "gpio11"; function = "blsp_i2c3"; drive-strength = <2>; bias-disable; }; - i2c3_sleep: i2c3-sleep { + i2c3_sleep: i2c3-sleep-state { pins = "gpio10", "gpio11"; function = "blsp_i2c3"; drive-strength = <2>; bias-pull-up; }; - i2c4_default: i2c4-default { + i2c4_default: i2c4-default-state { pins = "gpio14", "gpio15"; function = "blsp_i2c4"; drive-strength = <2>; bias-disable; }; - i2c4_sleep: i2c4-sleep { + i2c4_sleep: i2c4-sleep-state { pins = "gpio14", "gpio15"; function = "blsp_i2c4"; drive-strength = <2>; bias-pull-up; }; - i2c5_default: i2c5-default { + i2c5_default: i2c5-default-state { pins = "gpio18", "gpio19"; function = "blsp_i2c5"; drive-strength = <2>; bias-disable; }; - i2c5_sleep: i2c5-sleep { + i2c5_sleep: i2c5-sleep-state { pins = "gpio18", "gpio19"; function = "blsp_i2c5"; drive-strength = <2>; bias-pull-up; }; - i2c6_default: i2c6-default { + i2c6_default: i2c6-default-state { pins = "gpio22", "gpio23"; function = "blsp_i2c6"; drive-strength = <2>; bias-disable; }; - i2c6_sleep: i2c6-sleep { + i2c6_sleep: i2c6-sleep-state { pins = "gpio22", "gpio23"; function = "blsp_i2c6"; drive-strength = <2>; bias-pull-up; }; - i2c7_default: i2c7-default { + i2c7_default: i2c7-default-state { pins = "gpio26", "gpio27"; function = "blsp_i2c7"; drive-strength = <2>; bias-disable; }; - i2c7_sleep: i2c7-sleep { + i2c7_sleep: i2c7-sleep-state { pins = "gpio26", "gpio27"; function = "blsp_i2c7"; drive-strength = <2>; bias-pull-up; }; - i2c8_default: i2c8-default { + i2c8_default: i2c8-default-state { pins = "gpio30", "gpio31"; function = "blsp_i2c8_a"; drive-strength = <2>; bias-disable; }; - i2c8_sleep: i2c8-sleep { + i2c8_sleep: i2c8-sleep-state { pins = "gpio30", "gpio31"; function = "blsp_i2c8_a"; drive-strength = <2>; bias-pull-up; }; - cci0_default: cci0_default { - pinmux { - pins = "gpio36","gpio37"; - function = "cci_i2c"; - }; - - pinconf { - pins = "gpio36","gpio37"; - bias-pull-up; - drive-strength = <2>; - }; + cci0_default: cci0-default-state { + pins = "gpio36","gpio37"; + function = "cci_i2c"; + bias-pull-up; + drive-strength = <2>; }; - cci1_default: cci1_default { - pinmux { - pins = "gpio38","gpio39"; - function = "cci_i2c"; - }; - - pinconf { - pins = "gpio38","gpio39"; - bias-pull-up; - drive-strength = <2>; - }; + cci1_default: cci1-default-state { + pins = "gpio38","gpio39"; + function = "cci_i2c"; + bias-pull-up; + drive-strength = <2>; }; - sdc1_state_on: sdc1-on { - clk { + sdc1_state_on: sdc1-on-state { + clk-pins { pins = "sdc1_clk"; bias-disable; drive-strength = <16>; }; - cmd { + cmd-pins { pins = "sdc1_cmd"; bias-pull-up; drive-strength = <10>; }; - data { + data-pins { pins = "sdc1_data"; bias-pull-up; drive-strength = <10>; }; - rclk { + rclk-pins { pins = "sdc1_rclk"; bias-pull-down; }; }; - sdc1_state_off: sdc1-off { - clk { + sdc1_state_off: sdc1-off-state { + clk-pins { pins = "sdc1_clk"; bias-disable; drive-strength = <2>; }; - cmd { + cmd-pins { pins = "sdc1_cmd"; bias-pull-up; drive-strength = <2>; }; - data { + data-pins { pins = "sdc1_data"; bias-pull-up; drive-strength = <2>; }; - rclk { + rclk-pins { pins = "sdc1_rclk"; bias-pull-down; }; }; - sdc2_state_on: sdc2-on { - clk { + sdc2_state_on: sdc2-on-state { + clk-pins { pins = "sdc2_clk"; bias-disable; drive-strength = <16>; }; - cmd { + cmd-pins { pins = "sdc2_cmd"; bias-pull-up; drive-strength = <10>; }; - data { + data-pins { pins = "sdc2_data"; bias-pull-up; drive-strength = <10>; }; }; - sdc2_state_off: sdc2-off { - clk { + sdc2_state_off: sdc2-off-state { + clk-pins { pins = "sdc2_clk"; bias-disable; drive-strength = <2>; }; - cmd { + cmd-pins { pins = "sdc2_cmd"; bias-pull-up; drive-strength = <2>; }; - data { + data-pins { pins = "sdc2_data"; bias-pull-up; drive-strength = <2>; diff --git a/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts b/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts index 58f687fc49e0..9702e5f59a1d 100644 --- a/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts +++ b/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts @@ -19,7 +19,7 @@ / { }; &sdc2_state_on { - clk { + clk-pins { drive-strength = <14>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index fea2c3e416e5..8fb2d1788742 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -372,16 +372,18 @@ &pm660l_wled { }; &sdc2_state_on { - sd-cd { + sd-cd-pins { pins = "gpio54"; + function = "gpio"; bias-pull-up; drive-strength = <2>; }; }; &sdc2_state_off { - sd-cd { + sd-cd-pins { pins = "gpio54"; + function = "gpio"; bias-disable; drive-strength = <2>; }; From 54a8d54b51839df625d376eb8684e51ceec08629 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 12 Oct 2022 23:56:13 +0200 Subject: [PATCH 105/261] arm64: dts: qcom: msm8996: remove bogus ufs_variant node This ufs_variant node seems to be a remnant from downstream devicetree. As it doesn't seem to be used by anything upstream, remove it from the dtsi. Signed-off-by: Luca Weiss Reviewed-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221012215613.32054-1-luca@z3ntu.xyz --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index a35fba4c0758..7547ad35b58e 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -2013,10 +2013,6 @@ ufshc: ufshc@624000 { lanes-per-direction = <1>; #reset-cells = <1>; status = "disabled"; - - ufs_variant { - compatible = "qcom,ufs_variant"; - }; }; ufsphy: phy@627000 { From e3d5e948d1b87e8531d842f4c98f56e0bb1a5c60 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 13 Oct 2022 17:06:09 -0400 Subject: [PATCH 106/261] arm64: dts: qcom: msm8998: add gpio-ranges to TLMM Qualcomm pinctrl bindings and drivers expect gpio-ranges property. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221013210612.95994-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index f150bae67b74..bc3c28513f2b 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -1056,6 +1056,7 @@ tlmm: pinctrl@3400000 { compatible = "qcom,msm8998-pinctrl"; reg = <0x03400000 0xc00000>; interrupts = ; + gpio-ranges = <&tlmm 0 0 150>; gpio-controller; #gpio-cells = <2>; interrupt-controller; From 46546f28825cf3a5ef6873b9cf947cd85c8a7258 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 13 Oct 2022 17:06:10 -0400 Subject: [PATCH 107/261] arm64: dts: qcom: msm8998-oneplus-cheeseburger: fix backlight pin function There is no "normal" function, so use "gpio" for backlight button pin configuration. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221013210612.95994-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts b/arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts index ef2a88a64d32..122f6c25220e 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts @@ -35,7 +35,7 @@ &pmi8998_gpio { button_backlight_default: button-backlight-state { pinconf { pins = "gpio5"; - function = "normal"; + function = "gpio"; bias-pull-down; qcom,drive-strength = ; }; From ed9ba9e9b7437416ed97b36fe06ecb6001f0b067 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 13 Oct 2022 17:06:11 -0400 Subject: [PATCH 108/261] arm64: dts: qcom: msm8998: align TLMM pin configuration with DT schema DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221013210612.95994-3-krzysztof.kozlowski@linaro.org --- .../boot/dts/qcom/msm8998-clamshell.dtsi | 7 +- .../boot/dts/qcom/msm8998-fxtec-pro1.dts | 16 ++-- arch/arm64/boot/dts/qcom/msm8998-mtp.dts | 4 +- .../dts/qcom/msm8998-oneplus-cheeseburger.dts | 10 +-- .../boot/dts/qcom/msm8998-oneplus-common.dtsi | 14 ++-- .../dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 30 ++++---- arch/arm64/boot/dts/qcom/msm8998.dtsi | 76 +++++++++---------- 7 files changed, 78 insertions(+), 79 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi b/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi index 63413e39572c..3b7172aa4037 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi @@ -35,7 +35,7 @@ bluetooth { }; &blsp1_uart3_on { - rx { + rx-pins { /delete-property/ bias-disable; /* * Configure a pull-up on 45 (RX). This is needed to @@ -46,7 +46,7 @@ rx { bias-pull-up; }; - cts { + cts-pins { /delete-property/ bias-disable; /* * Configure a pull-down on 47 (CTS) to match the pull @@ -357,8 +357,9 @@ &sdhc2 { &tlmm { gpio-reserved-ranges = <0 4>, <81 4>; - touchpad: touchpad-pin { + touchpad: touchpad-pin-state { pins = "gpio123"; + function = "gpio"; bias-pull-up; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts index a7a79ddd3bea..2aee2fd29a07 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts @@ -216,7 +216,7 @@ bluetooth { }; &blsp1_uart3_on { - rx { + rx-pins { /delete-property/ bias-disable; /* * Configure a pull-up on 45 (RX). This is needed to @@ -227,7 +227,7 @@ rx { bias-pull-up; }; - cts { + cts-pins { /delete-property/ bias-disable; /* * Configure a pull-down on 47 (CTS) to match the pull @@ -615,14 +615,14 @@ &remoteproc_slpi { &tlmm { gpio-reserved-ranges = <0 4>; - mdp_vsync_n: mdp-vsync-n { + mdp_vsync_n: mdp-vsync-n-state { pins = "gpio10"; function = "mdp_vsync_a"; bias-pull-down; drive-strength = <2>; }; - gpio_kb_pins_extra: gpio-kb-pins-extra { + gpio_kb_pins_extra: gpio-kb-pins-extra-state { pins = "gpio21", "gpio32", "gpio33", "gpio114", "gpio128", "gpio129"; function = "gpio"; @@ -630,21 +630,21 @@ gpio_kb_pins_extra: gpio-kb-pins-extra { bias-pull-up; }; - ts_vio_default: ts-vio-def { + ts_vio_default: ts-vio-def-state { pins = "gpio81"; function = "gpio"; bias-disable; drive-strength = <2>; }; - ts_rst_n: ts-rst-n { + ts_rst_n: ts-rst-n-state { pins = "gpio89"; function = "gpio"; bias-pull-up; drive-strength = <8>; }; - hall_sensor1_default: hall-sensor1-def { + hall_sensor1_default: hall-sensor1-def-state { pins = "gpio124"; function = "gpio"; bias-disable; @@ -652,7 +652,7 @@ hall_sensor1_default: hall-sensor1-def { input-enable; }; - ts_int_n: ts-int-n { + ts_int_n: ts-int-n-state { pins = "gpio125"; function = "gpio"; bias-disable; diff --git a/arch/arm64/boot/dts/qcom/msm8998-mtp.dts b/arch/arm64/boot/dts/qcom/msm8998-mtp.dts index abea3ffa0094..00032ed3f4aa 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-mtp.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-mtp.dts @@ -46,7 +46,7 @@ bluetooth { }; &blsp1_uart3_on { - rx { + rx-pins { /delete-property/ bias-disable; /* * Configure a pull-up on 45 (RX). This is needed to @@ -57,7 +57,7 @@ rx { bias-pull-up; }; - cts { + cts-pins { /delete-property/ bias-disable; /* * Configure a pull-down on 47 (CTS) to match the pull diff --git a/arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts b/arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts index 122f6c25220e..b951f98d1b7b 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts @@ -33,11 +33,9 @@ button-backlight { &pmi8998_gpio { button_backlight_default: button-backlight-state { - pinconf { - pins = "gpio5"; - function = "gpio"; - bias-pull-down; - qcom,drive-strength = ; - }; + pins = "gpio5"; + function = "gpio"; + bias-pull-down; + qcom,drive-strength = ; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi index 3af6deed2e86..5b058c7693ff 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi @@ -233,7 +233,7 @@ bluetooth { }; &blsp1_uart3_on { - rx { + rx-pins { /delete-property/ bias-disable; /* * Configure a pull-up on 46 (RX). This is needed to @@ -244,7 +244,7 @@ rx { bias-pull-up; }; - cts { + cts-pins { /delete-property/ bias-disable; /* * Configure a pull-down on 47 (CTS) to match the pull @@ -492,7 +492,7 @@ vreg_bob: bob { &tlmm { gpio-reserved-ranges = <0 4>, <81 4>; - hall_sensor_default: hall-sensor-default { + hall_sensor_default: hall-sensor-default-state { pins = "gpio124"; function = "gpio"; drive-strength = <2>; @@ -500,28 +500,28 @@ hall_sensor_default: hall-sensor-default { input-enable; }; - ts_int_active: ts-int-active { + ts_int_active: ts-int-active-state { pins = "gpio125"; function = "gpio"; drive-strength = <8>; bias-pull-up; }; - ts_reset_active: ts-reset-active { + ts_reset_active: ts-reset-active-state { pins = "gpio89"; function = "gpio"; drive-strength = <8>; bias-pull-up; }; - nfc_int_active: nfc-int-active { + nfc_int_active: nfc-int-active-state { pins = "gpio92"; function = "gpio"; drive-strength = <6>; bias-pull-up; }; - nfc_enable_active: nfc-enable-active { + nfc_enable_active: nfc-enable-active-state { pins = "gpio12", "gpio116"; function = "gpio"; drive-strength = <6>; diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index 332eda4ae50f..5da87baa2b23 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -596,14 +596,14 @@ &sdhc2 { &tlmm { gpio-reserved-ranges = <0 4>, <81 4>; - mdp_vsync_n: mdp-vsync-n { + mdp_vsync_n: mdp-vsync-n-state { pins = "gpio10"; function = "mdp_vsync_a"; drive-strength = <2>; bias-pull-down; }; - nfc_ven: nfc-ven { + nfc_ven: nfc-ven-state { pins = "gpio12"; function = "gpio"; bias-disable; @@ -611,42 +611,42 @@ nfc_ven: nfc-ven { output-low; }; - msm_mclk0_default: msm-mclk0-active { + msm_mclk0_default: msm-mclk0-active-state { pins = "gpio13"; function = "cam_mclk"; drive-strength = <2>; bias-disable; }; - msm_mclk1_default: msm-mclk1-active { + msm_mclk1_default: msm-mclk1-active-state { pins = "gpio14"; function = "cam_mclk"; drive-strength = <2>; bias-disable; }; - cci0_default: cci0-default { + cci0_default: cci0-default-state { pins = "gpio18", "gpio19"; function = "cci_i2c"; bias-disable; drive-strength = <2>; }; - cci1_default: cci1-default { + cci1_default: cci1-default-state { pins = "gpio19", "gpio20"; function = "cci_i2c"; bias-disable; drive-strength = <2>; }; - cam0_vdig_default: cam0-vdig-default { + cam0_vdig_default: cam0-vdig-default-state { pins = "gpio21"; function = "gpio"; bias-disable; drive-strength = <2>; }; - tof_int: tof-int { + tof_int: tof-int-state { pins = "gpio22"; function = "gpio"; bias-pull-up; @@ -654,28 +654,28 @@ tof_int: tof-int { input-enable; }; - cam1_vdig_default: cam1-vdig-default { + cam1_vdig_default: cam1-vdig-default-state { pins = "gpio25"; function = "gpio"; bias-disable; drive-strength = <2>; }; - usb_extcon_active: usb-extcon-active { + usb_extcon_active: usb-extcon-active-state { pins = "gpio38"; function = "gpio"; bias-disable; drive-strength = <16>; }; - tof_reset: tof-reset { + tof_reset: tof-reset-state { pins = "gpio27"; function = "gpio"; bias-disable; drive-strength = <2>; }; - hall_sensor0_default: acc-cover-open { + hall_sensor0_default: acc-cover-open-state { pins = "gpio124"; function = "gpio"; bias-disable; @@ -683,14 +683,14 @@ hall_sensor0_default: acc-cover-open { input-enable; }; - ts_int_n: ts-int-n { + ts_int_n: ts-int-n-state { pins = "gpio125"; function = "gpio"; drive-strength = <8>; bias-pull-up; }; - usb_vbus_active: usb-vbus-active { + usb_vbus_active: usb-vbus-active-state { pins = "gpio128"; function = "gpio"; bias-disable; @@ -698,7 +698,7 @@ usb_vbus_active: usb-vbus-active { output-low; }; - ts_vddio_en: ts-vddio-en-default { + ts_vddio_en: ts-vddio-en-default-state { pins = "gpio133"; function = "gpio"; bias-disable; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index bc3c28513f2b..da2dd87e3f4f 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -1062,76 +1062,76 @@ tlmm: pinctrl@3400000 { interrupt-controller; #interrupt-cells = <2>; - sdc2_on: sdc2-on { - clk { + sdc2_on: sdc2-on-state { + clk-pins { pins = "sdc2_clk"; drive-strength = <16>; bias-disable; }; - cmd { + cmd-pins { pins = "sdc2_cmd"; drive-strength = <10>; bias-pull-up; }; - data { + data-pins { pins = "sdc2_data"; drive-strength = <10>; bias-pull-up; }; }; - sdc2_off: sdc2-off { - clk { + sdc2_off: sdc2-off-state { + clk-pins { pins = "sdc2_clk"; drive-strength = <2>; bias-disable; }; - cmd { + cmd-pins { pins = "sdc2_cmd"; drive-strength = <2>; bias-pull-up; }; - data { + data-pins { pins = "sdc2_data"; drive-strength = <2>; bias-pull-up; }; }; - sdc2_cd: sdc2-cd { + sdc2_cd: sdc2-cd-state { pins = "gpio95"; function = "gpio"; bias-pull-up; drive-strength = <2>; }; - blsp1_uart3_on: blsp1-uart3-on { - tx { + blsp1_uart3_on: blsp1-uart3-on-state { + tx-pins { pins = "gpio45"; function = "blsp_uart3_a"; drive-strength = <2>; bias-disable; }; - rx { + rx-pins { pins = "gpio46"; function = "blsp_uart3_a"; drive-strength = <2>; bias-disable; }; - cts { + cts-pins { pins = "gpio47"; function = "blsp_uart3_a"; drive-strength = <2>; bias-disable; }; - rfr { + rfr-pins { pins = "gpio48"; function = "blsp_uart3_a"; drive-strength = <2>; @@ -1139,168 +1139,168 @@ rfr { }; }; - blsp1_i2c1_default: blsp1-i2c1-default { + blsp1_i2c1_default: blsp1-i2c1-default-state { pins = "gpio2", "gpio3"; function = "blsp_i2c1"; drive-strength = <2>; bias-disable; }; - blsp1_i2c1_sleep: blsp1-i2c1-sleep { + blsp1_i2c1_sleep: blsp1-i2c1-sleep-state-state { pins = "gpio2", "gpio3"; function = "blsp_i2c1"; drive-strength = <2>; bias-pull-up; }; - blsp1_i2c2_default: blsp1-i2c2-default { + blsp1_i2c2_default: blsp1-i2c2-default-state { pins = "gpio32", "gpio33"; function = "blsp_i2c2"; drive-strength = <2>; bias-disable; }; - blsp1_i2c2_sleep: blsp1-i2c2-sleep { + blsp1_i2c2_sleep: blsp1-i2c2-sleep-state-state { pins = "gpio32", "gpio33"; function = "blsp_i2c2"; drive-strength = <2>; bias-pull-up; }; - blsp1_i2c3_default: blsp1-i2c3-default { + blsp1_i2c3_default: blsp1-i2c3-default-state { pins = "gpio47", "gpio48"; function = "blsp_i2c3"; drive-strength = <2>; bias-disable; }; - blsp1_i2c3_sleep: blsp1-i2c3-sleep { + blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { pins = "gpio47", "gpio48"; function = "blsp_i2c3"; drive-strength = <2>; bias-pull-up; }; - blsp1_i2c4_default: blsp1-i2c4-default { + blsp1_i2c4_default: blsp1-i2c4-default-state { pins = "gpio10", "gpio11"; function = "blsp_i2c4"; drive-strength = <2>; bias-disable; }; - blsp1_i2c4_sleep: blsp1-i2c4-sleep { + blsp1_i2c4_sleep: blsp1-i2c4-sleep-state { pins = "gpio10", "gpio11"; function = "blsp_i2c4"; drive-strength = <2>; bias-pull-up; }; - blsp1_i2c5_default: blsp1-i2c5-default { + blsp1_i2c5_default: blsp1-i2c5-default-state { pins = "gpio87", "gpio88"; function = "blsp_i2c5"; drive-strength = <2>; bias-disable; }; - blsp1_i2c5_sleep: blsp1-i2c5-sleep { + blsp1_i2c5_sleep: blsp1-i2c5-sleep-state { pins = "gpio87", "gpio88"; function = "blsp_i2c5"; drive-strength = <2>; bias-pull-up; }; - blsp1_i2c6_default: blsp1-i2c6-default { + blsp1_i2c6_default: blsp1-i2c6-default-state { pins = "gpio43", "gpio44"; function = "blsp_i2c6"; drive-strength = <2>; bias-disable; }; - blsp1_i2c6_sleep: blsp1-i2c6-sleep { + blsp1_i2c6_sleep: blsp1-i2c6-sleep-state { pins = "gpio43", "gpio44"; function = "blsp_i2c6"; drive-strength = <2>; bias-pull-up; }; /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */ - blsp2_i2c1_default: blsp2-i2c1-default { + blsp2_i2c1_default: blsp2-i2c1-default-state { pins = "gpio55", "gpio56"; function = "blsp_i2c7"; drive-strength = <2>; bias-disable; }; - blsp2_i2c1_sleep: blsp2-i2c1-sleep { + blsp2_i2c1_sleep: blsp2-i2c1-sleep-state { pins = "gpio55", "gpio56"; function = "blsp_i2c7"; drive-strength = <2>; bias-pull-up; }; - blsp2_i2c2_default: blsp2-i2c2-default { + blsp2_i2c2_default: blsp2-i2c2-default-state { pins = "gpio6", "gpio7"; function = "blsp_i2c8"; drive-strength = <2>; bias-disable; }; - blsp2_i2c2_sleep: blsp2-i2c2-sleep { + blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { pins = "gpio6", "gpio7"; function = "blsp_i2c8"; drive-strength = <2>; bias-pull-up; }; - blsp2_i2c3_default: blsp2-i2c3-default { + blsp2_i2c3_default: blsp2-i2c3-default-state { pins = "gpio51", "gpio52"; function = "blsp_i2c9"; drive-strength = <2>; bias-disable; }; - blsp2_i2c3_sleep: blsp2-i2c3-sleep { + blsp2_i2c3_sleep: blsp2-i2c3-sleep-state { pins = "gpio51", "gpio52"; function = "blsp_i2c9"; drive-strength = <2>; bias-pull-up; }; - blsp2_i2c4_default: blsp2-i2c4-default { + blsp2_i2c4_default: blsp2-i2c4-default-state { pins = "gpio67", "gpio68"; function = "blsp_i2c10"; drive-strength = <2>; bias-disable; }; - blsp2_i2c4_sleep: blsp2-i2c4-sleep { + blsp2_i2c4_sleep: blsp2-i2c4-sleep-state { pins = "gpio67", "gpio68"; function = "blsp_i2c10"; drive-strength = <2>; bias-pull-up; }; - blsp2_i2c5_default: blsp2-i2c5-default { + blsp2_i2c5_default: blsp2-i2c5-default-state { pins = "gpio60", "gpio61"; function = "blsp_i2c11"; drive-strength = <2>; bias-disable; }; - blsp2_i2c5_sleep: blsp2-i2c5-sleep { + blsp2_i2c5_sleep: blsp2-i2c5-sleep-state { pins = "gpio60", "gpio61"; function = "blsp_i2c11"; drive-strength = <2>; bias-pull-up; }; - blsp2_i2c6_default: blsp2-i2c6-default { + blsp2_i2c6_default: blsp2-i2c6-default-state { pins = "gpio83", "gpio84"; function = "blsp_i2c12"; drive-strength = <2>; bias-disable; }; - blsp2_i2c6_sleep: blsp2-i2c6-sleep { + blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { pins = "gpio83", "gpio84"; function = "blsp_i2c12"; drive-strength = <2>; From 0cde1210f7b9f6f17f3af450bde598c0ad9d54cc Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Sun, 16 Oct 2022 11:00:31 +0200 Subject: [PATCH 109/261] arm64: dts: qcom: sc7280: Fix cpufreq-epss compatible The bindings require a SoC-specific compatible to be used next to qcom,cpufreq-epss. Add it to make dtbs_check happy. Signed-off-by: Luca Weiss Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221016090035.565350-2-luca@z3ntu.xyz --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 5f4142ab85b8..cb981174612a 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -5355,7 +5355,7 @@ epss_l3: interconnect@18590000 { }; cpufreq_hw: cpufreq@18591000 { - compatible = "qcom,cpufreq-epss"; + compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss"; reg = <0 0x18591000 0 0x1000>, <0 0x18592000 0 0x1000>, <0 0x18593000 0 0x1000>; From 691dfbf54214c9c42444f357fc3a8103a10ad738 Mon Sep 17 00:00:00 2001 From: Caleb Connolly Date: Sun, 16 Oct 2022 18:29:41 +0100 Subject: [PATCH 110/261] arm64: dts: qcom: sdm845: commonize bluetooth UART pinmux The 4-pin configuration for UART6 is used for all or almost all SDM845 devices with built in Bluetooth. Move the pinmux configuration to sdm845.dtsi in preparation to be removed from individual devices in future patches. Suggested-by: Dmitry Baryshkov Signed-off-by: Caleb Connolly Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221016172944.1892206-2-kc@postmarketos.org --- arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 37 +------------------ arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 25 +------------ .../boot/dts/qcom/sdm845-oneplus-common.dtsi | 28 +------------- .../qcom/sdm845-xiaomi-beryllium-common.dtsi | 27 +------------- .../boot/dts/qcom/sdm845-xiaomi-polaris.dts | 27 +------------- arch/arm64/boot/dts/qcom/sdm845.dtsi | 22 +++++++++++ 6 files changed, 32 insertions(+), 134 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi index 5eafb556cc0c..41aedb60e16d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -860,6 +860,8 @@ i2c_tunnel: i2c-tunnel { &uart6 { status = "okay"; + pinctrl-0 = <&qup_uart6_4pin>; + bluetooth: wcn3990-bt { compatible = "qcom,wcn3990-bt"; vddio-supply = <&src_pp1800_s4a>; @@ -1079,41 +1081,6 @@ pinconf { }; }; -&qup_uart6_default { - /* Change pinmux to all 4 pins since CTS and RTS are connected */ - pinmux { - pins = "gpio45", "gpio46", - "gpio47", "gpio48"; - }; - - pinconf-cts { - /* - * Configure a pull-down on 45 (CTS) to match the pull of - * the Bluetooth module. - */ - pins = "gpio45"; - bias-pull-down; - }; - - pinconf-rts-tx { - /* We'll drive 46 (RTS) and 47 (TX), so no pull */ - pins = "gpio46", "gpio47"; - drive-strength = <2>; - bias-disable; - }; - - pinconf-rx { - /* - * Configure a pull-up on 48 (RX). This is needed to avoid - * garbage data when the TX pin of the Bluetooth module is - * in tri-state (module powered off or not driving the - * signal yet). - */ - pins = "gpio48"; - bias-pull-up; - }; -}; - &qup_uart9_default { pinconf-tx { pins = "gpio4"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 72d26ceb4baf..741968ef6f31 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -986,6 +986,8 @@ &uart3 { &uart6 { status = "okay"; + pinctrl-0 = <&qup_uart6_4pin>; + bluetooth { compatible = "qcom,wcn3990-bt"; @@ -1144,29 +1146,6 @@ pinconf { }; }; -&qup_uart6_default { - pinmux { - pins = "gpio45", "gpio46", "gpio47", "gpio48"; - function = "qup6"; - }; - - cts { - pins = "gpio45"; - bias-disable; - }; - - rts-tx { - pins = "gpio46", "gpio47"; - drive-strength = <2>; - bias-disable; - }; - - rx { - pins = "gpio48"; - bias-pull-up; - }; -}; - &qup_uart9_default { pinconf-tx { pins = "gpio4"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 392461c29e76..02ec0fa4e5f0 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -500,35 +500,11 @@ pinconf-rx { }; }; -/* - * Prevent garbage data on bluetooth UART lines - */ -&qup_uart6_default { - pinmux { - pins = "gpio45", "gpio46", "gpio47", "gpio48"; - function = "qup6"; - }; - - cts { - pins = "gpio45"; - bias-pull-down; - }; - - rts-tx { - pins = "gpio46", "gpio47"; - drive-strength = <2>; - bias-disable; - }; - - rx { - pins = "gpio48"; - bias-pull-up; - }; -}; - &uart6 { status = "okay"; + pinctrl-0 = <&qup_uart6_4pin>; + bluetooth { compatible = "qcom,wcn3990-bt"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index 163bf9c1a1d8..bcd8e7a97f1e 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -480,6 +480,8 @@ wcd_intr_default: wcd_intr_default { &uart6 { status = "okay"; + pinctrl-0 = <&qup_uart6_4pin>; + bluetooth { compatible = "qcom,wcn3990-bt"; @@ -566,28 +568,3 @@ &wifi { vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; vdd-3.3-ch1-supply = <&vreg_l23a_3p3>; }; - -/* PINCTRL - additions to nodes defined in sdm845.dtsi */ - -&qup_uart6_default { - pinmux { - pins = "gpio45", "gpio46", "gpio47", "gpio48"; - function = "qup6"; - }; - - cts { - pins = "gpio45"; - bias-disable; - }; - - rts-tx { - pins = "gpio46", "gpio47"; - drive-strength = <2>; - bias-disable; - }; - - rx { - pins = "gpio48"; - bias-pull-up; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts index 4081822e0686..fc189f7caaa4 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts @@ -639,6 +639,8 @@ wcd_intr_default: wcd-intr-default { &uart6 { status = "okay"; + pinctrl-0 = <&qup_uart6_4pin>; + bluetooth { compatible = "qcom,wcn3990-bt"; @@ -735,28 +737,3 @@ &wifi { qcom,snoc-host-cap-skip-quirk; status = "okay"; }; - -/* PINCTRL - additions to nodes defined in sdm845.dtsi */ - -&qup_uart6_default { - pinmux { - pins = "gpio45", "gpio46", "gpio47", "gpio48"; - function = "qup6"; - }; - - cts { - pins = "gpio45"; - bias-disable; - }; - - rts-tx { - pins = "gpio46", "gpio47"; - drive-strength = <2>; - bias-disable; - }; - - rx { - pins = "gpio48"; - bias-pull-up; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 5f867b1a2df0..1a257f672887 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -3008,6 +3008,28 @@ pinmux { }; }; + qup_uart6_4pin: qup-uart6-4pin-state { + + cts-pins { + pins = "gpio45"; + function = "qup6"; + bias-pull-down; + }; + + rts-tx-pins { + pins = "gpio46", "gpio47"; + function = "qup6"; + drive-strength = <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio48"; + function = "qup6"; + bias-pull-up; + }; + }; + qup_uart7_default: qup-uart7-default { pinmux { pins = "gpio95", "gpio96"; From 9833e23b6905d0ab342deb16a6c2312759ab5a0d Mon Sep 17 00:00:00 2001 From: Dylan Van Assche Date: Sun, 16 Oct 2022 18:29:42 +0100 Subject: [PATCH 111/261] arm64: dts: qcom: sdm845-shift-axolotl: fix Bluetooth Add serial1 alias, firmware name and use 4 pin UART pinmux. Signed-off-by: Dylan Van Assche Signed-off-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221016172944.1892206-3-kc@postmarketos.org --- arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index 83261c9bb4f2..bb77ccfdc68c 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -23,6 +23,7 @@ / { aliases { display0 = &framebuffer0; serial0 = &uart9; + serial1 = &uart6; }; chosen { @@ -693,9 +694,17 @@ config { &uart6 { status = "okay"; + pinctrl-0 = <&qup_uart6_4pin>; + bluetooth { compatible = "qcom,wcn3990-bt"; + /* + * This path is relative to the qca/ + * subdir under lib/firmware. + */ + firmware-name = "axolotl/crnv21.bin"; + vddio-supply = <&vreg_s4a_1p8>; vddxo-supply = <&vreg_l7a_1p8>; vddrf-supply = <&vreg_l17a_1p3>; From 4772c03002c3eb2fc6dd0f908af0d8371a622499 Mon Sep 17 00:00:00 2001 From: Caleb Connolly Date: Sun, 16 Oct 2022 18:29:43 +0100 Subject: [PATCH 112/261] arm64: dts: qcom: sdm845-*: fix uart6 aliases Some devices have been using hsuart0 as an alias for the bluetooth UART, rename this to serial1 Signed-off-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221016172944.1892206-4-kc@postmarketos.org --- arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 2 +- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 2 +- arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 2 +- arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi index 41aedb60e16d..ca676e04687b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -16,7 +16,7 @@ / { aliases { bluetooth0 = &bluetooth; - hsuart0 = &uart6; + serial1 = &uart6; serial0 = &uart9; wifi0 = &wifi; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 741968ef6f31..8ba3188ac4c3 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -22,7 +22,7 @@ / { aliases { serial0 = &uart9; - hsuart0 = &uart6; + serial1 = &uart6; }; chosen { diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 02ec0fa4e5f0..5d99908d4628 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -19,7 +19,7 @@ / { aliases { serial0 = &uart9; - hsuart0 = &uart6; + serial1 = &uart6; }; chosen { diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index bcd8e7a97f1e..c2bed7b4ade8 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -33,7 +33,7 @@ / { qcom,msm-id = <321 0x20001>; aliases { - hsuart0 = &uart6; + serial1 = &uart6; }; gpio-keys { From c0b9575a36069f52f09fbe9b8f7a9db940cb952c Mon Sep 17 00:00:00 2001 From: Vladimir Lypak Date: Sun, 16 Oct 2022 18:15:52 +0200 Subject: [PATCH 113/261] arm64: dts: qcom: msm8953: add APPS IOMMU Add the nodes describing the iommu and its context banks that are found on msm8953 SoCs. Signed-off-by: Vladimir Lypak Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221016161554.673006-3-luca@z3ntu.xyz --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 36 +++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index db94e6fd18f5..5fa2d5b9ee06 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -726,6 +726,42 @@ tcsr_phy_clk_scheme_sel: syscon@193f044 { reg = <0x193f044 0x4>; }; + apps_iommu: iommu@1e00000 { + compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v1"; + ranges = <0 0x1e20000 0x20000>; + + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_APSS_TCU_ASYNC_CLK>; + clock-names = "iface", "bus"; + + qcom,iommu-secure-id = <17>; + + #address-cells = <1>; + #iommu-cells = <1>; + #size-cells = <1>; + + // vfe + iommu-ctx@14000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x14000 0x1000>; + interrupts = ; + }; + + // mdp_0 + iommu-ctx@15000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x15000 0x1000>; + interrupts = ; + }; + + // venus_ns + iommu-ctx@16000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x16000 0x1000>; + interrupts = ; + }; + }; + spmi_bus: spmi@200f000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x200f000 0x1000>, From cf6c35d1bc89e0942c379f841e1d9095fc66d642 Mon Sep 17 00:00:00 2001 From: Vladimir Lypak Date: Sun, 16 Oct 2022 18:15:53 +0200 Subject: [PATCH 114/261] arm64: dts: qcom: msm8953: add MDSS Add the MDSS, MDP and DSI nodes that are found on msm8953 SoC. Signed-off-by: Vladimir Lypak Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221016161554.673006-4-luca@z3ntu.xyz --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 208 ++++++++++++++++++++++++++ 1 file changed, 208 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 5fa2d5b9ee06..f2ff18ac9141 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -726,6 +726,214 @@ tcsr_phy_clk_scheme_sel: syscon@193f044 { reg = <0x193f044 0x4>; }; + mdss: mdss@1a00000 { + compatible = "qcom,mdss"; + + reg = <0x1a00000 0x1000>, + <0x1ab0000 0x1040>; + reg-names = "mdss_phys", + "vbif_phys"; + + power-domains = <&gcc MDSS_GDSC>; + interrupts = ; + + interrupt-controller; + #interrupt-cells = <1>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>, + <&gcc GCC_MDSS_MDP_CLK>; + clock-names = "iface", + "bus", + "vsync", + "core"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + status = "disabled"; + + mdp: mdp@1a01000 { + compatible = "qcom,msm8953-mdp5", "qcom,mdp5"; + reg = <0x1a01000 0x89000>; + reg-names = "mdp_phys"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + power-domains = <&gcc MDSS_GDSC>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "core", + "vsync"; + + iommus = <&apps_iommu 0x15>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdp5_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + mdp5_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; + + dsi0: dsi@1a94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0x1a94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + assigned-clocks = <&gcc BYTE0_CLK_SRC>, + <&gcc PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, + <&dsi0_phy 1>; + + clocks = <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + clock-names = "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core"; + + phys = <&dsi0_phy>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&mdp5_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi0_phy: phy@1a94400 { + compatible = "qcom,dsi-phy-14nm-8953"; + reg = <0x1a94400 0x100>, + <0x1a94500 0x300>, + <0x1a94800 0x188>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, <&xo_board>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + dsi1: dsi@1a96000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0x1a96000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + assigned-clocks = <&gcc BYTE1_CLK_SRC>, + <&gcc PCLK1_CLK_SRC>; + assigned-clock-parents = <&dsi1_phy 0>, + <&dsi1_phy 1>; + + clocks = <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_BYTE1_CLK>, + <&gcc GCC_MDSS_PCLK1_CLK>, + <&gcc GCC_MDSS_ESC1_CLK>; + clock-names = "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core"; + + phys = <&dsi1_phy>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&mdp5_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: phy@1a96400 { + compatible = "qcom,dsi-phy-14nm-8953"; + reg = <0x1a96400 0x100>, + <0x1a96500 0x300>, + <0x1a96800 0x188>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, <&xo_board>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + }; + apps_iommu: iommu@1e00000 { compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v1"; ranges = <0 0x1e20000 0x20000>; From aab0dd5cf11f8d9edd766e2b65f65a4cf1166c7c Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Tue, 28 Jun 2022 13:04:35 +0100 Subject: [PATCH 115/261] arm64: dts: qcom: msm8916: Fix lpass compat string to match yaml The documented yaml compat string for the apq8016 is "qcom,apq8016-lpass-cpu" not "qcom,lpass-cpu-apq8016". Looking at the other lpass compat strings the general form is "qcom,socnum-lpass-cpu". We need to fix both the driver and dts to match. Signed-off-by: Bryan O'Donoghue Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220628120435.3044939-3-bryan.odonoghue@linaro.org --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index a60eb8a59dca..c938d6715ca6 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1437,7 +1437,7 @@ sound: sound@7702000 { lpass: audio-controller@7708000 { status = "disabled"; - compatible = "qcom,lpass-cpu-apq8016"; + compatible = "qcom,apq8016-lpass-cpu"; /* * Note: Unlike the name would suggest, the SEC_I2S_CLK From 5ffe618764a36c2d259674b854abd574790ea56b Mon Sep 17 00:00:00 2001 From: Nikita Travkin Date: Thu, 20 Oct 2022 11:56:08 +0000 Subject: [PATCH 116/261] arm64: dts: qcom: msm8916-samsung-a2015: Add vibrator Both a2015 devices use motor drivers controlled with PWM signal. A5 additionally has a fixed regulator that powers the driver and is controlled by enable signal. A3 routes that enable signal to the motor driver itself. To simplify the description, add the motor to the common dtsi and assume a regulator is used for both. Signed-off-by: Nikita Travkin [Rename the nodes to be reusable in msm8916-sansung-e2015] Signed-off-by: Lin, Meng-Bo Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221020115255.2026-1-linmengbo0689@protonmail.com --- .../qcom/msm8916-samsung-a2015-common.dtsi | 52 +++++++++++++++++++ .../boot/dts/qcom/msm8916-samsung-a3u-eur.dts | 8 +++ .../boot/dts/qcom/msm8916-samsung-a5u-eur.dts | 8 +++ .../qcom/msm8916-samsung-e2015-common.dtsi | 26 ++-------- 4 files changed, 73 insertions(+), 21 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index 5f7cec347a4f..2a074e70c4da 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -23,6 +23,17 @@ tz-apps@85500000 { }; }; + clk_pwm: pwm { + compatible = "clk-pwm"; + #pwm-cells = <2>; + + clocks = <&gcc GCC_GP2_CLK>; + + pinctrl-names = "default"; + pinctrl-0 = <&motor_pwm_default>; + status = "disabled"; + }; + gpio-keys { compatible = "gpio-keys"; @@ -61,6 +72,24 @@ event-hall-sensor { }; }; + /* + * NOTE: A5 connects GPIO 76 to a reglator powering the motor + * driver IC but A3 connects the same signal to an ENABLE pin of + * the driver. + */ + reg_motor_vdd: regulator-motor-vdd { + compatible = "regulator-fixed"; + regulator-name = "motor_vdd"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + gpio = <&msmgpio 76 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&motor_en_default>; + }; + reg_vdd_tsp_a: regulator-vdd-tsp-a { compatible = "regulator-fixed"; regulator-name = "vdd_tsp_a"; @@ -153,6 +182,16 @@ nfc@27 { pinctrl-0 = <&nfc_default &nfc_clk_req>; }; }; + + vibrator: vibrator { + compatible = "pwm-vibrator"; + + pwms = <&clk_pwm 0 100000>; + pwm-names = "enable"; + + vcc-supply = <®_motor_vdd>; + status = "disabled"; + }; }; &blsp_i2c2 { @@ -397,6 +436,19 @@ mdss_sleep: mdss-sleep { }; }; + motor_en_default: motor-en-default { + pins = "gpio76"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + motor_pwm_default: motor-pwm-default { + pins = "gpio50"; + function = "gcc_gp2_clk_a"; + }; + muic_i2c_default: muic-i2c-default { pins = "gpio105", "gpio106"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts index 6db5f78ca286..d495d5ae5cc3 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts @@ -81,6 +81,10 @@ touchscreen@20 { }; }; +&clk_pwm { + status = "okay"; +}; + &dsi0 { panel@0 { reg = <0>; @@ -104,6 +108,10 @@ &dsi0_out { remote-endpoint = <&panel_in>; }; +&vibrator { + status = "okay"; +}; + &msmgpio { panel_vdd3_default: panel-vdd3-default { pins = "gpio9"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts index 5fb8ecd0c9ca..c03504ab27b7 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts @@ -50,6 +50,10 @@ touchscreen@48 { }; }; +&clk_pwm { + status = "okay"; +}; + &pronto { iris { compatible = "qcom,wcn3660b"; @@ -61,6 +65,10 @@ &touchkey { vdd-supply = <®_touch_key>; }; +&vibrator { + status = "okay"; +}; + &msmgpio { tkey_en_default: tkey-en-default { pins = "gpio97"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi index 542010fdfb8a..edd24b597a15 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi @@ -26,19 +26,6 @@ muic: extcon@14 { }; }; - reg_motor_vdd: regulator-motor-vdd { - compatible = "regulator-fixed"; - regulator-name = "motor_vdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&msmgpio 76 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&motor_en_default>; - }; - reg_touch_key: regulator-touch-key { compatible = "regulator-fixed"; regulator-name = "touch_key"; @@ -61,20 +48,17 @@ &blsp_i2c2 { /delete-node/ magnetometer@12; }; +®_motor_vdd { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +}; + &touchkey { vcc-supply = <®_touch_key>; vdd-supply = <®_touch_key>; }; &msmgpio { - motor_en_default: motor-en-default { - pins = "gpio76"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - tkey_en_default: tkey-en-default { pins = "gpio97"; function = "gpio"; From c4cd760d369604976a6ce97210b909a255985bda Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Mon, 24 Oct 2022 14:58:43 +0200 Subject: [PATCH 117/261] arm64: dts: qcom: sc8280xp: add TCSR node Add the TCSR node which is needed for PCIe configuration. Signed-off-by: Johan Hovold Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221024125843.25261-1-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 9fad81bd22d2..c1becbf949c3 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -983,6 +983,11 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells = <1>; }; + tcsr: syscon@1fc0000 { + compatible = "qcom,sc8280xp-tcsr", "syscon"; + reg = <0x0 0x01fc0000 0x0 0x30000>; + }; + usb_0_hsphy: phy@88e5000 { compatible = "qcom,sc8280xp-usb-hs-phy", "qcom,usb-snps-hs-5nm-phy"; From f1f9a6a0b9d0dd54ce7c58dc4067273efb540480 Mon Sep 17 00:00:00 2001 From: Iskren Chernev Date: Mon, 19 Sep 2022 21:06:13 +0300 Subject: [PATCH 118/261] dt-bindings: arm: qcom: Add compatible for oneplus,billie2 phone oneplus,billie2 (OnePlus Nord N100) is based on QualComm Snapdragon SM4250 SoC. Add support for the same in dt-bindings. Signed-off-by: Iskren Chernev Reviewed-by: Krzysztof Kozlowski Reviewed-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220919180618.1840194-4-iskren.chernev@gmail.com --- Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 6a4df5833024..f4e26bd66c41 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -54,6 +54,8 @@ description: | sdm845 sdx55 sdx65 + sm4250 + sm6115 sm6125 sm6350 sm7225 @@ -707,6 +709,11 @@ properties: - xiaomi,polaris - const: qcom,sdm845 + - items: + - enum: + - oneplus,billie2 + - const: qcom,sm4250 + - items: - enum: - sony,pdx201 From 97e563bf5ba187378e07145c08ae12508cba7361 Mon Sep 17 00:00:00 2001 From: Iskren Chernev Date: Mon, 19 Sep 2022 21:06:16 +0300 Subject: [PATCH 119/261] arm64: dts: qcom: sm6115: Add basic soc dtsi Add support for Qualcomm SM6115 SoC. This includes: - GCC - Pinctrl - RPM (CC+PD) - USB - MMC - UFS Signed-off-by: Iskren Chernev Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220919180618.1840194-7-iskren.chernev@gmail.com --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 854 +++++++++++++++++++++++++++ 1 file changed, 854 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm6115.dtsi diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi new file mode 100644 index 000000000000..0340ed21be05 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -0,0 +1,854 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2021, Iskren Chernev + */ + +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x1>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x2>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x3>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU4: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <1638>; + dynamic-power-coefficient = <282>; + next-level-cache = <&L2_1>; + L2_1: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + CPU5: cpu@101 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x101>; + capacity-dmips-mhz = <1638>; + dynamic-power-coefficient = <282>; + enable-method = "psci"; + next-level-cache = <&L2_1>; + }; + + CPU6: cpu@102 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x102>; + capacity-dmips-mhz = <1638>; + dynamic-power-coefficient = <282>; + enable-method = "psci"; + next-level-cache = <&L2_1>; + }; + + CPU7: cpu@103 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x103>; + capacity-dmips-mhz = <1638>; + dynamic-power-coefficient = <282>; + enable-method = "psci"; + next-level-cache = <&L2_1>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + + core3 { + cpu = <&CPU7>; + }; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-sm6115", "qcom,scm"; + #reset-cells = <1>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0 0x80000000 0 0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: memory@45700000 { + reg = <0x0 0x45700000 0x0 0x600000>; + no-map; + }; + + xbl_aop_mem: memory@45e00000 { + reg = <0x0 0x45e00000 0x0 0x140000>; + no-map; + }; + + sec_apps_mem: memory@45fff000 { + reg = <0x0 0x45fff000 0x0 0x1000>; + no-map; + }; + + smem_mem: memory@46000000 { + compatible = "qcom,smem"; + reg = <0x0 0x46000000 0x0 0x200000>; + no-map; + + hwlocks = <&tcsr_mutex 3>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + }; + + cdsp_sec_mem: memory@46200000 { + reg = <0x0 0x46200000 0x0 0x1e00000>; + no-map; + }; + + pil_modem_mem: memory@4ab00000 { + reg = <0x0 0x4ab00000 0x0 0x6900000>; + no-map; + }; + + pil_video_mem: memory@51400000 { + reg = <0x0 0x51400000 0x0 0x500000>; + no-map; + }; + + wlan_msa_mem: memory@51900000 { + reg = <0x0 0x51900000 0x0 0x100000>; + no-map; + }; + + pil_cdsp_mem: memory@51a00000 { + reg = <0x0 0x51a00000 0x0 0x1e00000>; + no-map; + }; + + pil_adsp_mem: memory@53800000 { + reg = <0x0 0x53800000 0x0 0x2800000>; + no-map; + }; + + pil_ipa_fw_mem: memory@56100000 { + reg = <0x0 0x56100000 0x0 0x10000>; + no-map; + }; + + pil_ipa_gsi_mem: memory@56110000 { + reg = <0x0 0x56110000 0x0 0x5000>; + no-map; + }; + + pil_gpu_mem: memory@56115000 { + reg = <0x0 0x56115000 0x0 0x2000>; + no-map; + }; + + cont_splash_memory: memory@5c000000 { + reg = <0x0 0x5c000000 0x0 0x00f00000>; + no-map; + }; + + dfps_data_memory: memory@5cf00000 { + reg = <0x0 0x5cf00000 0x0 0x0100000>; + no-map; + }; + + removed_mem: memory@60000000 { + reg = <0x0 0x60000000 0x0 0x3900000>; + no-map; + }; + }; + + rpm-glink { + compatible = "qcom,glink-rpm"; + + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-sm6115"; + qcom,glink-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc"; + #clock-cells = <1>; + }; + + rpmpd: power-controller { + compatible = "qcom,sm6115-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_min_svs: opp1 { + opp-level = ; + }; + + rpmpd_opp_low_svs: opp2 { + opp-level = ; + }; + + rpmpd_opp_svs: opp3 { + opp-level = ; + }; + + rpmpd_opp_svs_plus: opp4 { + opp-level = ; + }; + + rpmpd_opp_nom: opp5 { + opp-level = ; + }; + + rpmpd_opp_nom_plus: opp6 { + opp-level = ; + }; + + rpmpd_opp_turbo: opp7 { + opp-level = ; + }; + + rpmpd_opp_turbo_plus: opp8 { + opp-level = ; + }; + }; + }; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + + tcsr_mutex: hwlock@340000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x00340000 0x20000>; + #hwlock-cells = <1>; + }; + + tlmm: pinctrl@500000 { + compatible = "qcom,sm6115-tlmm"; + reg = <0x00500000 0x400000>, <0x00900000 0x400000>, <0x00d00000 0x400000>; + reg-names = "west", "south", "east"; + interrupts = ; + gpio-controller; + gpio-ranges = <&tlmm 0 0 121>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + sdc1_state_on: sdc1-on-state { + clk-pins { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd-pins { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data-pins { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_state_off: sdc1-off-state { + clk-pins { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd-pins { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data-pins { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_state_on: sdc2-on-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd-pins { + pins = "gpio88"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_state_off: sdc2-off-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + + sd-cd-pins { + pins = "gpio88"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + }; + }; + + gcc: clock-controller@1400000 { + compatible = "qcom,gcc-sm6115"; + reg = <0x01400000 0x1f0000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; + clock-names = "bi_tcxo", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + usb_1_hsphy: phy@1613000 { + compatible = "qcom,sm6115-qusb2-phy"; + reg = <0x01613000 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_AHB2PHY_USB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "cfg_ahb", "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + nvmem-cells = <&qusb2_hstx_trim>; + + status = "disabled"; + }; + + qfprom@1b40000 { + compatible = "qcom,sm6115-qfprom", "qcom,qfprom"; + reg = <0x01b40000 0x7000>; + #address-cells = <1>; + #size-cells = <1>; + + qusb2_hstx_trim: hstx-trim@25b { + reg = <0x25b 0x1>; + bits = <1 4>; + }; + }; + + spmi_bus: spmi@1c40000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x01c40000 0x1100>, + <0x01e00000 0x2000000>, + <0x03e00000 0x100000>, + <0x03f00000 0xa0000>, + <0x01c0a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + rpm_msg_ram: sram@45f0000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x045f0000 0x7000>; + }; + + sdhc_1: mmc@4744000 { + compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x04744000 0x1000>, <0x04745000 0x1000>, <0x04748000 0x8000>; + reg-names = "hc", "cqhci", "ice"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "iface", "core", "xo", "ice"; + + pinctrl-0 = <&sdc1_state_on>; + pinctrl-1 = <&sdc1_state_off>; + pinctrl-names = "default", "sleep"; + + bus-width = <8>; + status = "disabled"; + }; + + sdhc_2: mmc@4784000 { + compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x04784000 0x1000>; + reg-names = "hc"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; + clock-names = "iface", "core", "xo"; + + pinctrl-0 = <&sdc2_state_on>; + pinctrl-1 = <&sdc2_state_off>; + pinctrl-names = "default", "sleep"; + + power-domains = <&rpmpd SM6115_VDDCX>; + operating-points-v2 = <&sdhc2_opp_table>; + iommus = <&apps_smmu 0x00a0 0x0>; + resets = <&gcc GCC_SDCC2_BCR>; + + bus-width = <4>; + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; + status = "disabled"; + + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + }; + + ufs_mem_hc: ufs@4804000 { + compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; + reg = <0x04804000 0x3000>, <0x04810000 0x8000>; + interrupts = ; + phys = <&ufs_mem_phy_lanes>; + phy-names = "ufsphy"; + lanes-per-direction = <1>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + power-domains = <&gcc GCC_UFS_PHY_GDSC>; + iommus = <&apps_smmu 0x100 0>; + + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "ice_core_clk"; + + freq-table-hz = <50000000 200000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>; + + status = "disabled"; + }; + + ufs_mem_phy: phy@4807000 { + compatible = "qcom,sm6115-qmp-ufs-phy"; + reg = <0x04807000 0x1c4>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_UFS_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + clock-names = "ref", "ref_aux"; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + status = "disabled"; + + ufs_mem_phy_lanes: phy@4807400 { + reg = <0x4807400 0x098>, + <0x4807600 0x130>, + <0x4807c00 0x16c>; + #phy-cells = <0>; + }; + }; + + usb_1: usb@4ef8800 { + compatible = "qcom,sm6115-dwc3", "qcom,dwc3"; + reg = <0x04ef8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>; + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "xo"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <66666667>; + + interrupts = , + ; + interrupt-names = "hs_phy_irq", "ss_phy_irq"; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; + qcom,select-utmi-as-pipe-clk; + status = "disabled"; + + usb_1_dwc3: usb@4e00000 { + compatible = "snps,dwc3"; + reg = <0x04e00000 0xcd00>; + interrupts = ; + phys = <&usb_1_hsphy>; + phy-names = "usb2-phy"; + iommus = <&apps_smmu 0x120 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + maximum-speed = "high-speed"; + dr_mode = "peripheral"; + }; + }; + + apps_smmu: iommu@c600000 { + compatible = "qcom,sm6115-smmu-500", "arm,mmu-500"; + reg = <0x0c600000 0x80000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + apcs_glb: mailbox@f111000 { + compatible = "qcom,sm6115-apcs-hmss-global"; + reg = <0x0f111000 0x1000>; + + #mbox-cells = <1>; + }; + + timer@f120000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0f120000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clock-frequency = <19200000>; + + frame@f121000 { + reg = <0x0f121000 0x1000>, <0x0f122000 0x1000>; + frame-number = <0>; + interrupts = , + ; + }; + + frame@f123000 { + reg = <0x0f123000 0x1000>; + frame-number = <1>; + interrupts = ; + status = "disabled"; + }; + + frame@f124000 { + reg = <0x0f124000 0x1000>; + frame-number = <2>; + interrupts = ; + status = "disabled"; + }; + + frame@f125000 { + reg = <0x0f125000 0x1000>; + frame-number = <3>; + interrupts = ; + status = "disabled"; + }; + + frame@f126000 { + reg = <0x0f126000 0x1000>; + frame-number = <4>; + interrupts = ; + status = "disabled"; + }; + + frame@f127000 { + reg = <0x0f127000 0x1000>; + frame-number = <5>; + interrupts = ; + status = "disabled"; + }; + + frame@f128000 { + reg = <0x0f128000 0x1000>; + frame-number = <6>; + interrupts = ; + status = "disabled"; + }; + }; + + intc: interrupt-controller@f200000 { + compatible = "arm,gic-v3"; + reg = <0x0f200000 0x10000>, <0x0f300000 0x100000>; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&intc>; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + interrupts = ; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; From 70f18c6313622380f7b9452f31a93aec3e525f64 Mon Sep 17 00:00:00 2001 From: Iskren Chernev Date: Mon, 19 Sep 2022 21:06:17 +0300 Subject: [PATCH 120/261] arm64: dts: qcom: sm4250: Add soc dtsi The SM4250 is a downclocked version of the SM6115. Signed-off-by: Iskren Chernev Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220919180618.1840194-8-iskren.chernev@gmail.com --- arch/arm64/boot/dts/qcom/sm4250.dtsi | 38 ++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm4250.dtsi diff --git a/arch/arm64/boot/dts/qcom/sm4250.dtsi b/arch/arm64/boot/dts/qcom/sm4250.dtsi new file mode 100644 index 000000000000..c5add8f44fc0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm4250.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2021, Iskren Chernev + */ + +#include "sm6115.dtsi" + +&CPU0 { + compatible = "qcom,kryo240"; +}; + +&CPU1 { + compatible = "qcom,kryo240"; +}; + +&CPU2 { + compatible = "qcom,kryo240"; +}; + +&CPU3 { + compatible = "qcom,kryo240"; +}; + +&CPU4 { + compatible = "qcom,kryo240"; +}; + +&CPU5 { + compatible = "qcom,kryo240"; +}; + +&CPU6 { + compatible = "qcom,kryo240"; +}; + +&CPU7 { + compatible = "qcom,kryo240"; +}; From f110f2af3a9b848c3b287137d9535074742bb8c3 Mon Sep 17 00:00:00 2001 From: Iskren Chernev Date: Mon, 19 Sep 2022 21:06:18 +0300 Subject: [PATCH 121/261] arm64: dts: qcom: sm4250: Add support for oneplus-billie2 Add initial support for OnePlus Nord N100, based on SM4250. Currently working: - boots - usb - built-in flash storage (UFS) - SD card reader Signed-off-by: Iskren Chernev Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220919180618.1840194-9-iskren.chernev@gmail.com --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sm4250-oneplus-billie2.dts | 241 ++++++++++++++++++ 2 files changed, 242 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index b0558d3389e5..eb2a58b8af5f 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -142,6 +142,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-polaris.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-shift-axolotl.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm4250-oneplus-billie2.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6350-sony-xperia-lena-pdx213.dtb dtb-$(CONFIG_ARCH_QCOM) += sm7225-fairphone-fp4.dtb diff --git a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts new file mode 100644 index 000000000000..a3f1c7c41fd7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2021, Iskren Chernev + */ + +/dts-v1/; + +#include "sm4250.dtsi" + +/ { + model = "OnePlus Nord N100"; + compatible = "oneplus,billie2", "qcom,sm4250"; + + /* required for bootloader to select correct board */ + qcom,msm-id = <0x1a1 0x10000 0x1bc 0x10000>; + qcom,board-id = <0x1000b 0x00>; + + aliases { + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "framebuffer0"; + + framebuffer0: framebuffer@9d400000 { + compatible = "simple-framebuffer"; + reg = <0 0x5c000000 0 (1600 * 720 * 4)>; + width = <720>; + height = <1600>; + stride = <(720 * 4)>; + format = "a8r8g8b8"; + }; + }; +}; + +&reserved_memory { + bootloader_log_mem: memory@5fff7000 { + reg = <0x0 0x5fff7000 0x0 0x8000>; + no-map; + }; + + ramoops@cbe00000 { + compatible = "ramoops"; + reg = <0x0 0xcbe00000 0x0 0x400000>; + record-size = <0x40000>; + pmsg-size = <0x200000>; + console-size = <0x40000>; + ftrace-size = <0x40000>; + }; + + param_mem: memory@cc200000 { + reg = <0x0 0xcc200000 0x0 0x100000>; + no-map; + }; + + mtp_mem: memory@cc300000 { + reg = <0x00 0xcc300000 0x00 0xb00000>; + no-map; + }; +}; + +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pm6125-regulators"; + + vreg_s6a: s6 { + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <1456000>; + }; + + vreg_s7a: s7 { + regulator-min-microvolt = <1280000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s8a: s8 { + regulator-min-microvolt = <1064000>; + regulator-max-microvolt = <1304000>; + }; + + vreg_l1a: l1 { + regulator-min-microvolt = <952000>; + regulator-max-microvolt = <1152000>; + }; + + vreg_l4a: l4 { + regulator-min-microvolt = <488000>; + regulator-max-microvolt = <1000000>; + }; + + vreg_l5a: l5 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <3056000>; + }; + + vreg_l6a: l6 { + regulator-min-microvolt = <576000>; + regulator-max-microvolt = <656000>; + }; + + vreg_l7a: l7 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1304000>; + }; + + vreg_l8a: l8 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <728000>; + }; + + vreg_l9a: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + }; + + vreg_l10a: l10 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + }; + + vreg_l11a: l11 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1952000>; + }; + + vreg_l12a: l12 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <1984000>; + }; + + vreg_l13a: l13 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <1952000>; + }; + + vreg_l14a: l14 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + }; + + vreg_l15a: l15 { + regulator-min-microvolt = <2920000>; + regulator-max-microvolt = <3232000>; + }; + + vreg_l16a: l16 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + }; + + vreg_l17a: l17 { + regulator-min-microvolt = <1152000>; + regulator-max-microvolt = <1304000>; + }; + + vreg_l18a: l18 { + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1304000>; + }; + + vreg_l19a: l19 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <3304000>; + }; + + vreg_l20a: l20 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <3304000>; + }; + + vreg_l21a: l21 { + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3544000>; + }; + + vreg_l22a: l22 { + regulator-min-microvolt = <2952000>; + regulator-max-microvolt = <3304000>; + }; + + vreg_l23a: l23 { + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3304000>; + }; + + vreg_l24a: l24 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3544000>; + }; + }; +}; + +&sleep_clk { + clock-frequency = <32764>; +}; + +&sdhc_2 { + vmmc-supply = <&vreg_l22a>; + vqmmc-supply = <&vreg_l5a>; + + cd-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <14 4>; +}; + +&ufs_mem_hc { + vcc-supply = <&vreg_l24a>; + vcc-max-microamp = <600000>; + vccq2-supply = <&vreg_l11a>; + vccq2-max-microamp = <600000>; + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l4a>; + vdda-pll-supply = <&vreg_l12a>; + vddp-ref-clk-supply = <&vreg_l18a>; + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l4a>; + vdda-pll-supply = <&vreg_l12a>; + vdda-phy-dpdm-supply = <&vreg_l15a>; + status = "okay"; +}; + +&xo_board { + clock-frequency = <19200000>; +}; From f1e6243b37db8e589009cb333140fa23ee4d984c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 18 Sep 2022 10:54:30 +0100 Subject: [PATCH 122/261] dt-bindings: arm: qcom: document Google Cheza Document Google Cheza board compatibles recently added. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220918095430.18068-1-krzysztof.kozlowski@linaro.org --- Documentation/devicetree/bindings/arm/qcom.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index f4e26bd66c41..c26a7cc4a8ba 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -692,6 +692,9 @@ properties: - items: - enum: + - google,cheza + - google,cheza-rev1 + - google,cheza-rev2 - lenovo,yoga-c630 - lg,judyln - lg,judyp From dd12b33d3c0aa1ff81063dced32997887b924cd1 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 24 Sep 2022 12:43:47 +0300 Subject: [PATCH 123/261] arm64: dts: qcom: msm8996: change HDMI PHY node name to generic one Change HDMI PHY node name from custom 'hdmi-phy' to the generic 'phy'. Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220924094347.178666-3-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 7547ad35b58e..7f24c6a33ace 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1163,7 +1163,7 @@ hdmi_in: endpoint { }; }; - hdmi_phy: hdmi-phy@9a0600 { + hdmi_phy: phy@9a0600 { #phy-cells = <0>; compatible = "qcom,hdmi-phy-8996"; reg = <0x009a0600 0x1c4>, From 3da503c26ec572628802b4ffbe738a5d373cd3f6 Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Mon, 26 Sep 2022 21:01:44 +0200 Subject: [PATCH 124/261] dt-bindings: mfd: qcom-spmi-pmic: Add pm6125 compatible Document support for the pm6125, typically paired with the sm6125 SoC. Signed-off-by: Marijn Suijten Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220926190148.283805-2-marijn.suijten@somainline.org --- Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml index 6a3e3ede1ede..a5edab6f2e40 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml @@ -33,6 +33,7 @@ properties: compatible: items: - enum: + - qcom,pm6125 - qcom,pm6150 - qcom,pm6150l - qcom,pm6350 From 02549ba5de0a09a27616496c3512db5af4ad7862 Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Mon, 26 Sep 2022 21:01:45 +0200 Subject: [PATCH 125/261] arm64: dts: qcom: pm660: Use unique ADC5_VCOIN address in node name The register address in the node name is shadowing vph_pwr@83, whereas the ADC5_VCOIN register resolves to 0x85. Fix this copy-paste discrepancy. Fixes: 4bf097540506 ("arm64: dts: qcom: pm660: Add VADC and temp alarm nodes") Signed-off-by: Marijn Suijten Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220926190148.283805-3-marijn.suijten@somainline.org --- arch/arm64/boot/dts/qcom/pm660.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pm660.dtsi b/arch/arm64/boot/dts/qcom/pm660.dtsi index ab934ff51f6d..fc0eccaccdf6 100644 --- a/arch/arm64/boot/dts/qcom/pm660.dtsi +++ b/arch/arm64/boot/dts/qcom/pm660.dtsi @@ -163,7 +163,7 @@ vadc_vph_pwr: vph_pwr@83 { qcom,pre-scaling = <1 3>; }; - vcoin: vcoin@83 { + vcoin: vcoin@85 { reg = ; qcom,decimation = <1024>; qcom,pre-scaling = <1 3>; From 7c969c6e216654cab8b124383dd99a276049994d Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Mon, 26 Sep 2022 21:01:46 +0200 Subject: [PATCH 126/261] arm64: dts: qcom: Add PM6125 PMIC This PMIC is commonly used on boards with an SM6125 SoC and looks very similar in layout to the PM6150. Downstream declares more nodes to be available, but these have been omitted from this patch: the pwm/lpg block is unused on my reference device making it impossible to test/validate, and the spmi-clkdiv does not have a single device-tree binding using this driver yet, hence inclusion is better postponed until ie. audio which uses these clocks is brought up. Signed-off-by: Marijn Suijten Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220926190148.283805-4-marijn.suijten@somainline.org --- arch/arm64/boot/dts/qcom/pm6125.dtsi | 154 +++++++++++++++++++++++++++ 1 file changed, 154 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pm6125.dtsi diff --git a/arch/arm64/boot/dts/qcom/pm6125.dtsi b/arch/arm64/boot/dts/qcom/pm6125.dtsi new file mode 100644 index 000000000000..1c8ccda26ffb --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm6125.dtsi @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: BSD-3-Clause + +#include +#include +#include +#include +#include + +/ { + thermal-zones { + pm6125-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pm6125_temp>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus { + pmic@0 { + compatible = "qcom,pm6125", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm6125_pon: pon@800 { + compatible = "qcom,pm8998-pon"; + reg = <0x800>; + mode-bootloader = <0x2>; + mode-recovery = <0x1>; + + pon_pwrkey: pwrkey { + compatible = "qcom,pm8941-pwrkey"; + interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + linux,code = ; + bias-pull-up; + status = "disabled"; + }; + + pon_resin: resin { + compatible = "qcom,pm8941-resin"; + interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + status = "disabled"; + }; + }; + + pm6125_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; + io-channels = <&pm6125_adc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pm6125_adc: adc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + #io-channel-cells = <1>; + + ref-gnd@0 { + reg = ; + qcom,pre-scaling = <1 1>; + }; + + vref-1p25@1 { + reg = ; + qcom,pre-scaling = <1 1>; + }; + + die-temp@6 { + reg = ; + qcom,pre-scaling = <1 1>; + }; + + vph-pwr@83 { + reg = ; + qcom,pre-scaling = <1 3>; + }; + + vcoin@85 { + reg = ; + qcom,pre-scaling = <1 3>; + }; + + xo-therm@4c { + reg = ; + qcom,pre-scaling = <1 1>; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + }; + }; + + pm6125_adc_tm: adc-tm@3500 { + compatible = "qcom,spmi-adc-tm5"; + reg = <0x3500>; + interrupts = <0x0 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #thermal-sensor-cells = <1>; + status = "disabled"; + }; + + pm6125_rtc: rtc@6000 { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>, <0x6100>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + }; + + pm6125_gpio: gpio@c000 { + compatible = "qcom,pm6125-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + gpio-ranges = <&pm6125_gpio 0 0 9>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmic@1 { + compatible = "qcom,pm6125", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + }; +}; From 7401035f2ef8841d0db9724507b45841d16894b6 Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Mon, 26 Sep 2022 21:01:47 +0200 Subject: [PATCH 127/261] arm64: dts: qcom: sm6125-seine: Include PM6125 and configure PON The Sony Xperia Seine board uses the PM6125; include it and configure the PON buttons that provide the power and volume-up key. Signed-off-by: Marijn Suijten Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220926190148.283805-5-marijn.suijten@somainline.org --- .../boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts index 9af4b76fa6d7..290842afc323 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts +++ b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts @@ -6,8 +6,8 @@ /dts-v1/; #include "sm6125.dtsi" +#include "pm6125.dtsi" #include -#include #include / { @@ -86,6 +86,15 @@ &hsusb_phy1 { status = "okay"; }; +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + status = "okay"; + linux,code = ; +}; + &sdc2_off_state { sd-cd-pins { pins = "gpio98"; From 4ba146dd8897353e4e18a12c7866127f85c251e7 Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Mon, 26 Sep 2022 21:01:48 +0200 Subject: [PATCH 128/261] arm64: dts: qcom: sm6125-seine: Configure additional trinket thermistors In addition to PMIC-specific (pm6125) thermistors downstream extends this set with the rf-pa0/rf-pa1, quiet, camera-flash and UFS/eMMC thermistors in sm6125 (trinket) board and seine-specific DT files. All thermistors report sensible temperature readings in userspace. The sensors are also added to their respective Thermal Monitor node, with thermal zones to match where applicable: emmc-ufs and camera-flash are not available on the TM5 block, hence cannot be configured with a tripping point and will not have a thermal zone. Signed-off-by: Marijn Suijten Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220926190148.283805-6-marijn.suijten@somainline.org --- .../qcom/sm6125-sony-xperia-seine-pdx201.dts | 151 ++++++++++++++++++ 1 file changed, 151 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts index 290842afc323..0de6c5b7f742 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts +++ b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts @@ -9,6 +9,7 @@ #include "pm6125.dtsi" #include #include +#include / { /* required for bootloader to select correct board */ @@ -80,12 +81,162 @@ cmdline_mem: memory@ffd00000 { no-map; }; }; + + thermal-zones { + rf-pa0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm6125_adc_tm 0>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + quiet-thermal { + polling-delay-passive = <0>; + polling-delay = <5000>; + thermal-sensors = <&pm6125_adc_tm 1>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + xo-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm6125_adc_tm 2>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + rf-pa1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm6125_adc_tm 3>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; }; &hsusb_phy1 { status = "okay"; }; +&pm6125_adc { + pinctrl-names = "default"; + pinctrl-0 = <&camera_flash_therm &emmc_ufs_therm &rf_pa1_therm>; + + rf-pa0-therm@4d { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + quiet-therm@4e { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + camera-flash-therm@52 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + emmc-ufs-therm@54 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + rf-pa1-therm@55 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm6125_adc_tm { + status = "okay"; + + rf-pa0-therm@0 { + reg = <0>; + io-channels = <&pm6125_adc ADC5_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + quiet-therm@1 { + reg = <1>; + io-channels = <&pm6125_adc ADC5_AMUX_THM2_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + xo-therm@2 { + reg = <2>; + io-channels = <&pm6125_adc ADC5_XO_THERM_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + rf-pa1-therm@3 { + reg = <3>; + io-channels = <&pm6125_adc ADC5_GPIO4_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pm6125_gpio { + camera_flash_therm: camera-flash-therm-state { + pins = "gpio3"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-high-impedance; + }; + + emmc_ufs_therm: emmc-ufs-therm-state { + pins = "gpio6"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-high-impedance; + }; + + rf_pa1_therm: rf-pa1-therm-state { + pins = "gpio7"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-high-impedance; + }; +}; + &pon_pwrkey { status = "okay"; }; From 67cb6e988f8937105560c782bf04520c3d0db841 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 27 Sep 2022 17:34:18 +0200 Subject: [PATCH 129/261] arm64: dts: qcom: sc7280: drop clock-cells from LPASS TLMM The LPASS pin-controller is not a clock provider: qcom/sc7280-herobrine-herobrine-r1.dtb: pinctrl@33c0000: '#clock-cells' does not match any of the regexes: '-state$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220927153429.55365-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index cb981174612a..5916d16c80bc 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2465,8 +2465,6 @@ lpass_tlmm: pinctrl@33c0000 { #gpio-cells = <2>; gpio-ranges = <&lpass_tlmm 0 0 15>; - #clock-cells = <1>; - lpass_dmic01_clk: dmic01-clk { pins = "gpio6"; function = "dmic1_clk"; From 886a50bd031aae7b6880030a4076a146d0429492 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 27 Sep 2022 17:34:19 +0200 Subject: [PATCH 130/261] arm64: dts: qcom: sc7280: align LPASS pin configuration with DT schema DT schema expects LPASS pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220927153429.55365-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 32 ++++++++++++++-------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 5916d16c80bc..e3fa4fb1d711 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2465,82 +2465,82 @@ lpass_tlmm: pinctrl@33c0000 { #gpio-cells = <2>; gpio-ranges = <&lpass_tlmm 0 0 15>; - lpass_dmic01_clk: dmic01-clk { + lpass_dmic01_clk: dmic01-clk-state { pins = "gpio6"; function = "dmic1_clk"; }; - lpass_dmic01_clk_sleep: dmic01-clk-sleep { + lpass_dmic01_clk_sleep: dmic01-clk-sleep-state { pins = "gpio6"; function = "dmic1_clk"; }; - lpass_dmic01_data: dmic01-data { + lpass_dmic01_data: dmic01-data-state { pins = "gpio7"; function = "dmic1_data"; }; - lpass_dmic01_data_sleep: dmic01-data-sleep { + lpass_dmic01_data_sleep: dmic01-data-sleep-state { pins = "gpio7"; function = "dmic1_data"; }; - lpass_dmic23_clk: dmic23-clk { + lpass_dmic23_clk: dmic23-clk-state { pins = "gpio8"; function = "dmic2_clk"; }; - lpass_dmic23_clk_sleep: dmic23-clk-sleep { + lpass_dmic23_clk_sleep: dmic23-clk-sleep-state { pins = "gpio8"; function = "dmic2_clk"; }; - lpass_dmic23_data: dmic23-data { + lpass_dmic23_data: dmic23-data-state { pins = "gpio9"; function = "dmic2_data"; }; - lpass_dmic23_data_sleep: dmic23-data-sleep { + lpass_dmic23_data_sleep: dmic23-data-sleep-state { pins = "gpio9"; function = "dmic2_data"; }; - lpass_rx_swr_clk: rx-swr-clk { + lpass_rx_swr_clk: rx-swr-clk-state { pins = "gpio3"; function = "swr_rx_clk"; }; - lpass_rx_swr_clk_sleep: rx-swr-clk-sleep { + lpass_rx_swr_clk_sleep: rx-swr-clk-sleep-state { pins = "gpio3"; function = "swr_rx_clk"; }; - lpass_rx_swr_data: rx-swr-data { + lpass_rx_swr_data: rx-swr-data-state { pins = "gpio4", "gpio5"; function = "swr_rx_data"; }; - lpass_rx_swr_data_sleep: rx-swr-data-sleep { + lpass_rx_swr_data_sleep: rx-swr-data-sleep-state { pins = "gpio4", "gpio5"; function = "swr_rx_data"; }; - lpass_tx_swr_clk: tx-swr-clk { + lpass_tx_swr_clk: tx-swr-clk-state { pins = "gpio0"; function = "swr_tx_clk"; }; - lpass_tx_swr_clk_sleep: tx-swr-clk-sleep { + lpass_tx_swr_clk_sleep: tx-swr-clk-sleep-state { pins = "gpio0"; function = "swr_tx_clk"; }; - lpass_tx_swr_data: tx-swr-data { + lpass_tx_swr_data: tx-swr-data-state { pins = "gpio1", "gpio2", "gpio14"; function = "swr_tx_data"; }; - lpass_tx_swr_data_sleep: tx-swr-data-sleep { + lpass_tx_swr_data_sleep: tx-swr-data-sleep-state { pins = "gpio1", "gpio2", "gpio14"; function = "swr_tx_data"; }; From 195a0a11d66d6c696cbcf398d6bc3f3a3a462f7c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 27 Sep 2022 17:34:20 +0200 Subject: [PATCH 131/261] arm64: dts: qcom: sm8250: correct LPASS pin pull down The pull-down property is actually bias-pull-down. Fixes: 3160c1b894d9 ("arm64: dts: qcom: sm8250: add lpass lpi pin controller node") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220927153429.55365-4-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index eb5a10cbcd71..676b08fd0d99 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2454,7 +2454,7 @@ data { pins = "gpio7"; function = "dmic1_data"; drive-strength = <2>; - pull-down; + bias-pull-down; input-enable; }; }; From 031f5436c9b7209446eb90fe512d1e379ace0e1b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 27 Sep 2022 17:34:21 +0200 Subject: [PATCH 132/261] arm64: dts: qcom: sm8250: align LPASS pin configuration with DT schema DT schema expects LPASS pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220927153429.55365-5-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 44 ++++++++++++++-------------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 676b08fd0d99..369252fe8a7b 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2388,8 +2388,8 @@ lpass_tlmm: pinctrl@33c0000{ <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; clock-names = "core", "audio"; - wsa_swr_active: wsa-swr-active-pins { - clk { + wsa_swr_active: wsa-swr-active-state { + clk-pins { pins = "gpio10"; function = "wsa_swr_clk"; drive-strength = <2>; @@ -2397,7 +2397,7 @@ clk { bias-disable; }; - data { + data-pins { pins = "gpio11"; function = "wsa_swr_data"; drive-strength = <2>; @@ -2407,8 +2407,8 @@ data { }; }; - wsa_swr_sleep: wsa-swr-sleep-pins { - clk { + wsa_swr_sleep: wsa-swr-sleep-state { + clk-pins { pins = "gpio10"; function = "wsa_swr_clk"; drive-strength = <2>; @@ -2416,7 +2416,7 @@ clk { bias-pull-down; }; - data { + data-pins { pins = "gpio11"; function = "wsa_swr_data"; drive-strength = <2>; @@ -2426,14 +2426,14 @@ data { }; }; - dmic01_active: dmic01-active-pins { - clk { + dmic01_active: dmic01-active-state { + clk-pins { pins = "gpio6"; function = "dmic1_clk"; drive-strength = <8>; output-high; }; - data { + data-pins { pins = "gpio7"; function = "dmic1_data"; drive-strength = <8>; @@ -2441,8 +2441,8 @@ data { }; }; - dmic01_sleep: dmic01-sleep-pins { - clk { + dmic01_sleep: dmic01-sleep-state { + clk-pins { pins = "gpio6"; function = "dmic1_clk"; drive-strength = <2>; @@ -2450,7 +2450,7 @@ clk { output-low; }; - data { + data-pins { pins = "gpio7"; function = "dmic1_data"; drive-strength = <2>; @@ -2459,8 +2459,8 @@ data { }; }; - rx_swr_active: rx_swr-active-pins { - clk { + rx_swr_active: rx-swr-active-state { + clk-pins { pins = "gpio3"; function = "swr_rx_clk"; drive-strength = <2>; @@ -2468,7 +2468,7 @@ clk { bias-disable; }; - data { + data-pins { pins = "gpio4", "gpio5"; function = "swr_rx_data"; drive-strength = <2>; @@ -2477,8 +2477,8 @@ data { }; }; - tx_swr_active: tx_swr-active-pins { - clk { + tx_swr_active: tx-swr-active-state { + clk-pins { pins = "gpio0"; function = "swr_tx_clk"; drive-strength = <2>; @@ -2486,7 +2486,7 @@ clk { bias-disable; }; - data { + data-pins { pins = "gpio1", "gpio2"; function = "swr_tx_data"; drive-strength = <2>; @@ -2495,8 +2495,8 @@ data { }; }; - tx_swr_sleep: tx_swr-sleep-pins { - clk { + tx_swr_sleep: tx-swr-sleep-state { + clk-pins { pins = "gpio0"; function = "swr_tx_clk"; drive-strength = <2>; @@ -2504,7 +2504,7 @@ clk { bias-pull-down; }; - data1 { + data1-pins { pins = "gpio1"; function = "swr_tx_data"; drive-strength = <2>; @@ -2512,7 +2512,7 @@ data1 { bias-bus-hold; }; - data2 { + data2-pins { pins = "gpio2"; function = "swr_tx_data"; drive-strength = <2>; From 20e88ca2960ee63450cc4b9383e387f18cc08fa8 Mon Sep 17 00:00:00 2001 From: Dzmitry Sankouski Date: Wed, 12 Oct 2022 21:54:10 +0300 Subject: [PATCH 133/261] dt-bindings: arm: add samsung,starqltechn board based on sdm845 chip Add samsung,starqltechn board (Samsung Galaxy S9) binding. Signed-off-by: Dzmitry Sankouski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221012185411.1282838-2-dsankouski@gmail.com --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index c26a7cc4a8ba..5148c4916bc1 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -702,6 +702,7 @@ properties: - oneplus,fajita - qcom,sdm845-mtp - shift,axolotl + - samsung,starqltechn - samsung,w737 - sony,akari-row - sony,akatsuki-row From d711b22eee55ced0e32645706f20329be249e207 Mon Sep 17 00:00:00 2001 From: Dzmitry Sankouski Date: Wed, 12 Oct 2022 21:54:11 +0300 Subject: [PATCH 134/261] arm64: dts: qcom: starqltechn: add initial device tree for starqltechn New device support - Samsung S9 (SM-G9600) phone What works: - simple framebuffer - storage (both main and sdcard) - ramoops Signed-off-by: Dzmitry Sankouski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221012185411.1282838-3-dsankouski@gmail.com --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../dts/qcom/sdm845-samsung-starqltechn.dts | 460 ++++++++++++++++++ 2 files changed, 461 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index eb2a58b8af5f..500e06c3d6d3 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -133,6 +133,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyp.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-oneplus-enchilada.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-oneplus-fajita.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm845-samsung-starqltechn.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-akari.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-akatsuki.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-apollo.dtb diff --git a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts new file mode 100644 index 000000000000..e742c27fe91f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts @@ -0,0 +1,460 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SDM845 Samsung S9 (SM-G9600) (starqltechn / star2qltechn) common device tree source + * + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +/dts-v1/; + +#include +#include +#include "sdm845.dtsi" + +/ { + chassis-type = "handset"; + model = "Samsung Galaxy S9 SM-G9600"; + compatible = "samsung,starqltechn", "qcom,sdm845"; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + framebuffer: framebuffer@9d400000 { + compatible = "simple-framebuffer"; + reg = <0 0x9d400000 0 (2960 * 1440 * 4)>;//2400000 + width = <1440>; + height = <2960>; + stride = <(1440 * 4)>; + format = "a8r8g8b8"; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + /* + * Apparently RPMh does not provide support for PM8998 S4 because it + * is always-on; model it as a fixed regulator. + */ + vreg_s4a_1p8: pm8998-smps4 { + compatible = "regulator-fixed"; + regulator-name = "vreg_s4a_1p8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&vph_pwr>; + }; + + reserved-memory { + memory@9d400000 { + reg = <0x0 0x9d400000 0x0 0x02400000>; + no-map; + }; + + memory@a1300000 { + compatible = "ramoops"; + reg = <0x0 0xa1300000 0x0 0x100000>; + record-size = <0x40000>; + console-size = <0x40000>; + ftrace-size = <0x40000>; + pmsg-size = <0x40000>; + }; + }; +}; + + +&apps_rsc { + pm8998-rpmh-regulators { + compatible = "qcom,pm8998-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-s11-supply = <&vph_pwr>; + vdd-s12-supply = <&vph_pwr>; + vdd-s13-supply = <&vph_pwr>; + vdd-l1-l27-supply = <&vreg_s7a_1p025>; + vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>; + vdd-l3-l11-supply = <&vreg_s7a_1p025>; + vdd-l4-l5-supply = <&vreg_s7a_1p025>; + vdd-l6-supply = <&vph_pwr>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; + vdd-l26-supply = <&vreg_s3a_1p35>; + vin-lvs-1-2-supply = <&vreg_s4a_1p8>; + + vreg_s2a_1p125: smps2 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + vreg_s3a_1p35: smps3 { + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + }; + + vreg_s5a_2p04: smps5 { + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s7a_1p025: smps7 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1028000>; + }; + + vdd_qusb_hs0: + vdda_hp_pcie_core: + vdda_mipi_csi0_0p9: + vdda_mipi_csi1_0p9: + vdda_mipi_csi2_0p9: + vdda_mipi_dsi0_pll: + vdda_mipi_dsi1_pll: + vdda_qlink_lv: + vdda_qlink_lv_ck: + vdda_qrefs_0p875: + vdda_pcie_core: + vdda_pll_cc_ebi01: + vdda_pll_cc_ebi23: + vdda_sp_sensor: + vdda_ufs1_core: + vdda_ufs2_core: + vdda_usb1_ss_core: + vdda_usb2_ss_core: + vreg_l1a_0p875: ldo1 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vddpx_10: + vreg_l2a_1p2: ldo2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l3a_1p0: ldo3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = ; + }; + + vdd_wcss_cx: + vdd_wcss_mx: + vdda_wcss_pll: + vreg_l5a_0p8: ldo5 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vddpx_13: + vreg_l6a_1p8: ldo6 { + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <1856000>; + regulator-initial-mode = ; + }; + + vreg_l7a_1p8: ldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l8a_1p2: ldo8 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1248000>; + regulator-initial-mode = ; + }; + + vreg_l9a_1p8: ldo9 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + vreg_l10a_1p8: ldo10 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + vreg_l11a_1p0: ldo11 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1048000>; + regulator-initial-mode = ; + }; + + vdd_qfprom: + vdd_qfprom_sp: + vdda_apc1_cs_1p8: + vdda_gfx_cs_1p8: + vdda_qrefs_1p8: + vdda_qusb_hs0_1p8: + vddpx_11: + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vddpx_2: + vreg_l13a_2p95: ldo13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l14a_1p88: ldo14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l15a_1p8: ldo15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l16a_2p7: ldo16 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + regulator-initial-mode = ; + }; + + vreg_l17a_1p3: ldo17 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l18a_2p7: ldo18 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l19a_3p0: ldo19 { + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = ; + }; + + vreg_l20a_2p95: ldo20 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l21a_2p95: ldo21 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l22a_2p85: ldo22 { + regulator-min-microvolt = <2864000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vreg_l23a_3p3: ldo23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vdda_qusb_hs0_3p1: + vreg_l24a_3p075: ldo24 { + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3088000>; + regulator-initial-mode = ; + }; + + vreg_l25a_3p3: ldo25 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vdda_hp_pcie_1p2: + vdda_hv_ebi0: + vdda_hv_ebi1: + vdda_hv_ebi2: + vdda_hv_ebi3: + vdda_mipi_csi_1p25: + vdda_mipi_dsi0_1p2: + vdda_mipi_dsi1_1p2: + vdda_pcie_1p2: + vdda_ufs1_1p2: + vdda_ufs2_1p2: + vdda_usb1_ss_1p2: + vdda_usb2_ss_1p2: + vreg_l26a_1p2: ldo26 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l28a_3p0: ldo28 { + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_lvs1a_1p8: lvs1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_lvs2a_1p8: lvs2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + pm8005-rpmh-regulators { + compatible = "qcom,pm8005-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s3c_0p6: smps3 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <600000>; + }; + }; +}; + +&gcc { + protected-clocks = , + , + , + , + ; +}; + +&i2c10 { + clock-frequency = <400000>; + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&uart9 { + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l20a_2p95>; + vcc-max-microamp = <600000>; + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vdda_ufs1_core>; + vdda-pll-supply = <&vdda_ufs1_1p2>; + status = "okay"; +}; + +&sdhc_2 { + pinctrl-names = "default"; + pinctrl-0 = <&sdc2_clk_state &sdc2_cmd_state &sdc2_data_state &sd_card_det_n_state>; + cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>; + vmmc-supply = <&vreg_l21a_2p95>; + vqmmc-supply = <&vddpx_2>; + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + /* Until we have Type C hooked up we'll force this as peripheral. */ + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + vdd-supply = <&vdda_usb1_ss_core>; + vdda-pll-supply = <&vdda_qusb_hs0_1p8>; + vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; + + qcom,imp-res-offset-value = <8>; + qcom,hstx-trim-value = ; + qcom,preemphasis-level = ; + qcom,preemphasis-width = ; + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vdda_usb1_ss_1p2>; + vdda-pll-supply = <&vdda_usb1_ss_core>; + status = "okay"; +}; + +&wifi { + vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; + vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <27 4>, <81 4>, <85 4>; + + sdc2_clk_state: sdc2-clk-state { + pins = "sdc2_clk"; + bias-disable; + + /* + * It seems that mmc_test reports errors if drive + * strength is not 16 on clk, cmd, and data pins. + */ + drive-strength = <16>; + }; + + sdc2_cmd_state: sdc2-cmd-state { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <16>; + }; + + sdc2_data_state: sdc2-data-state { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <16>; + }; + + sd_card_det_n_state: sd-card-det-n-state { + pins = "gpio126"; + function = "gpio"; + bias-pull-up; + }; +}; From 1cb78978d34e1b65bbb912d8265eb95713ae7a45 Mon Sep 17 00:00:00 2001 From: Caleb Connolly Date: Sun, 16 Oct 2022 19:03:25 +0100 Subject: [PATCH 135/261] arm64: dts: qcom: pmi8998: add rradc node Add a DT node for the Round Robin ADC found in the PMI8998 PMIC. Signed-off-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221016180330.1912214-2-caleb.connolly@linaro.org --- arch/arm64/boot/dts/qcom/pmi8998.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pmi8998.dtsi b/arch/arm64/boot/dts/qcom/pmi8998.dtsi index 485bebb685f0..cd1caeae8281 100644 --- a/arch/arm64/boot/dts/qcom/pmi8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8998.dtsi @@ -18,6 +18,14 @@ pmi8998_gpio: gpio@c000 { interrupt-controller; #interrupt-cells = <2>; }; + + pmi8998_rradc: adc@4500 { + compatible = "qcom,pmi8998-rradc"; + reg = <0x4500>; + #io-channel-cells = <1>; + + status = "disabled"; + }; }; pmi8998_lsid1: pmic@3 { From 868985181a69df53321035d96aa668d90f6cd5cb Mon Sep 17 00:00:00 2001 From: Caleb Connolly Date: Sun, 16 Oct 2022 19:03:26 +0100 Subject: [PATCH 136/261] arm64: dts: qcom: sdm845-oneplus: enable rradc Enable the RRADC for the OnePlus 6. Signed-off-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221016180330.1912214-3-caleb.connolly@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 5d99908d4628..7e9a66c3cf67 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -461,6 +461,10 @@ pinconf { }; }; +&pmi8998_rradc { + status = "okay"; +}; + &qupv3_id_1 { status = "okay"; }; From e779eb99859cc26d051f6fc723d2bd2d5990a812 Mon Sep 17 00:00:00 2001 From: Caleb Connolly Date: Sun, 16 Oct 2022 19:03:27 +0100 Subject: [PATCH 137/261] arm64: dts: qcom: sdm845-db845c: enable rradc Enable the Round Robin ADC for the db845c. Signed-off-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221016180330.1912214-4-caleb.connolly@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 8ba3188ac4c3..3a407af43596 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -649,6 +649,10 @@ led@5 { }; }; +&pmi8998_rradc { + status = "okay"; +}; + /* QUAT I2S Uses 4 I2S SD Lines for audio on LT9611 HDMI Bridge */ &q6afedai { dai@22 { From 53c54069d9ffd556b52893077324e628655cd591 Mon Sep 17 00:00:00 2001 From: Caleb Connolly Date: Sun, 16 Oct 2022 19:03:28 +0100 Subject: [PATCH 138/261] arm64: dts: qcom: sdm845-xiaomi-beryllium: enable rradc Enable the PMI8998 RRADC. Signed-off-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221016180330.1912214-5-caleb.connolly@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index c2bed7b4ade8..eb6b2b676eca 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -335,6 +335,10 @@ resin { }; }; +&pmi8998_rradc { + status = "okay"; +}; + /* QUAT I2S Uses 1 I2S SD Line for audio on TAS2559/60 amplifiers */ &q6afedai { dai@22 { From aac16a9d247e5496361bfe20d651f2c1333eb5dc Mon Sep 17 00:00:00 2001 From: Jami Kettunen Date: Sun, 16 Oct 2022 19:03:29 +0100 Subject: [PATCH 139/261] arm64: dts: qcom: msm8998-oneplus-common: enable RRADC Enable the Round Robin ADC for the OnePlus 5/5T. Signed-off-by: Jami Kettunen Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221016180330.1912214-6-caleb.connolly@linaro.org --- arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi index 5b058c7693ff..7d4a67d07501 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi @@ -279,6 +279,10 @@ vol_keys_default: vol-keys-state { }; }; +&pmi8998_rradc { + status = "okay"; +}; + &qusb2phy { status = "okay"; From e9f2053b7866ac09f2acebbe65056204ef3fe67d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 18 Oct 2022 19:03:50 -0400 Subject: [PATCH 140/261] arm64: dts: qcom: sc7280: Add GPI DMA compatible fallback Use SM6350 as fallback for GPI DMA, to indicate devices are compatible and that drivers can bind with only one compatible. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221018230352.1238479-4-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index e3fa4fb1d711..907f5f74cd4c 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -920,7 +920,7 @@ opp-384000000 { gpi_dma0: dma-controller@900000 { #dma-cells = <3>; - compatible = "qcom,sc7280-gpi-dma"; + compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0 0x00900000 0 0x60000>; interrupts = , , @@ -1435,7 +1435,7 @@ uart7: serial@99c000 { gpi_dma1: dma-controller@a00000 { #dma-cells = <3>; - compatible = "qcom,sc7280-gpi-dma"; + compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0 0x00a00000 0 0x60000>; interrupts = , , From b561e225dee5412609fd98340ca71ba0ab2e4b36 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 18 Oct 2022 19:03:51 -0400 Subject: [PATCH 141/261] arm64: dts: qcom: sm8350: Add GPI DMA compatible fallback Use SM6350 as fallback for GPI DMA, to indicate devices are compatible and that drivers can bind with only one compatible. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221018230352.1238479-5-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index a86d9ea93b9d..aa08c0e065c7 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -678,7 +678,7 @@ ipcc: mailbox@408000 { }; gpi_dma2: dma-controller@800000 { - compatible = "qcom,sm8350-gpi-dma"; + compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0 0x00800000 0 0x60000>; interrupts = , , @@ -904,7 +904,7 @@ spi19: spi@894000 { }; gpi_dma0: dma-controller@900000 { - compatible = "qcom,sm8350-gpi-dma"; + compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0 0x09800000 0 0x60000>; interrupts = , , @@ -1209,7 +1209,7 @@ spi7: spi@99c000 { }; gpi_dma1: dma-controller@a00000 { - compatible = "qcom,sm8350-gpi-dma"; + compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0 0x00a00000 0 0x60000>; interrupts = , , From 19e67894500a8a038cb103e7267da5e64bcc853c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 18 Oct 2022 19:03:52 -0400 Subject: [PATCH 142/261] arm64: dts: qcom: sm8450: Add GPI DMA compatible fallback Use SM6350 as fallback for GPI DMA, to indicate devices are compatible and that drivers can bind with only one compatible. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221018230352.1238479-6-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index eeff62d0954b..73e81f4c41be 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -731,7 +731,7 @@ gcc: clock-controller@100000 { }; gpi_dma2: dma-controller@800000 { - compatible = "qcom,sm8450-gpi-dma"; + compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; #dma-cells = <3>; reg = <0 0x800000 0 0x60000>; interrupts = , @@ -1059,7 +1059,7 @@ spi21: spi@898000 { }; gpi_dma0: dma-controller@900000 { - compatible = "qcom,sm8450-gpi-dma"; + compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; #dma-cells = <3>; reg = <0 0x900000 0 0x60000>; interrupts = , @@ -1395,7 +1395,7 @@ uart7: serial@99c000 { }; gpi_dma1: dma-controller@a00000 { - compatible = "qcom,sm8450-gpi-dma"; + compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; #dma-cells = <3>; reg = <0 0xa00000 0 0x60000>; interrupts = , From 59e787935cfe6f562fbb9117e2df4076eaf810d8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Oct 2022 18:51:33 -0400 Subject: [PATCH 143/261] arm64: dts: qcom: sc7180-trogdor-homestar: fully configure secondary I2S pins The Trogdor Homestar DTSI adds additional GPIO52 pin to secondary I2S pins ("sec_mi2s_active") and configures it to "mi2s_1" function. The Trogdor DTSI (which is included by Homestar) configures drive strength and bias for all "sec_mi2s_active" pins, thus the intention was to apply this configuration also to GPIO52 on Homestar. Reported-by: Doug Anderson Signed-off-by: Krzysztof Kozlowski Fixes: be0416a3f917 ("arm64: dts: qcom: Add sc7180-trogdor-homestar") Reviewed-by: Douglas Anderson Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221020225135.31750-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi index 7fcff4eddd3a..8264b8d5e778 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi @@ -194,6 +194,12 @@ pinmux { pins = "gpio49", "gpio50", "gpio51", "gpio52"; function = "mi2s_1"; }; + + pinconf { + pins = "gpio49", "gpio50", "gpio51", "gpio52"; + drive-strength = <2>; + bias-pull-down; + }; }; &ts_reset_l { From 8ddfa04de492ceac93e72063e027216bb9b07ca5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Oct 2022 18:51:34 -0400 Subject: [PATCH 144/261] arm64: dts: qcom: sc7180: revert "arm64: dts: qcom: sc7180: Avoid glitching SPI CS at bootup on trogdor" This reverts commit e440e30e26dd6b0424002ad0ddcbbcea783efd85 because it is not a reliable way of fixing SPI CS glitch and it depends on specific Linux kernel pin controller driver behavior. This behavior of kernel driver was changed in commit b991f8c3622c ("pinctrl: core: Handling pinmux and pinconf separately") thus effectively the DTS fix stopped being effective. Proper solution for the glitching SPI chip select must be implemented in the drivers, not via ordering of entries in DTS, and is already introduced in commit d21f4b7ffc22 ("pinctrl: qcom: Avoid glitching lines when we first mux to output"). Signed-off-by: Krzysztof Kozlowski Reviewed-by: Douglas Anderson Tested-by: Douglas Anderson Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221020225135.31750-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 27 +++----------------- 1 file changed, 3 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 1a1c346d619c..33817358ebb0 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -880,17 +880,17 @@ &sdhc_2 { }; &spi0 { - pinctrl-0 = <&qup_spi0_cs_gpio_init_high>, <&qup_spi0_cs_gpio>; + pinctrl-0 = <&qup_spi0_cs_gpio>; cs-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>; }; &spi6 { - pinctrl-0 = <&qup_spi6_cs_gpio_init_high>, <&qup_spi6_cs_gpio>; + pinctrl-0 = <&qup_spi6_cs_gpio>; cs-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; }; ap_spi_fp: &spi10 { - pinctrl-0 = <&qup_spi10_cs_gpio_init_high>, <&qup_spi10_cs_gpio>; + pinctrl-0 = <&qup_spi10_cs_gpio>; cs-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; cros_ec_fp: ec@0 { @@ -1422,27 +1422,6 @@ pinconf { }; }; - qup_spi0_cs_gpio_init_high: qup-spi0-cs-gpio-init-high { - pinconf { - pins = "gpio37"; - output-high; - }; - }; - - qup_spi6_cs_gpio_init_high: qup-spi6-cs-gpio-init-high { - pinconf { - pins = "gpio62"; - output-high; - }; - }; - - qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high { - pinconf { - pins = "gpio89"; - output-high; - }; - }; - qup_uart3_sleep: qup-uart3-sleep { pinmux { pins = "gpio38", "gpio39", From 2f0300a6946702ff48f6584e0146bbe62c32abac Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Oct 2022 18:51:35 -0400 Subject: [PATCH 145/261] arm64: dts: qcom: sc7180: align TLMM pin configuration with DT schema DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. Merge subnodes named 'pinconf' and 'pinmux' into one entry, add function where missing (required by bindings for GPIOs) and reorganize overriding pins by boards. Split the SPI and UART configuration into separate nodes 1. SPI (MOSI, MISO, SCLK), SPI chip-select, SPI chip-select via GPIO, 2. UART per each pin: TX, RX and optional CTS/RTS. This allows each board to customize them easily without adding any new nodes. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Douglas Anderson Tested-by: Douglas Anderson Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221020225135.31750-4-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc7180-idp.dts | 244 +++---- .../boot/dts/qcom/sc7180-trogdor-coachz.dtsi | 36 +- .../dts/qcom/sc7180-trogdor-homestar.dtsi | 47 +- .../dts/qcom/sc7180-trogdor-kingoftown-r0.dts | 16 +- .../dts/qcom/sc7180-trogdor-kingoftown.dtsi | 8 +- .../boot/dts/qcom/sc7180-trogdor-lazor.dtsi | 16 +- .../dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi | 25 +- .../boot/dts/qcom/sc7180-trogdor-mrbland.dtsi | 72 +- .../qcom/sc7180-trogdor-parade-ps8640.dtsi | 32 +- .../boot/dts/qcom/sc7180-trogdor-pazquel.dtsi | 8 +- .../boot/dts/qcom/sc7180-trogdor-pompom.dtsi | 14 +- .../qcom/sc7180-trogdor-quackingstick.dtsi | 56 +- .../arm64/boot/dts/qcom/sc7180-trogdor-r1.dts | 8 +- .../dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi | 16 +- .../qcom/sc7180-trogdor-wormdingler-rev0.dtsi | 25 +- .../dts/qcom/sc7180-trogdor-wormdingler.dtsi | 72 +- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 633 +++++++---------- arch/arm64/boot/dts/qcom/sc7180.dtsi | 669 +++++++++--------- 18 files changed, 818 insertions(+), 1179 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts index 9dee131b1e24..70fd9ff8dfa2 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts @@ -481,287 +481,261 @@ pinconf { }; &qspi_clk { - pinconf { - pins = "gpio63"; - bias-disable; - }; + bias-disable; }; &qspi_cs0 { - pinconf { - pins = "gpio68"; - bias-disable; - }; + bias-disable; }; &qspi_data01 { - pinconf { - pins = "gpio64", "gpio65"; - - /* High-Z when no transfers; nice to park the lines */ - bias-pull-up; - }; + /* High-Z when no transfers; nice to park the lines */ + bias-pull-up; }; &qup_i2c2_default { - pinconf { - pins = "gpio15", "gpio16"; - drive-strength = <2>; + drive-strength = <2>; - /* Has external pullup */ - bias-disable; - }; + /* Has external pullup */ + bias-disable; }; &qup_i2c4_default { - pinconf { - pins = "gpio115", "gpio116"; - drive-strength = <2>; + drive-strength = <2>; - /* Has external pullup */ - bias-disable; - }; + /* Has external pullup */ + bias-disable; }; &qup_i2c7_default { - pinconf { - pins = "gpio6", "gpio7"; - drive-strength = <2>; + drive-strength = <2>; - /* Has external pullup */ - bias-disable; - }; + /* Has external pullup */ + bias-disable; }; &qup_i2c9_default { - pinconf { - pins = "gpio46", "gpio47"; - drive-strength = <2>; + drive-strength = <2>; - /* Has external pullup */ - bias-disable; - }; + /* Has external pullup */ + bias-disable; }; -&qup_uart3_default { - pinconf-cts { - /* - * Configure a pull-down on CTS to match the pull of - * the Bluetooth module. - */ - pins = "gpio38"; - bias-pull-down; - }; - - pinconf-rts { - /* We'll drive RTS, so no pull */ - pins = "gpio39"; - drive-strength = <2>; - bias-disable; - }; - - pinconf-tx { - /* We'll drive TX, so no pull */ - pins = "gpio40"; - drive-strength = <2>; - bias-disable; - }; - - pinconf-rx { - /* - * Configure a pull-up on RX. This is needed to avoid - * garbage data when the TX pin of the Bluetooth module is - * in tri-state (module powered off or not driving the - * signal yet). - */ - pins = "gpio41"; - bias-pull-up; - }; +&qup_uart3_cts { + /* + * Configure a pull-down on CTS to match the pull of + * the Bluetooth module. + */ + bias-pull-down; }; -&qup_uart8_default { - pinconf-tx { - pins = "gpio44"; - drive-strength = <2>; - bias-disable; - }; - - pinconf-rx { - pins = "gpio45"; - drive-strength = <2>; - bias-pull-up; - }; +&qup_uart3_rts { + /* We'll drive RTS, so no pull */ + drive-strength = <2>; + bias-disable; }; -&qup_spi0_default { - pinconf { - pins = "gpio34", "gpio35", "gpio36", "gpio37"; - drive-strength = <2>; - bias-disable; - }; +&qup_uart3_tx { + /* We'll drive TX, so no pull */ + drive-strength = <2>; + bias-disable; }; -&qup_spi6_default { - pinconf { - pins = "gpio59", "gpio60", "gpio61", "gpio62"; - drive-strength = <2>; - bias-disable; - }; +&qup_uart3_rx { + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module is + * in tri-state (module powered off or not driving the + * signal yet). + */ + bias-pull-up; }; -&qup_spi10_default { - pinconf { - pins = "gpio86", "gpio87", "gpio88", "gpio89"; - drive-strength = <2>; - bias-disable; - }; +&qup_uart8_tx { + drive-strength = <2>; + bias-disable; +}; + +&qup_uart8_rx { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_spi0_spi { + drive-strength = <2>; + bias-disable; +}; + +&qup_spi0_cs { + drive-strength = <2>; + bias-disable; +}; + +&qup_spi6_spi { + drive-strength = <2>; + bias-disable; +}; + +&qup_spi6_cs { + drive-strength = <2>; + bias-disable; +}; + +&qup_spi10_spi { + drive-strength = <2>; + bias-disable; +}; + +&qup_spi10_cs { + drive-strength = <2>; + bias-disable; }; &tlmm { - qup_uart3_sleep: qup-uart3-sleep { - pinmux { - pins = "gpio38", "gpio39", - "gpio40", "gpio41"; - function = "gpio"; - }; - - pinconf-cts { + qup_uart3_sleep: qup-uart3-sleep-state { + cts-pins { /* * Configure a pull-down on CTS to match the pull of * the Bluetooth module. */ pins = "gpio38"; + function = "gpio"; bias-pull-down; }; - pinconf-rts { + rts-pins { /* * Configure pull-down on RTS. As RTS is active low * signal, pull it low to indicate the BT SoC that it * can wakeup the system anytime from suspend state by * pulling RX low (by sending wakeup bytes). */ - pins = "gpio39"; - bias-pull-down; + pins = "gpio39"; + function = "gpio"; + bias-pull-down; }; - pinconf-tx { + tx-pins { /* * Configure pull-up on TX when it isn't actively driven * to prevent BT SoC from receiving garbage during sleep. */ pins = "gpio40"; + function = "gpio"; bias-pull-up; }; - pinconf-rx { + rx-pins { /* * Configure a pull-up on RX. This is needed to avoid * garbage data when the TX pin of the Bluetooth module * is floating which may cause spurious wakeups. */ pins = "gpio41"; + function = "gpio"; bias-pull-up; }; }; - sdc1_on: sdc1-on { - pinconf-clk { + sdc1_on: sdc1-on-state { + clk-pins { pins = "sdc1_clk"; bias-disable; drive-strength = <16>; }; - pinconf-cmd { + cmd-pins { pins = "sdc1_cmd"; bias-pull-up; drive-strength = <10>; }; - pinconf-data { + data-pins { pins = "sdc1_data"; bias-pull-up; drive-strength = <10>; }; - pinconf-rclk { + rclk-pins { pins = "sdc1_rclk"; bias-pull-down; }; }; - sdc1_off: sdc1-off { - pinconf-clk { + sdc1_off: sdc1-off-state { + clk-pins { pins = "sdc1_clk"; bias-disable; drive-strength = <2>; }; - pinconf-cmd { + cmd-pins { pins = "sdc1_cmd"; bias-pull-up; drive-strength = <2>; }; - pinconf-data { + data-pins { pins = "sdc1_data"; bias-pull-up; drive-strength = <2>; }; - pinconf-rclk { + rclk-pins { pins = "sdc1_rclk"; bias-pull-down; }; }; - sdc2_on: sdc2-on { - pinconf-clk { + sdc2_on: sdc2-on-state { + clk-pins { pins = "sdc2_clk"; bias-disable; drive-strength = <16>; }; - pinconf-cmd { + cmd-pins { pins = "sdc2_cmd"; bias-pull-up; drive-strength = <10>; }; - pinconf-data { + data-pins { pins = "sdc2_data"; bias-pull-up; drive-strength = <10>; }; - pinconf-sd-cd { + sd-cd-pins { pins = "gpio69"; + function = "gpio"; bias-pull-up; drive-strength = <2>; }; }; - sdc2_off: sdc2-off { - pinconf-clk { + sdc2_off: sdc2-off-state { + clk-pins { pins = "sdc2_clk"; bias-disable; drive-strength = <2>; }; - pinconf-cmd { + cmd-pins { pins = "sdc2_cmd"; bias-pull-up; drive-strength = <2>; }; - pinconf-data { + data-pins { pins = "sdc2_data"; bias-pull-up; drive-strength = <2>; }; - pinconf-sd-cd { + sd-cd-pins { pins = "gpio69"; + function = "gpio"; bias-pull-up; drive-strength = <2>; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi index 1ce73187a562..8b8ea8af165d 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi @@ -181,23 +181,15 @@ &sound_multimedia0_codec { /* PINCTRL - modifications to sc7180-trogdor.dtsi */ &en_pp3300_dx_edp { - pinmux { - pins = "gpio67"; - }; - - pinconf { - pins = "gpio67"; - }; + pins = "gpio67"; }; &ts_reset_l { - pinconf { - /* - * We want reset state by default and it will be up to the - * driver to disable this when it's ready. - */ - output-low; - }; + /* + * We want reset state by default and it will be up to the + * driver to disable this when it's ready. + */ + output-low; }; /* PINCTRL - board-specific pinctrl */ @@ -327,16 +319,10 @@ &tlmm { "DP_HOT_PLUG_DET", "EC_IN_RW_ODL"; - dmic_clk_en: dmic_clk_en { - pinmux { - pins = "gpio83"; - function = "gpio"; - }; - - pinconf { - pins = "gpio83"; - drive-strength = <8>; - bias-pull-up; - }; + dmic_clk_en: dmic-clk-en-state { + pins = "gpio83"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi index 8264b8d5e778..70e52fdb606a 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi @@ -180,36 +180,19 @@ &wifi { /* PINCTRL - modifications to sc7180-trogdor.dtsi */ &en_pp3300_dx_edp { - pinmux { - pins = "gpio67"; - }; - - pinconf { - pins = "gpio67"; - }; + pins = "gpio67"; }; &sec_mi2s_active { - pinmux { - pins = "gpio49", "gpio50", "gpio51", "gpio52"; - function = "mi2s_1"; - }; - - pinconf { - pins = "gpio49", "gpio50", "gpio51", "gpio52"; - drive-strength = <2>; - bias-pull-down; - }; + pins = "gpio49", "gpio50", "gpio51", "gpio52"; }; &ts_reset_l { - pinconf { - /* - * We want reset state by default and it will be up to the - * driver to disable this when it's ready. - */ - output-low; - }; + /* + * We want reset state by default and it will be up to the + * driver to disable this when it's ready. + */ + output-low; }; /* PINCTRL - board-specific pinctrl */ @@ -339,16 +322,10 @@ &tlmm { "DP_HOT_PLUG_DET", "EC_IN_RW_ODL"; - en_pp3300_touch: en-pp3300-touch { - pinmux { - pins = "gpio87"; - function = "gpio"; - }; - - pinconf { - pins = "gpio87"; - drive-strength = <2>; - bias-disable; - }; + en_pp3300_touch: en-pp3300-touch-state { + pins = "gpio87"; + function = "gpio"; + drive-strength = <2>; + bias-disable; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r0.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r0.dts index 1a62e8d435ab..3abd6222fe46 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r0.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r0.dts @@ -29,16 +29,10 @@ &pp3300_fp_tp { }; &tlmm { - en_fp_rails: en-fp-rails { - pinmux { - pins = "gpio74"; - function = "gpio"; - }; - - pinconf { - pins = "gpio74"; - drive-strength = <2>; - bias-disable; - }; + en_fp_rails: en-fp-rails-state { + pins = "gpio74"; + function = "gpio"; + drive-strength = <2>; + bias-disable; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dtsi index 74f0e07ea5cf..4156ad6dbd96 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dtsi @@ -87,13 +87,7 @@ &wifi { /* PINCTRL - modifications to sc7180-trogdor.dtsi */ &en_pp3300_dx_edp { - pinmux { - pins = "gpio67"; - }; - - pinconf { - pins = "gpio67"; - }; + pins = "gpio67"; }; /* PINCTRL - board-specific pinctrl */ diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi index 002663d752da..269007d73162 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi @@ -75,21 +75,13 @@ &wifi { /* PINCTRL - modifications to sc7180-trogdor.dtsi */ &trackpad_int_1v8_odl { - pinmux { - pins = "gpio58"; - }; - - pinconf { - pins = "gpio58"; - }; + pins = "gpio58"; }; &ts_reset_l { - pinconf { - /* This pin is not connected on -rev0, pull up to park. */ - /delete-property/bias-disable; - bias-pull-up; - }; + /* This pin is not connected on -rev0, pull up to park. */ + /delete-property/bias-disable; + bias-pull-up; }; /* PINCTRL - board-specific pinctrl */ diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi index 7bc8402c018e..f4c1f3813664 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi @@ -24,30 +24,13 @@ &v1p8_mipi { /* PINCTRL - modifications to sc7180-trogdor-mrbland.dtsi */ &avdd_lcd_en { - pinmux { - pins = "gpio80"; - }; - - pinconf { - pins = "gpio80"; - }; + pins = "gpio80"; }; &mipi_1800_en { - pinmux { - pins = "gpio81"; - }; - - pinconf { - pins = "gpio81"; - }; + pins = "gpio81"; }; + &vdd_reset_1800 { - pinmux { - pins = "gpio76"; - }; - - pinconf { - pins = "gpio76"; - }; + pins = "gpio76"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi index 97cba7f8064f..5e563655baec 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi @@ -160,13 +160,7 @@ pp3300_disp_on: &pp3300_dx_edp { */ tp_en: &en_pp3300_dx_edp { - pinmux { - pins = "gpio85"; - }; - - pinconf { - pins = "gpio85"; - }; + pins = "gpio85"; }; /* PINCTRL - board-specific pinctrl */ @@ -296,55 +290,31 @@ &tlmm { "DP_HOT_PLUG_DET", "EC_IN_RW_ODL"; - avdd_lcd_en: avdd-lcd-en { - pinmux { - pins = "gpio88"; - function = "gpio"; - }; - - pinconf { - pins = "gpio88"; - drive-strength = <2>; - bias-disable; - }; + avdd_lcd_en: avdd-lcd-en-state { + pins = "gpio88"; + function = "gpio"; + drive-strength = <2>; + bias-disable; }; - avee_lcd_en: avee-lcd-en { - pinmux { - pins = "gpio21"; - function = "gpio"; - }; - - pinconf { - pins = "gpio21"; - drive-strength = <2>; - bias-disable; - }; + avee_lcd_en: avee-lcd-en-state { + pins = "gpio21"; + function = "gpio"; + drive-strength = <2>; + bias-disable; }; - mipi_1800_en: mipi-1800-en { - pinmux { - pins = "gpio86"; - function = "gpio"; - }; - - pinconf { - pins = "gpio86"; - drive-strength = <2>; - bias-disable; - }; + mipi_1800_en: mipi-1800-en-state { + pins = "gpio86"; + function = "gpio"; + drive-strength = <2>; + bias-disable; }; - vdd_reset_1800: vdd-reset-1800 { - pinmux { - pins = "gpio87"; - function = "gpio"; - }; - - pinconf { - pins = "gpio87"; - drive-strength = <2>; - bias-disable; - }; + vdd_reset_1800: vdd-reset-1800-state { + pins = "gpio87"; + function = "gpio"; + drive-strength = <2>; + bias-disable; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi index 6a84fba178d6..070b3acb7baa 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi @@ -83,29 +83,17 @@ panel_in_edp: endpoint { }; &tlmm { - edp_brij_ps8640_rst: edp-brij-ps8640-rst { - pinmux { - pins = "gpio11"; - function = "gpio"; - }; - - pinconf { - pins = "gpio11"; - drive-strength = <2>; - bias-disable; - }; + edp_brij_ps8640_rst: edp-brij-ps8640-rst-state { + pins = "gpio11"; + function = "gpio"; + drive-strength = <2>; + bias-disable; }; - en_pp3300_edp_brij_ps8640: en-pp3300-edp-brij-ps8640 { - pinmux { - pins = "gpio32"; - function = "gpio"; - }; - - pinconf { - pins = "gpio32"; - drive-strength = <2>; - bias-disable; - }; + en_pp3300_edp_brij_ps8640: en-pp3300-edp-brij-ps8640-state { + pins = "gpio32"; + function = "gpio"; + drive-strength = <2>; + bias-disable; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi index 56d787785fd5..d06cc4ea3375 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi @@ -84,13 +84,7 @@ &pp3300_dx_edp { }; &en_pp3300_dx_edp { - pinmux { - pins = "gpio67"; - }; - - pinconf { - pins = "gpio67"; - }; + pins = "gpio67"; }; /* PINCTRL - board-specific pinctrl */ diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi index a7582fb547ee..6c5287bd27d6 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi @@ -312,15 +312,9 @@ &tlmm { "DP_HOT_PLUG_DET", "EC_IN_RW_ODL"; - dmic_sel: dmic-sel { - pinmux { - pins = "gpio86"; - function = "gpio"; - }; - - pinconf { - pins = "gpio86"; - bias-pull-down; - }; + dmic_sel: dmic-sel-state { + pins = "gpio86"; + function = "gpio"; + bias-pull-down; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi index 695b04fe7221..c1367999eafb 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi @@ -147,13 +147,7 @@ pp3300_disp_on: &pp3300_dx_edp { */ tp_en: &en_pp3300_dx_edp { - pinmux { - pins = "gpio67"; - }; - - pinconf { - pins = "gpio67"; - }; + pins = "gpio67"; }; /* PINCTRL - board-specific pinctrl */ @@ -283,42 +277,24 @@ &tlmm { "DP_HOT_PLUG_DET", "EC_IN_RW_ODL"; - lcd_rst: lcd-rst { - pinmux { - pins = "gpio87"; - function = "gpio"; - }; - - pinconf { - pins = "gpio87"; - drive-strength = <2>; - bias-disable; - }; + lcd_rst: lcd-rst-state { + pins = "gpio87"; + function = "gpio"; + drive-strength = <2>; + bias-disable; }; - ppvar_lcd_en: ppvar-lcd-en { - pinmux { - pins = "gpio88"; - function = "gpio"; - }; - - pinconf { - pins = "gpio88"; - drive-strength = <2>; - bias-disable; - }; + ppvar_lcd_en: ppvar-lcd-en-state { + pins = "gpio88"; + function = "gpio"; + drive-strength = <2>; + bias-disable; }; - pp1800_disp_on: pp1800-disp-on { - pinmux { - pins = "gpio86"; - function = "gpio"; - }; - - pinconf { - pins = "gpio86"; - drive-strength = <2>; - bias-disable; - }; + pp1800_disp_on: pp1800-disp-on-state { + pins = "gpio86"; + function = "gpio"; + drive-strength = <2>; + bias-disable; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts index bc097d1b1b23..671b3691f1bb 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts @@ -63,13 +63,7 @@ &usb_hub_3_x { /* PINCTRL - modifications to sc7180-trogdor.dtsi */ &trackpad_int_1v8_odl { - pinmux { - pins = "gpio58"; - }; - - pinconf { - pins = "gpio58"; - }; + pins = "gpio58"; }; /* PINCTRL - board-specific pinctrl */ diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi index f869e6a343c1..65333709e529 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi @@ -76,16 +76,10 @@ panel_in_edp: endpoint { }; &tlmm { - edp_brij_irq: edp-brij-irq { - pinmux { - pins = "gpio11"; - function = "gpio"; - }; - - pinconf { - pins = "gpio11"; - drive-strength = <2>; - bias-pull-down; - }; + edp_brij_irq: edp-brij-irq-state { + pins = "gpio11"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0.dtsi index db29e0cba29d..7f272c6e95f6 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0.dtsi @@ -24,30 +24,13 @@ &v1p8_mipi { /* PINCTRL - modifications to sc7180-trogdor-wormdingler.dtsi */ &avdd_lcd_en { - pinmux { - pins = "gpio80"; - }; - - pinconf { - pins = "gpio80"; - }; + pins = "gpio80"; }; &mipi_1800_en { - pinmux { - pins = "gpio81"; - }; - - pinconf { - pins = "gpio81"; - }; + pins = "gpio81"; }; + &vdd_reset_1800 { - pinmux { - pins = "gpio76"; - }; - - pinconf { - pins = "gpio76"; - }; + pins = "gpio76"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi index 6312108e8b3e..123989ba97e1 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi @@ -222,13 +222,7 @@ pp3300_disp_on: &pp3300_dx_edp { */ tp_en: &en_pp3300_dx_edp { - pinmux { - pins = "gpio85"; - }; - - pinconf { - pins = "gpio85"; - }; + pins = "gpio85"; }; /* PINCTRL - board-specific pinctrl */ @@ -358,55 +352,31 @@ &tlmm { "DP_HOT_PLUG_DET", "EC_IN_RW_ODL"; - avdd_lcd_en: avdd-lcd-en { - pinmux { - pins = "gpio88"; - function = "gpio"; - }; - - pinconf { - pins = "gpio88"; - drive-strength = <2>; - bias-disable; - }; + avdd_lcd_en: avdd-lcd-en-state { + pins = "gpio88"; + function = "gpio"; + drive-strength = <2>; + bias-disable; }; - avee_lcd_en: avee-lcd-en { - pinmux { - pins = "gpio21"; - function = "gpio"; - }; - - pinconf { - pins = "gpio21"; - drive-strength = <2>; - bias-disable; - }; + avee_lcd_en: avee-lcd-en-state { + pins = "gpio21"; + function = "gpio"; + drive-strength = <2>; + bias-disable; }; - mipi_1800_en: mipi-1800-en { - pinmux { - pins = "gpio86"; - function = "gpio"; - }; - - pinconf { - pins = "gpio86"; - drive-strength = <2>; - bias-disable; - }; + mipi_1800_en: mipi-1800-en-state { + pins = "gpio86"; + function = "gpio"; + drive-strength = <2>; + bias-disable; }; - vdd_reset_1800: vdd-reset-1800 { - pinmux { - pins = "gpio87"; - function = "gpio"; - }; - - pinconf { - pins = "gpio87"; - drive-strength = <2>; - bias-disable; - }; + vdd_reset_1800: vdd-reset-1800-state { + pins = "gpio87"; + function = "gpio"; + drive-strength = <2>; + bias-disable; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 33817358ebb0..4a5ea17a15ba 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -880,17 +880,17 @@ &sdhc_2 { }; &spi0 { - pinctrl-0 = <&qup_spi0_cs_gpio>; + pinctrl-0 = <&qup_spi0_spi>, <&qup_spi0_cs_gpio>; cs-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>; }; &spi6 { - pinctrl-0 = <&qup_spi6_cs_gpio>; + pinctrl-0 = <&qup_spi6_spi>, <&qup_spi6_cs_gpio>; cs-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; }; ap_spi_fp: &spi10 { - pinctrl-0 = <&qup_spi10_cs_gpio>; + pinctrl-0 = <&qup_spi10_spi>, <&qup_spi10_cs_gpio>; cs-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; cros_ec_fp: ec@0 { @@ -997,175 +997,141 @@ wifi-firmware { /* PINCTRL - additions to nodes defined in sc7180.dtsi */ &dp_hot_plug_det { - pinconf { - pins = "gpio117"; - bias-disable; - }; + bias-disable; }; &pri_mi2s_active { - pinconf { - pins = "gpio53", "gpio54", "gpio55", "gpio56"; - drive-strength = <2>; - bias-pull-down; - }; + drive-strength = <2>; + bias-pull-down; }; &pri_mi2s_mclk_active { - pinconf { - pins = "gpio57"; - drive-strength = <2>; - bias-pull-down; - }; + drive-strength = <2>; + bias-pull-down; }; &qspi_cs0 { - pinconf { - pins = "gpio68"; - bias-disable; - }; + bias-disable; }; &qspi_clk { - pinconf { - pins = "gpio63"; - drive-strength = <8>; - bias-disable; - }; + drive-strength = <8>; + bias-disable; }; &qspi_data01 { - pinconf { - pins = "gpio64", "gpio65"; - - /* High-Z when no transfers; nice to park the lines */ - bias-pull-up; - }; + /* High-Z when no transfers; nice to park the lines */ + bias-pull-up; }; &qup_i2c2_default { - pinconf { - pins = "gpio15", "gpio16"; - drive-strength = <2>; + drive-strength = <2>; - /* Has external pullup */ - bias-disable; - }; + /* Has external pullup */ + bias-disable; }; &qup_i2c4_default { - pinconf { - pins = "gpio115", "gpio116"; - drive-strength = <2>; + drive-strength = <2>; - /* Has external pullup */ - bias-disable; - }; + /* Has external pullup */ + bias-disable; }; &qup_i2c5_default { - pinconf { - pins = "gpio25", "gpio26"; - drive-strength = <2>; + drive-strength = <2>; - /* Has external pullup */ - bias-disable; - }; + /* Has external pullup */ + bias-disable; }; &qup_i2c7_default { - pinconf { - pins = "gpio6", "gpio7"; - drive-strength = <2>; + drive-strength = <2>; - /* Has external pullup */ - bias-disable; - }; + /* Has external pullup */ + bias-disable; }; &qup_i2c9_default { - pinconf { - pins = "gpio46", "gpio47"; - drive-strength = <2>; + drive-strength = <2>; - /* Has external pullup */ - bias-disable; - }; + /* Has external pullup */ + bias-disable; +}; + +&qup_spi0_spi { + drive-strength = <2>; + bias-disable; }; &qup_spi0_cs_gpio { - pinconf { - pins = "gpio34", "gpio35", "gpio36", "gpio37"; - drive-strength = <2>; - bias-disable; - }; + drive-strength = <2>; + bias-disable; +}; + +&qup_spi6_spi { + drive-strength = <2>; + bias-disable; }; &qup_spi6_cs_gpio { - pinconf { - pins = "gpio59", "gpio60", "gpio61", "gpio62"; - drive-strength = <2>; - bias-disable; - }; + drive-strength = <2>; + bias-disable; +}; + +&qup_spi10_spi { + drive-strength = <2>; + bias-disable; }; &qup_spi10_cs_gpio { - pinconf { - pins = "gpio86", "gpio87", "gpio88", "gpio89"; - drive-strength = <2>; - bias-disable; - }; + drive-strength = <2>; + bias-disable; }; -&qup_uart3_default { - pinconf-cts { - /* - * Configure a pull-down on CTS to match the pull of - * the Bluetooth module. - */ - pins = "gpio38"; - bias-pull-down; - }; - - pinconf-rts-tx { - /* We'll drive RTS and TX, so no pull */ - pins = "gpio39", "gpio40"; - drive-strength = <2>; - bias-disable; - }; - - pinconf-rx { - /* - * Configure a pull-up on RX. This is needed to avoid - * garbage data when the TX pin of the Bluetooth module is - * in tri-state (module powered off or not driving the - * signal yet). - */ - pins = "gpio41"; - bias-pull-up; - }; +&qup_uart3_cts { + /* + * Configure a pull-down on CTS to match the pull of + * the Bluetooth module. + */ + bias-pull-down; }; -&qup_uart8_default { - pinconf-tx { - pins = "gpio44"; - drive-strength = <2>; - bias-disable; - }; +&qup_uart3_rts { + /* We'll drive RTS, so no pull */ + drive-strength = <2>; + bias-disable; +}; - pinconf-rx { - pins = "gpio45"; - drive-strength = <2>; - bias-pull-up; - }; +&qup_uart3_tx { + /* We'll drive TX, so no pull */ + drive-strength = <2>; + bias-disable; +}; + +&qup_uart3_rx { + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module is + * in tri-state (module powered off or not driving the + * signal yet). + */ + bias-pull-up; +}; + +&qup_uart8_tx { + drive-strength = <2>; + bias-disable; +}; + +&qup_uart8_rx { + drive-strength = <2>; + bias-pull-up; }; &sec_mi2s_active { - pinconf { - pins = "gpio49", "gpio50", "gpio51"; - drive-strength = <2>; - bias-pull-down; - }; + drive-strength = <2>; + bias-pull-down; }; /* PINCTRL - board-specific pinctrl */ @@ -1196,447 +1162,324 @@ &tlmm { pinctrl-names = "default"; pinctrl-0 = <&bios_flash_wp_l>, <&ap_suspend_l_neuter>; - amp_en: amp-en { - pinmux { - pins = "gpio23"; - function = "gpio"; - }; - - pinconf { - pins = "gpio23"; - bias-pull-down; - }; + amp_en: amp-en-state { + pins = "gpio23"; + function = "gpio"; + bias-pull-down; }; - ap_ec_int_l: ap-ec-int-l { - pinmux { - pins = "gpio94"; - function = "gpio"; - input-enable; - }; - - pinconf { - pins = "gpio94"; - bias-pull-up; - }; + ap_ec_int_l: ap-ec-int-l-state { + pins = "gpio94"; + function = "gpio"; + input-enable; + bias-pull-up; }; - ap_edp_bklten: ap-edp-bklten { - pinmux { - pins = "gpio12"; - function = "gpio"; - }; + ap_edp_bklten: ap-edp-bklten-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <2>; + bias-disable; - pinconf { - pins = "gpio12"; - drive-strength = <2>; - bias-disable; - - /* Force backlight to be disabled to match state at boot. */ - output-low; - }; + /* Force backlight to be disabled to match state at boot. */ + output-low; }; - ap_suspend_l_neuter: ap-suspend-l-neuter { - pinmux { - pins = "gpio27"; - function = "gpio"; - }; - - pinconf { - pins = "gpio27"; - bias-disable; - }; + ap_suspend_l_neuter: ap-suspend-l-neuter-state { + pins = "gpio27"; + function = "gpio"; + bias-disable; }; - bios_flash_wp_l: bios-flash-wp-l { - pinmux { - pins = "gpio66"; - function = "gpio"; - input-enable; - }; - - pinconf { - pins = "gpio66"; - bias-disable; - }; + bios_flash_wp_l: bios-flash-wp-l-state { + pins = "gpio66"; + function = "gpio"; + input-enable; + bias-disable; }; - edp_brij_en: edp-brij-en { - pinmux { - pins = "gpio104"; - function = "gpio"; - }; - - pinconf { - pins = "gpio104"; - drive-strength = <2>; - bias-disable; - }; + edp_brij_en: edp-brij-en-state { + pins = "gpio104"; + function = "gpio"; + drive-strength = <2>; + bias-disable; }; - en_pp3300_codec: en-pp3300-codec { - pinmux { - pins = "gpio83"; - function = "gpio"; - }; - - pinconf { - pins = "gpio83"; - drive-strength = <2>; - bias-disable; - }; + en_pp3300_codec: en-pp3300-codec-state { + pins = "gpio83"; + function = "gpio"; + drive-strength = <2>; + bias-disable; }; - en_pp3300_dx_edp: en-pp3300-dx-edp { - pinmux { - pins = "gpio30"; - function = "gpio"; - }; - - pinconf { - pins = "gpio30"; - drive-strength = <2>; - bias-disable; - }; + en_pp3300_dx_edp: en-pp3300-dx-edp-state { + pins = "gpio30"; + function = "gpio"; + drive-strength = <2>; + bias-disable; }; - en_pp3300_hub: en-pp3300-hub { - pinmux { - pins = "gpio84"; - function = "gpio"; - }; - - pinconf { - pins = "gpio84"; - drive-strength = <2>; - bias-disable; - }; + en_pp3300_hub: en-pp3300-hub-state { + pins = "gpio84"; + function = "gpio"; + drive-strength = <2>; + bias-disable; }; - fp_to_ap_irq_l: fp-to-ap-irq-l { - pinmux { - pins = "gpio4"; - function = "gpio"; - input-enable; - }; + fp_to_ap_irq_l: fp-to-ap-irq-l-state { + pins = "gpio4"; + function = "gpio"; + input-enable; - pinconf { - pins = "gpio4"; - - /* Has external pullup */ - bias-disable; - }; + /* Has external pullup */ + bias-disable; }; - h1_ap_int_odl: h1-ap-int-odl { - pinmux { - pins = "gpio42"; - function = "gpio"; - input-enable; - }; - - pinconf { - pins = "gpio42"; - bias-pull-up; - }; + h1_ap_int_odl: h1-ap-int-odl-state { + pins = "gpio42"; + function = "gpio"; + input-enable; + bias-pull-up; }; - hp_irq: hp-irq { - pinmux { - pins = "gpio28"; - function = "gpio"; - }; - - pinconf { - pins = "gpio28"; - bias-pull-up; - }; + hp_irq: hp-irq-state { + pins = "gpio28"; + function = "gpio"; + bias-pull-up; }; - pen_irq_l: pen-irq-l { - pinmux { - pins = "gpio21"; - function = "gpio"; - }; + pen_irq_l: pen-irq-l-state { + pins = "gpio21"; + function = "gpio"; - pinconf { - pins = "gpio21"; - - /* Has external pullup */ - bias-disable; - }; + /* Has external pullup */ + bias-disable; }; - pen_pdct_l: pen-pdct-l { - pinmux { - pins = "gpio52"; - function = "gpio"; - }; + pen_pdct_l: pen-pdct-l-state-state { + pins = "gpio52"; + function = "gpio"; - pinconf { - pins = "gpio52"; - - /* Has external pullup */ - bias-disable; - }; + /* Has external pullup */ + bias-disable; }; - pen_rst_odl: pen-rst-odl { - pinmux { - pins = "gpio18"; - function = "gpio"; - }; + pen_rst_odl: pen-rst-odl-state { + pins = "gpio18"; + function = "gpio"; + bias-disable; + drive-strength = <2>; - pinconf { - pins = "gpio18"; - bias-disable; - drive-strength = <2>; - - /* - * The pen driver doesn't currently support - * driving this reset line. By specifying - * output-high here we're relying on the fact - * that this pin has a default pulldown at boot - * (which makes sure the pen was in reset if it - * was powered) and then we set it high here to - * take it out of reset. Better would be if the - * pen driver could control this and we could - * remove "output-high" here. - */ - output-high; /* TODO: Remove this? */ - }; + /* + * The pen driver doesn't currently support + * driving this reset line. By specifying + * output-high here we're relying on the fact + * that this pin has a default pulldown at boot + * (which makes sure the pen was in reset if it + * was powered) and then we set it high here to + * take it out of reset. Better would be if the + * pen driver could control this and we could + * remove "output-high" here. + */ + output-high; /* TODO: Remove this? */ }; - p_sensor_int_l: p-sensor-int-l { - pinmux { - pins = "gpio24"; - function = "gpio"; - input-enable; - }; + p_sensor_int_l: p-sensor-int-l-state { + pins = "gpio24"; + function = "gpio"; + input-enable; - pinconf { - pins = "gpio24"; - /* Has external pullup */ - bias-disable; - }; + /* Has external pullup */ + bias-disable; }; - qup_uart3_sleep: qup-uart3-sleep { - pinmux { - pins = "gpio38", "gpio39", - "gpio40", "gpio41"; - function = "gpio"; - }; - - pinconf-cts { + qup_uart3_sleep: qup-uart3-sleep-state { + cts-pins { /* * Configure a pull-down on CTS to match the pull of * the Bluetooth module. */ pins = "gpio38"; + function = "gpio"; bias-pull-down; }; - pinconf-rts { + rts-pins { /* * Configure pull-down on RTS. As RTS is active low * signal, pull it low to indicate the BT SoC that it * can wakeup the system anytime from suspend state by * pulling RX low (by sending wakeup bytes). */ - pins = "gpio39"; - bias-pull-down; + pins = "gpio39"; + function = "gpio"; + bias-pull-down; }; - pinconf-tx { + tx-pins { /* * Configure pull-up on TX when it isn't actively driven * to prevent BT SoC from receiving garbage during sleep. */ pins = "gpio40"; + function = "gpio"; bias-pull-up; }; - pinconf-rx { + rx-pins { /* * Configure a pull-up on RX. This is needed to avoid * garbage data when the TX pin of the Bluetooth module * is floating which may cause spurious wakeups. */ pins = "gpio41"; + function = "gpio"; bias-pull-up; }; }; /* Named trackpad_int_1v8_odl on earlier revision schematics */ trackpad_int_1v8_odl: - tp_int_odl: tp-int-odl { - pinmux { - pins = "gpio0"; - function = "gpio"; - }; + tp_int_odl: tp-int-odl-state { + pins = "gpio0"; + function = "gpio"; - pinconf { - pins = "gpio0"; - - /* Has external pullup */ - bias-disable; - }; + /* Has external pullup */ + bias-disable; }; - ts_int_l: ts-int-l { - pinmux { - pins = "gpio9"; - function = "gpio"; - }; - - pinconf { - pins = "gpio9"; - bias-pull-up; - }; + ts_int_l: ts-int-l-state { + pins = "gpio9"; + function = "gpio"; + bias-pull-up; }; - ts_reset_l: ts-reset-l { - pinmux { - pins = "gpio8"; - function = "gpio"; - }; - - pinconf { - pins = "gpio8"; - bias-disable; - drive-strength = <2>; - }; + ts_reset_l: ts-reset-l-state { + pins = "gpio8"; + function = "gpio"; + bias-disable; + drive-strength = <2>; }; - sdc1_on: sdc1-on { - pinconf-clk { + sdc1_on: sdc1-on-state { + clk-pins { pins = "sdc1_clk"; bias-disable; drive-strength = <16>; }; - pinconf-cmd { + cmd-pins { pins = "sdc1_cmd"; bias-pull-up; drive-strength = <16>; }; - pinconf-data { + data-pins { pins = "sdc1_data"; bias-pull-up; drive-strength = <16>; }; - pinconf-rclk { + rclk-pins { pins = "sdc1_rclk"; bias-pull-down; }; }; - sdc1_off: sdc1-off { - pinconf-clk { + sdc1_off: sdc1-off-state { + clk-pins { pins = "sdc1_clk"; bias-disable; drive-strength = <2>; }; - pinconf-cmd { + cmd-pins { pins = "sdc1_cmd"; bias-pull-up; drive-strength = <2>; }; - pinconf-data { + data-pins { pins = "sdc1_data"; bias-pull-up; drive-strength = <2>; }; - pinconf-rclk { + rclk-pins { pins = "sdc1_rclk"; bias-pull-down; }; }; - sdc2_on: sdc2-on { - pinconf-clk { + sdc2_on: sdc2-on-state { + clk-pins { pins = "sdc2_clk"; bias-disable; drive-strength = <16>; }; - pinconf-cmd { + cmd-pins { pins = "sdc2_cmd"; bias-pull-up; drive-strength = <10>; }; - pinconf-data { + data-pins { pins = "sdc2_data"; bias-pull-up; drive-strength = <10>; }; - pinconf-sd-cd { + sd-cd-pins { pins = "gpio69"; + function = "gpio"; bias-pull-up; drive-strength = <2>; }; }; - sdc2_off: sdc2-off { - pinconf-clk { + sdc2_off: sdc2-off-state { + clk-pins { pins = "sdc2_clk"; bias-disable; drive-strength = <2>; }; - pinconf-cmd { + cmd-pins { pins = "sdc2_cmd"; bias-pull-up; drive-strength = <2>; }; - pinconf-data { + data-pins { pins = "sdc2_data"; bias-pull-up; drive-strength = <2>; }; - pinconf-sd-cd { + sd-cd-pins { pins = "gpio69"; + function = "gpio"; bias-pull-up; drive-strength = <2>; }; }; - uf_cam_en: uf-cam-en { - pinmux { - pins = "gpio6"; - function = "gpio"; - }; + uf_cam_en: uf-cam-en-state { + pins = "gpio6"; + function = "gpio"; + drive-strength = <2>; - pinconf { - pins = "gpio6"; - drive-strength = <2>; - /* External pull down */ - bias-disable; - }; + /* External pull down */ + bias-disable; }; - wf_cam_en: wf-cam-en { - pinmux { - pins = "gpio7"; - function = "gpio"; - }; + wf_cam_en: wf-cam-en-state { + pins = "gpio7"; + function = "gpio"; + drive-strength = <2>; - pinconf { - pins = "gpio7"; - drive-strength = <2>; - /* External pull down */ - bias-disable; - }; + /* External pull down */ + bias-disable; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index f1482675610a..ea886cf08b4d 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -796,7 +796,7 @@ spi0: spi@880000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi0_default>; + pinctrl-0 = <&qup_spi0_spi>, <&qup_spi0_cs>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -850,7 +850,7 @@ spi1: spi@884000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi1_default>; + pinctrl-0 = <&qup_spi1_spi>, <&qup_spi1_cs>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -940,7 +940,7 @@ spi3: spi@88c000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi3_default>; + pinctrl-0 = <&qup_spi3_spi>, <&qup_spi3_cs>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -1030,7 +1030,7 @@ spi5: spi@894000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi5_default>; + pinctrl-0 = <&qup_spi5_spi>, <&qup_spi5_cs>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -1097,7 +1097,7 @@ spi6: spi@a80000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi6_default>; + pinctrl-0 = <&qup_spi6_spi>, <&qup_spi6_cs>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -1187,7 +1187,7 @@ spi8: spi@a88000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi8_default>; + pinctrl-0 = <&qup_spi8_spi>, <&qup_spi8_cs>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -1277,7 +1277,7 @@ spi10: spi@a90000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi10_default>; + pinctrl-0 = <&qup_spi10_spi>, <&qup_spi10_cs>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -1331,7 +1331,7 @@ spi11: spi@a94000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi11_default>; + pinctrl-0 = <&qup_spi11_spi>, <&qup_spi11_cs>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -1487,410 +1487,443 @@ tlmm: pinctrl@3500000 { gpio-ranges = <&tlmm 0 0 120>; wakeup-parent = <&pdc>; - dp_hot_plug_det: dp-hot-plug-det { - pinmux { - pins = "gpio117"; - function = "dp_hot"; - }; + dp_hot_plug_det: dp-hot-plug-det-state { + pins = "gpio117"; + function = "dp_hot"; }; - qspi_clk: qspi-clk { - pinmux { - pins = "gpio63"; - function = "qspi_clk"; - }; + qspi_clk: qspi-clk-state { + pins = "gpio63"; + function = "qspi_clk"; }; - qspi_cs0: qspi-cs0 { - pinmux { - pins = "gpio68"; - function = "qspi_cs"; - }; + qspi_cs0: qspi-cs0-state { + pins = "gpio68"; + function = "qspi_cs"; }; - qspi_cs1: qspi-cs1 { - pinmux { - pins = "gpio72"; - function = "qspi_cs"; - }; + qspi_cs1: qspi-cs1-state { + pins = "gpio72"; + function = "qspi_cs"; }; - qspi_data01: qspi-data01 { - pinmux-data { - pins = "gpio64", "gpio65"; - function = "qspi_data"; - }; + qspi_data01: qspi-data01-state { + pins = "gpio64", "gpio65"; + function = "qspi_data"; }; - qspi_data12: qspi-data12 { - pinmux-data { - pins = "gpio66", "gpio67"; - function = "qspi_data"; - }; + qspi_data12: qspi-data12-state { + pins = "gpio66", "gpio67"; + function = "qspi_data"; }; - qup_i2c0_default: qup-i2c0-default { - pinmux { - pins = "gpio34", "gpio35"; - function = "qup00"; - }; + qup_i2c0_default: qup-i2c0-default-state { + pins = "gpio34", "gpio35"; + function = "qup00"; }; - qup_i2c1_default: qup-i2c1-default { - pinmux { - pins = "gpio0", "gpio1"; - function = "qup01"; - }; + qup_i2c1_default: qup-i2c1-default-state { + pins = "gpio0", "gpio1"; + function = "qup01"; }; - qup_i2c2_default: qup-i2c2-default { - pinmux { - pins = "gpio15", "gpio16"; - function = "qup02_i2c"; - }; + qup_i2c2_default: qup-i2c2-default-state { + pins = "gpio15", "gpio16"; + function = "qup02_i2c"; }; - qup_i2c3_default: qup-i2c3-default { - pinmux { - pins = "gpio38", "gpio39"; - function = "qup03"; - }; + qup_i2c3_default: qup-i2c3-default-state { + pins = "gpio38", "gpio39"; + function = "qup03"; }; - qup_i2c4_default: qup-i2c4-default { - pinmux { - pins = "gpio115", "gpio116"; - function = "qup04_i2c"; - }; + qup_i2c4_default: qup-i2c4-default-state { + pins = "gpio115", "gpio116"; + function = "qup04_i2c"; }; - qup_i2c5_default: qup-i2c5-default { - pinmux { - pins = "gpio25", "gpio26"; - function = "qup05"; - }; + qup_i2c5_default: qup-i2c5-default-state { + pins = "gpio25", "gpio26"; + function = "qup05"; }; - qup_i2c6_default: qup-i2c6-default { - pinmux { - pins = "gpio59", "gpio60"; - function = "qup10"; - }; + qup_i2c6_default: qup-i2c6-default-state { + pins = "gpio59", "gpio60"; + function = "qup10"; }; - qup_i2c7_default: qup-i2c7-default { - pinmux { - pins = "gpio6", "gpio7"; - function = "qup11_i2c"; - }; + qup_i2c7_default: qup-i2c7-default-state { + pins = "gpio6", "gpio7"; + function = "qup11_i2c"; }; - qup_i2c8_default: qup-i2c8-default { - pinmux { - pins = "gpio42", "gpio43"; - function = "qup12"; - }; + qup_i2c8_default: qup-i2c8-default-state { + pins = "gpio42", "gpio43"; + function = "qup12"; }; - qup_i2c9_default: qup-i2c9-default { - pinmux { - pins = "gpio46", "gpio47"; - function = "qup13_i2c"; - }; + qup_i2c9_default: qup-i2c9-default-state { + pins = "gpio46", "gpio47"; + function = "qup13_i2c"; }; - qup_i2c10_default: qup-i2c10-default { - pinmux { - pins = "gpio86", "gpio87"; - function = "qup14"; - }; + qup_i2c10_default: qup-i2c10-default-state { + pins = "gpio86", "gpio87"; + function = "qup14"; }; - qup_i2c11_default: qup-i2c11-default { - pinmux { - pins = "gpio53", "gpio54"; - function = "qup15"; - }; + qup_i2c11_default: qup-i2c11-default-state { + pins = "gpio53", "gpio54"; + function = "qup15"; }; - qup_spi0_default: qup-spi0-default { - pinmux { - pins = "gpio34", "gpio35", - "gpio36", "gpio37"; - function = "qup00"; - }; + qup_spi0_spi: qup-spi0-spi-state { + pins = "gpio34", "gpio35", "gpio36"; + function = "qup00"; }; - qup_spi0_cs_gpio: qup-spi0-cs-gpio { - pinmux { - pins = "gpio34", "gpio35", - "gpio36"; + qup_spi0_cs: qup-spi0-cs-state { + pins = "gpio37"; + function = "qup00"; + }; + + qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { + pins = "gpio37"; + function = "gpio"; + }; + + qup_spi1_spi: qup-spi1-spi-state { + pins = "gpio0", "gpio1", "gpio2"; + function = "qup01"; + }; + + qup_spi1_cs: qup-spi1-cs-state { + pins = "gpio3"; + function = "qup01"; + }; + + qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { + pins = "gpio3"; + function = "gpio"; + }; + + qup_spi3_spi: qup-spi3-spi-state { + pins = "gpio38", "gpio39", "gpio40"; + function = "qup03"; + }; + + qup_spi3_cs: qup-spi3-cs-state { + pins = "gpio41"; + function = "qup03"; + }; + + qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { + pins = "gpio41"; + function = "gpio"; + }; + + qup_spi5_spi: qup-spi5-spi-state { + pins = "gpio25", "gpio26", "gpio27"; + function = "qup05"; + }; + + qup_spi5_cs: qup-spi5-cs-state { + pins = "gpio28"; + function = "qup05"; + }; + + qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { + pins = "gpio28"; + function = "gpio"; + }; + + qup_spi6_spi: qup-spi6-spi-state { + pins = "gpio59", "gpio60", "gpio61"; + function = "qup10"; + }; + + qup_spi6_cs: qup-spi6-cs-state { + pins = "gpio62"; + function = "qup10"; + }; + + qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { + pins = "gpio62"; + function = "gpio"; + }; + + qup_spi8_spi: qup-spi8-spi-state { + pins = "gpio42", "gpio43", "gpio44"; + function = "qup12"; + }; + + qup_spi8_cs: qup-spi8-cs-state { + pins = "gpio45"; + function = "qup12"; + }; + + qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { + pins = "gpio45"; + function = "gpio"; + }; + + qup_spi10_spi: qup-spi10-spi-state { + pins = "gpio86", "gpio87", "gpio88"; + function = "qup14"; + }; + + qup_spi10_cs: qup-spi10-cs-state { + pins = "gpio89"; + function = "qup14"; + }; + + qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { + pins = "gpio89"; + function = "gpio"; + }; + + qup_spi11_spi: qup-spi11-spi-state { + pins = "gpio53", "gpio54", "gpio55"; + function = "qup15"; + }; + + qup_spi11_cs: qup-spi11-cs-state { + pins = "gpio56"; + function = "qup15"; + }; + + qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { + pins = "gpio56"; + function = "gpio"; + }; + + qup_uart0_default: qup-uart0-default-state { + qup_uart0_cts: cts-pins { + pins = "gpio34"; function = "qup00"; }; - pinmux-cs { + qup_uart0_rts: rts-pins { + pins = "gpio35"; + function = "qup00"; + }; + + qup_uart0_tx: tx-pins { + pins = "gpio36"; + function = "qup00"; + }; + + qup_uart0_rx: rx-pins { pins = "gpio37"; - function = "gpio"; - }; - }; - - qup_spi1_default: qup-spi1-default { - pinmux { - pins = "gpio0", "gpio1", - "gpio2", "gpio3"; - function = "qup01"; - }; - }; - - qup_spi1_cs_gpio: qup-spi1-cs-gpio { - pinmux { - pins = "gpio0", "gpio1", - "gpio2"; - function = "qup01"; - }; - - pinmux-cs { - pins = "gpio3"; - function = "gpio"; - }; - }; - - qup_spi3_default: qup-spi3-default { - pinmux { - pins = "gpio38", "gpio39", - "gpio40", "gpio41"; - function = "qup03"; - }; - }; - - qup_spi3_cs_gpio: qup-spi3-cs-gpio { - pinmux { - pins = "gpio38", "gpio39", - "gpio40"; - function = "qup03"; - }; - - pinmux-cs { - pins = "gpio41"; - function = "gpio"; - }; - }; - - qup_spi5_default: qup-spi5-default { - pinmux { - pins = "gpio25", "gpio26", - "gpio27", "gpio28"; - function = "qup05"; - }; - }; - - qup_spi5_cs_gpio: qup-spi5-cs-gpio { - pinmux { - pins = "gpio25", "gpio26", - "gpio27"; - function = "qup05"; - }; - - pinmux-cs { - pins = "gpio28"; - function = "gpio"; - }; - }; - - qup_spi6_default: qup-spi6-default { - pinmux { - pins = "gpio59", "gpio60", - "gpio61", "gpio62"; - function = "qup10"; - }; - }; - - qup_spi6_cs_gpio: qup-spi6-cs-gpio { - pinmux { - pins = "gpio59", "gpio60", - "gpio61"; - function = "qup10"; - }; - - pinmux-cs { - pins = "gpio62"; - function = "gpio"; - }; - }; - - qup_spi8_default: qup-spi8-default { - pinmux { - pins = "gpio42", "gpio43", - "gpio44", "gpio45"; - function = "qup12"; - }; - }; - - qup_spi8_cs_gpio: qup-spi8-cs-gpio { - pinmux { - pins = "gpio42", "gpio43", - "gpio44"; - function = "qup12"; - }; - - pinmux-cs { - pins = "gpio45"; - function = "gpio"; - }; - }; - - qup_spi10_default: qup-spi10-default { - pinmux { - pins = "gpio86", "gpio87", - "gpio88", "gpio89"; - function = "qup14"; - }; - }; - - qup_spi10_cs_gpio: qup-spi10-cs-gpio { - pinmux { - pins = "gpio86", "gpio87", - "gpio88"; - function = "qup14"; - }; - - pinmux-cs { - pins = "gpio89"; - function = "gpio"; - }; - }; - - qup_spi11_default: qup-spi11-default { - pinmux { - pins = "gpio53", "gpio54", - "gpio55", "gpio56"; - function = "qup15"; - }; - }; - - qup_spi11_cs_gpio: qup-spi11-cs-gpio { - pinmux { - pins = "gpio53", "gpio54", - "gpio55"; - function = "qup15"; - }; - - pinmux-cs { - pins = "gpio56"; - function = "gpio"; - }; - }; - - qup_uart0_default: qup-uart0-default { - pinmux { - pins = "gpio34", "gpio35", - "gpio36", "gpio37"; function = "qup00"; }; }; - qup_uart1_default: qup-uart1-default { - pinmux { - pins = "gpio0", "gpio1", - "gpio2", "gpio3"; + qup_uart1_default: qup-uart1-default-state { + qup_uart1_cts: cts-pins { + pins = "gpio0"; + function = "qup01"; + }; + + qup_uart1_rts: rts-pins { + pins = "gpio1"; + function = "qup01"; + }; + + qup_uart1_tx: tx-pins { + pins = "gpio2"; + function = "qup01"; + }; + + qup_uart1_rx: rx-pins { + pins = "gpio3"; function = "qup01"; }; }; - qup_uart2_default: qup-uart2-default { - pinmux { - pins = "gpio15", "gpio16"; + qup_uart2_default: qup-uart2-default-state { + qup_uart2_tx: tx-pins { + pins = "gpio15"; + function = "qup02_uart"; + }; + + qup_uart2_rx: rx-pins { + pins = "gpio16"; function = "qup02_uart"; }; }; - qup_uart3_default: qup-uart3-default { - pinmux { - pins = "gpio38", "gpio39", - "gpio40", "gpio41"; + qup_uart3_default: qup-uart3-default-state { + qup_uart3_cts: cts-pins { + pins = "gpio38"; + function = "qup03"; + }; + + qup_uart3_rts: rts-pins { + pins = "gpio39"; + function = "qup03"; + }; + + qup_uart3_tx: tx-pins { + pins = "gpio40"; + function = "qup03"; + }; + + qup_uart3_rx: rx-pins { + pins = "gpio41"; function = "qup03"; }; }; - qup_uart4_default: qup-uart4-default { - pinmux { - pins = "gpio115", "gpio116"; + qup_uart4_default: qup-uart4-default-state { + qup_uart4_tx: tx-pins { + pins = "gpio115"; + function = "qup04_uart"; + }; + + qup_uart4_rx: rx-pins { + pins = "gpio116"; function = "qup04_uart"; }; }; - qup_uart5_default: qup-uart5-default { - pinmux { - pins = "gpio25", "gpio26", - "gpio27", "gpio28"; + qup_uart5_default: qup-uart5-default-state { + qup_uart5_cts: cts-pins { + pins = "gpio25"; + function = "qup05"; + }; + + qup_uart5_rts: rts-pins { + pins = "gpio26"; + function = "qup05"; + }; + + qup_uart5_tx: tx-pins { + pins = "gpio27"; + function = "qup05"; + }; + + qup_uart5_rx: rx-pins { + pins = "gpio28"; function = "qup05"; }; }; - qup_uart6_default: qup-uart6-default { - pinmux { - pins = "gpio59", "gpio60", - "gpio61", "gpio62"; + qup_uart6_default: qup-uart6-default-state { + qup_uart6_cts: cts-pins { + pins = "gpio59"; + function = "qup10"; + }; + + qup_uart6_rts: rts-pins { + pins = "gpio60"; + function = "qup10"; + }; + + qup_uart6_tx: tx-pins { + pins = "gpio61"; + function = "qup10"; + }; + + qup_uart6_rx: rx-pins { + pins = "gpio62"; function = "qup10"; }; }; - qup_uart7_default: qup-uart7-default { - pinmux { - pins = "gpio6", "gpio7"; + qup_uart7_default: qup-uart7-default-state { + qup_uart7_tx: tx-pins { + pins = "gpio6"; + function = "qup11_uart"; + }; + + qup_uart7_rx: rx-pins { + pins = "gpio7"; function = "qup11_uart"; }; }; - qup_uart8_default: qup-uart8-default { - pinmux { - pins = "gpio44", "gpio45"; + qup_uart8_default: qup-uart8-default-state { + qup_uart8_tx: tx-pins { + pins = "gpio44"; + function = "qup12"; + }; + + qup_uart8_rx: rx-pins { + pins = "gpio45"; function = "qup12"; }; }; - qup_uart9_default: qup-uart9-default { - pinmux { - pins = "gpio46", "gpio47"; + qup_uart9_default: qup-uart9-default-state { + qup_uart9_tx: tx-pins { + pins = "gpio46"; + function = "qup13_uart"; + }; + + qup_uart9_rx: rx-pins { + pins = "gpio47"; function = "qup13_uart"; }; }; - qup_uart10_default: qup-uart10-default { - pinmux { - pins = "gpio86", "gpio87", - "gpio88", "gpio89"; + qup_uart10_default: qup-uart10-default-state { + qup_uart10_cts: cts-pins { + pins = "gpio86"; + function = "qup14"; + }; + + qup_uart10_rts: rts-pins { + pins = "gpio87"; + function = "qup14"; + }; + + qup_uart10_tx: tx-pins { + pins = "gpio88"; + function = "qup14"; + }; + + qup_uart10_rx: rx-pins { + pins = "gpio89"; function = "qup14"; }; }; - qup_uart11_default: qup-uart11-default { - pinmux { - pins = "gpio53", "gpio54", - "gpio55", "gpio56"; + qup_uart11_default: qup-uart11-default-state { + qup_uart11_cts: cts-pins { + pins = "gpio53"; + function = "qup15"; + }; + + qup_uart11_rts: rts-pins { + pins = "gpio54"; + function = "qup15"; + }; + + qup_uart11_tx: tx-pins { + pins = "gpio55"; + function = "qup15"; + }; + + qup_uart11_rx: rx-pins { + pins = "gpio56"; function = "qup15"; }; }; - sec_mi2s_active: sec-mi2s-active { - pinmux { - pins = "gpio49", "gpio50", "gpio51"; - function = "mi2s_1"; - }; + sec_mi2s_active: sec-mi2s-active-state { + pins = "gpio49", "gpio50", "gpio51"; + function = "mi2s_1"; }; - pri_mi2s_active: pri-mi2s-active { - pinmux { - pins = "gpio53", "gpio54", "gpio55", "gpio56"; - function = "mi2s_0"; - }; + pri_mi2s_active: pri-mi2s-active-state { + pins = "gpio53", "gpio54", "gpio55", "gpio56"; + function = "mi2s_0"; }; - pri_mi2s_mclk_active: pri-mi2s-mclk-active { - pinmux { - pins = "gpio57"; - function = "lpass_ext"; - }; + pri_mi2s_mclk_active: pri-mi2s-mclk-active-state { + pins = "gpio57"; + function = "lpass_ext"; }; }; From 5ecbf096e0565d4761e0294aaa2e79ce44a53e6d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Oct 2022 18:53:08 -0400 Subject: [PATCH 146/261] arm64: dts: qcom: msm8996-sony-xperia-tone: drop incorrect wlan pin input Pin configuration has no "input-high" property, so drop it from node described as Wifi host wake up pin. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221020225309.32116-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi index de61c3c94903..cb9a169bb38b 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi @@ -912,7 +912,6 @@ wl_host_wake: wl-host-wake { function = "gpio"; drive-strength = <2>; bias-pull-down; - input-high; }; wl_reg_on: wl-reg-on { From 169e1553accfd31386a7d364ab57293802027ab7 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Oct 2022 18:53:09 -0400 Subject: [PATCH 147/261] arm64: dts: qcom: msm8996: align TLMM pin configuration with DT schema DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221020225309.32116-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 96 ++++------ arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts | 68 ++------ .../dts/qcom/msm8996-sony-xperia-tone.dtsi | 26 +-- .../boot/dts/qcom/msm8996-xiaomi-common.dtsi | 10 +- .../boot/dts/qcom/msm8996-xiaomi-gemini.dts | 8 +- arch/arm64/boot/dts/qcom/msm8996.dtsi | 164 +++++++++--------- .../dts/qcom/msm8996pro-xiaomi-natrium.dts | 4 +- .../dts/qcom/msm8996pro-xiaomi-scorpio.dts | 8 +- 8 files changed, 153 insertions(+), 231 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index 7f10372178d6..1b0a01f1e237 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -422,82 +422,46 @@ &tlmm { "NC", /* GPIO_148 */ "NC"; /* GPIO_149 */ - sdc2_cd_on: sdc2_cd_on { - mux { - pins = "gpio38"; - function = "gpio"; - }; - - config { - pins = "gpio38"; - bias-pull-up; /* pull up */ - drive-strength = <16>; /* 16 MA */ - }; + sdc2_cd_on: sdc2-cd-on-state { + pins = "gpio38"; + function = "gpio"; + bias-pull-up; + drive-strength = <16>; }; - sdc2_cd_off: sdc2_cd_off { - mux { - pins = "gpio38"; - function = "gpio"; - }; - - config { - pins = "gpio38"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ - }; + sdc2_cd_off: sdc2-cd-off-state { + pins = "gpio38"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; }; - hdmi_hpd_active: hdmi_hpd_active { - mux { - pins = "gpio34"; - function = "hdmi_hot"; - }; - - config { - pins = "gpio34"; - bias-pull-down; - drive-strength = <16>; - }; + hdmi_hpd_active: hdmi-hpd-active-state { + pins = "gpio34"; + function = "hdmi_hot"; + bias-pull-down; + drive-strength = <16>; }; - hdmi_hpd_suspend: hdmi_hpd_suspend { - mux { - pins = "gpio34"; - function = "hdmi_hot"; - }; - - config { - pins = "gpio34"; - bias-pull-down; - drive-strength = <2>; - }; + hdmi_hpd_suspend: hdmi-hpd-suspend-state { + pins = "gpio34"; + function = "hdmi_hot"; + bias-pull-down; + drive-strength = <2>; }; - hdmi_ddc_active: hdmi_ddc_active { - mux { - pins = "gpio32", "gpio33"; - function = "hdmi_ddc"; - }; - - config { - pins = "gpio32", "gpio33"; - drive-strength = <2>; - bias-pull-up; - }; + hdmi_ddc_active: hdmi-ddc-active-state { + pins = "gpio32", "gpio33"; + function = "hdmi_ddc"; + drive-strength = <2>; + bias-pull-up; }; - hdmi_ddc_suspend: hdmi_ddc_suspend { - mux { - pins = "gpio32", "gpio33"; - function = "hdmi_ddc"; - }; - - config { - pins = "gpio32", "gpio33"; - drive-strength = <2>; - bias-pull-down; - }; + hdmi_ddc_suspend: hdmi-ddc-suspend-state { + pins = "gpio32", "gpio33"; + function = "hdmi_ddc"; + drive-strength = <2>; + bias-pull-down; }; }; diff --git a/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts b/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts index 3ea793b20e7f..71e0a500599c 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts @@ -104,60 +104,22 @@ &mdss { status = "okay"; }; -&tlmm { - sdc2_pins_default: sdc2-pins-default { - clk { - pins = "sdc2_clk"; - bias-disable; - drive-strength = <16>; - }; +&sdc2_state_on { + cd-pins { + pins = "gpio38"; + function = "gpio"; - cmd { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <10>; - }; - - data { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <10>; - }; - - cd { - pins = "gpio38"; - function = "gpio"; - - bias-pull-up; - drive-strength = <16>; - }; + bias-pull-up; + drive-strength = <16>; }; +}; - sdc2_pins_sleep: sdc2-pins-sleep { - clk { - pins = "sdc2_clk"; - bias-disable; - drive-strength = <2>; - }; - - cmd { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <2>; - }; - - data { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <2>; - }; - - cd { - pins = "gpio38"; - function = "gpio"; - bias-pull-up; - drive-strength = <2>; - }; +&sdc2_state_off { + cd-pins { + pins = "gpio38"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; }; }; @@ -372,10 +334,6 @@ &sdhc2 { vmmc-supply = <&vreg_l21a_2p95>; vqmmc-supply = <&vreg_l13a_2p95>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_pins_default>; - pinctrl-1 = <&sdc2_pins_sleep>; }; &ufshc { diff --git a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi index cb9a169bb38b..dec361b93cce 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi @@ -847,28 +847,28 @@ &tlmm { pinctrl-0 = <&sw_service_gpio>; pinctrl-names = "default"; - disp_reset_n_gpio: disp-reset-n { + disp_reset_n_gpio: disp-reset-n-state { pins = "gpio8"; function = "gpio"; drive-strength = <2>; bias-disable; }; - mdp_vsync_p_gpio: mdp-vsync-p { + mdp_vsync_p_gpio: mdp-vsync-p-state { pins = "gpio10"; function = "mdp_vsync"; drive-strength = <2>; bias-disable; }; - sw_service_gpio: sw-service-gpio { + sw_service_gpio: sw-service-gpio-state { pins = "gpio16"; function = "gpio"; drive-strength = <2>; bias-pull-up; }; - usb_detect: usb-detect { + usb_detect: usb-detect-state { pins = "gpio25"; function = "gpio"; drive-strength = <2>; @@ -876,7 +876,7 @@ usb_detect: usb-detect { output-high; }; - uim_detect_en: uim-detect-en { + uim_detect_en: uim-detect-en-state { pins = "gpio29"; function = "gpio"; drive-strength = <2>; @@ -884,14 +884,14 @@ uim_detect_en: uim-detect-en { output-high; }; - tray_det_pin: tray-det { + tray_det_pin: tray-det-state { pins = "gpio40"; function = "gpio"; drive-strength = <2>; bias-disable; }; - tp_vddio_en: tp-vddio-en { + tp_vddio_en: tp-vddio-en-state { pins = "gpio50"; function = "gpio"; drive-strength = <2>; @@ -899,7 +899,7 @@ tp_vddio_en: tp-vddio-en { output-high; }; - lcd_vddio_en: lcd-vddio-en { + lcd_vddio_en: lcd-vddio-en-state { pins = "gpio51"; function = "gpio"; drive-strength = <2>; @@ -907,14 +907,14 @@ lcd_vddio_en: lcd-vddio-en { output-low; }; - wl_host_wake: wl-host-wake { + wl_host_wake: wl-host-wake-state { pins = "gpio79"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; - wl_reg_on: wl-reg-on { + wl_reg_on: wl-reg-on-state { pins = "gpio84"; function = "gpio"; drive-strength = <2>; @@ -922,20 +922,20 @@ wl_reg_on: wl-reg-on { output-low; }; - ts_reset_n: ts-rst-n { + ts_reset_n: ts-rst-n-state { pins = "gpio89"; function = "gpio"; drive-strength = <2>; }; - touch_int_n: touch-int-n { + touch_int_n: touch-int-n-state { pins = "gpio125"; function = "gpio"; drive-strength = <2>; bias-pull-up; }; - touch_int_sleep: touch-int-sleep { + touch_int_sleep: touch-int-sleep-state { pins = "gpio125"; function = "gpio"; drive-strength = <2>; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi index d2637909a356..5b47b8de69da 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi @@ -691,35 +691,35 @@ divclk4_pin_a: divclk4-state { }; &tlmm { - mdss_dsi_default: mdss_dsi_default { + mdss_dsi_default: mdss-dsi-default-state { pins = "gpio8"; function = "gpio"; drive-strength = <8>; bias-disable; }; - mdss_dsi_sleep: mdss_dsi_sleep { + mdss_dsi_sleep: mdss-dsi-sleep-state { pins = "gpio8"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; - mdss_te_default: mdss_te_default { + mdss_te_default: mdss-te-default-state { pins = "gpio10"; function = "mdp_vsync"; drive-strength = <2>; bias-pull-down; }; - mdss_te_sleep: mdss_te_sleep { + mdss_te_sleep: mdss-te-sleep-state { pins = "gpio10"; function = "mdp_vsync"; drive-strength = <2>; bias-pull-down; }; - nfc_default: nfc_default { + nfc_default: nfc-default-state { pins = "gpio12", "gpio21"; function = "gpio"; drive-strength = <16>; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts index 40f964ae80db..d8734913482f 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts @@ -446,28 +446,28 @@ &tlmm { "RFFE1_DATA", /* GPIO_148 */ "RFFE1_CLK"; /* GPIO_149 */ - touchscreen_default: touchscreen_default { + touchscreen_default: touchscreen-default-state { pins = "gpio89", "gpio125"; function = "gpio"; drive-strength = <10>; bias-pull-up; }; - touchscreen_sleep: touchscreen_sleep { + touchscreen_sleep: touchscreen-sleep-state { pins = "gpio89", "gpio125"; function = "gpio"; drive-strength = <2>; bias-disable; }; - vibrator_default: vibrator_default { + vibrator_default: vibrator-default-state { pins = "gpio93"; function = "gpio"; drive-strength = <8>; bias-pull-up; }; - vibrator_sleep: vibrator_sleep { + vibrator_sleep: vibrator-sleep-state { pins = "gpio93"; function = "gpio"; drive-strength = <2>; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 7f24c6a33ace..b7e4fbf5744d 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1280,15 +1280,15 @@ tlmm: pinctrl@1010000 { interrupt-controller; #interrupt-cells = <2>; - blsp1_spi1_default: blsp1-spi1-default { - spi { + blsp1_spi1_default: blsp1-spi1-default-state { + spi-pins { pins = "gpio0", "gpio1", "gpio3"; function = "blsp_spi1"; drive-strength = <12>; bias-disable; }; - cs { + cs-pins { pins = "gpio2"; function = "gpio"; drive-strength = <16>; @@ -1297,42 +1297,42 @@ cs { }; }; - blsp1_spi1_sleep: blsp1-spi1-sleep { + blsp1_spi1_sleep: blsp1-spi1-sleep-state { pins = "gpio0", "gpio1", "gpio2", "gpio3"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; - blsp2_uart2_2pins_default: blsp2-uart1-2pins { + blsp2_uart2_2pins_default: blsp2-uart1-2pins-state { pins = "gpio4", "gpio5"; function = "blsp_uart8"; drive-strength = <16>; bias-disable; }; - blsp2_uart2_2pins_sleep: blsp2-uart1-2pins-sleep { + blsp2_uart2_2pins_sleep: blsp2-uart1-2pins-sleep-state { pins = "gpio4", "gpio5"; function = "gpio"; drive-strength = <2>; bias-disable; }; - blsp2_i2c2_default: blsp2-i2c2 { + blsp2_i2c2_default: blsp2-i2c2-state { pins = "gpio6", "gpio7"; function = "blsp_i2c8"; drive-strength = <16>; bias-disable; }; - blsp2_i2c2_sleep: blsp2-i2c2-sleep { + blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { pins = "gpio6", "gpio7"; function = "gpio"; drive-strength = <2>; bias-disable; }; - cci0_default: cci0-default { + cci0_default: cci0-default-state { pins = "gpio17", "gpio18"; function = "cci_i2c"; drive-strength = <16>; @@ -1340,22 +1340,22 @@ cci0_default: cci0-default { }; camera0_state_on: - camera_rear_default: camera-rear-default { - camera0_mclk: mclk0 { + camera_rear_default: camera-rear-default-state { + camera0_mclk: mclk0-pins { pins = "gpio13"; function = "cam_mclk"; drive-strength = <16>; bias-disable; }; - camera0_rst: rst { + camera0_rst: rst-pins { pins = "gpio25"; function = "gpio"; drive-strength = <16>; bias-disable; }; - camera0_pwdn: pwdn { + camera0_pwdn: pwdn-pins { pins = "gpio26"; function = "gpio"; drive-strength = <16>; @@ -1363,7 +1363,7 @@ camera0_pwdn: pwdn { }; }; - cci1_default: cci1-default { + cci1_default: cci1-default-state { pins = "gpio19", "gpio20"; function = "cci_i2c"; drive-strength = <16>; @@ -1371,22 +1371,22 @@ cci1_default: cci1-default { }; camera1_state_on: - camera_board_default: camera-board-default { - mclk1 { + camera_board_default: camera-board-default-state { + mclk1-pins { pins = "gpio14"; function = "cam_mclk"; drive-strength = <16>; bias-disable; }; - pwdn { + pwdn-pins { pins = "gpio98"; function = "gpio"; drive-strength = <16>; bias-disable; }; - rst { + rst-pins { pins = "gpio104"; function = "gpio"; drive-strength = <16>; @@ -1395,22 +1395,22 @@ rst { }; camera2_state_on: - camera_front_default: camera-front-default { - camera2_mclk: mclk2 { + camera_front_default: camera-front-default-state { + camera2_mclk: mclk2-pins { pins = "gpio15"; function = "cam_mclk"; drive-strength = <16>; bias-disable; }; - camera2_rst: rst { + camera2_rst: rst-pins { pins = "gpio23"; function = "gpio"; drive-strength = <16>; bias-disable; }; - pwdn { + pwdn-pins { pins = "gpio133"; function = "gpio"; drive-strength = <16>; @@ -1418,22 +1418,22 @@ pwdn { }; }; - pcie0_state_on: pcie0-state-on { - perst { + pcie0_state_on: pcie0-state-on-state { + perst-pins { pins = "gpio35"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; - clkreq { + clkreq-pins { pins = "gpio36"; function = "pci_e0"; drive-strength = <2>; bias-pull-up; }; - wake { + wake-pins { pins = "gpio37"; function = "gpio"; drive-strength = <2>; @@ -1441,22 +1441,22 @@ wake { }; }; - pcie0_state_off: pcie0-state-off { - perst { + pcie0_state_off: pcie0-state-off-state { + perst-pins { pins = "gpio35"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; - clkreq { + clkreq-pins { pins = "gpio36"; function = "gpio"; drive-strength = <2>; bias-disable; }; - wake { + wake-pins { pins = "gpio37"; function = "gpio"; drive-strength = <2>; @@ -1464,63 +1464,63 @@ wake { }; }; - blsp1_uart2_default: blsp1-uart2-default { + blsp1_uart2_default: blsp1-uart2-default-state { pins = "gpio41", "gpio42", "gpio43", "gpio44"; function = "blsp_uart2"; drive-strength = <16>; bias-disable; }; - blsp1_uart2_sleep: blsp1-uart2-sleep { + blsp1_uart2_sleep: blsp1-uart2-sleep-state { pins = "gpio41", "gpio42", "gpio43", "gpio44"; function = "gpio"; drive-strength = <2>; bias-disable; }; - blsp1_i2c3_default: blsp1-i2c2-default { + blsp1_i2c3_default: blsp1-i2c2-default-state { pins = "gpio47", "gpio48"; function = "blsp_i2c3"; drive-strength = <16>; bias-disable; }; - blsp1_i2c3_sleep: blsp1-i2c2-sleep { + blsp1_i2c3_sleep: blsp1-i2c2-sleep-state { pins = "gpio47", "gpio48"; function = "gpio"; drive-strength = <2>; bias-disable; }; - blsp2_uart3_4pins_default: blsp2-uart2-4pins { + blsp2_uart3_4pins_default: blsp2-uart2-4pins-state { pins = "gpio49", "gpio50", "gpio51", "gpio52"; function = "blsp_uart9"; drive-strength = <16>; bias-disable; }; - blsp2_uart3_4pins_sleep: blsp2-uart2-4pins-sleep { + blsp2_uart3_4pins_sleep: blsp2-uart2-4pins-sleep-state { pins = "gpio49", "gpio50", "gpio51", "gpio52"; function = "blsp_uart9"; drive-strength = <2>; bias-disable; }; - blsp2_i2c3_default: blsp2-i2c3 { + blsp2_i2c3_default: blsp2-i2c3-state-state { pins = "gpio51", "gpio52"; function = "blsp_i2c9"; drive-strength = <16>; bias-disable; }; - blsp2_i2c3_sleep: blsp2-i2c3-sleep { + blsp2_i2c3_sleep: blsp2-i2c3-sleep-state { pins = "gpio51", "gpio52"; function = "gpio"; drive-strength = <2>; bias-disable; }; - wcd_intr_default: wcd-intr-default { + wcd_intr_default: wcd-intr-default-state { pins = "gpio54"; function = "gpio"; drive-strength = <2>; @@ -1528,21 +1528,21 @@ wcd_intr_default: wcd-intr-default { input-enable; }; - blsp2_i2c1_default: blsp2-i2c1 { + blsp2_i2c1_default: blsp2-i2c1-state { pins = "gpio55", "gpio56"; function = "blsp_i2c7"; drive-strength = <16>; bias-disable; }; - blsp2_i2c1_sleep: blsp2-i2c0-sleep { + blsp2_i2c1_sleep: blsp2-i2c0-sleep-state { pins = "gpio55", "gpio56"; function = "gpio"; drive-strength = <2>; bias-disable; }; - blsp2_i2c5_default: blsp2-i2c5 { + blsp2_i2c5_default: blsp2-i2c5-state { pins = "gpio60", "gpio61"; function = "blsp_i2c11"; drive-strength = <2>; @@ -1551,7 +1551,7 @@ blsp2_i2c5_default: blsp2-i2c5 { /* Sleep state for BLSP2_I2C5 is missing.. */ - cdc_reset_active: cdc-reset-active { + cdc_reset_active: cdc-reset-active-state { pins = "gpio64"; function = "gpio"; drive-strength = <16>; @@ -1559,7 +1559,7 @@ cdc_reset_active: cdc-reset-active { output-high; }; - cdc_reset_sleep: cdc-reset-sleep { + cdc_reset_sleep: cdc-reset-sleep-state { pins = "gpio64"; function = "gpio"; drive-strength = <16>; @@ -1567,15 +1567,15 @@ cdc_reset_sleep: cdc-reset-sleep { output-low; }; - blsp2_spi6_default: blsp2-spi5-default { - spi { + blsp2_spi6_default: blsp2-spi5-default-state { + spi-pins { pins = "gpio85", "gpio86", "gpio88"; function = "blsp_spi12"; drive-strength = <12>; bias-disable; }; - cs { + cs-pins { pins = "gpio87"; function = "gpio"; drive-strength = <16>; @@ -1584,43 +1584,43 @@ cs { }; }; - blsp2_spi6_sleep: blsp2-spi5-sleep { + blsp2_spi6_sleep: blsp2-spi5-sleep-state { pins = "gpio85", "gpio86", "gpio87", "gpio88"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; - blsp2_i2c6_default: blsp2-i2c6 { + blsp2_i2c6_default: blsp2-i2c6-state { pins = "gpio87", "gpio88"; function = "blsp_i2c12"; drive-strength = <16>; bias-disable; }; - blsp2_i2c6_sleep: blsp2-i2c6-sleep { + blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { pins = "gpio87", "gpio88"; function = "gpio"; drive-strength = <2>; bias-disable; }; - pcie1_state_on: pcie1-state-on { - perst { + pcie1_state_on: pcie1-on-state { + perst-pins { pins = "gpio130"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; - clkreq { + clkreq-pins { pins = "gpio131"; function = "pci_e1"; drive-strength = <2>; bias-pull-up; }; - wake { + wake-pins { pins = "gpio132"; function = "gpio"; drive-strength = <2>; @@ -1628,16 +1628,16 @@ wake { }; }; - pcie1_state_off: pcie1-state-off { + pcie1_state_off: pcie1-off-state { /* Perst is missing? */ - clkreq { + clkreq-pins { pins = "gpio131"; function = "gpio"; drive-strength = <2>; bias-disable; }; - wake { + wake-pins { pins = "gpio132"; function = "gpio"; drive-strength = <2>; @@ -1645,22 +1645,22 @@ wake { }; }; - pcie2_state_on: pcie2-state-on { - perst { + pcie2_state_on: pcie2-on-state { + perst-pins { pins = "gpio114"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; - clkreq { + clkreq-pins { pins = "gpio115"; function = "pci_e2"; drive-strength = <2>; bias-pull-up; }; - wake { + wake-pins { pins = "gpio116"; function = "gpio"; drive-strength = <2>; @@ -1668,16 +1668,16 @@ wake { }; }; - pcie2_state_off: pcie2-state-off { + pcie2_state_off: pcie2-off-state { /* Perst is missing? */ - clkreq { + clkreq-pins { pins = "gpio115"; function = "gpio"; drive-strength = <2>; bias-disable; }; - wake { + wake-pins { pins = "gpio116"; function = "gpio"; drive-strength = <2>; @@ -1685,90 +1685,90 @@ wake { }; }; - sdc1_state_on: sdc1-state-on { - clk { + sdc1_state_on: sdc1-on-state { + clk-pins { pins = "sdc1_clk"; bias-disable; drive-strength = <16>; }; - cmd { + cmd-pins { pins = "sdc1_cmd"; bias-pull-up; drive-strength = <10>; }; - data { + data-pins { pins = "sdc1_data"; bias-pull-up; drive-strength = <10>; }; - rclk { + rclk-pins { pins = "sdc1_rclk"; bias-pull-down; }; }; - sdc1_state_off: sdc1-state-off { - clk { + sdc1_state_off: sdc1-off-state { + clk-pins { pins = "sdc1_clk"; bias-disable; drive-strength = <2>; }; - cmd { + cmd-pins { pins = "sdc1_cmd"; bias-pull-up; drive-strength = <2>; }; - data { + data-pins { pins = "sdc1_data"; bias-pull-up; drive-strength = <2>; }; - rclk { + rclk-pins { pins = "sdc1_rclk"; bias-pull-down; }; }; - sdc2_state_on: sdc2-clk-on { - clk { + sdc2_state_on: sdc2-on-state { + clk-pins { pins = "sdc2_clk"; bias-disable; drive-strength = <16>; }; - cmd { + cmd-pins { pins = "sdc2_cmd"; bias-pull-up; drive-strength = <10>; }; - data { + data-pins { pins = "sdc2_data"; bias-pull-up; drive-strength = <10>; }; }; - sdc2_state_off: sdc2-clk-off { - clk { + sdc2_state_off: sdc2-off-state { + clk-pins { pins = "sdc2_clk"; bias-disable; drive-strength = <2>; }; - cmd { + cmd-pins { pins = "sdc2_cmd"; bias-pull-up; drive-strength = <2>; }; - data { + data-pins { pins = "sdc2_data"; bias-pull-up; drive-strength = <2>; diff --git a/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts b/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts index b18ee5c1f678..d18d0b0eda95 100644 --- a/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts +++ b/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts @@ -399,14 +399,14 @@ &tlmm { "RFFE1_DATA", /* GPIO_148 */ "RFFE1_CLK"; /* GPIO_149 */ - touchscreen_default: touchscreen-default { + touchscreen_default: touchscreen-default-state { pins = "gpio89", "gpio125"; function = "gpio"; drive-strength = <10>; bias-pull-up; }; - touchscreen_sleep: touchscreen-sleep { + touchscreen_sleep: touchscreen-sleep-state { pins = "gpio89", "gpio125"; function = "gpio"; drive-strength = <2>; diff --git a/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-scorpio.dts b/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-scorpio.dts index 7bf6ad1a214b..5e3b9130e9c2 100644 --- a/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-scorpio.dts +++ b/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-scorpio.dts @@ -469,28 +469,28 @@ &tlmm { "RFFE1_DATA", /* GPIO_148 */ "RFFE1_CLK"; /* GPIO_149 */ - touchkey_default: touchkey_default { + touchkey_default: touchkey-default-state { pins = "gpio77"; function = "gpio"; drive-strength = <16>; bias-pull-up; }; - touchkey_sleep: touchkey_sleep { + touchkey_sleep: touchkey-sleep-state { pins = "gpio77"; function = "gpio"; drive-strength = <2>; bias-disable; }; - touchscreen_default: touchscreen_default { + touchscreen_default: touchscreen-default-state { pins = "gpio75", "gpio125"; function = "gpio"; drive-strength = <10>; bias-pull-up; }; - touchscreen_sleep: touchscreen_sleep { + touchscreen_sleep: touchscreen-sleep-state { pins = "gpio75", "gpio125"; function = "gpio"; drive-strength = <2>; From 1a94ba5b44c5448c7ec962a5ce66eb12a6042288 Mon Sep 17 00:00:00 2001 From: Harry Austen Date: Sun, 23 Oct 2022 20:45:27 +0000 Subject: [PATCH 148/261] arm64: dts: qcom: msm8996: standardize blsp indexing Use one-based indexing throughout the file for BLSP devices to avoid confusion. Most of the node names and labels are consistent already. This patch just fixes a few pinconf node names to match the one-based indexing used in the label names. Signed-off-by: Harry Austen Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221023204505.115141-2-hpausten@protonmail.com --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index b7e4fbf5744d..fdaaef7aae12 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1304,14 +1304,14 @@ blsp1_spi1_sleep: blsp1-spi1-sleep-state { bias-pull-down; }; - blsp2_uart2_2pins_default: blsp2-uart1-2pins-state { + blsp2_uart2_2pins_default: blsp2-uart2-2pins-state { pins = "gpio4", "gpio5"; function = "blsp_uart8"; drive-strength = <16>; bias-disable; }; - blsp2_uart2_2pins_sleep: blsp2-uart1-2pins-sleep-state { + blsp2_uart2_2pins_sleep: blsp2-uart2-2pins-sleep-state { pins = "gpio4", "gpio5"; function = "gpio"; drive-strength = <2>; @@ -1478,28 +1478,28 @@ blsp1_uart2_sleep: blsp1-uart2-sleep-state { bias-disable; }; - blsp1_i2c3_default: blsp1-i2c2-default-state { + blsp1_i2c3_default: blsp1-i2c3-default-state { pins = "gpio47", "gpio48"; function = "blsp_i2c3"; drive-strength = <16>; bias-disable; }; - blsp1_i2c3_sleep: blsp1-i2c2-sleep-state { + blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { pins = "gpio47", "gpio48"; function = "gpio"; drive-strength = <2>; bias-disable; }; - blsp2_uart3_4pins_default: blsp2-uart2-4pins-state { + blsp2_uart3_4pins_default: blsp2-uart3-4pins-state { pins = "gpio49", "gpio50", "gpio51", "gpio52"; function = "blsp_uart9"; drive-strength = <16>; bias-disable; }; - blsp2_uart3_4pins_sleep: blsp2-uart2-4pins-sleep-state { + blsp2_uart3_4pins_sleep: blsp2-uart3-4pins-sleep-state { pins = "gpio49", "gpio50", "gpio51", "gpio52"; function = "blsp_uart9"; drive-strength = <2>; @@ -1535,7 +1535,7 @@ blsp2_i2c1_default: blsp2-i2c1-state { bias-disable; }; - blsp2_i2c1_sleep: blsp2-i2c0-sleep-state { + blsp2_i2c1_sleep: blsp2-i2c1-sleep-state { pins = "gpio55", "gpio56"; function = "gpio"; drive-strength = <2>; @@ -1567,7 +1567,7 @@ cdc_reset_sleep: cdc-reset-sleep-state { output-low; }; - blsp2_spi6_default: blsp2-spi5-default-state { + blsp2_spi6_default: blsp2-spi6-default-state { spi-pins { pins = "gpio85", "gpio86", "gpio88"; function = "blsp_spi12"; @@ -1584,7 +1584,7 @@ cs-pins { }; }; - blsp2_spi6_sleep: blsp2-spi5-sleep-state { + blsp2_spi6_sleep: blsp2-spi6-sleep-state { pins = "gpio85", "gpio86", "gpio87", "gpio88"; function = "gpio"; drive-strength = <2>; From 18c32de673bf3ade651979be48e9a14bfe612487 Mon Sep 17 00:00:00 2001 From: Harry Austen Date: Sun, 23 Oct 2022 20:45:38 +0000 Subject: [PATCH 149/261] arm64: dts: qcom: msm8996: add blsp1_i2c6 node Add support for the sixth I2C interface on the MSM8996 SoC. Signed-off-by: Harry Austen Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221023204505.115141-3-hpausten@protonmail.com --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 31 +++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index fdaaef7aae12..de2af2b23d7b 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1332,6 +1332,20 @@ blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { bias-disable; }; + blsp1_i2c6_default: blsp1-i2c6-state { + pins = "gpio27", "gpio28"; + function = "blsp_i2c6"; + drive-strength = <16>; + bias-disable; + }; + + blsp1_i2c6_sleep: blsp1-i2c6-sleep-state { + pins = "gpio27", "gpio28"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + cci0_default: cci0-default-state { pins = "gpio17", "gpio18"; function = "cci_i2c"; @@ -3141,6 +3155,23 @@ blsp1_i2c3: i2c@7577000 { status = "disabled"; }; + blsp1_i2c6: i2c@757a000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x757a000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_i2c6_default>; + pinctrl-1 = <&blsp1_i2c6_sleep>; + dmas = <&blsp1_dma 22>, <&blsp1_dma 23>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + blsp2_dma: dma-controller@7584000 { compatible = "qcom,bam-v1.7.0"; reg = <0x07584000 0x2b000>; From ce5d6ba21ae6c83fc2db385f9202272ca0d403f2 Mon Sep 17 00:00:00 2001 From: Harry Austen Date: Sun, 23 Oct 2022 20:45:49 +0000 Subject: [PATCH 150/261] dt-bindings: arm: qcom: add oneplus3(t) devices Add compatible strings for the OnePlus 3 and 3T phones which utilise the Qualcomm MSM8996 SoC. Signed-off-by: Harry Austen Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221023204505.115141-4-hpausten@protonmail.com --- Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 5148c4916bc1..5facc588f7a6 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -223,6 +223,8 @@ properties: - items: - enum: + - oneplus,oneplus3 + - oneplus,oneplus3t - qcom,msm8996-mtp - sony,dora-row - sony,kagura-row From 5a134c940cd368b72d5bcf24132b8f951be9a4c1 Mon Sep 17 00:00:00 2001 From: Harry Austen Date: Sun, 23 Oct 2022 20:46:00 +0000 Subject: [PATCH 151/261] arm64: dts: qcom: msm8996: add support for oneplus3(t) Add initial support for OnePlus 3 and 3T mobile phones. They are based on the MSM8996 SoC. Co-developed-by: Yassine Oudjana Signed-off-by: Yassine Oudjana Signed-off-by: Harry Austen Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221023204505.115141-5-hpausten@protonmail.com --- arch/arm64/boot/dts/qcom/Makefile | 2 + .../boot/dts/qcom/msm8996-oneplus-common.dtsi | 787 ++++++++++++++++++ arch/arm64/boot/dts/qcom/msm8996-oneplus3.dts | 44 + .../arm64/boot/dts/qcom/msm8996-oneplus3t.dts | 45 + 4 files changed, 878 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi create mode 100644 arch/arm64/boot/dts/qcom/msm8996-oneplus3.dts create mode 100644 arch/arm64/boot/dts/qcom/msm8996-oneplus3t.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 500e06c3d6d3..4dff39f98861 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -33,6 +33,8 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-satsuki.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-sumire.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-suzuran.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8996-oneplus3.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8996-oneplus3t.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-dora.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-kagura.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-keyaki.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi new file mode 100644 index 000000000000..20f5c103c63b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi @@ -0,0 +1,787 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022, Harry Austen + */ + +#include "msm8996.dtsi" +#include "pm8994.dtsi" +#include "pmi8994.dtsi" +#include "pmi8996.dtsi" +#include +#include +#include +#include +#include + +/ { + aliases { + serial0 = &blsp1_uart2; + serial1 = &blsp2_uart2; + }; + + battery: battery { + compatible = "simple-battery"; + + constant-charge-current-max-microamp = <3000000>; + voltage-min-design-microvolt = <3400000>; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + clocks { + div1_mclk: div1-clk { + compatible = "gpio-gate-clock"; + pinctrl-names = "default"; + pinctrl-0 = <&audio_mclk>; + #clock-cells = <0>; + clocks = <&rpmcc RPM_SMD_DIV_CLK1>; + enable-gpios = <&pm8994_gpios 15 GPIO_ACTIVE_HIGH>; + }; + + divclk4: div4-clk { + compatible = "fixed-clock"; + pinctrl-names = "default"; + pinctrl-0 = <&divclk4_pin_a>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "divclk4"; + }; + }; + + reserved-memory { + ramoops@ac000000 { + compatible = "ramoops"; + reg = <0 0xac000000 0 0x200000>; + record-size = <0x20000>; + console-size = <0x100000>; + pmsg-size = <0x80000>; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + regulator-boot-on; + }; + + wlan_en: wlan-en-regulator { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_en_gpios>; + regulator-name = "wlan-en-regulator"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&pm8994_gpios 8 GPIO_ACTIVE_HIGH>; + + /* WLAN card specific delay */ + startup-delay-us = <70000>; + enable-active-high; + }; +}; + +&adsp_pil { + status = "okay"; +}; + +&blsp1_i2c3 { + status = "okay"; + + tfa9890_amp: audio-codec@36 { + compatible = "nxp,tfa9890"; + reg = <0x36>; + #sound-dai-cells = <0>; + }; +}; + +&blsp1_i2c6 { + status = "okay"; + + bq27541: fuel-gauge@55 { + compatible = "ti,bq27541"; + reg = <0x55>; + }; +}; + +&blsp1_uart2 { + label = "BT-UART"; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "qcom,qca6174-bt"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_en_gpios>; + enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>; + clocks = <&divclk4>; + }; +}; + +&blsp2_i2c1 { + status = "okay"; +}; + +&blsp2_i2c6 { + status = "okay"; + + synaptics_rmi4_i2c: touchscreen@20 { + compatible = "syna,rmi4-i2c"; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&touch_default>; + pinctrl-1 = <&touch_suspend>; + vdd-supply = <&vreg_l22a_3p0>; + vio-supply = <&vreg_s4a_1p8>; + syna,reset-delay-ms = <200>; + syna,startup-delay-ms = <200>; + + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <1>; + }; + + rmi4-f12@12 { + reg = <0x12>; + syna,sensor-type = <1>; + touchscreen-x-mm = <68>; + touchscreen-y-mm = <122>; + }; + }; +}; + +&blsp2_uart2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_uart2_2pins_default>; + pinctrl-1 = <&blsp2_uart2_2pins_sleep>; + status = "okay"; +}; + +&camss { + vdda-supply = <&vreg_l2a_1p25>; +}; + +&dsi0 { + vdda-supply = <&vreg_l2a_1p25>; + vcca-supply = <&vreg_l22a_3p0>; + status = "okay"; +}; + +&dsi0_out { + data-lanes = <0 1 2 3>; +}; + +&dsi0_phy { + vdda-supply = <&vreg_l2a_1p25>; + vcca-supply = <&vreg_l28a_0p925>; + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&hsusb_phy1 { + vdd-supply = <&vreg_l28a_0p925>; + vdda-pll-supply = <&vreg_l12a_1p8>; + vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; + status = "okay"; +}; + +&hsusb_phy2 { + vdd-supply = <&vreg_l28a_0p925>; + vdda-pll-supply = <&vreg_l12a_1p8>; + vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; + status = "okay"; +}; + +&mdp { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mmcc { + vdd-gfx-supply = <&vdd_gfx>; +}; + +&mss_pil { + pll-supply = <&vreg_l12a_1p8>; + status = "okay"; +}; + +&pcie0 { + perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; + vddpe-3v3-supply = <&wlan_en>; + vdda-supply = <&vreg_l28a_0p925>; + status = "okay"; +}; + +&pcie_phy { + vdda-phy-supply = <&vreg_l28a_0p925>; + vdda-pll-supply = <&vreg_l12a_1p8>; + status = "okay"; +}; + +&pm8994_gpios { + bt_en_gpios: bt-en-gpios-state { + pins = "gpio19"; + function = PMIC_GPIO_FUNC_NORMAL; + output-low; + power-source = ; + qcom,drive-strength = ; + bias-pull-down; + }; + + wlan_en_gpios: wlan-en-gpios-state { + pins = "gpio8"; + function = PMIC_GPIO_FUNC_NORMAL; + output-low; + power-source = ; + qcom,drive-strength = ; + bias-pull-down; + }; + + audio_mclk: divclk1-state { + pins = "gpio15"; + function = PMIC_GPIO_FUNC_FUNC1; + power-source = ; + }; + + divclk4_pin_a: divclk4-state { + pins = "gpio18"; + function = PMIC_GPIO_FUNC_FUNC2; + bias-disable; + power-source = ; + }; +}; + +&pm8994_spmi_regulators { + qcom,saw-reg = <&saw3>; + + s9 { + qcom,saw-slave; + }; + + s10 { + qcom,saw-slave; + }; + + s11 { + qcom,saw-leader; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1140000>; + regulator-max-step-microvolt = <150000>; + regulator-always-on; + }; +}; + +&pmi8994_spmi_regulators { + vdd_gfx: s2 { + regulator-name = "vdd-gfx"; + regulator-min-microvolt = <980000>; + regulator-max-microvolt = <1230000>; + }; +}; + +&q6asmdai { + #address-cells = <1>; + #size-cells = <0>; + + dai@0 { + reg = <0>; + }; + + dai@1 { + reg = <1>; + }; + + dai@2 { + reg = <2>; + }; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm8994-regulators"; + + vreg_s3a_1p3: s3 { + regulator-name = "vreg_s3a_1p3"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + vreg_s4a_1p8: s4 { + regulator-name = "vreg_s4a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vreg_s5a_2p15: s5 { + regulator-name = "vreg_s5a_2p15"; + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + }; + + vreg_s7a_0p8: s7 { + regulator-name = "vreg_s7a_0p8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + }; + + vreg_l1a_1p0: l1 { + regulator-name = "vreg_l1a_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + vreg_l2a_1p25: l2 { + regulator-name = "vreg_l2a_1p25"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-allow-set-load; + }; + + vreg_l3a_1p1: l3 { + regulator-name = "vreg_l3a_1p1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + vreg_l4a_1p225: l4 { + regulator-name = "vreg_l4a_1p225"; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + vreg_l6a_1p2: l6 { + regulator-name = "vreg_l6a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_l7a_1p8: l7 { + regulator-name = "vreg_l7a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_l9a_1p8: l9 { + regulator-name = "vreg_l9a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_l10a_1p8: l10 { + regulator-name = "vreg_l10a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_l11a_1p15: l11 { + regulator-name = "vreg_l11a_1p15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + }; + + vreg_l12a_1p8: l12 { + regulator-name = "vreg_l12a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allow-set-load; + }; + + vreg_l13a_2p95: l13 { + regulator-name = "vreg_l13a_2p95"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + vreg_l16a_2p7: l16 { + regulator-name = "vreg_l16a_2p7"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + vreg_l17a_2p6: l17 { + regulator-name = "vreg_l17a_2p6"; + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <2600000>; + }; + + vreg_l18a_3p3: l18 { + regulator-name = "vreg_l18a_3p3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vreg_l19a_3p0: l19 { + regulator-name = "vreg_l19a_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + vreg_l20a_2p95: l20 { + regulator-name = "vreg_l20a_2p95"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + }; + + vreg_l21a_2p95: l21 { + regulator-name = "vreg_l21a_2p95"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + regulator-system-load = <200000>; + }; + + vreg_l22a_3p0: l22 { + regulator-name = "vreg_l22a_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + vreg_l23a_2p8: l23 { + regulator-name = "vreg_l23a_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + vreg_l24a_3p075: l24 { + regulator-name = "vreg_l24a_3p075"; + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + vreg_l25a_1p2: l25 { + regulator-name = "vreg_l25a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-allow-set-load; + regulator-always-on; + }; + + vreg_l27a_1p2: l27 { + regulator-name = "vreg_l27a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_l28a_0p925: l28 { + regulator-name = "vreg_l28a_0p925"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <925000>; + regulator-allow-set-load; + }; + + vreg_l29a_2p8: l29 { + regulator-name = "vreg_l29a_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + vreg_l30a_1p8: l30 { + regulator-name = "vreg_l30a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_l32a_1p8: l32 { + regulator-name = "vreg_l32a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; +}; + +&slpi_pil { + status = "okay"; +}; + +&sound { + compatible = "qcom,apq8096-sndcard"; + model = "OnePlus3"; + audio-routing = "RX_BIAS", "MCLK", + "AMIC2", "MIC BIAS2", + "MIC BIAS2", "Headset Mic", + "AMIC4", "MIC BIAS1", + "MIC BIAS1", "Primary Mic", + "AMIC5", "MIC BIAS3", + "MIC BIAS3", "Noise Mic"; + + mm1-dai-link { + link-name = "MultiMedia1"; + + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; + }; + }; + + mm2-dai-link { + link-name = "MultiMedia2"; + + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; + }; + }; + + mm3-dai-link { + link-name = "MultiMedia3"; + + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; + }; + }; + + mm4-dai-link { + link-name = "MultiMedia4"; + + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA4>; + }; + }; + + mm5-dai-link { + link-name = "MultiMedia5"; + + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA5>; + }; + }; + + mm6-dai-link { + link-name = "MultiMedia6"; + + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA6>; + }; + }; + + mm7-dai-link { + link-name = "MultiMedia7"; + + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA7>; + }; + }; + + mm8-dai-link { + link-name = "MultiMedia8"; + + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA8>; + }; + }; + + mm9-dai-link { + link-name = "MultiMedia9"; + + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA9>; + }; + }; + + mm10-dai-link { + link-name = "MultiMedia10"; + + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA10>; + }; + }; + + mm11-dai-link { + link-name = "MultiMedia11"; + + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA11>; + }; + }; + + mm12-dai-link { + link-name = "MultiMedia12"; + + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA12>; + }; + }; + + mm13-dai-link { + link-name = "MultiMedia13"; + + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA13>; + }; + }; + + mm14-dai-link { + link-name = "MultiMedia14"; + + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA14>; + }; + }; + + mm15-dai-link { + link-name = "MultiMedia15"; + + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA15>; + }; + }; + + mm16-dai-link { + link-name = "MultiMedia16"; + + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA16>; + }; + }; + + slim-dai-link { + link-name = "SLIM Playback"; + + cpu { + sound-dai = <&q6afedai SLIMBUS_6_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&wcd9335 AIF4_PB>; + }; + }; + + slimcap-dai-link { + link-name = "SLIM Capture"; + + cpu { + sound-dai = <&q6afedai SLIMBUS_0_TX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&wcd9335 AIF1_CAP>; + }; + }; + + speaker-dai-link { + link-name = "Speaker"; + + cpu { + sound-dai = <&q6afedai QUATERNARY_MI2S_RX>; + }; + + codec { + sound-dai = <&tfa9890_amp>; + }; + }; +}; + +&tlmm { + gpio-reserved-ranges = <81 4>; + + mdss_dsi_active: mdss-dsi-active-state { + pins = "gpio8"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + mdss_dsi_suspend: mdss-dsi-suspend-state { + pins = "gpio8"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + mdss_te_active: mdss-te-active-state { + pins = "gpio10"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + mdss_te_suspend: mdss-te-suspend-state { + pins = "gpio10"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + touch_default: touch-default-state { + pins = "gpio89", "gpio125", "gpio49"; + function = "gpio"; + drive-strength = <16>; + bias-pull-up; + }; + + touch_suspend: touch-suspend-state { + pins = "gpio89", "gpio125", "gpio49"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&ufsphy { + vdda-phy-supply = <&vreg_l28a_0p925>; + vdda-pll-supply = <&vreg_l12a_1p8>; + vddp-ref-clk-supply = <&vreg_l25a_1p2>; + + status = "okay"; +}; + +&ufshc { + vcc-supply = <&vreg_l20a_2p95>; + vccq-supply = <&vreg_l25a_1p2>; + vccq2-supply = <&vreg_s4a_1p8>; + + vcc-max-microamp = <600000>; + vccq-max-microamp = <450000>; + vccq2-max-microamp = <450000>; + + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + phys = <&hsusb_phy1>; + phy-names = "usb2-phy"; + + maximum-speed = "high-speed"; +}; + +&venus { + status = "okay"; +}; + +&wcd9335 { + clock-names = "mclk", "slimbus"; + clocks = <&div1_mclk>, + <&rpmcc RPM_SMD_BB_CLK1>; + + vdd-buck-supply = <&vreg_s4a_1p8>; + vdd-buck-sido-supply = <&vreg_s4a_1p8>; + vdd-tx-supply = <&vreg_s4a_1p8>; + vdd-rx-supply = <&vreg_s4a_1p8>; + vdd-io-supply = <&vreg_s4a_1p8>; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8996-oneplus3.dts b/arch/arm64/boot/dts/qcom/msm8996-oneplus3.dts new file mode 100644 index 000000000000..1bdc1b134305 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8996-oneplus3.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022, Harry Austen + */ + +/dts-v1/; + +#include "msm8996-oneplus-common.dtsi" + +/ { + model = "OnePlus 3"; + compatible = "oneplus,oneplus3", "qcom,msm8996"; + chassis-type = "handset"; + qcom,board-id = <8 0 15801 15>, <8 0 15801 16>; + qcom,msm-id = <246 0x30001>; +}; + +&adsp_pil { + firmware-name = "qcom/msm8996/oneplus3/adsp.mbn"; +}; + +&battery { + charge-full-design-microamp-hours = <3000000>; + voltage-max-design-microvolt = <4350000>; +}; + +&gpu { + zap-shader { + firmware-name = "qcom/msm8996/oneplus3/a530_zap.mbn"; + }; +}; + +&mss_pil { + firmware-name = "qcom/msm8996/oneplus3/mba.mbn", + "qcom/msm8996/oneplus3/modem.mbn"; +}; + +&slpi_pil { + firmware-name = "qcom/msm8996/oneplus3/slpi.mbn"; +}; + +&venus { + firmware-name = "qcom/msm8996/oneplus3/venus.mbn"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8996-oneplus3t.dts b/arch/arm64/boot/dts/qcom/msm8996-oneplus3t.dts new file mode 100644 index 000000000000..34f837dd0c12 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8996-oneplus3t.dts @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022, Harry Austen + */ + +/dts-v1/; + +#include "msm8996-oneplus-common.dtsi" + +/ { + model = "OnePlus 3T"; + compatible = "oneplus,oneplus3t", "qcom,msm8996"; + chassis-type = "handset"; + qcom,board-id = <8 0 15811 26>, + <8 0 15811 27>, + <8 0 15811 28>; +}; + +&adsp_pil { + firmware-name = "qcom/msm8996/oneplus3t/adsp.mbn"; +}; + +&battery { + charge-full-design-microamp-hours = <3400000>; + voltage-max-design-microvolt = <4400000>; +}; + +&gpu { + zap-shader { + firmware-name = "qcom/msm8996/oneplus3t/a530_zap.mbn"; + }; +}; + +&mss_pil { + firmware-name = "qcom/msm8996/oneplus3t/mba.mbn", + "qcom/msm8996/oneplus3t/modem.mbn"; +}; + +&slpi_pil { + firmware-name = "qcom/msm8996/oneplus3t/slpi.mbn"; +}; + +&venus { + firmware-name = "qcom/msm8996/oneplus3t/venus.mbn"; +}; From 8b276ca036377a5baa4fd0692b80608f0de8a260 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 23 Oct 2022 20:23:56 -0400 Subject: [PATCH 152/261] arm64: dts: qcom: msm8916: align TLMM pin configuration with DT schema DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Reviewed-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221024002356.28261-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 14 +- .../boot/dts/qcom/msm8916-alcatel-idol347.dts | 14 +- .../arm64/boot/dts/qcom/msm8916-asus-z00l.dts | 24 +- .../arm64/boot/dts/qcom/msm8916-huawei-g7.dts | 20 +- .../boot/dts/qcom/msm8916-longcheer-l8150.dts | 16 +- .../boot/dts/qcom/msm8916-longcheer-l8910.dts | 8 +- arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 276 +++++++++--------- .../qcom/msm8916-samsung-a2015-common.dtsi | 64 ++-- .../boot/dts/qcom/msm8916-samsung-a3u-eur.dts | 6 +- .../boot/dts/qcom/msm8916-samsung-a5u-eur.dts | 2 +- .../qcom/msm8916-samsung-e2015-common.dtsi | 2 +- .../dts/qcom/msm8916-samsung-grandmax.dts | 2 +- .../boot/dts/qcom/msm8916-samsung-j5.dts | 2 +- .../dts/qcom/msm8916-samsung-serranove.dts | 41 +-- .../dts/qcom/msm8916-wingtech-wt88047.dts | 21 +- 15 files changed, 260 insertions(+), 252 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index 1b613098fb4a..9ebc506810f6 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -718,14 +718,14 @@ &msmgpio { "USR_LED_2_CTRL", /* GPIO 120 */ "SB_HS_ID"; - msmgpio_leds: msmgpio-leds { + msmgpio_leds: msmgpio-leds-state { pins = "gpio21", "gpio120"; function = "gpio"; output-low; }; - usb_id_default: usb-id-default { + usb_id_default: usb-id-default-state { pins = "gpio121"; function = "gpio"; @@ -734,7 +734,7 @@ usb_id_default: usb-id-default { bias-pull-up; }; - adv7533_int_active: adv533-int-active { + adv7533_int_active: adv533-int-active-state { pins = "gpio31"; function = "gpio"; @@ -742,7 +742,7 @@ adv7533_int_active: adv533-int-active { bias-disable; }; - adv7533_int_suspend: adv7533-int-suspend { + adv7533_int_suspend: adv7533-int-suspend-state { pins = "gpio31"; function = "gpio"; @@ -750,7 +750,7 @@ adv7533_int_suspend: adv7533-int-suspend { bias-disable; }; - adv7533_switch_active: adv7533-switch-active { + adv7533_switch_active: adv7533-switch-active-state { pins = "gpio32"; function = "gpio"; @@ -758,7 +758,7 @@ adv7533_switch_active: adv7533-switch-active { bias-disable; }; - adv7533_switch_suspend: adv7533-switch-suspend { + adv7533_switch_suspend: adv7533-switch-suspend-state { pins = "gpio32"; function = "gpio"; @@ -766,7 +766,7 @@ adv7533_switch_suspend: adv7533-switch-suspend { bias-disable; }; - msm_key_volp_n_default: msm-key-volp-n-default { + msm_key_volp_n_default: msm-key-volp-n-default-state { pins = "gpio107"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts index 3dc9619fde6e..668f8ff53229 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts @@ -260,7 +260,7 @@ l18 { }; &msmgpio { - accel_int_default: accel-int-default { + accel_int_default: accel-int-default-state { pins = "gpio31"; function = "gpio"; @@ -268,7 +268,7 @@ accel_int_default: accel-int-default { bias-disable; }; - gpio_keys_default: gpio-keys-default { + gpio_keys_default: gpio-keys-default-state { pins = "gpio107"; function = "gpio"; @@ -276,7 +276,7 @@ gpio_keys_default: gpio-keys-default { bias-pull-up; }; - gyro_int_default: gyro-int-default { + gyro_int_default: gyro-int-default-state { pins = "gpio97", "gpio98"; function = "gpio"; @@ -284,7 +284,7 @@ gyro_int_default: gyro-int-default { bias-disable; }; - mag_reset_default: mag-reset-default { + mag_reset_default: mag-reset-default-state { pins = "gpio8"; function = "gpio"; @@ -292,7 +292,7 @@ mag_reset_default: mag-reset-default { bias-disable; }; - proximity_int_default: proximity-int-default { + proximity_int_default: proximity-int-default-state { pins = "gpio12"; function = "gpio"; @@ -300,7 +300,7 @@ proximity_int_default: proximity-int-default { bias-pull-up; }; - ts_int_reset_default: ts-int-reset-default { + ts_int_reset_default: ts-int-reset-default-state { pins = "gpio13", "gpio100"; function = "gpio"; @@ -308,7 +308,7 @@ ts_int_reset_default: ts-int-reset-default { bias-disable; }; - usb_id_default: usb-id-default { + usb_id_default: usb-id-default-state { pins = "gpio69"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts b/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts index dd92070a1211..3618704a5330 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts @@ -263,7 +263,7 @@ l18 { }; &msmgpio { - gpio_keys_default: gpio-keys-default { + gpio_keys_default: gpio-keys-default-state { pins = "gpio107", "gpio117"; function = "gpio"; @@ -271,7 +271,7 @@ gpio_keys_default: gpio-keys-default { bias-pull-up; }; - imu_default: imu-default { + imu_default: imu-default-state { pins = "gpio36"; function = "gpio"; @@ -279,7 +279,7 @@ imu_default: imu-default { bias-disable; }; - mag_reset_default: mag-reset-default { + mag_reset_default: mag-reset-default-state { pins = "gpio112"; function = "gpio"; @@ -287,7 +287,7 @@ mag_reset_default: mag-reset-default { bias-disable; }; - sd_vmmc_en_default: sd-vmmc-en-default { + sd_vmmc_en_default: sd-vmmc-en-default-state { pins = "gpio87"; function = "gpio"; @@ -295,14 +295,16 @@ sd_vmmc_en_default: sd-vmmc-en-default { bias-disable; }; - touchscreen_default: touchscreen-default { - pins = "gpio13"; - function = "gpio"; + touchscreen_default: touchscreen-default-state { + touch-pins { + pins = "gpio13"; + function = "gpio"; - drive-strength = <2>; - bias-pull-up; + drive-strength = <2>; + bias-pull-up; + }; - reset { + reset-pins { pins = "gpio12"; function = "gpio"; @@ -311,7 +313,7 @@ reset { }; }; - usb_id_default: usb-id-default { + usb_id_default: usb-id-default-state { pins = "gpio110"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts index 9e470c67274e..a6a7d870f586 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts @@ -414,7 +414,7 @@ l18 { }; &msmgpio { - accel_irq_default: accel-irq-default { + accel_irq_default: accel-irq-default-state { pins = "gpio115"; function = "gpio"; @@ -422,7 +422,7 @@ accel_irq_default: accel-irq-default { bias-disable; }; - gpio_keys_default: gpio-keys-default { + gpio_keys_default: gpio-keys-default-state { pins = "gpio107"; function = "gpio"; @@ -430,7 +430,7 @@ gpio_keys_default: gpio-keys-default { bias-pull-up; }; - gpio_leds_default: gpio-leds-default { + gpio_leds_default: gpio-leds-default-state { pins = "gpio8", "gpio9", "gpio10"; function = "gpio"; @@ -438,7 +438,7 @@ gpio_leds_default: gpio-leds-default { bias-disable; }; - nfc_default: nfc-default { + nfc_default: nfc-default-state { pins = "gpio2", "gpio20", "gpio21"; function = "gpio"; @@ -446,7 +446,7 @@ nfc_default: nfc-default { bias-disable; }; - mag_reset_default: mag-reset-default { + mag_reset_default: mag-reset-default-state { pins = "gpio36"; function = "gpio"; @@ -454,7 +454,7 @@ mag_reset_default: mag-reset-default { bias-disable; }; - prox_irq_default: prox-irq-default { + prox_irq_default: prox-irq-default-state { pins = "gpio113"; function = "gpio"; @@ -462,7 +462,7 @@ prox_irq_default: prox-irq-default { bias-disable; }; - reg_lcd_en_default: reg-lcd-en-default { + reg_lcd_en_default: reg-lcd-en-default-state { pins = "gpio32", "gpio97"; function = "gpio"; @@ -470,7 +470,7 @@ reg_lcd_en_default: reg-lcd-en-default { bias-disable; }; - sdhc2_cd_default: sdhc2-cd-default { + sdhc2_cd_default: sdhc2-cd-default-state { pins = "gpio56"; function = "gpio"; @@ -478,7 +478,7 @@ sdhc2_cd_default: sdhc2-cd-default { bias-disable; }; - ts_irq_default: ts-irq-default { + ts_irq_default: ts-irq-default-state { pins = "gpio13"; function = "gpio"; @@ -486,7 +486,7 @@ ts_irq_default: ts-irq-default { bias-disable; }; - usb_id_default: usb-id-default { + usb_id_default: usb-id-default-state { pins = "gpio117"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index d85e7f7c0835..31214570be4b 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -367,7 +367,7 @@ l18 { }; &msmgpio { - accel_int_default: accel-int-default { + accel_int_default: accel-int-default-state { pins = "gpio116"; function = "gpio"; @@ -375,7 +375,7 @@ accel_int_default: accel-int-default { bias-disable; }; - camera_flash_default: camera-flash-default { + camera_flash_default: camera-flash-default-state { pins = "gpio31", "gpio32"; function = "gpio"; @@ -383,7 +383,7 @@ camera_flash_default: camera-flash-default { bias-disable; }; - ctp_pwr_en_default: ctp-pwr-en-default { + ctp_pwr_en_default: ctp-pwr-en-default-state { pins = "gpio17"; function = "gpio"; @@ -391,7 +391,7 @@ ctp_pwr_en_default: ctp-pwr-en-default { bias-disable; }; - gpio_keys_default: gpio-keys-default { + gpio_keys_default: gpio-keys-default-state { pins = "gpio107"; function = "gpio"; @@ -399,7 +399,7 @@ gpio_keys_default: gpio-keys-default { bias-pull-up; }; - gyro_int_default: gyro-int-default { + gyro_int_default: gyro-int-default-state { pins = "gpio22", "gpio23"; function = "gpio"; @@ -407,7 +407,7 @@ gyro_int_default: gyro-int-default { bias-disable; }; - light_int_default: light-int-default { + light_int_default: light-int-default-state { pins = "gpio115"; function = "gpio"; @@ -415,7 +415,7 @@ light_int_default: light-int-default { bias-disable; }; - magn_int_default: magn-int-default { + magn_int_default: magn-int-default-state { pins = "gpio113"; function = "gpio"; @@ -423,7 +423,7 @@ magn_int_default: magn-int-default { bias-disable; }; - tp_int_default: tp-int-default { + tp_int_default: tp-int-default-state { pins = "gpio13"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts index b4812f093b17..3899e11b9843 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts @@ -234,7 +234,7 @@ l18 { }; &msmgpio { - button_backlight_default: button-backlight-default { + button_backlight_default: button-backlight-default-state { pins = "gpio17"; function = "gpio"; @@ -242,7 +242,7 @@ button_backlight_default: button-backlight-default { bias-disable; }; - gpio_keys_default: gpio-keys-default { + gpio_keys_default: gpio-keys-default-state { pins = "gpio107"; function = "gpio"; @@ -250,7 +250,7 @@ gpio_keys_default: gpio-keys-default { bias-pull-up; }; - mag_reset_default: mag-reset-default { + mag_reset_default: mag-reset-default-state { pins = "gpio111"; function = "gpio"; @@ -258,7 +258,7 @@ mag_reset_default: mag-reset-default { bias-disable; }; - usb_id_default: usb-id-default { + usb_id_default: usb-id-default-state { pins = "gpio110"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi index 7dedb91b9930..db9e448d0a64 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi @@ -5,7 +5,7 @@ &msmgpio { - blsp1_uart1_default: blsp1-uart1-default { + blsp1_uart1_default: blsp1-uart1-default-state { // TX, RX, CTS_N, RTS_N pins = "gpio0", "gpio1", "gpio2", "gpio3"; function = "blsp_uart1"; @@ -14,7 +14,7 @@ blsp1_uart1_default: blsp1-uart1-default { bias-disable; }; - blsp1_uart1_sleep: blsp1-uart1-sleep { + blsp1_uart1_sleep: blsp1-uart1-sleep-state { pins = "gpio0", "gpio1", "gpio2", "gpio3"; function = "gpio"; @@ -22,7 +22,7 @@ blsp1_uart1_sleep: blsp1-uart1-sleep { bias-pull-down; }; - blsp1_uart2_default: blsp1-uart2-default { + blsp1_uart2_default: blsp1-uart2-default-state { pins = "gpio4", "gpio5"; function = "blsp_uart2"; @@ -30,7 +30,7 @@ blsp1_uart2_default: blsp1-uart2-default { bias-disable; }; - blsp1_uart2_sleep: blsp1-uart2-sleep { + blsp1_uart2_sleep: blsp1-uart2-sleep-state { pins = "gpio4", "gpio5"; function = "gpio"; @@ -38,14 +38,15 @@ blsp1_uart2_sleep: blsp1-uart2-sleep { bias-pull-down; }; - spi1_default: spi1-default { - pins = "gpio0", "gpio1", "gpio3"; - function = "blsp_spi1"; + spi1_default: spi1-default-state { + spi-pins { + pins = "gpio0", "gpio1", "gpio3"; + function = "blsp_spi1"; - drive-strength = <12>; - bias-disable; - - cs { + drive-strength = <12>; + bias-disable; + }; + cs-pins { pins = "gpio2"; function = "gpio"; @@ -55,7 +56,7 @@ cs { }; }; - spi1_sleep: spi1-sleep { + spi1_sleep: spi1-sleep-state { pins = "gpio0", "gpio1", "gpio2", "gpio3"; function = "gpio"; @@ -63,14 +64,15 @@ spi1_sleep: spi1-sleep { bias-pull-down; }; - spi2_default: spi2-default { - pins = "gpio4", "gpio5", "gpio7"; - function = "blsp_spi2"; + spi2_default: spi2-default-state { + spi-pins { + pins = "gpio4", "gpio5", "gpio7"; + function = "blsp_spi2"; - drive-strength = <12>; - bias-disable; - - cs { + drive-strength = <12>; + bias-disable; + }; + cs-pins { pins = "gpio6"; function = "gpio"; @@ -80,7 +82,7 @@ cs { }; }; - spi2_sleep: spi2-sleep { + spi2_sleep: spi2-sleep-state { pins = "gpio4", "gpio5", "gpio6", "gpio7"; function = "gpio"; @@ -88,14 +90,15 @@ spi2_sleep: spi2-sleep { bias-pull-down; }; - spi3_default: spi3-default { - pins = "gpio8", "gpio9", "gpio11"; - function = "blsp_spi3"; + spi3_default: spi3-default-state { + spi-pins { + pins = "gpio8", "gpio9", "gpio11"; + function = "blsp_spi3"; - drive-strength = <12>; - bias-disable; - - cs { + drive-strength = <12>; + bias-disable; + }; + cs-pins { pins = "gpio10"; function = "gpio"; @@ -105,7 +108,7 @@ cs { }; }; - spi3_sleep: spi3-sleep { + spi3_sleep: spi3-sleep-state { pins = "gpio8", "gpio9", "gpio10", "gpio11"; function = "gpio"; @@ -113,14 +116,15 @@ spi3_sleep: spi3-sleep { bias-pull-down; }; - spi4_default: spi4-default { - pins = "gpio12", "gpio13", "gpio15"; - function = "blsp_spi4"; + spi4_default: spi4-default-state { + spi-pins { + pins = "gpio12", "gpio13", "gpio15"; + function = "blsp_spi4"; - drive-strength = <12>; - bias-disable; - - cs { + drive-strength = <12>; + bias-disable; + }; + cs-pins { pins = "gpio14"; function = "gpio"; @@ -130,7 +134,7 @@ cs { }; }; - spi4_sleep: spi4-sleep { + spi4_sleep: spi4-sleep-state { pins = "gpio12", "gpio13", "gpio14", "gpio15"; function = "gpio"; @@ -138,14 +142,15 @@ spi4_sleep: spi4-sleep { bias-pull-down; }; - spi5_default: spi5-default { - pins = "gpio16", "gpio17", "gpio19"; - function = "blsp_spi5"; + spi5_default: spi5-default-state { + spi-pins { + pins = "gpio16", "gpio17", "gpio19"; + function = "blsp_spi5"; - drive-strength = <12>; - bias-disable; - - cs { + drive-strength = <12>; + bias-disable; + }; + cs-pins { pins = "gpio18"; function = "gpio"; @@ -155,7 +160,7 @@ cs { }; }; - spi5_sleep: spi5-sleep { + spi5_sleep: spi5-sleep-state { pins = "gpio16", "gpio17", "gpio18", "gpio19"; function = "gpio"; @@ -163,14 +168,15 @@ spi5_sleep: spi5-sleep { bias-pull-down; }; - spi6_default: spi6-default { - pins = "gpio20", "gpio21", "gpio23"; - function = "blsp_spi6"; + spi6_default: spi6-default-state { + spi-pins { + pins = "gpio20", "gpio21", "gpio23"; + function = "blsp_spi6"; - drive-strength = <12>; - bias-disable; - - cs { + drive-strength = <12>; + bias-disable; + }; + cs-pins { pins = "gpio22"; function = "gpio"; @@ -180,7 +186,7 @@ cs { }; }; - spi6_sleep: spi6-sleep { + spi6_sleep: spi6-sleep-state { pins = "gpio20", "gpio21", "gpio22", "gpio23"; function = "gpio"; @@ -188,7 +194,7 @@ spi6_sleep: spi6-sleep { bias-pull-down; }; - i2c1_default: i2c1-default { + i2c1_default: i2c1-default-state { pins = "gpio2", "gpio3"; function = "blsp_i2c1"; @@ -196,7 +202,7 @@ i2c1_default: i2c1-default { bias-disable; }; - i2c1_sleep: i2c1-sleep { + i2c1_sleep: i2c1-sleep-state { pins = "gpio2", "gpio3"; function = "gpio"; @@ -204,7 +210,7 @@ i2c1_sleep: i2c1-sleep { bias-disable; }; - i2c2_default: i2c2-default { + i2c2_default: i2c2-default-state { pins = "gpio6", "gpio7"; function = "blsp_i2c2"; @@ -212,7 +218,7 @@ i2c2_default: i2c2-default { bias-disable; }; - i2c2_sleep: i2c2-sleep { + i2c2_sleep: i2c2-sleep-state { pins = "gpio6", "gpio7"; function = "gpio"; @@ -220,7 +226,7 @@ i2c2_sleep: i2c2-sleep { bias-disable; }; - i2c3_default: i2c3-default { + i2c3_default: i2c3-default-state { pins = "gpio10", "gpio11"; function = "blsp_i2c3"; @@ -228,7 +234,7 @@ i2c3_default: i2c3-default { bias-disable; }; - i2c3_sleep: i2c3-sleep { + i2c3_sleep: i2c3-sleep-state { pins = "gpio10", "gpio11"; function = "gpio"; @@ -236,7 +242,7 @@ i2c3_sleep: i2c3-sleep { bias-disable; }; - i2c4_default: i2c4-default { + i2c4_default: i2c4-default-state { pins = "gpio14", "gpio15"; function = "blsp_i2c4"; @@ -244,7 +250,7 @@ i2c4_default: i2c4-default { bias-disable; }; - i2c4_sleep: i2c4-sleep { + i2c4_sleep: i2c4-sleep-state { pins = "gpio14", "gpio15"; function = "gpio"; @@ -252,7 +258,7 @@ i2c4_sleep: i2c4-sleep { bias-disable; }; - i2c5_default: i2c5-default { + i2c5_default: i2c5-default-state { pins = "gpio18", "gpio19"; function = "blsp_i2c5"; @@ -260,7 +266,7 @@ i2c5_default: i2c5-default { bias-disable; }; - i2c5_sleep: i2c5-sleep { + i2c5_sleep: i2c5-sleep-state { pins = "gpio18", "gpio19"; function = "gpio"; @@ -268,7 +274,7 @@ i2c5_sleep: i2c5-sleep { bias-disable; }; - i2c6_default: i2c6-default { + i2c6_default: i2c6-default-state { pins = "gpio22", "gpio23"; function = "blsp_i2c6"; @@ -276,7 +282,7 @@ i2c6_default: i2c6-default { bias-disable; }; - i2c6_sleep: i2c6-sleep { + i2c6_sleep: i2c6-sleep-state { pins = "gpio22", "gpio23"; function = "gpio"; @@ -284,14 +290,14 @@ i2c6_sleep: i2c6-sleep { bias-disable; }; - pmx-sdc1-clk { - sdc1_clk_on: clk-on { + pmx-sdc1-clk-state { + sdc1_clk_on: clk-on-pins { pins = "sdc1_clk"; bias-disable; drive-strength = <16>; }; - sdc1_clk_off: clk-off { + sdc1_clk_off: clk-off-pins { pins = "sdc1_clk"; bias-disable; @@ -299,14 +305,14 @@ sdc1_clk_off: clk-off { }; }; - pmx-sdc1-cmd { - sdc1_cmd_on: cmd-on { + pmx-sdc1-cmd-state { + sdc1_cmd_on: cmd-on-pins { pins = "sdc1_cmd"; bias-pull-up; drive-strength = <10>; }; - sdc1_cmd_off: cmd-off { + sdc1_cmd_off: cmd-off-pins { pins = "sdc1_cmd"; bias-pull-up; @@ -314,14 +320,14 @@ sdc1_cmd_off: cmd-off { }; }; - pmx-sdc1-data { - sdc1_data_on: data-on { + pmx-sdc1-data-state { + sdc1_data_on: data-on-pins { pins = "sdc1_data"; bias-pull-up; drive-strength = <10>; }; - sdc1_data_off: data-off { + sdc1_data_off: data-off-pins { pins = "sdc1_data"; bias-pull-up; @@ -329,14 +335,14 @@ sdc1_data_off: data-off { }; }; - pmx-sdc2-clk { - sdc2_clk_on: clk-on { + pmx-sdc2-clk-state { + sdc2_clk_on: clk-on-pins { pins = "sdc2_clk"; bias-disable; drive-strength = <16>; }; - sdc2_clk_off: clk-off { + sdc2_clk_off: clk-off-pins { pins = "sdc2_clk"; bias-disable; @@ -344,14 +350,14 @@ sdc2_clk_off: clk-off { }; }; - pmx-sdc2-cmd { - sdc2_cmd_on: cmd-on { + pmx-sdc2-cmd-state { + sdc2_cmd_on: cmd-on-pins { pins = "sdc2_cmd"; bias-pull-up; drive-strength = <10>; }; - sdc2_cmd_off: cmd-off { + sdc2_cmd_off: cmd-off-pins { pins = "sdc2_cmd"; bias-pull-up; @@ -359,14 +365,14 @@ sdc2_cmd_off: cmd-off { }; }; - pmx-sdc2-data { - sdc2_data_on: data-on { + pmx-sdc2-data-state { + sdc2_data_on: data-on-pins { pins = "sdc2_data"; bias-pull-up; drive-strength = <10>; }; - sdc2_data_off: data-off { + sdc2_data_off: data-off-pins { pins = "sdc2_data"; bias-pull-up; @@ -374,15 +380,15 @@ sdc2_data_off: data-off { }; }; - pmx-sdc2-cd-pin { - sdc2_cd_on: cd-on { + pmx-sdc2-cd-pin-state { + sdc2_cd_on: cd-on-pins { pins = "gpio38"; function = "gpio"; drive-strength = <2>; bias-pull-up; }; - sdc2_cd_off: cd-off { + sdc2_cd_off: cd-off-pins { pins = "gpio38"; function = "gpio"; @@ -391,8 +397,8 @@ sdc2_cd_off: cd-off { }; }; - cdc-pdm-lines { - cdc_pdm_lines_act: pdm-lines-on { + cdc-pdm-lines-state { + cdc_pdm_lines_act: pdm-lines-on-pins { pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68"; function = "cdc_pdm0"; @@ -400,7 +406,7 @@ cdc_pdm_lines_act: pdm-lines-on { drive-strength = <8>; bias-disable; }; - cdc_pdm_lines_sus: pdm-lines-off { + cdc_pdm_lines_sus: pdm-lines-off-pins { pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68"; function = "cdc_pdm0"; @@ -410,15 +416,15 @@ cdc_pdm_lines_sus: pdm-lines-off { }; }; - ext-pri-tlmm-lines { - ext_pri_tlmm_lines_act: ext-pa-on { + ext-pri-tlmm-lines-state { + ext_pri_tlmm_lines_act: ext-pa-on-pins { pins = "gpio113", "gpio114", "gpio115", "gpio116"; function = "pri_mi2s"; drive-strength = <8>; bias-disable; }; - ext_pri_tlmm_lines_sus: ext-pa-off { + ext_pri_tlmm_lines_sus: ext-pa-off-pins { pins = "gpio113", "gpio114", "gpio115", "gpio116"; function = "pri_mi2s"; @@ -427,15 +433,15 @@ ext_pri_tlmm_lines_sus: ext-pa-off { }; }; - ext-pri-ws-line { - ext_pri_ws_act: ext-pa-on { + ext-pri-ws-line-state { + ext_pri_ws_act: ext-pa-on-pins { pins = "gpio110"; function = "pri_mi2s_ws"; drive-strength = <8>; bias-disable; }; - ext_pri_ws_sus: ext-pa-off { + ext_pri_ws_sus: ext-pa-off-pins { pins = "gpio110"; function = "pri_mi2s_ws"; @@ -444,15 +450,15 @@ ext_pri_ws_sus: ext-pa-off { }; }; - ext-mclk-tlmm-lines { - ext_mclk_tlmm_lines_act: mclk-lines-on { + ext-mclk-tlmm-lines-state { + ext_mclk_tlmm_lines_act: mclk-lines-on-pins { pins = "gpio116"; function = "pri_mi2s"; drive-strength = <8>; bias-disable; }; - ext_mclk_tlmm_lines_sus: mclk-lines-off { + ext_mclk_tlmm_lines_sus: mclk-lines-off-pins { pins = "gpio116"; function = "pri_mi2s"; @@ -462,15 +468,15 @@ ext_mclk_tlmm_lines_sus: mclk-lines-off { }; /* secondary Mi2S */ - ext-sec-tlmm-lines { - ext_sec_tlmm_lines_act: tlmm-lines-on { + ext-sec-tlmm-lines-state { + ext_sec_tlmm_lines_act: tlmm-lines-on-pins { pins = "gpio112", "gpio117", "gpio118", "gpio119"; function = "sec_mi2s"; drive-strength = <8>; bias-disable; }; - ext_sec_tlmm_lines_sus: tlmm-lines-off { + ext_sec_tlmm_lines_sus: tlmm-lines-off-pins { pins = "gpio112", "gpio117", "gpio118", "gpio119"; function = "sec_mi2s"; @@ -479,40 +485,38 @@ ext_sec_tlmm_lines_sus: tlmm-lines-off { }; }; - cdc-dmic-lines { - cdc_dmic_lines_act: dmic-lines-on { - clk { - pins = "gpio0"; - function = "dmic0_clk"; + cdc_dmic_lines_act: cdc-dmic-lines-on-state { + clk-pins { + pins = "gpio0"; + function = "dmic0_clk"; - drive-strength = <8>; - }; - data { - pins = "gpio1"; - function = "dmic0_data"; - - drive-strength = <8>; - }; + drive-strength = <8>; }; - cdc_dmic_lines_sus: dmic-lines-off { - clk { - pins = "gpio0"; - function = "dmic0_clk"; + data-pins { + pins = "gpio1"; + function = "dmic0_data"; - drive-strength = <2>; - bias-disable; - }; - data { - pins = "gpio1"; - function = "dmic0_data"; + drive-strength = <8>; + }; + }; + cdc_dmic_lines_sus: cdc-dmic-lines-off-state { + clk-pins { + pins = "gpio0"; + function = "dmic0_clk"; - drive-strength = <2>; - bias-disable; - }; + drive-strength = <2>; + bias-disable; + }; + data-pins { + pins = "gpio1"; + function = "dmic0_data"; + + drive-strength = <2>; + bias-disable; }; }; - wcnss_pin_a: wcnss-active { + wcnss_pin_a: wcnss-active-state { pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44"; function = "wcss_wlan"; @@ -520,7 +524,7 @@ wcnss_pin_a: wcnss-active { bias-pull-up; }; - cci0_default: cci0-default { + cci0_default: cci0-default-state { pins = "gpio29", "gpio30"; function = "cci_i2c"; @@ -528,22 +532,22 @@ cci0_default: cci0-default { bias-disable; }; - camera_front_default: camera-front-default { - pwdn { + camera_front_default: camera-front-default-state { + pwdn-pins { pins = "gpio33"; function = "gpio"; drive-strength = <16>; bias-disable; }; - rst { + rst-pins { pins = "gpio28"; function = "gpio"; drive-strength = <16>; bias-disable; }; - mclk1 { + mclk1-pins { pins = "gpio27"; function = "cam_mclk1"; @@ -552,22 +556,22 @@ mclk1 { }; }; - camera_rear_default: camera-rear-default { - pwdn { + camera_rear_default: camera-rear-default-state { + pwdn-pins { pins = "gpio34"; function = "gpio"; drive-strength = <16>; bias-disable; }; - rst { + rst-pins { pins = "gpio35"; function = "gpio"; drive-strength = <16>; bias-disable; }; - mclk0 { + mclk0-pins { pins = "gpio26"; function = "cam_mclk0"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index 2a074e70c4da..d600916a0e55 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -387,7 +387,7 @@ l18 { }; &msmgpio { - accel_int_default: accel-int-default { + accel_int_default: accel-int-default-state { pins = "gpio115"; function = "gpio"; @@ -395,7 +395,7 @@ accel_int_default: accel-int-default { bias-disable; }; - fg_alert_default: fg-alert-default { + fg_alert_default: fg-alert-default-state { pins = "gpio121"; function = "gpio"; @@ -403,7 +403,7 @@ fg_alert_default: fg-alert-default { bias-disable; }; - gpio_keys_default: gpio-keys-default { + gpio_keys_default: gpio-keys-default-state { pins = "gpio107", "gpio109"; function = "gpio"; @@ -411,7 +411,7 @@ gpio_keys_default: gpio-keys-default { bias-pull-up; }; - gpio_hall_sensor_default: gpio-hall-sensor-default { + gpio_hall_sensor_default: gpio-hall-sensor-default-state { pins = "gpio52"; function = "gpio"; @@ -419,24 +419,22 @@ gpio_hall_sensor_default: gpio-hall-sensor-default { bias-disable; }; - mdss { - mdss_default: mdss-default { - pins = "gpio25"; - function = "gpio"; + mdss_default: mdss-default-state { + pins = "gpio25"; + function = "gpio"; - drive-strength = <8>; - bias-disable; - }; - mdss_sleep: mdss-sleep { - pins = "gpio25"; - function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + mdss_sleep: mdss-sleep-state { + pins = "gpio25"; + function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; + drive-strength = <2>; + bias-pull-down; }; - motor_en_default: motor-en-default { + motor_en_default: motor-en-default-stae { pins = "gpio76"; function = "gpio"; @@ -444,12 +442,12 @@ motor_en_default: motor-en-default { bias-disable; }; - motor_pwm_default: motor-pwm-default { + motor_pwm_default: motor-pwm-default-state { pins = "gpio50"; function = "gcc_gp2_clk_a"; }; - muic_i2c_default: muic-i2c-default { + muic_i2c_default: muic-i2c-default-state { pins = "gpio105", "gpio106"; function = "gpio"; @@ -457,7 +455,7 @@ muic_i2c_default: muic-i2c-default { bias-disable; }; - muic_int_default: muic-int-default { + muic_int_default: muic-int-default-state { pins = "gpio12"; function = "gpio"; @@ -465,14 +463,16 @@ muic_int_default: muic-int-default { bias-disable; }; - nfc_default: nfc-default { - pins = "gpio20", "gpio49"; - function = "gpio"; + nfc_default: nfc-default-state { + nfc-pins { + pins = "gpio20", "gpio49"; + function = "gpio"; - drive-strength = <2>; - bias-disable; + drive-strength = <2>; + bias-disable; + }; - irq { + irq-pins { pins = "gpio21"; function = "gpio"; @@ -481,7 +481,7 @@ irq { }; }; - nfc_i2c_default: nfc-i2c-default { + nfc_i2c_default: nfc-i2c-default-state { pins = "gpio0", "gpio1"; function = "gpio"; @@ -489,7 +489,7 @@ nfc_i2c_default: nfc-i2c-default { bias-disable; }; - tkey_default: tkey-default { + tkey_default: tkey-default-state { pins = "gpio98"; function = "gpio"; @@ -497,7 +497,7 @@ tkey_default: tkey-default { bias-disable; }; - tkey_i2c_default: tkey-i2c-default { + tkey_i2c_default: tkey-i2c-default-state { pins = "gpio16", "gpio17"; function = "gpio"; @@ -505,7 +505,7 @@ tkey_i2c_default: tkey-i2c-default { bias-disable; }; - tsp_en_default: tsp-en-default { + tsp_en_default: tsp-en-default-state { pins = "gpio73"; function = "gpio"; @@ -513,7 +513,7 @@ tsp_en_default: tsp-en-default { bias-disable; }; - ts_int_default: ts-int-default { + ts_int_default: ts-int-default-state { pins = "gpio13"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts index d495d5ae5cc3..c691cca2eb45 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts @@ -113,7 +113,7 @@ &vibrator { }; &msmgpio { - panel_vdd3_default: panel-vdd3-default { + panel_vdd3_default: panel-vdd3-default-state { pins = "gpio9"; function = "gpio"; @@ -121,7 +121,7 @@ panel_vdd3_default: panel-vdd3-default { bias-disable; }; - tkey_en_default: tkey-en-default { + tkey_en_default: tkey-en-default-state { pins = "gpio86"; function = "gpio"; @@ -129,7 +129,7 @@ tkey_en_default: tkey-en-default { bias-disable; }; - tkey_led_en_default: tkey-led-en-default { + tkey_led_en_default: tkey-led-en-default-state { pins = "gpio60"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts index c03504ab27b7..3dd819458785 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts @@ -70,7 +70,7 @@ &vibrator { }; &msmgpio { - tkey_en_default: tkey-en-default { + tkey_en_default: tkey-en-default-state { pins = "gpio97"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi index edd24b597a15..c95f0b4bc61f 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi @@ -59,7 +59,7 @@ &touchkey { }; &msmgpio { - tkey_en_default: tkey-en-default { + tkey_en_default: tkey-en-default-state { pins = "gpio97"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-grandmax.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-grandmax.dts index bc7134698978..a3d572d851ef 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-grandmax.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-grandmax.dts @@ -46,7 +46,7 @@ ®_touch_key { }; &msmgpio { - gpio_leds_default: gpio-led-default { + gpio_leds_default: gpio-led-default-state { pins = "gpio60"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts index eabeed18cfaa..7ac49a021563 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts @@ -199,7 +199,7 @@ l18 { }; &msmgpio { - gpio_keys_default: gpio-keys-default { + gpio_keys_default: gpio-keys-default-state { pins = "gpio107", "gpio109"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts index bbd6bb3f4fd7..f0ee5ed7cf81 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts @@ -422,7 +422,7 @@ l18 { }; &msmgpio { - fg_alert_default: fg-alert-default { + fg_alert_default: fg-alert-default-state { pins = "gpio121"; function = "gpio"; @@ -430,7 +430,7 @@ fg_alert_default: fg-alert-default { bias-disable; }; - gpio_keys_default: gpio-keys-default { + gpio_keys_default: gpio-keys-default-state { pins = "gpio107", "gpio109"; function = "gpio"; @@ -438,7 +438,7 @@ gpio_keys_default: gpio-keys-default { bias-pull-up; }; - gpio_hall_sensor_default: gpio-hall-sensor-default { + gpio_hall_sensor_default: gpio-hall-sensor-default-state { pins = "gpio52"; function = "gpio"; @@ -446,7 +446,7 @@ gpio_hall_sensor_default: gpio-hall-sensor-default { bias-disable; }; - imu_irq_default: imu-irq-default { + imu_irq_default: imu-irq-default-state { pins = "gpio115"; function = "gpio"; @@ -454,7 +454,7 @@ imu_irq_default: imu-irq-default { bias-disable; }; - muic_i2c_default: muic-i2c-default { + muic_i2c_default: muic-i2c-default-state { pins = "gpio105", "gpio106"; function = "gpio"; @@ -462,7 +462,7 @@ muic_i2c_default: muic-i2c-default { bias-disable; }; - muic_irq_default: muic-irq-default { + muic_irq_default: muic-irq-default-state { pins = "gpio12"; function = "gpio"; @@ -470,14 +470,15 @@ muic_irq_default: muic-irq-default { bias-disable; }; - nfc_default: nfc-default { - pins = "gpio20", "gpio49"; - function = "gpio"; + nfc_default: nfc-default-state { + nfc-pins { + pins = "gpio20", "gpio49"; + function = "gpio"; - drive-strength = <2>; - bias-disable; - - irq { + drive-strength = <2>; + bias-disable; + }; + irq-pins { pins = "gpio21"; function = "gpio"; @@ -486,7 +487,7 @@ irq { }; }; - nfc_i2c_default: nfc-i2c-default { + nfc_i2c_default: nfc-i2c-default-state { pins = "gpio0", "gpio1"; function = "gpio"; @@ -494,7 +495,7 @@ nfc_i2c_default: nfc-i2c-default { bias-disable; }; - tkey_default: tkey-default { + tkey_default: tkey-default-state { pins = "gpio98"; function = "gpio"; @@ -502,7 +503,7 @@ tkey_default: tkey-default { bias-disable; }; - tkey_en_default: tkey-en-default { + tkey_en_default: tkey-en-default-state { pins = "gpio86"; function = "gpio"; @@ -510,7 +511,7 @@ tkey_en_default: tkey-en-default { bias-disable; }; - tkey_i2c_default: tkey-i2c-default { + tkey_i2c_default: tkey-i2c-default-state { pins = "gpio16", "gpio17"; function = "gpio"; @@ -518,7 +519,7 @@ tkey_i2c_default: tkey-i2c-default { bias-disable; }; - tkey_led_en_default: tkey-led-en-default { + tkey_led_en_default: tkey-led-en-default-state { pins = "gpio60"; function = "gpio"; @@ -526,7 +527,7 @@ tkey_led_en_default: tkey-led-en-default { bias-disable; }; - tsp_en_default: tsp-en-default { + tsp_en_default: tsp-en-default-state { pins = "gpio73"; function = "gpio"; @@ -534,7 +535,7 @@ tsp_en_default: tsp-en-default { bias-disable; }; - tsp_irq_default: tsp-irq-default { + tsp_irq_default: tsp-irq-default-state { pins = "gpio13"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts index 84a352dcf9a2..399326b8f99e 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts @@ -272,7 +272,7 @@ l18 { }; &msmgpio { - gpio_keys_default: gpio-keys-default { + gpio_keys_default: gpio-keys-default-state { pins = "gpio107"; function = "gpio"; @@ -280,7 +280,7 @@ gpio_keys_default: gpio-keys-default { bias-pull-up; }; - imu_default: imu-default { + imu_default: imu-default-state { pins = "gpio115"; function = "gpio"; @@ -288,14 +288,15 @@ imu_default: imu-default { bias-disable; }; - touchscreen_default: touchscreen-default { - pins = "gpio13"; - function = "gpio"; + touchscreen_default: touchscreen-default-state { + touchscreen-pins { + pins = "gpio13"; + function = "gpio"; - drive-strength = <2>; - bias-pull-up; - - reset { + drive-strength = <2>; + bias-pull-up; + }; + reset-pins { pins = "gpio12"; function = "gpio"; @@ -304,7 +305,7 @@ reset { }; }; - usb_id_default: usb-id-default { + usb_id_default: usb-id-default-state { pins = "gpio110"; function = "gpio"; From 36a31b3a8d9ba1707a23de8d8dc1ceaef4eda695 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Mon, 24 Oct 2022 11:15:04 +0200 Subject: [PATCH 153/261] arm64: dts: qcom: sm8150: fix UFS PHY registers The sizes of the UFS PHY register regions are too small and does specifically not cover all registers used by the Linux driver. As Linux maps these regions as full pages this is currently not an issue on Linux, but let's update the sizes to match the vendor driver. Fixes: 3834a2e92229 ("arm64: dts: qcom: sm8150: Add ufs nodes") Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221024091507.20342-2-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 5fa575e4425a..18bf51ce8b13 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -2032,11 +2032,11 @@ ufs_mem_phy: phy@1d87000 { status = "disabled"; ufs_mem_phy_lanes: phy@1d87400 { - reg = <0 0x01d87400 0 0x108>, - <0 0x01d87600 0 0x1e0>, - <0 0x01d87c00 0 0x1dc>, - <0 0x01d87800 0 0x108>, - <0 0x01d87a00 0 0x1e0>; + reg = <0 0x01d87400 0 0x16c>, + <0 0x01d87600 0 0x200>, + <0 0x01d87c00 0 0x200>, + <0 0x01d87800 0 0x16c>, + <0 0x01d87a00 0 0x200>; #phy-cells = <0>; }; }; From 7f8b37dd4e7bf50160529530d9789b846153df71 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Mon, 24 Oct 2022 11:15:05 +0200 Subject: [PATCH 154/261] arm64: dts: qcom: sm8250: fix UFS PHY registers The sizes of the UFS PHY register regions are too small and does specifically not cover all registers used by the Linux driver. As Linux maps these regions as full pages this is currently not an issue on Linux, but let's update the sizes to match the vendor driver. Fixes: b7e2fba06622 ("arm64: dts: qcom: sm8250: Add UFS controller and PHY") Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221024091507.20342-3-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 369252fe8a7b..6b6a7277db5e 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2179,11 +2179,11 @@ ufs_mem_phy: phy@1d87000 { status = "disabled"; ufs_mem_phy_lanes: phy@1d87400 { - reg = <0 0x01d87400 0 0x108>, - <0 0x01d87600 0 0x1e0>, - <0 0x01d87c00 0 0x1dc>, - <0 0x01d87800 0 0x108>, - <0 0x01d87a00 0 0x1e0>; + reg = <0 0x01d87400 0 0x16c>, + <0 0x01d87600 0 0x200>, + <0 0x01d87c00 0 0x200>, + <0 0x01d87800 0 0x16c>, + <0 0x01d87a00 0 0x200>; #phy-cells = <0>; }; }; From b3c7839b698cc617e97dd2e4f1eeb4adc280fe58 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Mon, 24 Oct 2022 11:15:06 +0200 Subject: [PATCH 155/261] arm64: dts: qcom: sm8350: fix UFS PHY registers The sizes of the UFS PHY register regions are too small and does specifically not cover all registers used by the Linux driver. As Linux maps these regions as full pages this is currently not an issue on Linux, but let's update the sizes to match the vendor driver. Fixes: 59c7cf814783 ("arm64: dts: qcom: sm8350: Add UFS nodes") Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221024091507.20342-4-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index aa08c0e065c7..fa5911976b0f 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2142,11 +2142,11 @@ ufs_mem_phy: phy@1d87000 { status = "disabled"; ufs_mem_phy_lanes: phy@1d87400 { - reg = <0 0x01d87400 0 0x108>, - <0 0x01d87600 0 0x1e0>, - <0 0x01d87c00 0 0x1dc>, - <0 0x01d87800 0 0x108>, - <0 0x01d87a00 0 0x1e0>; + reg = <0 0x01d87400 0 0x188>, + <0 0x01d87600 0 0x200>, + <0 0x01d87c00 0 0x200>, + <0 0x01d87800 0 0x188>, + <0 0x01d87a00 0 0x200>; #phy-cells = <0>; }; }; From 7af949211a0554bbc06163b081fc2cb516674880 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Mon, 24 Oct 2022 11:15:07 +0200 Subject: [PATCH 156/261] arm64: dts: qcom: sm8450: fix UFS PHY registers The sizes of the UFS PHY register regions are too small and does specifically not cover all registers used by the Linux driver. As Linux maps these regions as full pages this is currently not an issue on Linux, but let's update the sizes to match the vendor driver. Fixes: 07fa917a335e ("arm64: dts: qcom: sm8450: add ufs nodes") Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221024091507.20342-5-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 73e81f4c41be..935112cd8797 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3331,11 +3331,11 @@ ufs_mem_phy: phy@1d87000 { status = "disabled"; ufs_mem_phy_lanes: phy@1d87400 { - reg = <0 0x01d87400 0 0x108>, - <0 0x01d87600 0 0x1e0>, - <0 0x01d87c00 0 0x1dc>, - <0 0x01d87800 0 0x108>, - <0 0x01d87a00 0 0x1e0>; + reg = <0 0x01d87400 0 0x188>, + <0 0x01d87600 0 0x200>, + <0 0x01d87c00 0 0x200>, + <0 0x01d87800 0 0x188>, + <0 0x01d87a00 0 0x200>; #phy-cells = <0>; }; }; From a0646262ec94faaf95b3dba8f17774d9762ee9ac Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 26 Oct 2022 16:03:54 -0400 Subject: [PATCH 157/261] arm64: dts: qcom: sm8450: move SDHCI pin configuration to DTSI The SDHCI pin configuration/mux nodes are actually common to all upstreamed boards, so define them in SoC DTSI to reduce code duplication. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221026200357.391635-2-krzysztof.kozlowski@linaro.org --- .../qcom/sm8450-sony-xperia-nagara-pdx223.dts | 20 ------------------- arch/arm64/boot/dts/qcom/sm8450.dtsi | 20 +++++++++++++++++++ 2 files changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts index 82918c2d956f..718c690af8ad 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts @@ -572,26 +572,6 @@ &spi10 { &tlmm { gpio-reserved-ranges = <28 4>; - sdc2_default_state: sdc2-default-state { - clk-pins { - pins = "sdc2_clk"; - drive-strength = <16>; - bias-disable; - }; - - cmd-pins { - pins = "sdc2_cmd"; - drive-strength = <16>; - bias-pull-up; - }; - - data-pins { - pins = "sdc2_data"; - drive-strength = <16>; - bias-pull-up; - }; - }; - ts_int_default: ts-int-default-state { pins = "gpio23"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 935112cd8797..e6997fc80fe9 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2490,6 +2490,26 @@ tlmm: pinctrl@f100000 { gpio-ranges = <&tlmm 0 0 211>; wakeup-parent = <&pdc>; + sdc2_default_state: sdc2-default-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <16>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <16>; + bias-pull-up; + }; + }; + sdc2_sleep_state: sdc2-sleep-state { clk-pins { pins = "sdc2_clk"; From 9d561dc4e5cc31e757f91eb7bb709d2e2a8c9ce0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 26 Oct 2022 16:03:55 -0400 Subject: [PATCH 158/261] arm64: dts: qcom: sm8450: disable SDHCI SDR104/SDR50 on all boards SDHCI on SM8450 HDK also has problems with SDR104/SDR50: mmc0: card never left busy state mmc0: error -110 whilst initialising SD card so I think it is safe to assume this issue affects all SM8450 boards. Move the quirk disallowing these modes to the SoC DTSI, to spare people working on other boards the misery of debugging this issue. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221026200357.391635-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts | 2 -- arch/arm64/boot/dts/qcom/sm8450.dtsi | 3 +++ 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts index 718c690af8ad..ae8ba297b0b6 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts @@ -556,8 +556,6 @@ &sdhc_2 { pinctrl-1 = <&sdc2_sleep_state &sdc2_card_det_n>; vmmc-supply = <&pm8350c_l9>; vqmmc-supply = <&pm8350c_l6>; - /* Forbid SDR104/SDR50 - broken hw! */ - sdhci-caps-mask = <0x3 0x0>; no-sdio; no-mmc; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index e6997fc80fe9..46f9576f786f 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3382,6 +3382,9 @@ sdhc_2: sdhci@8804000 { bus-width = <4>; dma-coherent; + /* Forbid SDR104/SDR50 - broken hw! */ + sdhci-caps-mask = <0x3 0x0>; + status = "disabled"; sdhc2_opp_table: opp-table { From 1f52331285ed9f412f85e321ae6574714725d634 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 26 Oct 2022 16:03:56 -0400 Subject: [PATCH 159/261] arm64: dts: qcom: sm8450-hdk: add SDHCI for microSD The HDK8450 has microSD card slot. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221026200357.391635-4-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 38ccd44620d0..2dd4f8c8f931 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -394,8 +394,27 @@ &qupv3_id_0 { status = "okay"; }; +&sdhc_2 { + cd-gpios = <&tlmm 92 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep_state &sdc2_card_det_n>; + vmmc-supply = <&vreg_l9c_2p96>; + vqmmc-supply = <&vreg_l6c_1p8>; + no-sdio; + no-mmc; + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <28 4>, <36 4>; + + sdc2_card_det_n: sd-card-det-n-state { + pins = "gpio92"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; }; &uart7 { From 4a5923fe4e1df52fafa4026363a349f30c061a15 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 26 Oct 2022 16:03:57 -0400 Subject: [PATCH 160/261] arm64: dts: qcom: sm8450-qrd: add SDHCI for microSD Based on downstream DTS, it seems that SM8450 QRD has microSD card slot. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221026200357.391635-5-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index e58fc7399799..ee62514fff68 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -388,6 +388,18 @@ &remoteproc_slpi { firmware-name = "qcom/sm8450/slpi.mbn"; }; +&sdhc_2 { + cd-gpios = <&tlmm 92 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep_state &sdc2_card_det_n>; + vmmc-supply = <&vreg_l9c_2p96>; + vqmmc-supply = <&vreg_l6c_1p8>; + no-sdio; + no-mmc; + status = "okay"; +}; + &spi4 { status = "okay"; }; @@ -402,6 +414,13 @@ &spi19 { &tlmm { gpio-reserved-ranges = <28 4>, <36 4>; + + sdc2_card_det_n: sd-card-det-n-state { + pins = "gpio92"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; }; &uart7 { From 76d21ffc5d425bf7ea9888652c49d7dbda15f356 Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Thu, 27 Oct 2022 00:46:47 -0700 Subject: [PATCH 161/261] arm64: dts: qcom: msm8996: fix sound card reset line polarity When resetting the block, the reset line is being driven low and then high, which means that the line in DTS should be annotated as "active low". It will become important when wcd9335 driver will be converted to gpiod API that respects declared line polarities. Fixes: f3eb39a55a1f ("arm64: dts: db820c: Add sound card support") Signed-off-by: Dmitry Torokhov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221027074652.1044235-1-dmitry.torokhov@gmail.com --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index de2af2b23d7b..7cd33f723da6 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -3385,7 +3385,7 @@ wcd9335: codec@1,0 { interrupt-names = "intr1", "intr2"; interrupt-controller; #interrupt-cells = <1>; - reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>; + reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; slim-ifc-dev = <&tasha_ifd>; From 15d9fcbb3e6e8420c7d1ae331405780c5d9c1c25 Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Thu, 27 Oct 2022 00:46:49 -0700 Subject: [PATCH 162/261] arm64: dts: qcom: sm8250-mtp: fix reset line polarity The driver for the codec, when resetting the chip, first drives the line low, and then high. This means that the line is active low. Change the annotation in the DTS accordingly. Fixes: 36c9d012f193 ("arm64: dts: qcom: use GPIO flags for tlmm") Fixes: 5a263cf629a8 ("arm64: dts: qcom: sm8250-mtp: Add wcd9380 audio codec node") Signed-off-by: Dmitry Torokhov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221027074652.1044235-3-dmitry.torokhov@gmail.com --- arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index 9db6136321b4..391806c62ccc 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -635,7 +635,7 @@ &soc { wcd938x: codec { compatible = "qcom,wcd9380-codec"; #sound-dai-cells = <1>; - reset-gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>; + reset-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>; vdd-buck-supply = <&vreg_s4a_1p8>; vdd-rxtx-supply = <&vreg_s4a_1p8>; vdd-io-supply = <&vreg_s4a_1p8>; From 1caf66104c02d327a2467a69ab18fb24b44e9715 Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Thu, 27 Oct 2022 00:46:50 -0700 Subject: [PATCH 163/261] arm64: dts: qcom: sc7280: fix codec reset line polarity for CRD 3.0/3.1 The driver for the codec, when resetting the chip, first drives the line low, and then high. This means that the line is active low. Change the annotation in the DTS accordingly. Fixes: 0a3a56a93fd9 ("arm64: dts: qcom: sc7280: Add wcd9385 codec node for CRD 3.0/3.1") Signed-off-by: Dmitry Torokhov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221027074652.1044235-4-dmitry.torokhov@gmail.com --- arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi index a42b5878a75f..df49564ae6dc 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi @@ -37,7 +37,7 @@ wcd9385: audio-codec-1 { pinctrl-0 = <&wcd_reset_n>, <&us_euro_hs_sel>; pinctrl-1 = <&wcd_reset_n_sleep>, <&us_euro_hs_sel>; - reset-gpios = <&tlmm 83 GPIO_ACTIVE_HIGH>; + reset-gpios = <&tlmm 83 GPIO_ACTIVE_LOW>; us-euro-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; qcom,rx-device = <&wcd_rx>; From b8f298d4f69d82119ac0d22809a17c80b1f188d1 Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Thu, 27 Oct 2022 00:46:51 -0700 Subject: [PATCH 164/261] arm64: dts: qcom: sc7280: fix codec reset line polarity for CRD 1.0/2.0 The driver for the codec, when resetting the chip, first drives the line low, and then high. This means that the line is active low. Change the annotation in the DTS accordingly. Fixes: f8b4eb64f200 ("arm64: dts: qcom: sc7280: Add wcd9385 codec node for CRD 1.0/2.0 and IDP boards") Signed-off-by: Dmitry Torokhov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221027074652.1044235-5-dmitry.torokhov@gmail.com --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 4884647a8a95..1ac7c091e03f 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -34,7 +34,7 @@ wcd9385: audio-codec-1 { pinctrl-0 = <&wcd_reset_n>; pinctrl-1 = <&wcd_reset_n_sleep>; - reset-gpios = <&tlmm 83 GPIO_ACTIVE_HIGH>; + reset-gpios = <&tlmm 83 GPIO_ACTIVE_LOW>; qcom,rx-device = <&wcd_rx>; qcom,tx-device = <&wcd_tx>; From 64323952aa5a14471a1225f2c1121aa5447c6ded Mon Sep 17 00:00:00 2001 From: Vincent Knecht Date: Fri, 4 Nov 2022 14:23:59 +0100 Subject: [PATCH 165/261] arm64: dts: qcom: msm8916-alcatel-idol347: add GPIO torch LED Add support for torch LED on GPIO 32. Signed-off-by: Vincent Knecht Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221104132400.1763218-3-vincent.knecht@mailoo.org --- .../boot/dts/qcom/msm8916-alcatel-idol347.dts | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts index 668f8ff53229..eadeb1a445fd 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts @@ -5,6 +5,7 @@ #include "msm8916-pm8916.dtsi" #include #include +#include / { model = "Alcatel OneTouch Idol 3 (4.7)"; @@ -34,6 +35,19 @@ button-volume-up { }; }; + gpio-leds { + compatible = "gpio-leds"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_leds_default>; + + led-0 { + gpios = <&msmgpio 32 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "torch"; + function = LED_FUNCTION_TORCH; + }; + }; + usb_id: usb-id { compatible = "linux,extcon-usb-gpio"; id-gpio = <&msmgpio 69 GPIO_ACTIVE_HIGH>; @@ -276,6 +290,14 @@ gpio_keys_default: gpio-keys-default-state { bias-pull-up; }; + gpio_leds_default: gpio-leds-default-state { + pins = "gpio32"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + gyro_int_default: gyro-int-default-state { pins = "gpio97", "gpio98"; function = "gpio"; From 1c8cc183d07059d23d28c29a8e345464c4055127 Mon Sep 17 00:00:00 2001 From: Vincent Knecht Date: Fri, 4 Nov 2022 14:24:00 +0100 Subject: [PATCH 166/261] arm64: dts: qcom: msm8916-alcatel-idol347: add LED indicator Add si-en,sn3190 LED controller to enable white LED indicator. This requires adding the additional "enable" gpio that the OEM choose to use, despite it not being mentioned in si-en,sn3190 datasheet nor supported by the driver. Signed-off-by: Vincent Knecht Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221104132400.1763218-4-vincent.knecht@mailoo.org --- .../boot/dts/qcom/msm8916-alcatel-idol347.dts | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts index eadeb1a445fd..701a5585d77e 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts @@ -130,6 +130,27 @@ gyroscope@68 { }; }; +&blsp_i2c6 { + status = "okay"; + + led-controller@68 { + compatible = "si-en,sn3190"; + reg = <0x68>; + shutdown-gpios = <&msmgpio 89 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&led_enable_default &led_shutdown_default>; + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + led-max-microamp = <5000>; + function = LED_FUNCTION_INDICATOR; + color = ; + }; + }; +}; + &pm8916_resin { status = "okay"; linux,code = ; @@ -306,6 +327,29 @@ gyro_int_default: gyro-int-default-state { bias-disable; }; + /* + * The OEM wired an additional GPIO to be asserted so that + * the si-en,sn3190 LED IC works. Since this GPIO is not + * part of the IC datasheet nor supported by the driver, + * force it asserted here. + */ + led_enable_default: led-enable-default-state { + pins = "gpio102"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + output-high; + }; + + led_shutdown_default: led-shutdown-default-state { + pins = "gpio89"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + mag_reset_default: mag-reset-default-state { pins = "gpio8"; function = "gpio"; From 965a6d823a0476f9500216f1855bb8fcc6b73551 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 4 Nov 2022 16:23:16 +0300 Subject: [PATCH 167/261] dt-bindings: qcom: add another exception to the device naming rule The 'qcom,dsi-ctrl-6g-qcm2290' compatibility string was added in the commit ee1f09678f14 ("drm/msm/dsi: Add support for qcm2290 dsi controller") in February 2022, but was not properly documented in the bindings. Adding this compatibility string to display/msm/dsi-controller-main.yaml caused a warning from qcom-soc.yaml. Fix the warning by adding an exception to the mentioned file. Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221104132316.1028137-1-dmitry.baryshkov@linaro.org --- Documentation/devicetree/bindings/arm/qcom-soc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom-soc.yaml b/Documentation/devicetree/bindings/arm/qcom-soc.yaml index 889fbfacf226..e333ec4a9c5f 100644 --- a/Documentation/devicetree/bindings/arm/qcom-soc.yaml +++ b/Documentation/devicetree/bindings/arm/qcom-soc.yaml @@ -43,6 +43,7 @@ properties: - pattern: "^qcom,rpm-(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$" - pattern: "^qcom,scm-(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$" - enum: + - qcom,dsi-ctrl-6g-qcm2290 - qcom,gpucc-sdm630 - qcom,gpucc-sdm660 - qcom,lcc-apq8064 From 22f1d06f4f283e36622036726093032a07d67c0d Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 3 Nov 2022 15:27:59 +0530 Subject: [PATCH 168/261] dt-bindings: iio: qcom: adc7-pm8350: Allow specifying SID for channels As per the new ADC7 architecture used by the Qualcomm PMICs, each PMIC has the static Slave ID (SID) assigned by default. The primary PMIC PMK8350 is responsible for collecting the temperature/voltage data from the slave PMICs and exposing them via it's registers. For getting the measurements from the slave PMICs, PMK8350 uses the channel ID encoded with the SID of the relevant PMIC. So far, the dt-binding for the slave PMIC PM8350 assumed that there will be only one PM8350 in a system. So it harcoded SID 1 with channel IDs. But this got changed in platforms such as Lenovo X13s where there are a couple of PM8350 PMICs available. So to address multiple PM8350s, change the binding to accept the SID specified by the user and use it for encoding the channel ID. It should be noted that, even though the SID is static it is not globally unique. Only the primary PMIC has the unique SID id 0. Reviewed-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski Acked-by: Rob Herring Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221103095810.64606-2-manivannan.sadhasivam@linaro.org --- .../bindings/thermal/qcom-spmi-adc-tm5.yaml | 6 +- .../dt-bindings/iio/qcom,spmi-adc7-pm8350.h | 88 +++++++++---------- 2 files changed, 45 insertions(+), 49 deletions(-) diff --git a/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml index feb390d50696..d20569b9b763 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml @@ -222,8 +222,8 @@ examples: qcom,hw-settle-time = <200>; }; - conn-therm@47 { - reg = ; + conn-therm@147 { + reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; }; @@ -247,7 +247,7 @@ examples: conn-therm@1 { reg = <1>; - io-channels = <&pmk8350_vadc PM8350_ADC7_AMUX_THM4_100K_PU>; + io-channels = <&pmk8350_vadc PM8350_ADC7_AMUX_THM4_100K_PU(1)>; qcom,avg-samples = <2>; qcom,ratiometric; qcom,hw-settle-time-us = <200>; diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h b/include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h index 9426f27a1946..09fd169ad18e 100644 --- a/include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h +++ b/include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h @@ -6,62 +6,58 @@ #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H #define _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H -#ifndef PM8350_SID -#define PM8350_SID 1 -#endif - /* ADC channels for PM8350_ADC for PMIC7 */ -#define PM8350_ADC7_REF_GND (PM8350_SID << 8 | 0x0) -#define PM8350_ADC7_1P25VREF (PM8350_SID << 8 | 0x01) -#define PM8350_ADC7_VREF_VADC (PM8350_SID << 8 | 0x02) -#define PM8350_ADC7_DIE_TEMP (PM8350_SID << 8 | 0x03) +#define PM8350_ADC7_REF_GND(sid) ((sid) << 8 | 0x0) +#define PM8350_ADC7_1P25VREF(sid) ((sid) << 8 | 0x01) +#define PM8350_ADC7_VREF_VADC(sid) ((sid) << 8 | 0x02) +#define PM8350_ADC7_DIE_TEMP(sid) ((sid) << 8 | 0x03) -#define PM8350_ADC7_AMUX_THM1 (PM8350_SID << 8 | 0x04) -#define PM8350_ADC7_AMUX_THM2 (PM8350_SID << 8 | 0x05) -#define PM8350_ADC7_AMUX_THM3 (PM8350_SID << 8 | 0x06) -#define PM8350_ADC7_AMUX_THM4 (PM8350_SID << 8 | 0x07) -#define PM8350_ADC7_AMUX_THM5 (PM8350_SID << 8 | 0x08) -#define PM8350_ADC7_GPIO1 (PM8350_SID << 8 | 0x0a) -#define PM8350_ADC7_GPIO2 (PM8350_SID << 8 | 0x0b) -#define PM8350_ADC7_GPIO3 (PM8350_SID << 8 | 0x0c) -#define PM8350_ADC7_GPIO4 (PM8350_SID << 8 | 0x0d) +#define PM8350_ADC7_AMUX_THM1(sid) ((sid) << 8 | 0x04) +#define PM8350_ADC7_AMUX_THM2(sid) ((sid) << 8 | 0x05) +#define PM8350_ADC7_AMUX_THM3(sid) ((sid) << 8 | 0x06) +#define PM8350_ADC7_AMUX_THM4(sid) ((sid) << 8 | 0x07) +#define PM8350_ADC7_AMUX_THM5(sid) ((sid) << 8 | 0x08) +#define PM8350_ADC7_GPIO1(sid) ((sid) << 8 | 0x0a) +#define PM8350_ADC7_GPIO2(sid) ((sid) << 8 | 0x0b) +#define PM8350_ADC7_GPIO3(sid) ((sid) << 8 | 0x0c) +#define PM8350_ADC7_GPIO4(sid) ((sid) << 8 | 0x0d) /* 30k pull-up1 */ -#define PM8350_ADC7_AMUX_THM1_30K_PU (PM8350_SID << 8 | 0x24) -#define PM8350_ADC7_AMUX_THM2_30K_PU (PM8350_SID << 8 | 0x25) -#define PM8350_ADC7_AMUX_THM3_30K_PU (PM8350_SID << 8 | 0x26) -#define PM8350_ADC7_AMUX_THM4_30K_PU (PM8350_SID << 8 | 0x27) -#define PM8350_ADC7_AMUX_THM5_30K_PU (PM8350_SID << 8 | 0x28) -#define PM8350_ADC7_GPIO1_30K_PU (PM8350_SID << 8 | 0x2a) -#define PM8350_ADC7_GPIO2_30K_PU (PM8350_SID << 8 | 0x2b) -#define PM8350_ADC7_GPIO3_30K_PU (PM8350_SID << 8 | 0x2c) -#define PM8350_ADC7_GPIO4_30K_PU (PM8350_SID << 8 | 0x2d) +#define PM8350_ADC7_AMUX_THM1_30K_PU(sid) ((sid) << 8 | 0x24) +#define PM8350_ADC7_AMUX_THM2_30K_PU(sid) ((sid) << 8 | 0x25) +#define PM8350_ADC7_AMUX_THM3_30K_PU(sid) ((sid) << 8 | 0x26) +#define PM8350_ADC7_AMUX_THM4_30K_PU(sid) ((sid) << 8 | 0x27) +#define PM8350_ADC7_AMUX_THM5_30K_PU(sid) ((sid) << 8 | 0x28) +#define PM8350_ADC7_GPIO1_30K_PU(sid) ((sid) << 8 | 0x2a) +#define PM8350_ADC7_GPIO2_30K_PU(sid) ((sid) << 8 | 0x2b) +#define PM8350_ADC7_GPIO3_30K_PU(sid) ((sid) << 8 | 0x2c) +#define PM8350_ADC7_GPIO4_30K_PU(sid) ((sid) << 8 | 0x2d) /* 100k pull-up2 */ -#define PM8350_ADC7_AMUX_THM1_100K_PU (PM8350_SID << 8 | 0x44) -#define PM8350_ADC7_AMUX_THM2_100K_PU (PM8350_SID << 8 | 0x45) -#define PM8350_ADC7_AMUX_THM3_100K_PU (PM8350_SID << 8 | 0x46) -#define PM8350_ADC7_AMUX_THM4_100K_PU (PM8350_SID << 8 | 0x47) -#define PM8350_ADC7_AMUX_THM5_100K_PU (PM8350_SID << 8 | 0x48) -#define PM8350_ADC7_GPIO1_100K_PU (PM8350_SID << 8 | 0x4a) -#define PM8350_ADC7_GPIO2_100K_PU (PM8350_SID << 8 | 0x4b) -#define PM8350_ADC7_GPIO3_100K_PU (PM8350_SID << 8 | 0x4c) -#define PM8350_ADC7_GPIO4_100K_PU (PM8350_SID << 8 | 0x4d) +#define PM8350_ADC7_AMUX_THM1_100K_PU(sid) ((sid) << 8 | 0x44) +#define PM8350_ADC7_AMUX_THM2_100K_PU(sid) ((sid) << 8 | 0x45) +#define PM8350_ADC7_AMUX_THM3_100K_PU(sid) ((sid) << 8 | 0x46) +#define PM8350_ADC7_AMUX_THM4_100K_PU(sid) ((sid) << 8 | 0x47) +#define PM8350_ADC7_AMUX_THM5_100K_PU(sid) ((sid) << 8 | 0x48) +#define PM8350_ADC7_GPIO1_100K_PU(sid) ((sid) << 8 | 0x4a) +#define PM8350_ADC7_GPIO2_100K_PU(sid) ((sid) << 8 | 0x4b) +#define PM8350_ADC7_GPIO3_100K_PU(sid) ((sid) << 8 | 0x4c) +#define PM8350_ADC7_GPIO4_100K_PU(sid) ((sid) << 8 | 0x4d) /* 400k pull-up3 */ -#define PM8350_ADC7_AMUX_THM1_400K_PU (PM8350_SID << 8 | 0x64) -#define PM8350_ADC7_AMUX_THM2_400K_PU (PM8350_SID << 8 | 0x65) -#define PM8350_ADC7_AMUX_THM3_400K_PU (PM8350_SID << 8 | 0x66) -#define PM8350_ADC7_AMUX_THM4_400K_PU (PM8350_SID << 8 | 0x67) -#define PM8350_ADC7_AMUX_THM5_400K_PU (PM8350_SID << 8 | 0x68) -#define PM8350_ADC7_GPIO1_400K_PU (PM8350_SID << 8 | 0x6a) -#define PM8350_ADC7_GPIO2_400K_PU (PM8350_SID << 8 | 0x6b) -#define PM8350_ADC7_GPIO3_400K_PU (PM8350_SID << 8 | 0x6c) -#define PM8350_ADC7_GPIO4_400K_PU (PM8350_SID << 8 | 0x6d) +#define PM8350_ADC7_AMUX_THM1_400K_PU(sid) ((sid) << 8 | 0x64) +#define PM8350_ADC7_AMUX_THM2_400K_PU(sid) ((sid) << 8 | 0x65) +#define PM8350_ADC7_AMUX_THM3_400K_PU(sid) ((sid) << 8 | 0x66) +#define PM8350_ADC7_AMUX_THM4_400K_PU(sid) ((sid) << 8 | 0x67) +#define PM8350_ADC7_AMUX_THM5_400K_PU(sid) ((sid) << 8 | 0x68) +#define PM8350_ADC7_GPIO1_400K_PU(sid) ((sid) << 8 | 0x6a) +#define PM8350_ADC7_GPIO2_400K_PU(sid) ((sid) << 8 | 0x6b) +#define PM8350_ADC7_GPIO3_400K_PU(sid) ((sid) << 8 | 0x6c) +#define PM8350_ADC7_GPIO4_400K_PU(sid) ((sid) << 8 | 0x6d) /* 1/3 Divider */ -#define PM8350_ADC7_GPIO4_DIV3 (PM8350_SID << 8 | 0x8d) +#define PM8350_ADC7_GPIO4_DIV3(sid) ((sid) << 8 | 0x8d) -#define PM8350_ADC7_VPH_PWR (PM8350_SID << 8 | 0x8e) +#define PM8350_ADC7_VPH_PWR(sid) ((sid) << 8 | 0x8e) #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H */ From 6c82f40ec94ed99eb5200fc0d3afe79648078d93 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 3 Nov 2022 15:28:00 +0530 Subject: [PATCH 169/261] arm64: dts: qcom: sc8280xp-pmics: Add temp alarm for PM8280_{1/2} PMICs Add support for temperature alarm feature in the PM8280_{1/2} PMICs. Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221103095810.64606-3-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi index 24836b6b9bbc..5de47b1434a4 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi @@ -33,6 +33,13 @@ pmc8280_1: pmic@1 { #address-cells = <1>; #size-cells = <0>; + pm8280_1_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + pmc8280_1_gpios: gpio@8800 { compatible = "qcom,pm8350-gpio", "qcom,spmi-gpio"; reg = <0x8800>; @@ -78,6 +85,13 @@ pmc8280_2: pmic@3 { #address-cells = <1>; #size-cells = <0>; + pm8280_2_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + pmc8280_2_gpios: gpio@8800 { compatible = "qcom,pm8350-gpio", "qcom,spmi-gpio"; reg = <0x8800>; From 448a7821daa1bb12ec0978694cd0e77be3d9663b Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 3 Nov 2022 15:28:01 +0530 Subject: [PATCH 170/261] arm64: dts: qcom: sc8280xp-pmics: Add thermal zones for PM8280_{1/2} PMICs Add thermal zones for the PM8280_{1/2} PMICs by using the temperature alarm blocks as the thermal sensors. Temperature trip points are inherited from PM8350 PMIC. Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221103095810.64606-4-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi | 44 ++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi index 5de47b1434a4..397ff4995003 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi @@ -7,6 +7,50 @@ #include #include +/ { + thermal-zones { + pm8280_1_thermal: pm8280-1-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pm8280_1_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pm8280_2_thermal: pm8280-2-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pm8280_2_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + &spmi_bus { pmk8280: pmic@0 { compatible = "qcom,pmk8350", "qcom,spmi-pmic"; From 34bd6d227ffc99d8ce1ced20bbfceacb14651869 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 3 Nov 2022 15:28:02 +0530 Subject: [PATCH 171/261] arm64: dts: qcom: sc8280xp-pmics: Add support for PMK8280 RESIN input The RESIN input can be used to reset the PMK8280 PMIC. Enabling the RESIN block allows the PMK8280 to detect reset input via RESIN_N pin. Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221103095810.64606-5-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi index 397ff4995003..4a3464f5e6e9 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi @@ -68,6 +68,12 @@ pmk8280_pon_pwrkey: pwrkey { linux,code = ; status = "disabled"; }; + + pmk8280_pon_resin: resin { + compatible = "qcom,pmk8350-resin"; + interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; + status = "disabled"; + }; }; }; From e0f681f7294a9899dbae897f31720efc30807582 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 3 Nov 2022 15:28:03 +0530 Subject: [PATCH 172/261] arm64: dts: qcom: sc8280xp-pmics: Add PMK8280 ADC7 block Add support for ADC7 block available in PMK8280 for reading the temperature via the AMUX pins. Reviewed-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221103095810.64606-6-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi index 4a3464f5e6e9..b1cdde2f7861 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi @@ -75,6 +75,16 @@ pmk8280_pon_resin: resin { status = "disabled"; }; }; + + pmk8280_vadc: adc@3100 { + compatible = "qcom,spmi-adc7"; + reg = <0x3100>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + status = "disabled"; + }; }; pmc8280_1: pmic@1 { From 5cd549c7e7cd55453e0c0d4f2c1f51d071061451 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 3 Nov 2022 15:28:04 +0530 Subject: [PATCH 173/261] arm64: dts: qcom: sc8280xp-pmics: Add support for TM5 block in PMK8280 Thermal Monitoring block ADC5 (TM5) in PMK8280 can be used to monitor the temperature from secondary PMICs like PM8280. Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221103095810.64606-7-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi index b1cdde2f7861..f2c0b71b5d8e 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi @@ -85,6 +85,16 @@ pmk8280_vadc: adc@3100 { #io-channel-cells = <1>; status = "disabled"; }; + + pmk8280_adc_tm: adc-tm@3400 { + compatible = "qcom,spmi-adc-tm5-gen2"; + reg = <0x3400>; + interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #thermal-sensor-cells = <1>; + status = "disabled"; + }; }; pmc8280_1: pmic@1 { From 7858c676c8b243941d1539c6e2619c1713292025 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 3 Nov 2022 15:28:05 +0530 Subject: [PATCH 174/261] arm64: dts: qcom: sc8280xp-x13s: Enable PMK8280 RESIN input Enable resetting the PMK8280 through RESIN block in SC8280XP X13s. Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221103095810.64606-8-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 68b61e8d03c0..0a332031f0d9 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -169,6 +169,10 @@ &pmk8280_pon_pwrkey { status = "okay"; }; +&pmk8280_pon_resin { + status = "okay"; +}; + &qup0 { status = "okay"; }; From 9a6b3042c5337141a2ad202c6e6a28e4e0440c29 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 3 Nov 2022 15:28:06 +0530 Subject: [PATCH 175/261] arm64: dts: qcom: sc8280xp-x13s: Add PMK8280 VADC channels Add VADC channels for measuring the on-chip die temperature and external crystal osciallator temperature of PMK8280. Reviewed-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221103095810.64606-9-manivannan.sadhasivam@linaro.org --- .../dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 0a332031f0d9..ee4b82a54cba 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -7,6 +7,7 @@ /dts-v1/; #include +#include #include #include "sc8280xp.dtsi" @@ -173,6 +174,21 @@ &pmk8280_pon_resin { status = "okay"; }; +&pmk8280_vadc { + status = "okay"; + + pmic-die-temp@3 { + reg = ; + qcom,pre-scaling = <1 1>; + }; + + xo-therm@44 { + reg = ; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + }; +}; + &qup0 { status = "okay"; }; From 3375151a71855d44edf4ff78aedac6d5272525ff Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 3 Nov 2022 15:28:07 +0530 Subject: [PATCH 176/261] arm64: dts: qcom: sc8280xp-x13s: Add PM8280_{1/2} VADC channels Add VADC channels of PM8280_{1/2} PMICs for measuring the on-chip die temperature and external thermistors connected to the AMUX pins. The measurements are collected by the primary PMIC PMK8280 from the secondary PMICs PM8280_{1/2} and exposed over the PMK8280's VADC channels. Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221103095810.64606-10-manivannan.sadhasivam@linaro.org --- .../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index ee4b82a54cba..665aad7a941a 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -7,6 +7,7 @@ /dts-v1/; #include +#include #include #include @@ -187,6 +188,64 @@ xo-therm@44 { qcom,hw-settle-time = <200>; qcom,ratiometric; }; + + pmic-die-temp@103 { + reg = ; + qcom,pre-scaling = <1 1>; + }; + + sys-therm@144 { + reg = ; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + }; + + sys-therm@145 { + reg = ; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + }; + + sys-therm@146 { + reg = ; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + }; + + sys-therm@147 { + reg = ; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + }; + + pmic-die-temp@303 { + reg = ; + qcom,pre-scaling = <1 1>; + }; + + sys-therm@344 { + reg = ; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + }; + + sys-therm@345 { + reg = ; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + }; + + sys-therm@346 { + reg = ; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + }; + + sys-therm@347 { + reg = ; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + }; }; &qup0 { From 9d41cd17394aca9ce3e00ab52edfa35f1848d2b3 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 3 Nov 2022 15:28:08 +0530 Subject: [PATCH 177/261] arm64: dts: qcom: sc8280xp-x13s: Add PMR735A VADC channel Add VADC channel of PMR735A for measuring the on-chip die temperature. Reviewed-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221103095810.64606-11-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 665aad7a941a..d1964bec9636 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -9,6 +9,7 @@ #include #include #include +#include #include #include "sc8280xp.dtsi" @@ -246,6 +247,11 @@ sys-therm@347 { qcom,hw-settle-time = <200>; qcom,ratiometric; }; + + pmic-die-temp@403 { + reg = ; + qcom,pre-scaling = <1 1>; + }; }; &qup0 { From 7c0151347401a55f98afa640f741f70e411ce685 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 3 Nov 2022 15:28:09 +0530 Subject: [PATCH 178/261] arm64: dts: qcom: sc8280xp-x13s: Add PM8280_{1/2} ADC_TM5 channels Add ADC_TM5 channels of PM8280_{1/2} for monitoring the temperature from external thermistors connected to AMUX pins. The temperature measurements are collected from the PMK8280's VADC channels that expose the measurements from secondary PMICs PM8280_{1/2}. Reviewed-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221103095810.64606-12-manivannan.sadhasivam@linaro.org --- .../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index d1964bec9636..6d96f0b54880 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -168,6 +168,74 @@ &pmc8280c_lpg { status = "okay"; }; +&pmk8280_adc_tm { + status = "okay"; + + sys-therm@0 { + reg = <0>; + io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM1_100K_PU(1)>; + qcom,hw-settle-time-us = <200>; + qcom,avg-samples = <2>; + qcom,ratiometric; + }; + + sys-therm@1 { + reg = <1>; + io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM2_100K_PU(1)>; + qcom,hw-settle-time-us = <200>; + qcom,avg-samples = <2>; + qcom,ratiometric; + }; + + sys-therm@2 { + reg = <2>; + io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM3_100K_PU(1)>; + qcom,hw-settle-time-us = <200>; + qcom,avg-samples = <2>; + qcom,ratiometric; + }; + + sys-therm@3 { + reg = <3>; + io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM4_100K_PU(1)>; + qcom,hw-settle-time-us = <200>; + qcom,avg-samples = <2>; + qcom,ratiometric; + }; + + sys-therm@4 { + reg = <4>; + io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM1_100K_PU(3)>; + qcom,hw-settle-time-us = <200>; + qcom,avg-samples = <2>; + qcom,ratiometric; + }; + + sys-therm@5 { + reg = <5>; + io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM2_100K_PU(3)>; + qcom,hw-settle-time-us = <200>; + qcom,avg-samples = <2>; + qcom,ratiometric; + }; + + sys-therm@6 { + reg = <6>; + io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM3_100K_PU(3)>; + qcom,hw-settle-time-us = <200>; + qcom,avg-samples = <2>; + qcom,ratiometric; + }; + + sys-therm@7 { + reg = <7>; + io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM4_100K_PU(3)>; + qcom,hw-settle-time-us = <200>; + qcom,avg-samples = <2>; + qcom,ratiometric; + }; +}; + &pmk8280_pon_pwrkey { status = "okay"; }; From 31863c523ac5bd2b0fe0857c6405a7431c59d653 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 3 Nov 2022 15:28:10 +0530 Subject: [PATCH 179/261] arm64: dts: qcom: sc8280xp-x13s: Add thermal zone support Add thermal zone support by making use of the thermistor SYS_THERM6. Based on experiments, this thermistor seems to reflect the actual surface temperature of the laptop. For the cooling device, all BIG CPU cores are throttled down to keep the temperature at a sane level. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221103095810.64606-13-manivannan.sadhasivam@linaro.org --- .../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 6d96f0b54880..66ca0136eb96 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -29,6 +29,52 @@ backlight { pinctrl-0 = <&edp_bl_en>, <&edp_bl_pwm>; }; + thermal-zones { + skin-temp-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + thermal-sensors = <&pmk8280_adc_tm 5>; + + trips { + skin_temp_alert0: trip-point0 { + temperature = <55000>; + hysteresis = <1000>; + type = "passive"; + }; + + skin_temp_alert1: trip-point1 { + temperature = <58000>; + hysteresis = <1000>; + type = "passive"; + }; + + skin-temp-crit { + temperature = <73000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&skin_temp_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map1 { + trip = <&skin_temp_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + vreg_edp_bl: regulator-edp-bl { compatible = "regulator-fixed"; From bb9f23e46ddcebe1bc68a43a0f7acfc1865a6472 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 26 Oct 2022 17:25:10 +0200 Subject: [PATCH 180/261] arm64: dts: qcom: sm8250: drop bogus DP PHY clock The QMP pipe clock is used by the USB part of the PHY so drop the corresponding properties from the DP child node. Fixes: 5aa0d1becd5b ("arm64: dts: qcom: sm8250: switch usb1 qmp phy to USB3+DP mode") Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221026152511.9661-2-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 6b6a7277db5e..076c161d76f6 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2897,9 +2897,6 @@ dp_phy: dp-phy@88ea200 { <0 0x088eaa00 0 0x100>; #phy-cells = <0>; #clock-cells = <1>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_phy_pipe_clk_src"; }; }; From 95fade4016cbd57ee050ab226c8f0483af1753c4 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 26 Oct 2022 17:25:11 +0200 Subject: [PATCH 181/261] arm64: dts: qcom: sm6350: drop bogus DP PHY clock The QMP pipe clock is used by the USB part of the PHY so drop the corresponding properties from the DP child node. Fixes: 23737b9557fe ("arm64: dts: qcom: sm6350: Add USB1 nodes") Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221026152511.9661-3-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index c39de7d3ace0..3a315280c34a 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1154,9 +1154,6 @@ dp_phy: dp-phy@88ea200 { <0 0x088eaa00 0 0x100>; #phy-cells = <0>; #clock-cells = <1>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_phy_pipe_clk_src"; }; }; From 42582b27dcb1cb60f3601ecac07d3564ce7dc378 Mon Sep 17 00:00:00 2001 From: Manikanta Pubbisetty Date: Mon, 17 Oct 2022 18:23:46 +0530 Subject: [PATCH 182/261] arm64: dts: qcom: sc7280: Add nodes to support WoW on WCN6750 Add DT nodes to support WoW (Wake on Wireless) feature on WCN6750 WiFi hardware on SC7280 SoC. Signed-off-by: Manikanta Pubbisetty Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221017125346.3691-3-quic_mpubbise@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 907f5f74cd4c..7878ae0a216e 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -752,6 +752,17 @@ wpss_smp2p_in: slave-kernel { interrupt-controller; #interrupt-cells = <2>; }; + + wlan_smp2p_out: wlan-ap-to-wpss { + qcom,entry-name = "wlan"; + #qcom,smem-state-cells = <1>; + }; + + wlan_smp2p_in: wlan-wpss-to-ap { + qcom,entry-name = "wlan"; + interrupt-controller; + #interrupt-cells = <2>; + }; }; pmu { @@ -2036,6 +2047,8 @@ wifi: wifi@17a10040 { qcom,rproc = <&remoteproc_wpss>; memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; status = "disabled"; + qcom,smem-states = <&wlan_smp2p_out 0>; + qcom,smem-state-names = "wlan-smp2p-out"; }; pcie1: pci@1c08000 { From 5d76dfb86850893f2506e15a1dc68977c3adc79f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 18 Oct 2022 11:54:48 -0400 Subject: [PATCH 183/261] arm64: dts: qcom: msm8994: Correct SPI10 CS pin The GPIO55 is part of SPI10 pins, not its chip-select. Probably the intention was to use one of dedicated chip-select GPIOs: 47 or 67. GPIO47 is used for UART2, so choose GPIO67. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221018155450.39816-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index ded5b7ceeaf9..7a582a5fe3a8 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -897,7 +897,7 @@ default { }; cs { function = "gpio"; - pins = "gpio55"; + pins = "gpio67"; drive-strength = <2>; bias-disable; }; From 9d7d01da9a24a8e37fa156d93dbea893a0665f94 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 18 Oct 2022 11:54:49 -0400 Subject: [PATCH 184/261] arm64: dts: qcom: msm8994: Align TLMM pin configuration with DT schema DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. Order the "function" and "pins" property to match other DTS. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221018155450.39816-2-krzysztof.kozlowski@linaro.org --- .../dts/qcom/msm8994-msft-lumia-octagon.dtsi | 8 +- .../qcom/msm8994-sony-xperia-kitakami.dtsi | 6 +- arch/arm64/boot/dts/qcom/msm8994.dtsi | 148 +++++++++--------- 3 files changed, 83 insertions(+), 79 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi index d8d732ec1b73..9b67f0d3820c 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi @@ -881,28 +881,28 @@ &sdhc2 { }; &tlmm { - grip_default: grip-default { + grip_default: grip-default-state { pins = "gpio39"; function = "gpio"; drive-strength = <6>; bias-pull-down; }; - grip_sleep: grip-sleep { + grip_sleep: grip-sleep-state { pins = "gpio39"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; - hall_front_default: hall-front-default { + hall_front_default: hall-front-default-state { pins = "gpio42"; function = "gpio"; drive-strength = <2>; bias-disable; }; - hall_back_default: hall-back-default { + hall_back_default: hall-back-default-state { pins = "gpio75"; function = "gpio"; drive-strength = <2>; diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi index 0c2680ff22a4..f3d153c34918 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi @@ -477,15 +477,17 @@ &sdhc2 { }; &tlmm { - ts_int_active: ts-int-active { + ts_int_active: ts-int-active-state { pins = "gpio42"; + function = "gpio"; drive-strength = <2>; bias-disable; input-enable; }; - ts_reset_active: ts-reset-active { + ts_reset_active: ts-reset-active-state { pins = "gpio109"; + function = "gpio"; drive-strength = <2>; bias-disable; output-low; diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 7a582a5fe3a8..ba687e64ba3c 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -773,254 +773,256 @@ tlmm: pinctrl@fd510000 { interrupt-controller; #interrupt-cells = <2>; - blsp1_uart2_default: blsp1-uart2-default { - function = "blsp_uart2"; + blsp1_uart2_default: blsp1-uart2-default-state { pins = "gpio4", "gpio5"; + function = "blsp_uart2"; drive-strength = <16>; bias-disable; }; - blsp1_uart2_sleep: blsp1-uart2-sleep { - function = "gpio"; + blsp1_uart2_sleep: blsp1-uart2-sleep-state { pins = "gpio4", "gpio5"; + function = "gpio"; drive-strength = <2>; bias-pull-down; }; - blsp2_uart2_default: blsp2-uart2-default { + blsp2_uart2_default: blsp2-uart2-default-state { + pins = "gpio45", "gpio46", "gpio47", "gpio48"; function = "blsp_uart8"; - pins = "gpio45", "gpio46", - "gpio47", "gpio48"; drive-strength = <16>; bias-disable; }; - blsp2_uart2_sleep: blsp2-uart2-sleep { + blsp2_uart2_sleep: blsp2-uart2-sleep-state { + pins = "gpio45", "gpio46", "gpio47", "gpio48"; function = "gpio"; - pins = "gpio45", "gpio46", - "gpio47", "gpio48"; drive-strength = <2>; bias-disable; }; - i2c1_default: i2c1-default { + i2c1_default: i2c1-default-state { + pins = "gpio2", "gpio3"; function = "blsp_i2c1"; - pins = "gpio2", "gpio3"; drive-strength = <2>; bias-disable; }; - i2c1_sleep: i2c1-sleep { + i2c1_sleep: i2c1-sleep-state { + pins = "gpio2", "gpio3"; function = "gpio"; - pins = "gpio2", "gpio3"; drive-strength = <2>; bias-disable; }; - i2c2_default: i2c2-default { + i2c2_default: i2c2-default-state { + pins = "gpio6", "gpio7"; function = "blsp_i2c2"; - pins = "gpio6", "gpio7"; drive-strength = <2>; bias-disable; }; - i2c2_sleep: i2c2-sleep { + i2c2_sleep: i2c2-sleep-state { + pins = "gpio6", "gpio7"; function = "gpio"; - pins = "gpio6", "gpio7"; drive-strength = <2>; bias-disable; }; - i2c4_default: i2c4-default { + i2c4_default: i2c4-default-state { + pins = "gpio19", "gpio20"; function = "blsp_i2c4"; - pins = "gpio19", "gpio20"; drive-strength = <2>; bias-disable; }; - i2c4_sleep: i2c4-sleep { - function = "gpio"; + i2c4_sleep: i2c4-sleep-state { pins = "gpio19", "gpio20"; + function = "gpio"; drive-strength = <2>; bias-pull-down; input-enable; }; - i2c5_default: i2c5-default { + i2c5_default: i2c5-default-state { + pins = "gpio23", "gpio24"; function = "blsp_i2c5"; - pins = "gpio23", "gpio24"; drive-strength = <2>; bias-disable; }; - i2c5_sleep: i2c5-sleep { + i2c5_sleep: i2c5-sleep-state { + pins = "gpio23", "gpio24"; function = "gpio"; - pins = "gpio23", "gpio24"; drive-strength = <2>; bias-disable; }; - i2c6_default: i2c6-default { + i2c6_default: i2c6-default-state { + pins = "gpio28", "gpio27"; function = "blsp_i2c6"; - pins = "gpio28", "gpio27"; drive-strength = <2>; bias-disable; }; - i2c6_sleep: i2c6-sleep { + i2c6_sleep: i2c6-sleep-state { + pins = "gpio28", "gpio27"; function = "gpio"; - pins = "gpio28", "gpio27"; drive-strength = <2>; bias-disable; }; - i2c7_default: i2c7-default { + i2c7_default: i2c7-default-state { + pins = "gpio44", "gpio43"; function = "blsp_i2c7"; - pins = "gpio44", "gpio43"; drive-strength = <2>; bias-disable; }; - i2c7_sleep: i2c7-sleep { + i2c7_sleep: i2c7-sleep-state { + pins = "gpio44", "gpio43"; function = "gpio"; - pins = "gpio44", "gpio43"; drive-strength = <2>; bias-disable; }; - blsp2_spi10_default: blsp2-spi10-default { - default { - function = "blsp_spi10"; + blsp2_spi10_default: blsp2-spi10-default-state { + default-pins { pins = "gpio53", "gpio54", "gpio55"; + function = "blsp_spi10"; drive-strength = <10>; bias-pull-down; }; - cs { - function = "gpio"; + + cs-pins { pins = "gpio67"; + function = "gpio"; drive-strength = <2>; bias-disable; }; }; - blsp2_spi10_sleep: blsp2-spi10-sleep { + blsp2_spi10_sleep: blsp2-spi10-sleep-state { pins = "gpio53", "gpio54", "gpio55"; - drive-strength = <2>; - bias-disable; - }; - - i2c11_default: i2c11-default { - function = "blsp_i2c11"; - pins = "gpio83", "gpio84"; - drive-strength = <2>; - bias-disable; - }; - - i2c11_sleep: i2c11-sleep { function = "gpio"; - pins = "gpio83", "gpio84"; drive-strength = <2>; bias-disable; }; - blsp1_spi1_default: blsp1-spi1-default { - default { - function = "blsp_spi1"; + i2c11_default: i2c11-default-state { + pins = "gpio83", "gpio84"; + function = "blsp_i2c11"; + drive-strength = <2>; + bias-disable; + }; + + i2c11_sleep: i2c11-sleep-state { + pins = "gpio83", "gpio84"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_spi1_default: blsp1-spi1-default-state { + default-pins { pins = "gpio0", "gpio1", "gpio3"; + function = "blsp_spi1"; drive-strength = <10>; bias-pull-down; }; - cs { - function = "gpio"; + + cs-pins { pins = "gpio8"; + function = "gpio"; drive-strength = <2>; bias-disable; }; }; - blsp1_spi1_sleep: blsp1-spi1-sleep { + blsp1_spi1_sleep: blsp1-spi1-sleep-state { pins = "gpio0", "gpio1", "gpio3"; + function = "gpio"; drive-strength = <2>; bias-disable; }; - sdc1_clk_on: clk-on { + sdc1_clk_on: clk-on-state { pins = "sdc1_clk"; bias-disable; drive-strength = <16>; }; - sdc1_clk_off: clk-off { + sdc1_clk_off: clk-off-state { pins = "sdc1_clk"; bias-disable; drive-strength = <2>; }; - sdc1_cmd_on: cmd-on { + sdc1_cmd_on: cmd-on-state { pins = "sdc1_cmd"; bias-pull-up; drive-strength = <8>; }; - sdc1_cmd_off: cmd-off { + sdc1_cmd_off: cmd-off-state { pins = "sdc1_cmd"; bias-pull-up; drive-strength = <2>; }; - sdc1_data_on: data-on { + sdc1_data_on: data-on-state { pins = "sdc1_data"; bias-pull-up; drive-strength = <8>; }; - sdc1_data_off: data-off { + sdc1_data_off: data-off-state { pins = "sdc1_data"; bias-pull-up; drive-strength = <2>; }; - sdc1_rclk_on: rclk-on { + sdc1_rclk_on: rclk-on-state { pins = "sdc1_rclk"; bias-pull-down; }; - sdc1_rclk_off: rclk-off { + sdc1_rclk_off: rclk-off-state { pins = "sdc1_rclk"; bias-pull-down; }; - sdc2_clk_on: sdc2-clk-on { + sdc2_clk_on: sdc2-clk-on-state { pins = "sdc2_clk"; bias-disable; drive-strength = <10>; }; - sdc2_clk_off: sdc2-clk-off { + sdc2_clk_off: sdc2-clk-off-state { pins = "sdc2_clk"; bias-disable; drive-strength = <2>; }; - sdc2_cmd_on: sdc2-cmd-on { + sdc2_cmd_on: sdc2-cmd-on-state { pins = "sdc2_cmd"; bias-pull-up; drive-strength = <10>; }; - sdc2_cmd_off: sdc2-cmd-off { + sdc2_cmd_off: sdc2-cmd-off-state { pins = "sdc2_cmd"; bias-pull-up; drive-strength = <2>; }; - sdc2_data_on: sdc2-data-on { + sdc2_data_on: sdc2-data-on-state { pins = "sdc2_data"; bias-pull-up; drive-strength = <10>; }; - sdc2_data_off: sdc2-data-off { + sdc2_data_off: sdc2-data-off-state { pins = "sdc2_data"; bias-pull-up; drive-strength = <2>; From a35ef6df1e61cba41a5266303f6a493d1a71b06b Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 25 Oct 2022 11:07:03 -0700 Subject: [PATCH 185/261] arm64: dts: qcom: Remove fingerprint node from herobrine-r1 It turns out that only a few people have the fingerprint sensor hooked up on their board. Leaving this enabled is slowing down boot for everyone else because the driver slowly fails to probe while trying to communicate with a sensor that isn't there. Remove the node to speed up boot, developers with the board can manually enable it themselves. Reported-by: Douglas Anderson Signed-off-by: Stephen Boyd Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221025180703.1806234-1-swboyd@chromium.org --- arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts index 977dfcd9814f..b04888a98203 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts @@ -48,10 +48,6 @@ &pp1200_wf_cam { /* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ -&ap_spi_fp { - status = "okay"; -}; - /* * Although the trackpad is really part of the herobrine baseboard, we'll * put the actual definition in the board device tree since different boards From bcfefc98c5781ee97f1b7a8063870830d9e42b30 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Tue, 25 Oct 2022 16:52:39 -0700 Subject: [PATCH 186/261] arm64: dts: qcom: sc7280: Villager doesn't have NVME The sc7280-herobrine-villager derivative doesn't have NVME enabled so we shouldn't mark the PCIe nodes as "okay" since they're just for boards that have NVME. Signed-off-by: Douglas Anderson Reviewed-by: Stephen Boyd Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221025164915.1.I38e2545eda2b3bd3fef6b41c98f451e32851ae70@changeid --- .../arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi index 3dff610fb946..17553e0fd6fd 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi @@ -78,16 +78,6 @@ &mdss_edp_phy { status = "okay"; }; -/* For nvme */ -&pcie1 { - status = "okay"; -}; - -/* For nvme */ -&pcie1_phy { - status = "okay"; -}; - &pwmleds { status = "okay"; }; From 16c0c46f38183573de5361d278772cfed2090b1c Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 28 Oct 2022 09:54:04 +0200 Subject: [PATCH 187/261] arm64: dts: qcom: pm6350: add temp sensor and thermal zone config MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add temp-alarm device tree node and a default configuration for the corresponding thermal zone for this PMIC. Temperatures are based on downstream values, except for trip2 where 125°C is used instead of 145°C due to limitations without a configured ADC. Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221028075405.124809-1-luca.weiss@fairphone.com --- arch/arm64/boot/dts/qcom/pm6350.dtsi | 38 ++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm6350.dtsi b/arch/arm64/boot/dts/qcom/pm6350.dtsi index 18c14257e2c1..a58273664cef 100644 --- a/arch/arm64/boot/dts/qcom/pm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6350.dtsi @@ -5,6 +5,37 @@ #include +/ { + thermal-zones { + pm6350-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pm6350_temp>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + &spmi_bus { pmic@0 { compatible = "qcom,pm6350", "qcom,spmi-pmic"; @@ -35,6 +66,13 @@ pm6350_resin: resin { }; }; + pm6350_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + pm6350_gpios: gpio@c000 { compatible = "qcom,pm6350-gpio", "qcom,spmi-gpio"; reg = <0xc000>; From ce1b5eb74b3ef042b1c797f04e8683e7cad34ae6 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 28 Oct 2022 09:54:05 +0200 Subject: [PATCH 188/261] arm64: dts: qcom: pm6150l: add temp sensor and thermal zone config MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add temp-alarm device tree node and a default configuration for the corresponding thermal zone for this PMIC. Temperatures are based on downstream values, except for trip2 where 125°C is used instead of 145°C due to limitations without a configured ADC. Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221028075405.124809-2-luca.weiss@fairphone.com --- arch/arm64/boot/dts/qcom/pm6150l.dtsi | 38 +++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm6150l.dtsi b/arch/arm64/boot/dts/qcom/pm6150l.dtsi index 8a7c18b134c7..0cf99a53a309 100644 --- a/arch/arm64/boot/dts/qcom/pm6150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150l.dtsi @@ -5,6 +5,37 @@ #include #include +/ { + thermal-zones { + pm6150l-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&pm6150l_temp>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + &spmi_bus { pm6150l_lsid4: pmic@4 { compatible = "qcom,pm6150l", "qcom,spmi-pmic"; @@ -12,6 +43,13 @@ pm6150l_lsid4: pmic@4 { #address-cells = <1>; #size-cells = <0>; + pm6150l_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + pm6150l_adc: adc@3100 { compatible = "qcom,spmi-adc5"; reg = <0x3100>; From e10d451e10418f12e72ed8564f22fdba8b10a9b0 Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Sun, 30 Oct 2022 08:32:23 +0100 Subject: [PATCH 189/261] arm64: dts: qcom: sm6350: Add resets for SDHCI 1/2 Make sure the SDHCI hardware is properly reset before interacting with it, to protect against any possibly indeterminate state left by the bootloader. Suggested-by: Konrad Dybcio Signed-off-by: Marijn Suijten Reviewed-by: Konrad Dybcio Reviewed-by: Luca Weiss Tested-by: Luca Weiss # sm7225-fairphone-fp4 Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221030073232.22726-2-marijn.suijten@somainline.org --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 3a315280c34a..2806194e6959 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -490,6 +490,7 @@ sdhc_1: mmc@7c4000 { <&gcc GCC_SDCC1_APPS_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", "core", "xo"; + resets = <&gcc GCC_SDCC1_BCR>; qcom,dll-config = <0x000f642c>; qcom,ddr-config = <0x80040868>; power-domains = <&rpmhpd SM6350_CX>; @@ -1068,6 +1069,7 @@ sdhc_2: mmc@8804000 { <&gcc GCC_SDCC2_APPS_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", "core", "xo"; + resets = <&gcc GCC_SDCC2_BCR>; interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>; interconnect-names = "sdhc-ddr", "cpu-sdhc"; From a5d0314b9d5166503e99336bb832b3b81b200399 Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Sun, 30 Oct 2022 08:32:24 +0100 Subject: [PATCH 190/261] arm64: dts: qcom: sm6350: Add pinctrl for SDHCI 2 Use the generic pin functions specifically for sdc2. Signed-off-by: Marijn Suijten Acked-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Reviewed-by: Luca Weiss Tested-by: Luca Weiss # sm7225-fairphone-fp4 Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221030073232.22726-3-marijn.suijten@somainline.org --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 44 ++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 2806194e6959..f0e7304764bd 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1074,6 +1074,10 @@ sdhc_2: mmc@8804000 { <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>; interconnect-names = "sdhc-ddr", "cpu-sdhc"; + pinctrl-0 = <&sdc2_on_state>; + pinctrl-1 = <&sdc2_off_state>; + pinctrl-names = "default", "sleep"; + qcom,dll-config = <0x0007642c>; qcom,ddr-config = <0x80040868>; power-domains = <&rpmhpd SM6350_CX>; @@ -1313,6 +1317,46 @@ tlmm: pinctrl@f100000 { #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 157>; + sdc2_off_state: sdc2-off-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + sdc2_on_state: sdc2-on-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <10>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + qup_uart9_default: qup-uart9-default-state { pins = "gpio25", "gpio26"; function = "qup13_f2"; From edf070fcbcec70765fe520d476fd9527b5e96477 Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Sun, 30 Oct 2022 08:32:25 +0100 Subject: [PATCH 191/261] arm64: dts: qcom: sm6350-lena: Add SD Card Detect to sdc2 on/off pinctrl In addition to the sdc2 pins, set the SD Card Detect pin in a sane state to be used as an interrupt when an SD Card is slotted in or removed. Signed-off-by: Marijn Suijten Acked-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221030073232.22726-4-marijn.suijten@somainline.org --- .../qcom/sm6350-sony-xperia-lena-pdx213.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts index 36911b9a5c04..9a96000fc95b 100644 --- a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts +++ b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts @@ -30,6 +30,24 @@ framebuffer: framebuffer@a0000000 { }; }; +&sdc2_off_state { + sd-cd-pins { + pins = "gpio94"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&sdc2_on_state { + sd-cd-pins { + pins = "gpio94"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; +}; + &sdhc_2 { status = "okay"; From f6e2d6914c7c095660a9c7c503328eebab1e2557 Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Sun, 30 Oct 2022 08:32:26 +0100 Subject: [PATCH 192/261] arm64: dts: qcom: pm6350: Include header for KEY_POWER Make pm6350.dtsi self-contained by including input.h, needed for the KEY_POWER constant used to define the power key. Fixes: d8a3c775d7cd ("arm64: dts: qcom: Add PM6350 PMIC") Signed-off-by: Marijn Suijten Reviewed-by: Konrad Dybcio Reviewed-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221030073232.22726-5-marijn.suijten@somainline.org --- arch/arm64/boot/dts/qcom/pm6350.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/pm6350.dtsi b/arch/arm64/boot/dts/qcom/pm6350.dtsi index a58273664cef..3a2a841e83f1 100644 --- a/arch/arm64/boot/dts/qcom/pm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6350.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2021, Luca Weiss */ +#include #include / { From 2b8bbe985659e640fda30435c187432c0f614f81 Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Sun, 30 Oct 2022 08:32:27 +0100 Subject: [PATCH 193/261] arm64: dts: qcom: sm6350-lena: Include pm6350 and configure buttons Include pm6350 to inherit its GPIO and button configuration, and configure "resin" to serve as volume up, and gpio2 as volume down. Signed-off-by: Marijn Suijten Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221030073232.22726-6-marijn.suijten@somainline.org --- .../qcom/sm6350-sony-xperia-lena-pdx213.dts | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts index 9a96000fc95b..4512b0bf7fe1 100644 --- a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts +++ b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts @@ -4,7 +4,9 @@ */ /dts-v1/; +#include #include "sm6350.dtsi" +#include "pm6350.dtsi" / { model = "Sony Xperia 10 III"; @@ -28,6 +30,35 @@ framebuffer: framebuffer@a0000000 { clocks = <&gcc GCC_DISP_AXI_CLK>; }; }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_state>; + + key-volume-down { + label = "volume_down"; + linux,code = ; + gpios = <&pm6350_gpios 2 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&pm6350_gpios { + gpio_keys_state: gpio-keys-state { + key-volume-down-pins { + pins = "gpio2"; + function = PMIC_GPIO_FUNC_NORMAL; + power-source = <0>; + bias-disable; + input-enable; + }; + }; +}; + +&pm6350_resin { + linux,code = ; + status = "okay"; }; &sdc2_off_state { From deaf8c88db7d327ba768ac224e53d29f56027331 Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Sun, 30 Oct 2022 08:32:28 +0100 Subject: [PATCH 194/261] arm64: dts: qcom: sm6350-lena: Define pm6350 and pm6150l regulators This regulator configuration was adopted from downstream, and is identical to the sm7225 FairPhone 4 configuration bar pm6350_l8a. Signed-off-by: Marijn Suijten Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221030073232.22726-7-marijn.suijten@somainline.org --- .../qcom/sm6350-sony-xperia-lena-pdx213.dts | 218 ++++++++++++++++++ 1 file changed, 218 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts index 4512b0bf7fe1..1aaa9612b061 100644 --- a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts +++ b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts @@ -5,6 +5,7 @@ /dts-v1/; #include +#include #include "sm6350.dtsi" #include "pm6350.dtsi" @@ -44,6 +45,223 @@ key-volume-down { }; }; +&apps_rsc { + regulators-0 { + compatible = "qcom,pm6350-rpmh-regulators"; + qcom,pmic-id = "a"; + + pm6350_s1: smps1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + pm6350_s2: smps2 { + regulator-min-microvolt = <1503000>; + regulator-max-microvolt = <2048000>; + regulator-initial-mode = ; + }; + + pm6350_l2: ldo2 { + regulator-min-microvolt = <1503000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = ; + }; + + pm6350_l3: ldo3 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + pm6350_l4: ldo4 { + regulator-min-microvolt = <352000>; + regulator-max-microvolt = <801000>; + regulator-initial-mode = ; + }; + + pm6350_l5: ldo5 { + regulator-min-microvolt = <1503000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = ; + }; + + pm6350_l6: ldo6 { + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + pm6350_l7: ldo7 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = ; + }; + + pm6350_l8: ldo8 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + pm6350_l9: ldo9 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3401000>; + regulator-initial-mode = ; + }; + + pm6350_l11: ldo11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + pm6350_l12: ldo12 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = ; + }; + + pm6350_l13: ldo13 { + regulator-min-microvolt = <570000>; + regulator-max-microvolt = <650000>; + regulator-initial-mode = ; + }; + + pm6350_l14: ldo14 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + regulator-initial-mode = ; + }; + + pm6350_l15: ldo15 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1305000>; + regulator-initial-mode = ; + }; + + pm6350_l16: ldo16 { + regulator-min-microvolt = <830000>; + regulator-max-microvolt = <921000>; + regulator-initial-mode = ; + }; + + pm6350_l18: ldo18 { + regulator-min-microvolt = <788000>; + regulator-max-microvolt = <1049000>; + regulator-initial-mode = ; + }; + + pm6350_l19: ldo19 { + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1305000>; + regulator-initial-mode = ; + }; + + pm6350_l20: ldo20 { + regulator-min-microvolt = <530000>; + regulator-max-microvolt = <801000>; + regulator-initial-mode = ; + }; + + pm6350_l21: ldo21 { + regulator-min-microvolt = <751000>; + regulator-max-microvolt = <825000>; + regulator-initial-mode = ; + }; + + pm6350_l22: ldo22 { + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1305000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm6150l-rpmh-regulators"; + qcom,pmic-id = "e"; + + pm6150l_s8: smps8 { + regulator-min-microvolt = <313000>; + regulator-max-microvolt = <1395000>; + regulator-initial-mode = ; + }; + + pm6150l_l1: ldo1 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = ; + }; + + pm6150l_l2: ldo2 { + regulator-min-microvolt = <1170000>; + regulator-max-microvolt = <1305000>; + regulator-initial-mode = ; + }; + + pm6150l_l3: ldo3 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1299000>; + regulator-initial-mode = ; + }; + + pm6150l_l4: ldo4 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + pm6150l_l5: ldo5 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + pm6150l_l6: ldo6 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + pm6150l_l7: ldo7 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + pm6150l_l8: ldo8 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + pm6150l_l9: ldo9 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + pm6150l_l10: ldo10 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3401000>; + regulator-initial-mode = ; + }; + + pm6150l_l11: ldo11 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3401000>; + regulator-initial-mode = ; + }; + + pm6150l_bob: bob { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <5492000>; + regulator-initial-mode = ; + regulator-allow-bypass; + }; + }; +}; + &pm6350_gpios { gpio_keys_state: gpio-keys-state { key-volume-down-pins { From 85eef5cb65ab7e8905725d13c98c90442bb93dbc Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Sun, 30 Oct 2022 08:32:29 +0100 Subject: [PATCH 195/261] arm64: dts: qcom: sm6350-lena: Provide power to SDHCI 2 (SDCard slot) Without power the SDCard slot / hardware remains dormant. Like many other platforms these regulators are used exclusively by SDHCI, and have their maximum voltage decreased to what downstream sets on the consumer side. Additionally the SDHCI driver supports setting a load, for which the regulator definition is extended much the same. Signed-off-by: Marijn Suijten Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221030073232.22726-8-marijn.suijten@somainline.org --- .../dts/qcom/sm6350-sony-xperia-lena-pdx213.dts | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts index 1aaa9612b061..5cb76026ef67 100644 --- a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts +++ b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts @@ -219,8 +219,13 @@ pm6150l_l5: ldo5 { pm6150l_l6: ldo6 { regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <3544000>; + regulator-max-microvolt = <2950000>; regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = + ; + }; pm6150l_l7: ldo7 { @@ -237,8 +242,13 @@ pm6150l_l8: ldo8 { pm6150l_l9: ldo9 { regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3544000>; + regulator-max-microvolt = <2960000>; regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = + ; + }; pm6150l_l10: ldo10 { @@ -300,6 +310,9 @@ sd-cd-pins { &sdhc_2 { status = "okay"; + vmmc-supply = <&pm6150l_l9>; + vqmmc-supply = <&pm6150l_l6>; + cd-gpios = <&tlmm 94 GPIO_ACTIVE_HIGH>; }; From 8bad51c68930eba8b26ce362c7c9bfce5d074a2f Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Sun, 30 Oct 2022 08:32:30 +0100 Subject: [PATCH 196/261] arm64: dts: qcom: sm6350-lena: Enable QUP and GPI DMA Enable QUP and GPI DMA hardware to be able to add functioning I2C nodes later. Signed-off-by: Marijn Suijten Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221030073232.22726-9-marijn.suijten@somainline.org --- .../dts/qcom/sm6350-sony-xperia-lena-pdx213.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts index 5cb76026ef67..6eb1d4e5e60f 100644 --- a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts +++ b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts @@ -272,6 +272,14 @@ pm6150l_bob: bob { }; }; +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + &pm6350_gpios { gpio_keys_state: gpio-keys-state { key-volume-down-pins { @@ -289,6 +297,14 @@ &pm6350_resin { status = "okay"; }; +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + &sdc2_off_state { sd-cd-pins { pins = "gpio94"; From 2904a41c50e408c0a1e90da0045400edb6f155fe Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Sun, 30 Oct 2022 08:32:31 +0100 Subject: [PATCH 197/261] arm64: dts: qcom: sm6350-lena: Configure Samsung touchscreen Use the generic samsung,s6sy761 touchscreen driver for this device, together with a few pins and regulators to power it up correctly. Signed-off-by: Marijn Suijten Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221030073232.22726-10-marijn.suijten@somainline.org --- .../qcom/sm6350-sony-xperia-lena-pdx213.dts | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts index 6eb1d4e5e60f..20f35623d1ef 100644 --- a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts +++ b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts @@ -43,6 +43,15 @@ key-volume-down { gpios = <&pm6350_gpios 2 GPIO_ACTIVE_LOW>; }; }; + + touch_en_vreg: touch-en-regulator { + compatible = "regulator-fixed"; + regulator-name = "touch_en_vreg"; + gpio = <&tlmm 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&pm6350_l6>; + }; }; &apps_rsc { @@ -280,6 +289,23 @@ &gpi_dma1 { status = "okay"; }; +&i2c8 { + clock-frequency = <400000>; + status = "okay"; + + touchscreen@48 { + compatible = "samsung,s6sy761"; + reg = <0x48>; + interrupt-parent = <&tlmm>; + interrupts = <22 0x2008>; + vdd-supply = <&pm6350_l11>; + avdd-supply = <&touch_en_vreg>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_default &ts_active>; + }; +}; + &pm6350_gpios { gpio_keys_state: gpio-keys-state { key-volume-down-pins { @@ -334,6 +360,21 @@ &sdhc_2 { &tlmm { gpio-reserved-ranges = <13 4>, <45 2>, <56 2>; + + ts_active: ts-active-state { + pins = "gpio21"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + ts_int_default: ts-int-default-state { + pins = "gpio22"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + input-enable; + }; }; &usb_1 { From 7372b944a6ba5ac86628eaacc89ed4f103435cb9 Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Sun, 30 Oct 2022 08:32:32 +0100 Subject: [PATCH 198/261] arm64: dts: qcom: sm6350: Add apps_smmu with streamID to SDHCI 1/2 nodes When enabling the APPS SMMU the mainline driver reconfigures the SMMU from its bootloader configuration, losing the stream mapping for (among which) the SDHCI hardware and breaking its ADMA feature. This feature can be disabled with: sdhci.debug_quirks=0x40 But it is of course desired to have this feature enabled and working through the SMMU. Signed-off-by: Marijn Suijten Reviewed-by: Konrad Dybcio Reviewed-by: Luca Weiss Tested-by: Luca Weiss # sm7225-fairphone-fp4 Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221030073232.22726-11-marijn.suijten@somainline.org --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index f0e7304764bd..0f01ff4feb55 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -485,6 +485,7 @@ sdhc_1: mmc@7c4000 { interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; + iommus = <&apps_smmu 0x60 0x0>; clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, @@ -1064,6 +1065,7 @@ sdhc_2: mmc@8804000 { interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; + iommus = <&apps_smmu 0x560 0x0>; clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>, From 65bebf78744f0342187e77124c8a8294a7a0f98c Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 30 Oct 2022 19:16:11 +0300 Subject: [PATCH 199/261] arm64: dts: qcom: msm8996: use hdmi_phy for the MMCC's hdmipll clock Link hdmi_phy as a clock provider of "hdmipll" clock to the MMCC. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221030161612.95471-1-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 7cd33f723da6..9d9b712b8184 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -882,7 +882,7 @@ mmcc: clock-controller@8c0000 { <&dsi0_phy 0>, <0>, <0>, - <0>; + <&hdmi_phy>; clock-names = "xo", "gcc_mmss_noc_cfg_ahb_clk", "gpll0", From 830493fc13d8868fd5be0620d16936fa75c3b9a4 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 30 Oct 2022 19:16:12 +0300 Subject: [PATCH 200/261] arm64: dts: qcom: msm8996: use dsi1_phy for the MMCC's dsi1 clocks Link dsi1_phy as a clock provider of "dsi1pll" and "dsi1pllbyte" clocks to the MMCC. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221030161612.95471-2-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 9d9b712b8184..ed27342045f7 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -880,8 +880,8 @@ mmcc: clock-controller@8c0000 { <&gcc GPLL0>, <&dsi0_phy 1>, <&dsi0_phy 0>, - <0>, - <0>, + <&dsi1_phy 1>, + <&dsi1_phy 0>, <&hdmi_phy>; clock-names = "xo", "gcc_mmss_noc_cfg_ahb_clk", From 3aa0b8cd957b3e7806004c2150c61c85a606821a Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Sun, 30 Oct 2022 18:57:03 +0100 Subject: [PATCH 201/261] arm64: dts: qcom: ipq8074: pass XO and sleep clocks to GCC Pass XO and sleep clocks to the GCC controller so it does not have to find them by matching globaly by name. If not passed directly, driver maintains backwards compatibility by then falling back to global lookup. Since we are here, set cell numbers in decimal instead of hex. Signed-off-by: Robert Marko Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221030175703.1103224-3-robimarko@gmail.com --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index d3d9e7eb5837..f7cb1d04a367 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -360,9 +360,11 @@ qpic_pins: qpic-pins { gcc: gcc@1800000 { compatible = "qcom,gcc-ipq8074"; reg = <0x01800000 0x80000>; - #clock-cells = <0x1>; + clocks = <&xo>, <&sleep_clk>; + clock-names = "xo", "sleep_clk"; + #clock-cells = <1>; #power-domain-cells = <1>; - #reset-cells = <0x1>; + #reset-cells = <1>; }; tcsr_mutex: hwlock@1905000 { From 0c9a86fb9ebc576e66a2ce6a667684431a14d2f1 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Mon, 31 Oct 2022 18:39:33 +0100 Subject: [PATCH 202/261] arm64: dts: qcom: pm8150b: change vbus-regulator node name Use the node name as now defined in the spmi-pmic bindings. Signed-off-by: Luca Weiss Reviewed-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221031173933.936147-3-luca@z3ntu.xyz --- arch/arm64/boot/dts/qcom/pm8150b.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pm8150b.dtsi b/arch/arm64/boot/dts/qcom/pm8150b.dtsi index cdded791d96e..66752cc063d6 100644 --- a/arch/arm64/boot/dts/qcom/pm8150b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150b.dtsi @@ -53,7 +53,7 @@ pon@800 { status = "disabled"; }; - pm8150b_vbus: dcdc@1100 { + pm8150b_vbus: usb-vbus-regulator@1100 { compatible = "qcom,pm8150b-vbus-reg"; status = "disabled"; reg = <0x1100>; From ef4fc701d4021eeb2a614fdffb3231560ee43c18 Mon Sep 17 00:00:00 2001 From: Sheng-Liang Pan Date: Mon, 7 Nov 2022 17:43:42 +0800 Subject: [PATCH 203/261] arm64: dts: qcom: sc7280: Add LTE SKU for sc7280-evoker family evoker have wifi/lte sku, add different dts for each sku. Signed-off-by: Sheng-Liang Pan Reviewed-by: Douglas Anderson Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221107173954.v11.2.If03e9e85e63ece4b1599db841c90ed785c47a4be@changeid --- arch/arm64/boot/dts/qcom/Makefile | 3 ++- .../boot/dts/qcom/sc7280-herobrine-evoker-lte.dts | 14 ++++++++++++++ .../boot/dts/qcom/sc7280-herobrine-evoker.dts | 15 +++++++++++++++ ...evoker-r0.dts => sc7280-herobrine-evoker.dtsi} | 7 ------- 4 files changed, 31 insertions(+), 8 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker-lte.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dts rename arch/arm64/boot/dts/qcom/{sc7280-herobrine-evoker-r0.dts => sc7280-herobrine-evoker.dtsi} (98%) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 4dff39f98861..8b4a63749a6c 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -108,7 +108,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-boe-rt5682s.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-crd.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-evoker-r0.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-evoker.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-evoker-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-herobrine-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-villager-r0.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-villager-r1.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker-lte.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker-lte.dts new file mode 100644 index 000000000000..3af9224a7492 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker-lte.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Evoker board device tree source + * + * Copyright 2022 Google LLC. + */ + +#include "sc7280-herobrine-evoker.dts" +#include "sc7280-herobrine-lte-sku.dtsi" + +/ { + model = "Google Evoker with LTE"; + compatible = "google,evoker-sku512", "qcom,sc7280"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dts new file mode 100644 index 000000000000..dcdd4eecfe67 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Evoker board device tree source + * + * Copyright 2022 Google LLC. + */ + +/dts-v1/; + +#include "sc7280-herobrine-evoker.dtsi" + +/ { + model = "Google Evoker"; + compatible = "google,evoker", "qcom,sc7280"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker-r0.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dtsi similarity index 98% rename from arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker-r0.dts rename to arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dtsi index 739e81bd6d68..a6015491c608 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker-r0.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dtsi @@ -5,15 +5,8 @@ * Copyright 2022 Google LLC. */ -/dts-v1/; - #include "sc7280-herobrine.dtsi" -/ { - model = "Google Evoker"; - compatible = "google,evoker", "qcom,sc7280"; -}; - /* * ADDITIONS TO FIXED REGULATORS DEFINED IN PARENT DEVICE TREE FILES * From 928263d17413e406d7bbcd10e585b081f36c4114 Mon Sep 17 00:00:00 2001 From: Sheng-Liang Pan Date: Mon, 7 Nov 2022 17:43:43 +0800 Subject: [PATCH 204/261] arm64: dts: qcom: sc7280: Add touchscreen and touchpad support for evoker Change touchpad and touchscreen node for evoker Touchpad: SA461D-1011 Touchscreen: GT7986U Signed-off-by: Sheng-Liang Pan Reviewed-by: Douglas Anderson Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221107173954.v11.3.I3ac715e729f6f9b5a3e3001b155df4f9d14e6186@changeid --- .../boot/dts/qcom/sc7280-herobrine-evoker.dtsi | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dtsi index a6015491c608..706dd82a7013 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dtsi @@ -23,16 +23,15 @@ ap_tp_i2c: &i2c0 { status = "okay"; clock-frequency = <400000>; - trackpad: trackpad@2c { - compatible = "hid-over-i2c"; - reg = <0x2c>; + trackpad: trackpad@15 { + compatible = "elan,ekth3000"; + reg = <0x15>; pinctrl-names = "default"; pinctrl-0 = <&tp_int_odl>; interrupt-parent = <&tlmm>; interrupts = <7 IRQ_TYPE_EDGE_FALLING>; - hid-descr-addr = <0x20>; vcc-supply = <&pp3300_z1>; wakeup-source; @@ -43,9 +42,9 @@ ts_i2c: &i2c13 { status = "okay"; clock-frequency = <400000>; - ap_ts: touchscreen@10 { - compatible = "elan,ekth6915"; - reg = <0x10>; + ap_ts: touchscreen@5d { + compatible = "goodix,gt7986u", "goodix,gt7375p"; + reg = <0x5d>; pinctrl-names = "default"; pinctrl-0 = <&ts_int_conn>, <&ts_rst_conn>; @@ -54,7 +53,7 @@ ap_ts: touchscreen@10 { reset-gpios = <&tlmm 54 GPIO_ACTIVE_LOW>; - vcc33-supply = <&ts_avdd>; + vdd-supply = <&ts_avdd>; }; }; From 5977c14285ca9ba933f4d048b0d995b046727788 Mon Sep 17 00:00:00 2001 From: Sheng-Liang Pan Date: Mon, 7 Nov 2022 17:43:44 +0800 Subject: [PATCH 205/261] arm64: dts: qcom: sc7280: add sc7280-herobrine-audio-rt5682-3mic3.dtsi for evoker add specific 3mic setting as sc7280-herobrine-audio-rt5682-3mic.dtsi, so we can include sc7280-herobrine-audio-rt5682-3mic.dtsi for evoker as it uses rt5682 with 3 mics. Signed-off-by: Sheng-Liang Pan Reviewed-by: Douglas Anderson Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221107173954.v11.4.I9718ac3622fa550e432209ae5c95c87b873a0f87@changeid --- .../sc7280-herobrine-audio-rt5682-3mic.dtsi | 195 ++++++++++++++++++ .../boot/dts/qcom/sc7280-herobrine-evoker.dts | 1 + 2 files changed, 196 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682-3mic.dtsi diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682-3mic.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682-3mic.dtsi new file mode 100644 index 000000000000..cf34334451d6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682-3mic.dtsi @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * + * This file defines the common audio settings for the child boards + * using rt5682 codec and having 3 dmics connected to sc7280. + * + * Copyright 2022 Google LLC. + */ + +/ { + /* BOARD-SPECIFIC TOP LEVEL NODES */ + sound: sound { + compatible = "google,sc7280-herobrine"; + model = "sc7280-rt5682-max98360a-3mic"; + + audio-routing = "VA DMIC0", "vdd-micb", + "VA DMIC1", "vdd-micb", + "VA DMIC2", "vdd-micb", + "VA DMIC3", "vdd-micb", + + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR"; + + #address-cells = <1>; + #size-cells = <0>; + + dai-link@0 { + link-name = "MAX98360"; + reg = <0>; + + cpu { + sound-dai = <&lpass_cpu MI2S_SECONDARY>; + }; + + codec { + sound-dai = <&max98360a>; + }; + }; + + dai-link@1 { + link-name = "DisplayPort"; + reg = <1>; + + cpu { + sound-dai = <&lpass_cpu LPASS_DP_RX>; + }; + + codec { + sound-dai = <&mdss_dp>; + }; + }; + + dai-link@2 { + link-name = "ALC5682"; + reg = <2>; + + cpu { + sound-dai = <&lpass_cpu MI2S_PRIMARY>; + }; + + codec { + sound-dai = <&alc5682 0 /* aif1 */>; + }; + }; + + dai-link@4 { + link-name = "DMIC"; + reg = <4>; + + cpu { + sound-dai = <&lpass_cpu LPASS_CDC_DMA_VA_TX0>; + }; + + codec { + sound-dai = <&lpass_va_macro 0>; + }; + }; + }; +}; + +hp_i2c: &i2c2 { + clock-frequency = <400000>; + status = "okay"; + + alc5682: codec@1a { + compatible = "realtek,rt5682s"; + reg = <0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_irq>; + + #sound-dai-cells = <1>; + + interrupt-parent = <&tlmm>; + interrupts = <101 IRQ_TYPE_EDGE_BOTH>; + + AVDD-supply = <&pp1800_alc5682>; + MICVDD-supply = <&pp3300_codec>; + + realtek,dmic1-data-pin = <1>; + realtek,dmic1-clk-pin = <2>; + realtek,jd-src = <1>; + realtek,dmic-clk-rate-hz = <2048000>; + }; +}; + +&lpass_cpu { + pinctrl-names = "default"; + pinctrl-0 = <&mi2s0_data0>, <&mi2s0_data1>, <&mi2s0_mclk>, <&mi2s0_sclk>, <&mi2s0_ws>, + <&mi2s1_data0>, <&mi2s1_sclk>, <&mi2s1_ws>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + dai-link@0 { + reg = ; + qcom,playback-sd-lines = <1>; + qcom,capture-sd-lines = <0>; + }; + + dai-link@1 { + reg = ; + qcom,playback-sd-lines = <0>; + }; + + dai-link@5 { + reg = ; + }; + + dai-link@25 { + reg = ; + }; +}; + +&lpass_va_macro { + vdd-micb-supply = <&pp1800_l2c>; + pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>, <&lpass_dmic23_clk>, + <&lpass_dmic23_data>; + + status = "okay"; +}; + +/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */ + +&lpass_dmic01_clk { + drive-strength = <8>; + bias-disable; +}; + +&lpass_dmic01_clk_sleep { + drive-strength = <2>; +}; + +&lpass_dmic01_data { + bias-pull-down; +}; + +&lpass_dmic23_clk { + drive-strength = <8>; + bias-disable; +}; + +&lpass_dmic23_clk_sleep { + drive-strength = <2>; +}; + +&lpass_dmic23_data { + bias-pull-down; +}; + +&mi2s0_data0 { + drive-strength = <6>; + bias-disable; +}; + +&mi2s0_data1 { + drive-strength = <6>; + bias-disable; +}; + +&mi2s0_mclk { + drive-strength = <6>; + bias-disable; +}; + +&mi2s0_sclk { + drive-strength = <6>; + bias-disable; +}; + +&mi2s0_ws { + drive-strength = <6>; + bias-disable; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dts index dcdd4eecfe67..51f0401b11ed 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "sc7280-herobrine-evoker.dtsi" +#include "sc7280-herobrine-audio-rt5682-3mic.dtsi" / { model = "Google Evoker"; From 3d11e7e120eee29ef837830bee8442195a2c4552 Mon Sep 17 00:00:00 2001 From: Sheng-Liang Pan Date: Mon, 7 Nov 2022 17:43:45 +0800 Subject: [PATCH 206/261] arm64: dts: qcom: sc7280: sort out the "Status" to last property with sc7280-herobrine-audio-rt5682.dtsi To keep diffs clean, sort out "Status" to last property. Signed-off-by: Sheng-Liang Pan Reviewed-by: Douglas Anderson Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221107173954.v11.5.I4c6d97e6f3cf8cdc691d2d4519883c3018dd4372@changeid --- .../dts/qcom/sc7280-herobrine-audio-rt5682.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682.dtsi index 2dbdeeb29ece..fc7a659dfe4a 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682.dtsi @@ -13,14 +13,14 @@ sound: sound { compatible = "google,sc7280-herobrine"; model = "sc7280-rt5682-max98360a-1mic"; - status = "okay"; - audio-routing = - "Headphone Jack", "HPOL", - "Headphone Jack", "HPOR"; + audio-routing = "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR"; #address-cells = <1>; #size-cells = <0>; + status = "okay"; + dai-link@0 { link-name = "MAX98360"; reg = <0>; @@ -50,8 +50,8 @@ codec { }; hp_i2c: &i2c2 { - status = "okay"; clock-frequency = <400000>; + status = "okay"; alc5682: codec@1a { compatible = "realtek,rt5682s"; @@ -75,8 +75,6 @@ alc5682: codec@1a { }; &lpass_cpu { - status = "okay"; - pinctrl-names = "default"; pinctrl-0 = <&mi2s0_data0>, <&mi2s0_data1>, <&mi2s0_mclk>, <&mi2s0_sclk>, <&mi2s0_ws>, <&mi2s1_data0>, <&mi2s1_sclk>, <&mi2s1_ws>; @@ -84,6 +82,8 @@ &lpass_cpu { #address-cells = <1>; #size-cells = <0>; + status = "okay"; + dai-link@0 { reg = ; qcom,playback-sd-lines = <1>; From 0d0be9d88bf2b1c36146712761ab04623a855647 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Mon, 7 Nov 2022 09:17:05 +0100 Subject: [PATCH 207/261] arm64: dts: qcom: sc8280xp: fix USB MP QMP PHY nodes Update the USB MP QMP PHY nodes to match the new binding which specifically includes the missing register regions (e.g. PCS_USB). Signed-off-by: Johan Hovold Reviewed-by: Andrew Halaney Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221107081705.18446-1-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 62 ++++++++++---------------- 1 file changed, 24 insertions(+), 38 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index c1becbf949c3..700c6273df13 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1053,70 +1053,56 @@ usb_2_hsphy3: phy@88ea000 { status = "disabled"; }; - usb_2_qmpphy0: phy-wrapper@88ef000 { + usb_2_qmpphy0: phy@88ef000 { compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; - reg = <0 0x088ef000 0 0x1c8>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + reg = <0 0x088ef000 0 0x2000>; clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_USB3_MP0_CLKREF_CLK>, - <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>; - clock-names = "aux", "ref_clk_src", "ref", "com_aux"; + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; + clock-names = "aux", "ref_clk_src", "ref", "com_aux", + "pipe"; resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; - reset-names = "phy", "common"; + reset-names = "phy", "phy_phy"; power-domains = <&gcc USB30_MP_GDSC>; - status = "disabled"; + #clock-cells = <0>; + clock-output-names = "usb2_phy0_pipe_clk"; - usb_2_ssphy0: phy@88efe00 { - reg = <0 0x088efe00 0 0x160>, - <0 0x088f0000 0 0x1ec>, - <0 0x088ef200 0 0x1f0>; - #phy-cells = <0>; - #clock-cells = <0>; - clocks = <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb2_phy0_pipe_clk"; - }; + #phy-cells = <0>; + + status = "disabled"; }; - usb_2_qmpphy1: phy-wrapper@88f1000 { + usb_2_qmpphy1: phy@88f1000 { compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; - reg = <0 0x088f1000 0 0x1c8>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + reg = <0 0x088f1000 0 0x2000>; clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_USB3_MP1_CLKREF_CLK>, - <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>; - clock-names = "aux", "ref_clk_src", "ref", "com_aux"; + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; + clock-names = "aux", "ref_clk_src", "ref", "com_aux", + "pipe"; resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; - reset-names = "phy", "common"; + reset-names = "phy", "phy_phy"; power-domains = <&gcc USB30_MP_GDSC>; - status = "disabled"; + #clock-cells = <0>; + clock-output-names = "usb2_phy1_pipe_clk"; - usb_2_ssphy1: phy@88f1e00 { - reg = <0 0x088f1e00 0 0x160>, - <0 0x088f2000 0 0x1ec>, - <0 0x088f1200 0 0x1f0>; - #phy-cells = <0>; - #clock-cells = <0>; - clocks = <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb2_phy1_pipe_clk"; - }; + #phy-cells = <0>; + + status = "disabled"; }; remoteproc_adsp: remoteproc@3000000 { From d0ee86d3c0f0da1481cfab51a386fc22b00a0630 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 7 Nov 2022 10:22:07 +0100 Subject: [PATCH 208/261] MAINTAINERS: Update Konrad Dybcio's email address Use my new Linaro address in place of my SoMainline one. Signed-off-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Reviewed-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221107092207.5832-1-konrad.dybcio@linaro.org --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index cf0f18502372..3bdac09e9050 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2620,7 +2620,7 @@ W: http://www.armlinux.org.uk/ ARM/QUALCOMM SUPPORT M: Andy Gross M: Bjorn Andersson -R: Konrad Dybcio +R: Konrad Dybcio L: linux-arm-msm@vger.kernel.org S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git From 7284a3943909606016128b79fb18dd107bc0fe26 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Mon, 7 Nov 2022 10:29:28 +0100 Subject: [PATCH 209/261] arm64: dts: qcom: hk10: use "okay" instead of "ok" Use "okay" instead of "ok" in USB nodes as "ok" is deprecated. Signed-off-by: Robert Marko Reviewed-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221107092930.33325-1-robimarko@gmail.com --- arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi index db4b87944cdf..262b937e0bc6 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi @@ -22,7 +22,7 @@ memory { }; &blsp1_spi1 { - status = "ok"; + status = "okay"; flash@0 { #address-cells = <1>; @@ -34,33 +34,33 @@ flash@0 { }; &blsp1_uart5 { - status = "ok"; + status = "okay"; }; &pcie0 { - status = "ok"; + status = "okay"; perst-gpios = <&tlmm 58 0x1>; }; &pcie1 { - status = "ok"; + status = "okay"; perst-gpios = <&tlmm 61 0x1>; }; &pcie_phy0 { - status = "ok"; + status = "okay"; }; &pcie_phy1 { - status = "ok"; + status = "okay"; }; &qpic_bam { - status = "ok"; + status = "okay"; }; &qpic_nand { - status = "ok"; + status = "okay"; nand@0 { reg = <0>; From 3f49bdaf6f84959bb8fc3ed5add7983907491240 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Mon, 7 Nov 2022 10:29:29 +0100 Subject: [PATCH 210/261] arm64: dts: qcom: hk10: use GPIO flags for tlmm Use respective GPIO_ACTIVE_LOW/HIGH flags for tlmm GPIOs instead of harcoding the cell value. Signed-off-by: Robert Marko Reviewed-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221107092930.33325-2-robimarko@gmail.com --- arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi index 262b937e0bc6..651a231554e0 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi @@ -5,6 +5,7 @@ /dts-v1/; #include "ipq8074.dtsi" +#include / { aliases { @@ -39,12 +40,12 @@ &blsp1_uart5 { &pcie0 { status = "okay"; - perst-gpios = <&tlmm 58 0x1>; + perst-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>; }; &pcie1 { status = "okay"; - perst-gpios = <&tlmm 61 0x1>; + perst-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>; }; &pcie_phy0 { From 1bc6b7f26bc72c8fd5a49ff000bb76a234e75e11 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Mon, 7 Nov 2022 10:29:30 +0100 Subject: [PATCH 211/261] arm64: dts: qcom: hk01: use GPIO flags for tlmm Use respective GPIO_ACTIVE_LOW/HIGH flags for tlmm GPIOs instead of harcoding the cell value. Signed-off-by: Robert Marko Reviewed-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221107092930.33325-3-robimarko@gmail.com --- arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts index b60b2d4c2ea5..c3f3f78271e9 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts @@ -4,6 +4,7 @@ */ #include "ipq8074.dtsi" #include "pmp8074.dtsi" +#include / { model = "Qualcomm Technologies, Inc. IPQ8074-HK01"; @@ -52,12 +53,12 @@ &blsp1_uart5 { &pcie0 { status = "okay"; - perst-gpios = <&tlmm 61 0x1>; + perst-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>; }; &pcie1 { status = "okay"; - perst-gpios = <&tlmm 58 0x1>; + perst-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>; }; &pcie_phy0 { From a979f2e5d5b530d190b9c02393f3c69160f06aae Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 4 Nov 2022 12:11:30 -0400 Subject: [PATCH 212/261] arm64: dts: qcom: qcs404: align TLMM pin configuration with DT schema DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221104161131.57719-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts | 20 +++--- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 52 +++++++-------- arch/arm64/boot/dts/qcom/qcs404.dtsi | 66 ++++++++++++-------- 3 files changed, 71 insertions(+), 67 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts b/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts index 08d5d51221cf..9c7d4e780357 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts +++ b/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts @@ -37,54 +37,54 @@ phy1: phy@4 { }; &tlmm { - ethernet_defaults: ethernet-defaults { - int { + ethernet_defaults: ethernet-defaults-state { + int-pins { pins = "gpio61"; function = "rgmii_int"; bias-disable; drive-strength = <2>; }; - mdc { + mdc-pins { pins = "gpio76"; function = "rgmii_mdc"; bias-pull-up; }; - mdio { + mdio-pins { pins = "gpio75"; function = "rgmii_mdio"; bias-pull-up; }; - tx { + tx-pins { pins = "gpio67", "gpio66", "gpio65", "gpio64"; function = "rgmii_tx"; bias-pull-up; drive-strength = <16>; }; - rx { + rx-pins { pins = "gpio73", "gpio72", "gpio71", "gpio70"; function = "rgmii_rx"; bias-disable; drive-strength = <2>; }; - tx-ctl { + tx-ctl-pins { pins = "gpio68"; function = "rgmii_ctl"; bias-pull-up; drive-strength = <16>; }; - rx-ctl { + rx-ctl-pins { pins = "gpio74"; function = "rgmii_ctl"; bias-disable; drive-strength = <2>; }; - tx-ck { + tx-ck-pins { pins = "gpio63"; function = "rgmii_ck"; bias-pull-up; drive-strength = <16>; }; - rx-ck { + rx-ck-pins { pins = "gpio69"; function = "rgmii_ck"; bias-disable; diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index dbbe1653718b..4d53cd544e41 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -229,7 +229,7 @@ &sdcc1 { }; &tlmm { - perst_state: perst { + perst_state: perst-state { pins = "gpio43"; function = "gpio"; @@ -238,68 +238,63 @@ perst_state: perst { output-low; }; - sdc1_on: sdc1-on { - clk { + sdc1_on: sdc1-on-state { + clk-pins { pins = "sdc1_clk"; bias-disable; drive-strength = <16>; }; - cmd { + cmd-pins { pins = "sdc1_cmd"; bias-pull-up; drive-strength = <10>; }; - data { + data-pins { pins = "sdc1_data"; bias-pull-up; drive-strength = <10>; }; - rclk { + rclk-pins { pins = "sdc1_rclk"; bias-pull-down; }; }; - sdc1_off: sdc1-off { - clk { + sdc1_off: sdc1-off-state { + clk-pins { pins = "sdc1_clk"; bias-disable; drive-strength = <2>; }; - cmd { + cmd-pins { pins = "sdc1_cmd"; bias-pull-up; drive-strength = <2>; }; - data { + data-pins { pins = "sdc1_data"; bias-pull-up; drive-strength = <2>; }; - rclk { + rclk-pins { pins = "sdc1_rclk"; bias-pull-down; }; }; - usb3_id_pin: usb3-id-pin { - pinmux { - pins = "gpio116"; - function = "gpio"; - }; + usb3_id_pin: usb3-id-state { + pins = "gpio116"; + function = "gpio"; - pinconf { - pins = "gpio116"; - drive-strength = <2>; - bias-pull-up; - input-enable; - }; + drive-strength = <2>; + bias-pull-up; + input-enable; }; }; @@ -366,31 +361,28 @@ &wifi { /* PINCTRL - additions to nodes defined in qcs404.dtsi */ &blsp1_uart2_default { - rx { + rx-pins { drive-strength = <2>; bias-disable; }; - tx { + tx-pins { drive-strength = <2>; bias-disable; }; }; &blsp1_uart3_default { - cts { - pins = "gpio84"; + cts-pins { bias-disable; }; - rts-tx { - pins = "gpio85", "gpio82"; + rts-tx-pins { drive-strength = <2>; bias-disable; }; - rx { - pins = "gpio83"; + rx-pins { bias-pull-up; }; }; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 80f2d05595fa..577d76662468 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -593,118 +593,130 @@ tlmm: pinctrl@1000000 { interrupt-controller; #interrupt-cells = <2>; - blsp1_i2c0_default: blsp1-i2c0-default { + blsp1_i2c0_default: blsp1-i2c0-default-state { pins = "gpio32", "gpio33"; function = "blsp_i2c0"; }; - blsp1_i2c1_default: blsp1-i2c1-default { + blsp1_i2c1_default: blsp1-i2c1-default-state { pins = "gpio24", "gpio25"; function = "blsp_i2c1"; }; - blsp1_i2c2_default: blsp1-i2c2-default { - sda { + blsp1_i2c2_default: blsp1-i2c2-default-state { + sda-pins { pins = "gpio19"; function = "blsp_i2c_sda_a2"; }; - scl { + scl-pins { pins = "gpio20"; function = "blsp_i2c_scl_a2"; }; }; - blsp1_i2c3_default: blsp1-i2c3-default { + blsp1_i2c3_default: blsp1-i2c3-default-state { pins = "gpio84", "gpio85"; function = "blsp_i2c3"; }; - blsp1_i2c4_default: blsp1-i2c4-default { + blsp1_i2c4_default: blsp1-i2c4-default-state { pins = "gpio117", "gpio118"; function = "blsp_i2c4"; }; - blsp1_uart0_default: blsp1-uart0-default { + blsp1_uart0_default: blsp1-uart0-default-state { pins = "gpio30", "gpio31", "gpio32", "gpio33"; function = "blsp_uart0"; }; - blsp1_uart1_default: blsp1-uart1-default { + blsp1_uart1_default: blsp1-uart1-default-state { pins = "gpio22", "gpio23"; function = "blsp_uart1"; }; - blsp1_uart2_default: blsp1-uart2-default { - rx { + blsp1_uart2_default: blsp1-uart2-default-state { + rx-pins { pins = "gpio18"; function = "blsp_uart_rx_a2"; }; - tx { + tx-pins { pins = "gpio17"; function = "blsp_uart_tx_a2"; }; }; - blsp1_uart3_default: blsp1-uart3-default { - pins = "gpio82", "gpio83", "gpio84", "gpio85"; - function = "blsp_uart3"; + blsp1_uart3_default: blsp1-uart3-default-state { + cts-pins { + pins = "gpio84"; + function = "blsp_uart3"; + }; + + rts-tx-pins { + pins = "gpio85", "gpio82"; + function = "blsp_uart3"; + }; + + rx-pins { + pins = "gpio83"; + function = "blsp_uart3"; + }; }; - blsp2_i2c0_default: blsp2-i2c0-default { + blsp2_i2c0_default: blsp2-i2c0-default-state { pins = "gpio28", "gpio29"; function = "blsp_i2c5"; }; - blsp1_spi0_default: blsp1-spi0-default { + blsp1_spi0_default: blsp1-spi0-default-state { pins = "gpio30", "gpio31", "gpio32", "gpio33"; function = "blsp_spi0"; }; - blsp1_spi1_default: blsp1-spi1-default { - mosi { + blsp1_spi1_default: blsp1-spi1-default-state { + mosi-pins { pins = "gpio22"; function = "blsp_spi_mosi_a1"; }; - miso { + miso-pins { pins = "gpio23"; function = "blsp_spi_miso_a1"; }; - cs_n { + cs-n-pins { pins = "gpio24"; function = "blsp_spi_cs_n_a1"; }; - clk { + clk-pins { pins = "gpio25"; function = "blsp_spi_clk_a1"; }; }; - blsp1_spi2_default: blsp1-spi2-default { + blsp1_spi2_default: blsp1-spi2-default-state { pins = "gpio17", "gpio18", "gpio19", "gpio20"; function = "blsp_spi2"; }; - blsp1_spi3_default: blsp1-spi3-default { + blsp1_spi3_default: blsp1-spi3-default-state { pins = "gpio82", "gpio83", "gpio84", "gpio85"; function = "blsp_spi3"; }; - blsp1_spi4_default: blsp1-spi4-default { + blsp1_spi4_default: blsp1-spi4-default-state { pins = "gpio37", "gpio38", "gpio117", "gpio118"; function = "blsp_spi4"; }; - blsp2_spi0_default: blsp2-spi0-default { + blsp2_spi0_default: blsp2-spi0-default-state { pins = "gpio26", "gpio27", "gpio28", "gpio29"; function = "blsp_spi5"; }; - blsp2_uart0_default: blsp2-uart0-default { + blsp2_uart0_default: blsp2-uart0-default-state { pins = "gpio26", "gpio27", "gpio28", "gpio29"; function = "blsp_uart5"; }; From 4bb376f6cc715fb9182942df08d492965d5f0127 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 7 Nov 2022 15:55:11 +0100 Subject: [PATCH 213/261] arm64: dts: qcom: msm/apq8x16-*: Fix up comments Switch '//' comments to C-style /* */ and fix up the contents of some. Make sure all multiline C-style commends begin with just '/*' with the comment text starting on a new line. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221107145522.6706-2-konrad.dybcio@linaro.org --- arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 2 +- arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts | 4 +++- arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts | 6 +++--- arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts | 4 +++- arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts | 4 +++- arch/arm64/boot/dts/qcom/msm8916.dtsi | 10 +++++----- 7 files changed, 19 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index 9ebc506810f6..ef5b39ba1238 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -839,7 +839,7 @@ ls_exp_gpio_f: pm8916-mpp4-state { function = "digital"; output-low; - power-source = ; // 1.8V + power-source = ; /* 1.8V */ }; pm8916_mpps_leds: pm8916-mpps-state { diff --git a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts index a6a7d870f586..8c07eca900d3 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts @@ -1,5 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only -// Copyright (C) 2021 Stephan Gerhold +/* + * Copyright (C) 2021 Stephan Gerhold + */ /dts-v1/; diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index 31214570be4b..d1e8cf2f50c0 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -22,7 +22,7 @@ chosen { }; reserved-memory { - // wcnss.mdt is not relocatable, so it must be loaded at 0x8b600000 + /* wcnss.mdt is not relocatable, so it must be loaded at 0x8b600000 */ /delete-node/ wcnss@89300000; wcnss_mem: wcnss@8b600000 { @@ -204,12 +204,12 @@ rmi4@20 { rmi4-f01@1 { reg = <0x1>; - syna,nosleep-mode = <1>; // Allow sleeping + syna,nosleep-mode = <1>; /* Allow sleeping */ }; rmi4-f12@12 { reg = <0x12>; - syna,sensor-type = <1>; // Touchscreen + syna,sensor-type = <1>; /* Touchscreen */ }; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi index db9e448d0a64..33dfcf318a81 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi @@ -6,7 +6,7 @@ &msmgpio { blsp1_uart1_default: blsp1-uart1-default-state { - // TX, RX, CTS_N, RTS_N + /* TX, RX, CTS_N, RTS_N */ pins = "gpio0", "gpio1", "gpio2", "gpio3"; function = "blsp_uart1"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts index f0ee5ed7cf81..d4984b3af802 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts @@ -1,5 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only -// Copyright (C) 2019 Stephan Gerhold +/* + * Copyright (C) 2019 Stephan Gerhold + */ /dts-v1/; diff --git a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts index 399326b8f99e..166bed05996f 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts @@ -1,5 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only -// Copyright (C) 2020 Stephan Gerhold +/* + * Copyright (C) 2020 Stephan Gerhold + */ /dts-v1/; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index c938d6715ca6..2ca8e977fc2a 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1263,21 +1263,21 @@ apps_iommu: iommu@1ef0000 { clock-names = "iface", "bus"; qcom,iommu-secure-id = <17>; - // vfe: + /* VFE */ iommu-ctx@3000 { compatible = "qcom,msm-iommu-v1-sec"; reg = <0x3000 0x1000>; interrupts = ; }; - // mdp_0: + /* MDP_0 */ iommu-ctx@4000 { compatible = "qcom,msm-iommu-v1-ns"; reg = <0x4000 0x1000>; interrupts = ; }; - // venus_ns: + /* VENUS_NS */ iommu-ctx@5000 { compatible = "qcom,msm-iommu-v1-sec"; reg = <0x5000 0x1000>; @@ -1296,14 +1296,14 @@ gpu_iommu: iommu@1f08000 { clock-names = "iface", "bus"; qcom,iommu-secure-id = <18>; - // gfx3d_user: + /* GFX3D_USER */ iommu-ctx@1000 { compatible = "qcom,msm-iommu-v1-ns"; reg = <0x1000 0x1000>; interrupts = ; }; - // gfx3d_priv: + /* GFX3D_PRIV */ iommu-ctx@2000 { compatible = "qcom,msm-iommu-v1-ns"; reg = <0x2000 0x1000>; From bd95b48a591cc0fd767b3c737b8d59cea5ff428d Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 7 Nov 2022 15:55:12 +0100 Subject: [PATCH 214/261] arm64: dts: qcom: msm/apq8x96-*: Fix up comments Switch '//' comments to C-style /* */ and fix up the contents of some. Make sure all multiline C-style commends begin with just '/*' with the comment text starting on a new line. Also, fix up a single raw '2' to PM8994_GPIO_S4 while at it. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221107145522.6706-3-konrad.dybcio@linaro.org --- arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 14 +++++++------- arch/arm64/boot/dts/qcom/msm8996.dtsi | 3 ++- 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index 1b0a01f1e237..fe6c415e8229 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -524,7 +524,7 @@ pinconf { pins = "gpio5"; function = PMIC_GPIO_FUNC_NORMAL; output-low; - power-source = <2>; // PM8994_GPIO_S4, 1.8V + power-source = ; /* 1.8V */ }; }; @@ -533,7 +533,7 @@ pinconf { pins = "gpio19"; function = PMIC_GPIO_FUNC_NORMAL; output-low; - power-source = ; // 1.8V + power-source = ; /* 1.8V */ qcom,drive-strength = ; bias-pull-down; }; @@ -544,7 +544,7 @@ pinconf { pins = "gpio8"; function = PMIC_GPIO_FUNC_NORMAL; output-low; - power-source = ; // 1.8V + power-source = ; /* 1.8V */ qcom,drive-strength = ; bias-pull-down; }; @@ -554,7 +554,7 @@ audio_mclk: clk-div1-state { pinconf { pins = "gpio15"; function = "func1"; - power-source = ; // 1.8V + power-source = ; /* 1.8V */ }; }; @@ -566,7 +566,7 @@ pinconf { drive-push-pull; bias-pull-up; qcom,drive-strength = ; - power-source = ; // 1.8V + power-source = ; /* 1.8V */ }; }; @@ -587,7 +587,7 @@ pinconf { input-enable; bias-pull-down; qcom,drive-strength = ; - power-source = ; // 1.8V + power-source = ; /* 1.8V */ }; }; }; @@ -643,7 +643,7 @@ pinconf { input-enable; bias-pull-down; qcom,drive-strength = ; - power-source = ; // 1.8V + power-source = ; /* 1.8V */ }; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index ed27342045f7..747e1aac497f 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. +/* + * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. */ #include From 83e8692144fbda4a8f86087170d9ce26e64993d7 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 7 Nov 2022 15:55:13 +0100 Subject: [PATCH 215/261] arm64: dts: qcom: msm8953: Fix up comments Switch '//' comments to C-style /* */ and fix up the contents of some. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221107145522.6706-4-konrad.dybcio@linaro.org --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index f2ff18ac9141..32349174c4bd 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -948,21 +948,21 @@ apps_iommu: iommu@1e00000 { #iommu-cells = <1>; #size-cells = <1>; - // vfe + /* VFE */ iommu-ctx@14000 { compatible = "qcom,msm-iommu-v1-ns"; reg = <0x14000 0x1000>; interrupts = ; }; - // mdp_0 + /* MDP_0 */ iommu-ctx@15000 { compatible = "qcom,msm-iommu-v1-ns"; reg = <0x15000 0x1000>; interrupts = ; }; - // venus_ns + /* VENUS_NS */ iommu-ctx@16000 { compatible = "qcom,msm-iommu-v1-ns"; reg = <0x16000 0x1000>; From 689469ea4ce0fc17f1ddf2f5f730cb565bb5ef9c Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 7 Nov 2022 15:55:14 +0100 Subject: [PATCH 216/261] arm64: dts: qcom: msm8998-*: Fix up comments Switch '//' comments to C-style /* */ and fix up the contents of some. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221107145522.6706-5-konrad.dybcio@linaro.org --- arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts | 8 ++------ arch/arm64/boot/dts/qcom/msm8998-mtp.dts | 8 ++------ 2 files changed, 4 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts index 2aee2fd29a07..310f7a2df1e8 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts @@ -310,15 +310,11 @@ &funnel3 { }; &funnel4 { - // FIXME: Figure out why clock late_initcall crashes the board with - // this enabled. - // status = "okay"; + /* FIXME: Figure out why clock late_initcall crashes the board with this enabled. */ }; &funnel5 { - // FIXME: Figure out why clock late_initcall crashes the board with - // this enabled. - // status = "okay"; + /* FIXME: Figure out why clock late_initcall crashes the board with this enabled. */ }; &pcie0 { diff --git a/arch/arm64/boot/dts/qcom/msm8998-mtp.dts b/arch/arm64/boot/dts/qcom/msm8998-mtp.dts index 00032ed3f4aa..453a1c9e9808 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-mtp.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-mtp.dts @@ -124,15 +124,11 @@ &funnel3 { }; &funnel4 { - // FIXME: Figure out why clock late_initcall crashes the board with - // this enabled. - // status = "okay"; + /* FIXME: Figure out why clock late_initcall crashes the board with this enabled. */ }; &funnel5 { - // FIXME: Figure out why clock late_initcall crashes the board with - // this enabled. - // status = "okay"; + /* FIXME: Figure out why clock late_initcall crashes the board with this enabled. */ }; &pcie0 { From b47fac7ab95b2567b6b39dae8dd66926368f2713 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 7 Nov 2022 15:55:15 +0100 Subject: [PATCH 217/261] arm64: dts: qcom: sc8280xp-x13s: Fix up comments Switch '//' comments to C-style /* */. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221107145522.6706-6-konrad.dybcio@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 66ca0136eb96..cf0076d7e798 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -144,7 +144,7 @@ vreg_l6b: ldo6 { regulator-max-microvolt = <880000>; regulator-initial-mode = ; regulator-boot-on; - regulator-always-on; // FIXME: VDD_A_EDP_0_0P9 + regulator-always-on; /* FIXME: VDD_A_EDP_0_0P9 */ }; }; From 108162894a5db9d1eba20650d050de27e730d818 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 7 Nov 2022 15:55:16 +0100 Subject: [PATCH 218/261] arm64: dts: qcom: sdm845-*: Fix up comments Switch '//' comments to C-style /* */. Make sure all multiline C-style commends begin with just '/*' with the comment text starting on a new line. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221107145522.6706-7-konrad.dybcio@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 38 +++++++++++-------- .../boot/dts/qcom/sdm845-oneplus-common.dtsi | 5 ++- .../boot/dts/qcom/sdm850-samsung-w737.dts | 2 +- 3 files changed, 27 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 3a407af43596..02dcf75c0745 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -120,9 +120,11 @@ lt9611_3v3: lt9611-3v3 { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - // TODO: make it possible to drive same GPIO from two clients - // gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>; - // enable-active-high; + /* + * TODO: make it possible to drive same GPIO from two clients + * gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>; + * enable-active-high; + */ }; pcie0_1p05v: pcie-0-1p05v-regulator { @@ -133,9 +135,11 @@ pcie0_1p05v: pcie-0-1p05v-regulator { regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; - // TODO: make it possible to drive same GPIO from two clients - // gpio = <&tlmm 90 GPIO_ACTIVE_HIGH>; - // enable-active-high; + /* + * TODO: make it possible to drive same GPIO from two clients + * gpio = <&tlmm 90 GPIO_ACTIVE_HIGH>; + * enable-active-high; + */ }; cam0_dvdd_1v2: reg_cam0_dvdd_1v2 { @@ -195,9 +199,11 @@ v5p0_hdmiout: v5p0-hdmiout-regulator { regulator-min-microvolt = <500000>; regulator-max-microvolt = <500000>; - // TODO: make it possible to drive same GPIO from two clients - // gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>; - // enable-active-high; + /* + * TODO: make it possible to drive same GPIO from two clients + * gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>; + * enable-active-high; + */ }; vbat: vbat-regulator { @@ -1196,7 +1202,7 @@ camera@10 { compatible = "ovti,ov8856"; reg = <0x10>; - // CAM0_RST_N + /* CAM0_RST_N */ reset-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&cam0_default>; @@ -1205,7 +1211,8 @@ camera@10 { clock-names = "xvclk"; clock-frequency = <19200000>; - /* The &vreg_s4a_1p8 trace is powered on as a, + /* + * The &vreg_s4a_1p8 trace is powered on as a, * so it is represented by a fixed regulator. * * The 2.8V vdda-supply and 1.2V vddd-supply regulators @@ -1233,10 +1240,10 @@ &cci_i2c1 { camera@60 { compatible = "ovti,ov7251"; - // I2C address as per ov7251.txt linux documentation + /* I2C address as per ov7251.txt linux documentation */ reg = <0x60>; - // CAM3_RST_N + /* CAM3_RST_N */ enable-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&cam3_default>; @@ -1245,7 +1252,8 @@ camera@60 { clock-names = "xclk"; clock-frequency = <24000000>; - /* The &vreg_s4a_1p8 trace always powered on. + /* + * The &vreg_s4a_1p8 trace always powered on. * * The 2.8V vdda-supply regulator is enabled when the * vreg_s4a_1p8 trace is pulled high. @@ -1261,7 +1269,7 @@ camera@60 { port { ov7251_ep: endpoint { data-lanes = <0 1>; -// remote-endpoint = <&csiphy3_ep>; +/* remote-endpoint = <&csiphy3_ep>; */ }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 7e9a66c3cf67..42cf4dd5ea28 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -50,7 +50,8 @@ key-vol-up { }; reserved-memory { - /* The rmtfs_mem needs to be guarded due to "XPU limitations" + /* + * The rmtfs_mem needs to be guarded due to "XPU limitations" * it is otherwise possible for an allocation adjacent to the * rmtfs_mem region to trigger an XPU violation, causing a crash. */ @@ -433,7 +434,7 @@ &mdss { status = "okay"; }; -/* Modem/wifi*/ +/* Modem/wifi */ &mss_pil { status = "okay"; firmware-name = "qcom/sdm845/oneplus6/mba.mbn", "qcom/sdm845/oneplus6/modem.mbn"; diff --git a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts index f93d748e2c94..b712834a5d64 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts @@ -43,7 +43,7 @@ chosen { #size-cells = <2>; ranges; - // Firmware initialized the display at 1280p instead of 1440p + /* Firmware initialized the display at 1280p instead of 1440p */ framebuffer0: framebuffer@80400000 { compatible = "simple-framebuffer"; reg = <0 0x80400000 0 (1920 * 1280 * 4)>; From d5d8e59f356d426ba164ea37adfa629196b4fbd0 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 7 Nov 2022 15:55:17 +0100 Subject: [PATCH 219/261] arm64: dts: qcom: ipq8074-*: Fix up comments Make sure all multiline C-style commends begin with just '/*' with the comment text starting on a new line. Also, fix up some whitespace within comments. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221107145522.6706-8-konrad.dybcio@linaro.org --- arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 3 ++- arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts | 3 ++- arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts | 3 ++- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 12 ++++++------ 4 files changed, 12 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts index c3f3f78271e9..ca3f96646b90 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /dts-v1/; -/* Copyright (c) 2017, The Linux Foundation. All rights reserved. +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. */ #include "ipq8074.dtsi" #include "pmp8074.dtsi" diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts index 2bfcf42aeabc..cc1992ca0519 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2020 The Linux Foundation. All rights reserved. +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts index 7da39f1d979b..d7f0efda6b8e 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /dts-v1/; -/* Copyright (c) 2020 The Linux Foundation. All rights reserved. +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. */ #include "ipq8074-hk10.dtsi" diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index f7cb1d04a367..9d7893327095 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -129,10 +129,10 @@ ssphy_1: phy@58000 { status = "disabled"; usb1_ssphy: phy@58200 { - reg = <0x00058200 0x130>, /* Tx */ + reg = <0x00058200 0x130>, /* Tx */ <0x00058400 0x200>, /* Rx */ - <0x00058800 0x1f8>, /* PCS */ - <0x00058600 0x044>; /* PCS misc*/ + <0x00058800 0x1f8>, /* PCS */ + <0x00058600 0x044>; /* PCS misc */ #phy-cells = <0>; #clock-cells = <0>; clocks = <&gcc GCC_USB1_PIPE_CLK>; @@ -172,10 +172,10 @@ ssphy_0: phy@78000 { status = "disabled"; usb0_ssphy: phy@78200 { - reg = <0x00078200 0x130>, /* Tx */ + reg = <0x00078200 0x130>, /* Tx */ <0x00078400 0x200>, /* Rx */ - <0x00078800 0x1f8>, /* PCS */ - <0x00078600 0x044>; /* PCS misc*/ + <0x00078800 0x1f8>, /* PCS */ + <0x00078600 0x044>; /* PCS misc */ #phy-cells = <0>; #clock-cells = <0>; clocks = <&gcc GCC_USB0_PIPE_CLK>; From 290d43062d261cebd17ff590dc91f1d1e3fe6eed Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 7 Nov 2022 15:55:18 +0100 Subject: [PATCH 220/261] arm64: dts: qcom: msm8992-*: Fix up comments Make sure all multiline C-style commends begin with just '/*' with the comment text starting on a new line. Also, trim off downstream regulator properties from comments to prevent them from accidentally landing into mainline one day.. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221107145522.6706-9-konrad.dybcio@linaro.org --- .../dts/qcom/msm8992-lg-bullhead-rev-10.dts | 3 +- .../dts/qcom/msm8992-lg-bullhead-rev-101.dts | 3 +- .../boot/dts/qcom/msm8992-lg-bullhead.dtsi | 41 ++++++++++--------- arch/arm64/boot/dts/qcom/msm8992.dtsi | 3 +- 4 files changed, 28 insertions(+), 22 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-10.dts b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-10.dts index 7e6bce4af441..4159fc35571a 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-10.dts +++ b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-10.dts @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) Jean Thomas +/* + * Copyright (c) Jean Thomas */ /dts-v1/; diff --git a/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-101.dts index e6a5ebd30e2f..ad9702dd171b 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-101.dts +++ b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-101.dts @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) Jean Thomas +/* + * Copyright (c) Jean Thomas */ /dts-v1/; diff --git a/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi index aef92f3c49da..87c90e93667f 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2015, LGE Inc. All rights reserved. +/* + * Copyright (c) 2015, LGE Inc. All rights reserved. * Copyright (c) 2016, The Linux Foundation. All rights reserved. * Copyright (c) 2021, Petr Vorel */ @@ -236,9 +237,11 @@ pm8994_l25: l25 { }; pm8994_l26: l26 { - /* TODO: value from downstream - regulator-min-microvolt = <987500>; - fails to apply */ + /* + * TODO: value from downstream + * regulator-min-microvolt = <987500>; + * fails to apply + */ }; pm8994_l27: l27 { @@ -252,19 +255,19 @@ pm8994_l28: l28 { }; pm8994_l29: l29 { - /* TODO: Unsupported voltage range. - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - qcom,init-voltage = <2800000>; - */ + /* + * TODO: Unsupported voltage range. + * regulator-min-microvolt = <2800000>; + * regulator-max-microvolt = <2800000>; + */ }; pm8994_l30: l30 { - /* TODO: get this verified - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,init-voltage = <1800000>; - */ + /* + * TODO: get this verified + * regulator-min-microvolt = <1800000>; + * regulator-max-microvolt = <1800000>; + */ }; pm8994_l31: l31 { @@ -273,11 +276,11 @@ pm8994_l31: l31 { }; pm8994_l32: l32 { - /* TODO: get this verified - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,init-voltage = <1800000>; - */ + /* + * TODO: get this verified + * regulator-min-microvolt = <1800000>; + * regulator-max-microvolt = <1800000>; + */ }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index 750643763a76..10adb4986ef1 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. +/* + * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. */ #include "msm8994.dtsi" From 79b185d055703004aeb9252f2aa60ab03c868803 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 7 Nov 2022 15:55:19 +0100 Subject: [PATCH 221/261] arm64: dts: qcom: msm8994-*: Fix up comments Make sure all multiline C-style commends begin with just '/*' with the comment text starting on a new line. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221107145522.6706-10-konrad.dybcio@linaro.org --- arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts | 3 ++- arch/arm64/boot/dts/qcom/msm8994.dtsi | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts index dbfbb77e9ff5..85abff0e9b3f 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts +++ b/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2015, Huawei Inc. All rights reserved. +/* + * Copyright (c) 2015, Huawei Inc. All rights reserved. * Copyright (c) 2016, The Linux Foundation. All rights reserved. * Copyright (c) 2021-2022, Petr Vorel */ diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index ba687e64ba3c..adcea31a0c68 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. +/* + * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. */ #include From 3e3a2be79035a9e554ee5f62faf955601f85fca9 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 7 Nov 2022 15:55:20 +0100 Subject: [PATCH 222/261] arm64: dts: qcom: qcs404-*: Fix up comments Switch '//' comments to C-style /* */. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221107145522.6706-11-konrad.dybcio@linaro.org --- arch/arm64/boot/dts/qcom/qcs404-evb-1000.dts | 4 +++- arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts | 4 +++- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 4 +++- arch/arm64/boot/dts/qcom/qcs404.dtsi | 4 +++- 4 files changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb-1000.dts b/arch/arm64/boot/dts/qcom/qcs404-evb-1000.dts index 937eb4555ffe..fc29b194cd34 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb-1000.dts +++ b/arch/arm64/boot/dts/qcom/qcs404-evb-1000.dts @@ -1,5 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018, Linaro Limited +/* + * Copyright (c) 2018, Linaro Limited + */ /dts-v1/; diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts b/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts index 9c7d4e780357..59702ba24f35 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts +++ b/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts @@ -1,5 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018, Linaro Limited +/* + * Copyright (c) 2018, Linaro Limited + */ /dts-v1/; diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index 4d53cd544e41..04c82d1624eb 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -1,5 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018, Linaro Limited +/* + * Copyright (c) 2018, Linaro Limited + */ #include #include "qcs404.dtsi" diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 577d76662468..a5324eecb50a 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -1,5 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018, Linaro Limited +/* + * Copyright (c) 2018, Linaro Limited + */ #include #include From 5d9bf21088fddefe681a70d061b78b9b58fb764b Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 7 Nov 2022 15:55:21 +0100 Subject: [PATCH 223/261] arm64: dts: qcom: pm6150/l/pm7325/pms405: Fix up comments Make sure all multiline C-style commends begin with just '/*' with the comment text starting on a new line. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221107145522.6706-12-konrad.dybcio@linaro.org --- arch/arm64/boot/dts/qcom/pm6150.dtsi | 4 +++- arch/arm64/boot/dts/qcom/pm6150l.dtsi | 4 +++- arch/arm64/boot/dts/qcom/pm7325.dtsi | 4 +++- arch/arm64/boot/dts/qcom/pms405.dtsi | 4 +++- 4 files changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm6150.dtsi b/arch/arm64/boot/dts/qcom/pm6150.dtsi index 3cfd3eadccbf..3d91fb405ca2 100644 --- a/arch/arm64/boot/dts/qcom/pm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150.dtsi @@ -1,5 +1,7 @@ // SPDX-License-Identifier: BSD-3-Clause -// Copyright (c) 2019, The Linux Foundation. All rights reserved. +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ #include #include diff --git a/arch/arm64/boot/dts/qcom/pm6150l.dtsi b/arch/arm64/boot/dts/qcom/pm6150l.dtsi index 0cf99a53a309..90aac61ad264 100644 --- a/arch/arm64/boot/dts/qcom/pm6150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150l.dtsi @@ -1,5 +1,7 @@ // SPDX-License-Identifier: BSD-3-Clause -// Copyright (c) 2019, The Linux Foundation. All rights reserved. +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ #include #include diff --git a/arch/arm64/boot/dts/qcom/pm7325.dtsi b/arch/arm64/boot/dts/qcom/pm7325.dtsi index cfd4b80c6e35..d1c5476af5ee 100644 --- a/arch/arm64/boot/dts/qcom/pm7325.dtsi +++ b/arch/arm64/boot/dts/qcom/pm7325.dtsi @@ -1,5 +1,7 @@ // SPDX-License-Identifier: BSD-3-Clause -// Copyright (c) 2021, The Linux Foundation. All rights reserved. +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ #include #include diff --git a/arch/arm64/boot/dts/qcom/pms405.dtsi b/arch/arm64/boot/dts/qcom/pms405.dtsi index 634b0681d04c..ffe9e33808d0 100644 --- a/arch/arm64/boot/dts/qcom/pms405.dtsi +++ b/arch/arm64/boot/dts/qcom/pms405.dtsi @@ -1,5 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018, Linaro Limited +/* + * Copyright (c) 2018, Linaro Limited + */ #include #include From 4ab3acd6379242281d4a55acfd6441830f1984a0 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Mon, 31 Oct 2022 18:51:18 +0100 Subject: [PATCH 224/261] arm64: dts: qcom: pm8998: adjust coincell node name to bindings The spmi-pmic bindings say that pm8941-coincell should be called 'charger'. Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221031175119.939860-3-luca@z3ntu.xyz --- arch/arm64/boot/dts/qcom/pm8998.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pm8998.dtsi b/arch/arm64/boot/dts/qcom/pm8998.dtsi index 0d5163c720b7..6a0e14382be8 100644 --- a/arch/arm64/boot/dts/qcom/pm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8998.dtsi @@ -63,7 +63,7 @@ pm8998_temp: temp-alarm@2400 { #thermal-sensor-cells = <0>; }; - pm8998_coincell: coincell@2800 { + pm8998_coincell: charger@2800 { compatible = "qcom,pm8941-coincell"; reg = <0x2800>; From 3de1172624b3c4ca65730bc34333ab493510b3e1 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 26 Oct 2022 12:36:46 -0400 Subject: [PATCH 225/261] arm64: dts: qcom: sm6125: fix SDHCI CQE reg names SM6125 comes with SDCC (SDHCI controller) v5, so the second range of registers is cqhci, not core. Fixes: cff4bbaf2a2d ("arm64: dts: qcom: Add support for SM6125") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Marijn Suijten Tested-by: Marijn Suijten # Sony Xperia 10 II Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221026163646.37433-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index af49a748e511..24ee7c0c1195 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -458,7 +458,7 @@ rpm_msg_ram: sram@45f0000 { sdhc_1: mmc@4744000 { compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5"; reg = <0x04744000 0x1000>, <0x04745000 0x1000>; - reg-names = "hc", "core"; + reg-names = "hc", "cqhci"; interrupts = , ; From f53152d1d4e6c711bb9728611bbe0b32deda36b1 Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Mon, 7 Nov 2022 22:47:01 +0100 Subject: [PATCH 226/261] arm64: dts: qcom: sm6125: Enable Command Queue Engine (CQE) for SDHCI 1 Downstream sources confirm sm6125 supports CQE, and after fixing the reg name for this range [1] this feature probes and enables correctly: [ 0.391950] sdhci_msm 4744000.mmc: mmc0: CQE init: success [1]: https://lore.kernel.org/all/20221026163646.37433-1-krzysztof.kozlowski@linaro.org/ Signed-off-by: Marijn Suijten Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221107214702.311271-1-marijn.suijten@somainline.org --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 24ee7c0c1195..7e25a4f85594 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -476,6 +476,8 @@ sdhc_1: mmc@4744000 { bus-width = <8>; non-removable; + supports-cqe; + status = "disabled"; }; From aefd5370ab5e55a18c94573b9602083132e24601 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Mon, 7 Nov 2022 11:15:34 -0800 Subject: [PATCH 227/261] arm64: dts: qcom: sc7280: Fully describe fingerprint node on Herobrine Update the fingerprint node on Herobrine to match the fingerprint DT binding. This will allow us to drive the reset and boot gpios from the driver when it is re-attached after flashing. We'll also be able to boot the fingerprint processor if the BIOS isn't doing it for us. Cc: Douglas Anderson Cc: Matthias Kaehlcke Cc: Alexandru M Stan Signed-off-by: Stephen Boyd Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221107191535.624371-2-swboyd@chromium.org --- arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index ca02ef26f161..448da9794722 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -503,13 +503,16 @@ ap_spi_fp: &spi9 { cs-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>; cros_ec_fp: ec@0 { - compatible = "google,cros-ec-spi"; + compatible = "google,cros-ec-fp", "google,cros-ec-spi"; reg = <0>; interrupt-parent = <&tlmm>; interrupts = <61 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&fp_to_ap_irq_l>, <&fp_rst_l>, <&fpmcu_boot0>; + boot0-gpios = <&tlmm 68 GPIO_ACTIVE_HIGH>; + reset-gpios = <&tlmm 78 GPIO_ACTIVE_LOW>; spi-max-frequency = <3000000>; + vdd-supply = <&pp3300_fp_mcu>; }; }; From 9ec68fea9e53d25177618d2ce1bc4a1b1b724938 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Mon, 7 Nov 2022 11:15:35 -0800 Subject: [PATCH 228/261] arm64: dts: qcom: sc7180: Fully describe fingerprint node on Trogdor Update the fingerprint node on Trogdor to match the fingerprint DT binding. This will allow us to drive the reset and boot gpios from the driver when it is re-attached after flashing. We'll also be able to boot the fingerprint processor if the BIOS isn't doing it for us. Cc: Douglas Anderson Cc: Matthias Kaehlcke Cc: Alexandru M Stan Signed-off-by: Stephen Boyd Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221107191535.624371-3-swboyd@chromium.org --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 4a5ea17a15ba..65601bea0797 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -894,13 +894,16 @@ ap_spi_fp: &spi10 { cs-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; cros_ec_fp: ec@0 { - compatible = "google,cros-ec-spi"; + compatible = "google,cros-ec-fp", "google,cros-ec-spi"; reg = <0>; interrupt-parent = <&tlmm>; interrupts = <4 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; - pinctrl-0 = <&fp_to_ap_irq_l>; + pinctrl-0 = <&fp_to_ap_irq_l>, <&fp_rst_l>, <&fpmcu_boot0>; + boot0-gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>; + reset-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>; spi-max-frequency = <3000000>; + vdd-supply = <&pp3300_fp_tp>; }; }; @@ -1226,6 +1229,13 @@ en_pp3300_hub: en-pp3300-hub-state { bias-disable; }; + fp_rst_l: fp-rst-l-state { + pins = "gpio22"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + fp_to_ap_irq_l: fp-to-ap-irq-l-state { pins = "gpio4"; function = "gpio"; @@ -1235,6 +1245,12 @@ fp_to_ap_irq_l: fp-to-ap-irq-l-state { bias-disable; }; + fpmcu_boot0: fpmcu-boot0-state { + pins = "gpio10"; + function = "gpio"; + bias-disable; + }; + h1_ap_int_odl: h1-ap-int-odl-state { pins = "gpio42"; function = "gpio"; From 7c1b74e079b983196512769f19812d883d4b87fa Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 7 Nov 2022 13:09:16 +0100 Subject: [PATCH 229/261] dt-bindings: arm: cpus: Add Kryo 660 CPUs Add a compatible for Kryo 660 CPUs found in at least Qualcomm SM6375. Signed-off-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221107120920.12593-1-konrad.dybcio@linaro.org --- Documentation/devicetree/bindings/arm/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 5c13b73e4d57..b2058345bb8e 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -183,6 +183,7 @@ properties: - qcom,kryo485 - qcom,kryo560 - qcom,kryo570 + - qcom,kryo660 - qcom,kryo685 - qcom,kryo780 - qcom,scorpion From 59d34ca97f91df08d56d3ac843c7a8c6935bfca8 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 7 Nov 2022 13:09:18 +0100 Subject: [PATCH 230/261] arm64: dts: qcom: Add initial device tree for SM6375 Add an initial device tree for the SM6375 (SD695) SoC. Signed-off-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221107120920.12593-3-konrad.dybcio@linaro.org --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 804 +++++++++++++++++++++++++++ 1 file changed, 804 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm6375.dtsi diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi new file mode 100644 index 000000000000..9b1a497e5ca7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -0,0 +1,804 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Konrad Dybcio + */ + +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board_clk: xo-board-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo660"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_0: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo660"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&L2_100>; + qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_100: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo660"; + reg = <0x0 0x200>; + enable-method = "psci"; + next-level-cache = <&L2_200>; + qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_200: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo660"; + reg = <0x0 0x300>; + enable-method = "psci"; + next-level-cache = <&L2_300>; + qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_300: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo660"; + reg = <0x0 0x400>; + enable-method = "psci"; + next-level-cache = <&L2_400>; + qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_400: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo660"; + reg = <0x0 0x500>; + enable-method = "psci"; + next-level-cache = <&L2_500>; + qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_500: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo660"; + reg = <0x0 0x600>; + enable-method = "psci"; + next-level-cache = <&L2_600>; + qcom,freq-domain = <&cpufreq_hw 1>; + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_600: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo660"; + reg = <0x0 0x700>; + enable-method = "psci"; + next-level-cache = <&L2_700>; + qcom,freq-domain = <&cpufreq_hw 1>; + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_700: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + + core4 { + cpu = <&CPU4>; + }; + + core5 { + cpu = <&CPU5>; + }; + + core6 { + cpu = <&CPU6>; + }; + + core7 { + cpu = <&CPU7>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "silver-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <702>; + exit-latency-us = <915>; + min-residency-us = <4001>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "gold-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <526>; + exit-latency-us = <1854>; + min-residency-us = <5555>; + local-timer-stop; + }; + }; + + domain-idle-states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "domain-idle-state"; + idle-state-name = "cluster-power-collapse"; + arm,psci-suspend-param = <0x41000044>; + entry-latency-us = <2752>; + exit-latency-us = <3048>; + min-residency-us = <6118>; + local-timer-stop; + }; + }; + }; + + firmware { + scm { + compatible = "qcom,scm-sm6375", "qcom,scm"; + clocks = <&rpmcc RPM_SMD_CE1_CLK>; + clock-names = "core"; + #reset-cells = <1>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0x80000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD1: cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD2: cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD3: cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD4: cpu4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD5: cpu5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD6: cpu6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD7: cpu7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CLUSTER_PD: cpu-cluster0 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_0>; + }; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hypervisor@80000000 { + reg = <0 0x80000000 0 0x600000>; + no-map; + }; + + xbl_aop_mem: xbl-aop@80700000 { + reg = <0 0x80700000 0 0x100000>; + no-map; + }; + + reserved_xbl_uefi: xbl-uefi-res@80880000 { + reg = <0 0x80880000 0 0x14000>; + no-map; + }; + + smem_mem: smem@80900000 { + compatible = "qcom,smem"; + reg = <0 0x80900000 0 0x200000>; + hwlocks = <&tcsr_mutex 3>; + no-map; + }; + + fw_mem: fw@80b00000 { + reg = <0 0x80b00000 0 0x100000>; + no-map; + }; + + cdsp_secure_heap_mem: cdsp-sec-heap@80c00000 { + reg = <0 0x80c00000 0 0x1e00000>; + no-map; + }; + + dfps_data_mem: dpfs-data@85e00000 { + reg = <0 0x85e00000 0 0x100000>; + no-map; + }; + + pil_wlan_mem: pil-wlan@86500000 { + reg = <0 0x86500000 0 0x200000>; + no-map; + }; + + pil_adsp_mem: pil-adsp@86700000 { + reg = <0 0x86700000 0 0x2000000>; + no-map; + }; + + pil_cdsp_mem: pil-cdsp@88700000 { + reg = <0 0x88700000 0 0x1e00000>; + no-map; + }; + + pil_video_mem: pil-video@8a500000 { + reg = <0 0x8a500000 0 0x500000>; + no-map; + }; + + pil_ipa_fw_mem: pil-ipa-fw@8aa00000 { + reg = <0 0x8aa00000 0 0x10000>; + no-map; + }; + + pil_ipa_gsi_mem: pil-ipa-gsi@8aa10000 { + reg = <0 0x8aa10000 0 0xa000>; + no-map; + }; + + pil_gpu_micro_code_mem: pil-gpu-ucode@8aa1a000 { + reg = <0 0x8aa1a000 0 0x2000>; + no-map; + }; + + pil_mpss_wlan_mem: pil-mpss-wlan@8b800000 { + reg = <0 0x8b800000 0 0x10000000>; + no-map; + }; + + removed_mem: removed@c0000000 { + reg = <0 0xc0000000 0 0x5100000>; + no-map; + }; + + debug_mem: debug@ffb00000 { + reg = <0 0xffb00000 0 0xc0000>; + no-map; + }; + + last_log_mem: lastlog@ffbc0000 { + reg = <0 0xffbc0000 0 0x80000>; + no-map; + }; + + cmdline_region: cmdline@ffd00000 { + reg = <0 0xffd00000 0 0x1000>; + no-map; + }; + }; + + rpm-glink { + compatible = "qcom,glink-rpm"; + interrupts-extended = <&ipcc IPCC_CLIENT_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-sm6375"; + qcom,glink-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-sm6375", "qcom,rpmcc"; + clocks = <&xo_board_clk>; + clock-names = "xo"; + #clock-cells = <1>; + }; + + rpmpd: power-controller { + compatible = "qcom,sm6375-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmpd_opp_min_svs: opp2 { + opp-level = ; + }; + + rpmpd_opp_low_svs: opp3 { + opp-level = ; + }; + + rpmpd_opp_svs: opp4 { + opp-level = ; + }; + + rpmpd_opp_svs_plus: opp5 { + opp-level = ; + }; + + rpmpd_opp_nom: opp6 { + opp-level = ; + }; + + rpmpd_opp_nom_plus: opp7 { + opp-level = ; + }; + + rpmpd_opp_turbo: opp8 { + opp-level = ; + }; + + rpmpd_opp_turbo_no_cpr: opp9 { + opp-level = ; + }; + }; + }; + }; + }; + + soc: soc@0 { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + compatible = "simple-bus"; + + ipcc: mailbox@208000 { + compatible = "qcom,sm6375-ipcc", "qcom,ipcc"; + reg = <0 0x00208000 0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + tcsr_mutex: hwlock@340000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x00340000 0x0 0x40000>; + #hwlock-cells = <1>; + }; + + tlmm: pinctrl@500000 { + compatible = "qcom,sm6375-tlmm"; + reg = <0 0x00500000 0 0x800000>; + interrupts = ; + gpio-ranges = <&tlmm 0 0 157>; + /* TODO: Hook up MPM as wakeup-parent when it's there */ + interrupt-controller; + gpio-controller; + #interrupt-cells = <2>; + #gpio-cells = <2>; + }; + + gcc: clock-controller@1400000 { + compatible = "qcom,sm6375-gcc"; + reg = <0 0x01400000 0 0x1f0000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&rpmcc RPM_SMD_XO_A_CLK_SRC>, + <&sleep_clk>; + #power-domain-cells = <1>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + usb_1_hsphy: phy@162b000 { + compatible = "qcom,sm6375-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy"; + reg = <0 0x0162b000 0 0x400>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "ref"; + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + #phy-cells = <0>; + + status = "disabled"; + }; + + spmi_bus: spmi@1c40000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0 0x01c40000 0 0x1100>, + <0 0x01e00000 0 0x2000000>, + <0 0x03e00000 0 0x100000>, + <0 0x03f00000 0 0xa0000>, + <0 0x01c0a000 0 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + rpm_msg_ram: sram@45f0000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0 0x045f0000 0 0x7000>; + }; + + usb_1: usb@4ef8800 { + compatible = "qcom,sm6375-dwc3", "qcom,dwc3"; + reg = <0 0x04ef8800 0 0x400>; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "xo"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <133333333>; + + interrupts = , + , + , + ; + interrupt-names = "hs_phy_irq", + "ss_phy_irq", + "dm_hs_phy_irq", + "dp_hs_phy_irq"; + + power-domains = <&gcc USB30_PRIM_GDSC>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + /* + * This property is there to allow USB2 to work, as + * USB3 is not implemented yet - (re)move it when + * proper support is in place. + */ + qcom,select-utmi-as-pipe-clk; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + usb_1_dwc3: usb@4e00000 { + compatible = "snps,dwc3"; + reg = <0 0x04e00000 0 0xcd00>; + interrupts = ; + maximum-speed = "high-speed"; + phys = <&usb_1_hsphy>; + phy-names = "usb2-phy"; + iommus = <&apps_smmu 0xe0 0x0>; + + /* Yes, this impl *does* have an unfunny number of quirks.. */ + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb2-gadget-lpm-disable; + snps,dis_u2_susphy_quirk; + snps,is-utmi-l1-suspend; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,usb3_lpm_capable; + snps,has-lpm-erratum; + tx-fifo-resize; + }; + }; + + apps_smmu: iommu@c600000 { + compatible = "qcom,sm6375-smmu-500", "arm,mmu-500"; + reg = <0 0x0c600000 0 0x100000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + power-domains = <&gcc HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC>, + <&gcc HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC>, + <&gcc HLOS1_VOTE_TURING_MMU_TBU0_GDSC>; + #global-interrupts = <1>; + #iommu-cells = <2>; + }; + + intc: interrupt-controller@f200000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x0f200000 0x0 0x10000>, /* GICD */ + <0x0 0x0f240000 0x0 0x100000>; /* GICR * 8 */ + interrupts = ; + #redistributor-regions = <1>; + #interrupt-cells = <3>; + redistributor-stride = <0 0x20000>; + interrupt-controller; + }; + + timer@f420000 { + compatible = "arm,armv7-timer-mem"; + reg = <0 0x0f420000 0 0x1000>; + ranges = <0 0 0 0x20000000>; + #address-cells = <1>; + #size-cells = <1>; + + frame@f421000 { + reg = <0x0f421000 0x1000>, <0x0f422000 0x1000>; + interrupts = , + ; + frame-number = <0>; + }; + + frame@f423000 { + reg = <0x0f243000 0x1000>; + interrupts = ; + frame-number = <1>; + status = "disabled"; + }; + + frame@f425000 { + reg = <0x0f425000 0x1000>; + interrupts = ; + frame-number = <2>; + status = "disabled"; + }; + + frame@f427000 { + reg = <0x0f427000 0x1000>; + interrupts = ; + frame-number = <3>; + status = "disabled"; + }; + + frame@f429000 { + reg = <0x0f429000 0x1000>; + interrupts = ; + frame-number = <4>; + status = "disabled"; + }; + + frame@f42b000 { + reg = <0x0f42b000 0x1000>; + interrupts = ; + frame-number = <5>; + status = "disabled"; + }; + + frame@f42d000 { + reg = <0x0f42d000 0x1000>; + interrupts = ; + frame-number = <6>; + status = "disabled"; + }; + }; + + cpufreq_hw: cpufreq@fd91000 { + compatible = "qcom,sm6375-cpufreq-epss", "qcom,cpufreq-epss"; + reg = <0 0x0fd91000 0 0x1000>, <0 0x0fd92000 0 0x1000>; + reg-names = "freq-domain0", "freq-domain1"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + interrupts = , + ; + interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; + #freq-domain-cells = <1>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; From 4420e60416cb9073fb0d2cb6f10d1830e2a84646 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 7 Nov 2022 13:09:19 +0100 Subject: [PATCH 231/261] arm64: dts: qcom: Add device tree for Sony Xperia 10 IV Add support for Sony Xperia 10 IV, a.k.a PDX225. This device is a part of the SoMC SM6375 Murray platform and currently it is the only device based on that board, so no -common DTSI is created until (if?) other Murray devices appear. This commit brings support for: * USB (only USB2 for now) * Display via simplefb To create a working boot image, you need to run: cat arch/arm64/boot/Image.gz arch/arm64/boot/dts/qcom/sm6375-sony-xperia-\ murray-pdx225.dtb > .Image.gz-dtb mkbootimg \ --kernel .Image.gz-dtb \ --ramdisk some_initrd.img \ --pagesize 4096 \ --base 0x0 \ --kernel_offset 0x8000 \ --ramdisk_offset 0x1000000 \ --tags_offset 0x100 \ --cmdline "SOME_CMDLINE" \ --dtb_offset 0x1f00000 \ --header_version 1 \ --os_version 12 \ --os_patch_level 2022-04 \ # or newer -o boot.img-sony-xperia-pdx225 Then, you need to flash it on the device and get rid of all the vendor_boot/dtbo mess: First, you need to get rid of vendor_boot. However, the bootloader is utterly retarded and it will not let you neither flash nor erase it. There are a couple ways to handle this: you can either dd /dev/zero to it from Android (if you have root) or a custom recovery or from fastbootd (fastboot/adb reboot fastboot). You will not be able to boot Android images on your phone unless you lock the bootloader (fastboot oem lock) and restore the factory image with Xperia Companion Windows-and-macOS-only software. The best way so far is probably to use the second (_b) slot and flash mainline there. This will however require you to flash some partitions manually, as they are not populated from factory: (boot_b, dtbo_b, vendor_boot_b, vbmeta_b, vbmeta_system_b) - these we don't really care about as we nuke/replace them (dsp_b, imagefv_b, modem_b, oem_b, rdimage_b) - these you NEED to populate to get a successful boot on slot B, otherwise you will have limited / no functionality. To switch slots, simply run: fastboot --set-active=a //or =b The rest assumes you are on slot A. // You have to either pull vbmeta{"","_system"} from // /dev/block/bootdevice/by-name/ or build one as a part of AOSP fastboot --disable-verity --disable-verification flash vbmeta_b vbmeta.img fastboot --disable-verity --disable-verification flash vbmeta_system_b \ vbmeta_system.img fastboot flash boot_b boot.img-sony-xperia-pdx225 fastboot reboot fastboot // entering fastbootd fastboot flash vendor_boot_b emptything.img fastboot flash dtbo_b emptything.img fastboot reboot bootloader // entering bootloader fastboot fastboot --set-active=b fastboot reboot // mainline time! Where emptything.img is a tiny file that consists of 2 bytes (all zeroes), doing a "fastboot erase" won't cut it, the bootloader will go crazy and things will fall apart when it tries to overlay random bytes from an empty partition onto a perfectly good appended DTB. From there on you can flash new mainline builds by simply flashing boot.img that you create after each kernel rebuild. Signed-off-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221107120920.12593-4-konrad.dybcio@linaro.org --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../qcom/sm6375-sony-xperia-murray-pdx225.dts | 86 +++++++++++++++++++ 2 files changed, 87 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 8b4a63749a6c..d534888bcfe5 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -149,6 +149,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb dtb-$(CONFIG_ARCH_QCOM) += sm4250-oneplus-billie2.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6350-sony-xperia-lena-pdx213.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm6375-sony-xperia-murray-pdx225.dtb dtb-$(CONFIG_ARCH_QCOM) += sm7225-fairphone-fp4.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-microsoft-surface-duo.dtb diff --git a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts new file mode 100644 index 000000000000..450d4a557df1 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Konrad Dybcio + */ + +/dts-v1/; + +#include +#include "sm6375.dtsi" +#include "pmr735a.dtsi" + +/ { + model = "Sony Xperia 10 IV"; + compatible = "sony,pdx225", "qcom,sm6375"; + chassis-type = "handset"; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer: framebuffer@85200000 { + compatible = "simple-framebuffer"; + reg = <0 0x85200000 0 0xc00000>; + + width = <1080>; + height = <2520>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + /* + * That's (going to be) a lot of clocks, but it's necessary due + * to unused clk cleanup & no panel driver yet + */ + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_THROTTLE_CORE_CLK>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; + }; + }; + + reserved-memory { + cont_splash_mem: memory@85200000 { + reg = <0 0x85200000 0 0xc00000>; + no-map; + }; + + ramoops@ffc40000 { + compatible = "ramoops"; + reg = <0 0xffc40000 0 0xb0000>; + record-size = <0x10000>; + console-size = <0x60000>; + ftrace-size = <0x10000>; + pmsg-size = <0x20000>; + ecc-size = <16>; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&tlmm { + gpio-reserved-ranges = <13 4>; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + status = "okay"; +}; + +&xo_board_clk { + clock-frequency = <19200000>; +}; From 6d9a666d49bf57c6a176e5fcf1b39046ee6a728f Mon Sep 17 00:00:00 2001 From: Job Noorman Date: Mon, 7 Nov 2022 11:56:04 +0100 Subject: [PATCH 232/261] arm64: dts: qcom: sdm632: fairphone-fp3: add touchscreen Add Himax hx83112b touchscreen to the FP3 DT. Signed-off-by: Job Noorman Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221107105604.26541-4-job@noorman.info --- arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts index c238fba2fe7c..3fb513cad0a9 100644 --- a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts +++ b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts @@ -49,6 +49,20 @@ &hsusb_phy { vdda-phy-dpdm-supply = <&pm8953_l13>; }; +&i2c_3 { + status = "okay"; + + touchscreen@48 { + compatible = "himax,hx83112b"; + reg = <0x48>; + interrupt-parent = <&tlmm>; + interrupts = <65 IRQ_TYPE_LEVEL_LOW>; + touchscreen-size-x = <1080>; + touchscreen-size-y = <2160>; + reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; + }; +}; + &pm8953_resin { status = "okay"; linux,code = ; From d6e636787d462c047a424dd442b68a249edde2a7 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 2 Nov 2022 21:44:10 +0300 Subject: [PATCH 233/261] arm64: dts: qcom: msm8996: change order of SMMU clocks on this platform Change order of SMMU clocks to match the schema. Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221102184420.534094-2-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 31 +++++++++++++-------------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 747e1aac497f..1e976dcb416d 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -2234,9 +2234,9 @@ adreno_smmu: iommu@b40000 { ; #iommu-cells = <1>; - clocks = <&mmcc GPU_AHB_CLK>, - <&gcc GCC_MMSS_BIMC_GFX_CLK>; - clock-names = "iface", "bus"; + clocks = <&gcc GCC_MMSS_BIMC_GFX_CLK>, + <&mmcc GPU_AHB_CLK>; + clock-names = "bus", "iface"; power-domains = <&mmcc GPU_GDSC>; }; @@ -2301,9 +2301,9 @@ mdp_smmu: iommu@d00000 { , ; #iommu-cells = <1>; - clocks = <&mmcc SMMU_MDP_AHB_CLK>, - <&mmcc SMMU_MDP_AXI_CLK>; - clock-names = "iface", "bus"; + clocks = <&mmcc SMMU_MDP_AXI_CLK>, + <&mmcc SMMU_MDP_AHB_CLK>; + clock-names = "bus", "iface"; power-domains = <&mmcc MDSS_GDSC>; }; @@ -2321,9 +2321,9 @@ venus_smmu: iommu@d40000 { , ; power-domains = <&mmcc MMAGIC_VIDEO_GDSC>; - clocks = <&mmcc SMMU_VIDEO_AHB_CLK>, - <&mmcc SMMU_VIDEO_AXI_CLK>; - clock-names = "iface", "bus"; + clocks = <&mmcc SMMU_VIDEO_AXI_CLK>, + <&mmcc SMMU_VIDEO_AHB_CLK>; + clock-names = "bus", "iface"; #iommu-cells = <1>; status = "okay"; }; @@ -2337,10 +2337,9 @@ vfe_smmu: iommu@da0000 { , ; power-domains = <&mmcc MMAGIC_CAMSS_GDSC>; - clocks = <&mmcc SMMU_VFE_AHB_CLK>, - <&mmcc SMMU_VFE_AXI_CLK>; - clock-names = "iface", - "bus"; + clocks = <&mmcc SMMU_VFE_AXI_CLK>, + <&mmcc SMMU_VFE_AHB_CLK>; + clock-names = "bus", "iface"; #iommu-cells = <1>; }; @@ -2365,9 +2364,9 @@ lpass_q6_smmu: iommu@1600000 { , ; - clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>, - <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>; - clock-names = "iface", "bus"; + clocks = <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>, + <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>; + clock-names = "bus", "iface"; }; slpi_pil: remoteproc@1c00000 { From 2ffa0ca4d37a1fef0b423f32007067fbce8708a3 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Tue, 18 Oct 2022 17:28:34 +0200 Subject: [PATCH 234/261] arm64: dts: qcom: Add power-domains property for apps_rsc Add power-domains property which allows apps_rsc device to attach to cluster power domain on sm8150, sm8250, sm8350 and sm8450. Signed-off-by: Maulik Shah Reviewed-by: Ulf Hansson Tested-by: Dmitry Baryshkov # SM8450 Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221018152837.619426-4-ulf.hansson@linaro.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 1 + arch/arm64/boot/dts/qcom/sm8250.dtsi | 1 + arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 + arch/arm64/boot/dts/qcom/sm8450.dtsi | 1 + 4 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 18bf51ce8b13..d1b64280ab0b 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -3890,6 +3890,7 @@ apps_rsc: rsc@18200000 { , , ; + power-domains = <&CLUSTER_PD>; rpmhcc: clock-controller { compatible = "qcom,sm8150-rpmh-clk"; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 076c161d76f6..7a77251dc529 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -4818,6 +4818,7 @@ apps_rsc: rsc@18200000 { qcom,drv-id = <2>; qcom,tcs-config = , , , ; + power-domains = <&CLUSTER_PD>; rpmhcc: clock-controller { compatible = "qcom,sm8250-rpmh-clk"; diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index fa5911976b0f..552c0da3c479 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2004,6 +2004,7 @@ apps_rsc: rsc@18200000 { qcom,drv-id = <2>; qcom,tcs-config = , , , ; + power-domains = <&CLUSTER_PD>; rpmhcc: clock-controller { compatible = "qcom,sm8350-rpmh-clk"; diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 46f9576f786f..fcc61bc849c8 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3189,6 +3189,7 @@ apps_rsc: rsc@17a00000 { qcom,drv-id = <2>; qcom,tcs-config = , , , ; + power-domains = <&CLUSTER_PD>; apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; From d4d4a7c4fd5f1b802ccf329edf11a3ade69b55e0 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Tue, 8 Nov 2022 14:16:25 -0600 Subject: [PATCH 235/261] arm64: dts: qcom: sc7280-idp: don't modify &ipa twice In "sc7280-idp.dts", the IPA node is modified after being defined. However that file includes "sc7280-idp.dtsi", which also modifies the IPA node (in the same way). This only needs to be done in "sc7280-idp.dtsi". Signed-off-by: Alex Elder Reviewed-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221108201625.1220919-1-elder@linaro.org --- arch/arm64/boot/dts/qcom/sc7280-idp.dts | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts index 7559164cdda0..9ddfdfdd354e 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts @@ -61,11 +61,6 @@ &bluetooth { vddio-supply = <&vreg_l19b_1p8>; }; -&ipa { - status = "okay"; - modem-init; -}; - &pmk8350_rtc { status = "okay"; }; From bd35f4b0179692cacc8cd80aece56012b3b36c69 Mon Sep 17 00:00:00 2001 From: Srinivasa Rao Mandadapu Date: Tue, 8 Nov 2022 20:16:00 +0530 Subject: [PATCH 236/261] arm64: dts: qcom: Update soundwire secondary node names Update soundwire secondary nodes of WSA speaker to match with dt-bindings pattern properties regular expression. This modification is required to avoid dtbs-check errors occurred with qcom,soundwire.yaml. Signed-off-by: Srinivasa Rao Mandadapu Co-developed-by: Ratna Deepthi Kudaravalli Signed-off-by: Ratna Deepthi Kudaravalli Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1667918763-32445-2-git-send-email-quic_srivasam@quicinc.com --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 4 ++-- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 4 ++-- arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 4 ++-- arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 4 ++-- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 2c0850016cc4..4c39cec0b13e 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -1007,7 +1007,7 @@ can@0 { }; &swr0 { - left_spkr: wsa8810-left { + left_spkr: speaker@0,3 { compatible = "sdw10217211000"; reg = <0 3>; powerdown-gpios = <&tlmm 130 GPIO_ACTIVE_HIGH>; @@ -1016,7 +1016,7 @@ left_spkr: wsa8810-left { #sound-dai-cells = <0>; }; - right_spkr: wsa8810-right { + right_spkr: speaker@0,4 { compatible = "sdw10217211000"; reg = <0 4>; powerdown-gpios = <&tlmm 130 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 02dcf75c0745..3e7ceb0861eb 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -1101,7 +1101,7 @@ &wcd9340 { vdd-io-supply = <&vreg_s4a_1p8>; swm: swm@c85 { - left_spkr: wsa8810-left { + left_spkr: speaker@0,1 { compatible = "sdw10217201000"; reg = <0 1>; powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>; @@ -1110,7 +1110,7 @@ left_spkr: wsa8810-left { #sound-dai-cells = <0>; }; - right_spkr: wsa8810-right { + right_spkr: speaker@0,2 { compatible = "sdw10217201000"; powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>; reg = <0 2>; diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index 0c375ec795b8..f32b7445f7c9 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -785,7 +785,7 @@ &wcd9340{ qcom,mbhc-headphone-vthreshold-microvolt = <50000>; swm: swm@c85 { - left_spkr: wsa8810-left { + left_spkr: speaker@0,3 { compatible = "sdw10217211000"; reg = <0 3>; powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>; @@ -794,7 +794,7 @@ left_spkr: wsa8810-left { #sound-dai-cells = <0>; }; - right_spkr: wsa8810-right { + right_spkr: speaker@0,4 { compatible = "sdw10217211000"; powerdown-gpios = <&wcdgpio 2 GPIO_ACTIVE_HIGH>; reg = <0 4>; diff --git a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts index b712834a5d64..daca1e0ad62a 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts @@ -717,7 +717,7 @@ &wcd9340{ qcom,mbhc-headphone-vthreshold-microvolt = <50000>; swm: swm@c85 { - left_spkr: wsa8810-left { + left_spkr: speaker@0,3 { compatible = "sdw10217211000"; reg = <0 3>; powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>; @@ -726,7 +726,7 @@ left_spkr: wsa8810-left { #sound-dai-cells = <0>; }; - right_spkr: wsa8810-right { + right_spkr: speaker@0,4 { compatible = "sdw10217211000"; powerdown-gpios = <&wcdgpio 2 GPIO_ACTIVE_HIGH>; reg = <0 4>; diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index 391806c62ccc..3ed8c84e25b8 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -757,7 +757,7 @@ codec { }; &swr0 { - left_spkr: wsa8810-right@0,3{ + left_spkr: speaker@0,3 { compatible = "sdw10217211000"; reg = <0 3>; powerdown-gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>; @@ -766,7 +766,7 @@ left_spkr: wsa8810-right@0,3{ #sound-dai-cells = <0>; }; - right_spkr: wsa8810-left@0,4{ + right_spkr: speaker@0,4 { compatible = "sdw10217211000"; reg = <0 4>; powerdown-gpios = <&tlmm 127 GPIO_ACTIVE_HIGH>; From 837f597ebc529b2dce6451da27f24d93ebe194c8 Mon Sep 17 00:00:00 2001 From: Srinivasa Rao Mandadapu Date: Tue, 8 Nov 2022 20:16:01 +0530 Subject: [PATCH 237/261] arm64: dts: qcom: sm8250: Remove redundant soundwire property Remove redundant and undocumented property qcom,port-offset in soundwire controller nodes. This patch is required to avoid dtbs_check errors with qcom,soundwire.yaml Fixes: 24f52ef0c4bf ("arm64: dts: qcom: sm8250: Add nodes for tx and rx macros with soundwire masters") Signed-off-by: Srinivasa Rao Mandadapu Co-developed-by: Ratna Deepthi Kudaravalli Signed-off-by: Ratna Deepthi Kudaravalli Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1667918763-32445-3-git-send-email-quic_srivasam@quicinc.com --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 7a77251dc529..5daaa57dd4a8 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2360,7 +2360,6 @@ swr2: soundwire-controller@3230000 { qcom,ports-word-length = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; qcom,ports-lane-control = /bits/ 8 <0xFF 0x00 0x01 0x00 0x01>; - qcom,port-offset = <1>; #sound-dai-cells = <1>; #address-cells = <2>; #size-cells = <0>; From 78043031281bbb31f89b66128982f404bcde94e8 Mon Sep 17 00:00:00 2001 From: Srinivasa Rao Mandadapu Date: Tue, 8 Nov 2022 20:16:02 +0530 Subject: [PATCH 238/261] arm64: dts: qcom: sc7280: Remove redundant soundwire property Remove redundant and undocumented property qcom,port-offset in soundwire controller nodes. This patch is required to avoid dtbs_check errors with qcom,soundwire.yaml Fixes: 12ef689f09ab ("arm64: dts: qcom: sc7280: Add nodes for soundwire and va tx rx digital macro codecs") Signed-off-by: Srinivasa Rao Mandadapu Co-developed-by: Ratna Deepthi Kudaravalli Signed-off-by: Ratna Deepthi Kudaravalli Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1667918763-32445-4-git-send-email-quic_srivasam@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 7878ae0a216e..5a886513940b 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2330,7 +2330,6 @@ swr1: soundwire@3230000 { qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; - qcom,port-offset = <1>; #sound-dai-cells = <1>; #address-cells = <2>; From 1c3c31a6e7f6b467c160a4c58e385b2991e49139 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Nov 2022 15:23:57 +0100 Subject: [PATCH 239/261] arm64: dts: qcom: ipq8074: align TLMM pin configuration with DT schema DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221108142357.67202-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 9d7893327095..4e51d8e3df04 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -317,35 +317,35 @@ tlmm: pinctrl@1000000 { interrupt-controller; #interrupt-cells = <0x2>; - serial_4_pins: serial4-pinmux { + serial_4_pins: serial4-state { pins = "gpio23", "gpio24"; function = "blsp4_uart1"; drive-strength = <8>; bias-disable; }; - i2c_0_pins: i2c-0-pinmux { + i2c_0_pins: i2c-0-state { pins = "gpio42", "gpio43"; function = "blsp1_i2c"; drive-strength = <8>; bias-disable; }; - spi_0_pins: spi-0-pins { + spi_0_pins: spi-0-state { pins = "gpio38", "gpio39", "gpio40", "gpio41"; function = "blsp0_spi"; drive-strength = <8>; bias-disable; }; - hsuart_pins: hsuart-pins { + hsuart_pins: hsuart-state { pins = "gpio46", "gpio47", "gpio48", "gpio49"; function = "blsp2_uart"; drive-strength = <8>; bias-disable; }; - qpic_pins: qpic-pins { + qpic_pins: qpic-state { pins = "gpio1", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", "gpio10", "gpio11", From a607fe5ea21324a91f03301194bfcda1df2108a6 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Sat, 30 Jul 2022 12:36:17 -0700 Subject: [PATCH 240/261] arm64: dts: qcom: sc8280xp-x13s: Add LID switch Add gpio-keys for exposing the LID switch state. Signed-off-by: Bjorn Andersson Reviewed-by: Johan Hovold Tested-by: Johan Hovold Reviewed-by: Konrad Dybcio Tested-by: Steev Klimaszewski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220730193617.1688563-1-bjorn.andersson@linaro.org --- .../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index cf0076d7e798..02083342bfca 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -10,6 +10,8 @@ #include #include #include +#include +#include #include #include "sc8280xp.dtsi" @@ -75,6 +77,21 @@ map1 { }; }; + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&hall_int_n_default>; + + switch-lid { + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + wakeup-source; + wakeup-event-action = ; + }; + }; + vreg_edp_bl: regulator-edp-bl { compatible = "regulator-fixed"; @@ -548,6 +565,13 @@ edp_bl_pwm: edp-bl-pwm-state { &tlmm { gpio-reserved-ranges = <70 2>, <74 6>, <83 4>, <125 2>, <128 2>, <154 7>; + hall_int_n_default: hall-int-n-state { + pins = "gpio107"; + function = "gpio"; + input-enable; + bias-disable; + }; + kybd_default: kybd-default-state { disable-pins { pins = "gpio102"; From b69e4bb48abdc5dd1fa6725dd1753f8abce3f38c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 10 Nov 2022 16:27:41 +0100 Subject: [PATCH 241/261] arm64: dts: qcom: sm8450: drop incorrect spi-max-frequency spi-max-frequency is a property of SPI device, not the controller: qcom/sm8450-hdk.dtb: geniqup@8c0000: spi@880000: Unevaluated properties are not allowed ('spi-max-frequency' was unexpected Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221110152741.542024-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 7 ------- 1 file changed, 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index fcc61bc849c8..19a0f5033cc9 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -792,7 +792,6 @@ spi15: spi@880000 { interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; - spi-max-frequency = <50000000>; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; interconnect-names = "qup-core", "qup-config"; @@ -832,7 +831,6 @@ spi16: spi@884000 { interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; - spi-max-frequency = <50000000>; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; interconnect-names = "qup-core", "qup-config"; @@ -872,7 +870,6 @@ spi17: spi@888000 { interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; - spi-max-frequency = <50000000>; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; interconnect-names = "qup-core", "qup-config"; @@ -912,7 +909,6 @@ spi18: spi@88c000 { interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; - spi-max-frequency = <50000000>; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; interconnect-names = "qup-core", "qup-config"; @@ -952,7 +948,6 @@ spi19: spi@890000 { interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; - spi-max-frequency = <50000000>; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; interconnect-names = "qup-core", "qup-config"; @@ -1005,7 +1000,6 @@ spi20: spi@894000 { interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; - spi-max-frequency = <50000000>; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; interconnect-names = "qup-core", "qup-config"; @@ -1045,7 +1039,6 @@ spi21: spi@898000 { interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; - spi-max-frequency = <50000000>; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; interconnect-names = "qup-core", "qup-config"; From 94262a18d74b85704a025855819582b5e256c8f0 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Thu, 10 Nov 2022 16:15:06 +0100 Subject: [PATCH 242/261] arm64: dts: qcom: sm7225-fairphone-fp4: Enable SD card Fairphone 4 uses sdhc_2 for the SD card, configure the pins for it and enable it. The regulators which are exclusively used for SDHCI have their maximum voltage decreased to what downstream sets on the consumer side, like on many other platforms and allowed to set the load. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221110151507.53650-1-luca.weiss@fairphone.com --- .../boot/dts/qcom/sm7225-fairphone-fp4.dts | 39 ++++++++++++++++++- 1 file changed, 37 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index 30c94fd4fe61..1cb14051ab1b 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -279,8 +279,12 @@ vreg_l5e: ldo5 { vreg_l6e: ldo6 { regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <3544000>; + regulator-max-microvolt = <2950000>; regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = + ; }; vreg_l7e: ldo7 { @@ -297,8 +301,12 @@ vreg_l8e: ldo8 { vreg_l9e: ldo9 { regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3544000>; + regulator-max-microvolt = <2960000>; regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = + ; }; vreg_l10e: ldo10 { @@ -424,6 +432,33 @@ &qupv3_id_1 { status = "okay"; }; +&sdc2_off_state { + sd-cd-pins { + pins = "gpio94"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&sdc2_on_state { + sd-cd-pins { + pins = "gpio94"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; +}; + +&sdhc_2 { + vmmc-supply = <&vreg_l9e>; + vqmmc-supply = <&vreg_l6e>; + + cd-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <13 4>, <56 2>; }; From 3c800bcf07a5957da01593e8f83d797b285a37e0 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Thu, 10 Nov 2022 12:38:12 +0530 Subject: [PATCH 243/261] arm64: dts: qcom: sc7280: Mark all Qualcomm reference boards as LTE When the modem node was re-located to a separate LTE source file "sc7280-herobrine-lte-sku.dtsi", some of the previous LTE users weren't marked appropriately. Fix this by marking all Qualcomm reference devices as LTE. Suggested-by: Douglas Anderson Fixes: d42fae738f3a ("arm64: dts: qcom: Add LTE SKUs for sc7280-villager family") Signed-off-by: Sibi Sankar Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221110070813.1777-1-quic_sibis@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280-idp.dts | 1 - arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts index 9ddfdfdd354e..ba64316b4427 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts @@ -10,7 +10,6 @@ #include #include "sc7280-idp.dtsi" #include "pmr735a.dtsi" -#include "sc7280-herobrine-lte-sku.dtsi" / { model = "Qualcomm Technologies, Inc. sc7280 IDP SKU1 platform"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 1ac7c091e03f..8ca228111681 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -13,6 +13,7 @@ #include "pmk8350.dtsi" #include "sc7280-chrome-common.dtsi" +#include "sc7280-herobrine-lte-sku.dtsi" / { aliases { From 87548e54b86e06190e018665bd77528f72038fbe Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Thu, 10 Nov 2022 12:38:13 +0530 Subject: [PATCH 244/261] arm64: dts: qcom: sc7280: Add Google Herobrine WIFI SKU dts fragment The Google Herobrine WIFI SKU can save 256M by not having modem/mba/rmtfs memory regions defined. Add the dts fragment and mark all the board files appropriately. Reviewed-by: Douglas Anderson Signed-off-by: Sibi Sankar Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221110070813.1777-2-quic_sibis@quicinc.com --- .../boot/dts/qcom/sc7280-chrome-common.dtsi | 15 -------- .../dts/qcom/sc7280-herobrine-evoker-lte.dts | 4 +- .../boot/dts/qcom/sc7280-herobrine-evoker.dts | 2 +- .../dts/qcom/sc7280-herobrine-evoker.dtsi | 1 + .../dts/qcom/sc7280-herobrine-lte-sku.dtsi | 19 ++++++++++ .../qcom/sc7280-herobrine-villager-r1-lte.dts | 4 +- .../dts/qcom/sc7280-herobrine-villager-r1.dts | 31 +--------------- .../qcom/sc7280-herobrine-villager-r1.dtsi | 37 +++++++++++++++++++ .../dts/qcom/sc7280-herobrine-wifi-sku.dtsi | 11 ++++++ 9 files changed, 77 insertions(+), 47 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r1.dtsi create mode 100644 arch/arm64/boot/dts/qcom/sc7280-herobrine-wifi-sku.dtsi diff --git a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi index 25f31c81b2b7..16fb20369c01 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi @@ -39,20 +39,10 @@ venus_mem: memory@8b200000 { no-map; }; - mpss_mem: memory@8b800000 { - reg = <0x0 0x8b800000 0x0 0xf600000>; - no-map; - }; - wpss_mem: memory@9ae00000 { reg = <0x0 0x9ae00000 0x0 0x1900000>; no-map; }; - - mba_mem: memory@9c700000 { - reg = <0x0 0x9c700000 0x0 0x200000>; - no-map; - }; }; }; @@ -88,11 +78,6 @@ &remoteproc_wpss { firmware-name = "ath11k/WCN6750/hw1.0/wpss.mdt"; }; -/* Increase the size from 2.5MB to 8MB */ -&rmtfs_mem { - reg = <0x0 0x9c900000 0x0 0x800000>; -}; - &wifi { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker-lte.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker-lte.dts index 3af9224a7492..14f20e705869 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker-lte.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker-lte.dts @@ -5,7 +5,9 @@ * Copyright 2022 Google LLC. */ -#include "sc7280-herobrine-evoker.dts" +/dts-v1/; + +#include "sc7280-herobrine-evoker.dtsi" #include "sc7280-herobrine-lte-sku.dtsi" / { diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dts index 51f0401b11ed..4f781fe25c9c 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dts @@ -8,7 +8,7 @@ /dts-v1/; #include "sc7280-herobrine-evoker.dtsi" -#include "sc7280-herobrine-audio-rt5682-3mic.dtsi" +#include "sc7280-herobrine-wifi-sku.dtsi" / { model = "Google Evoker"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dtsi index 706dd82a7013..3d639c70a06e 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dtsi @@ -6,6 +6,7 @@ */ #include "sc7280-herobrine.dtsi" +#include "sc7280-herobrine-audio-rt5682-3mic.dtsi" /* * ADDITIONS TO FIXED REGULATORS DEFINED IN PARENT DEVICE TREE FILES diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-lte-sku.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-lte-sku.dtsi index a92eeccd2b2a..ad66e5e9db4e 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-lte-sku.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-lte-sku.dtsi @@ -6,6 +6,20 @@ */ /* Modem setup is different on Chrome setups than typical Qualcomm setup */ +/ { + reserved-memory { + mpss_mem: memory@8b800000 { + reg = <0x0 0x8b800000 0x0 0xf600000>; + no-map; + }; + + mba_mem: memory@9c700000 { + reg = <0x0 0x9c700000 0x0 0x200000>; + no-map; + }; + }; +}; + &remoteproc_mpss { compatible = "qcom,sc7280-mss-pil"; iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>; @@ -15,3 +29,8 @@ &remoteproc_mpss { "qcom/sc7280-herobrine/modem/qdsp6sw.mbn"; status = "okay"; }; + +/* Increase the size from 2.5MB to 8MB */ +&rmtfs_mem { + reg = <0x0 0x9c900000 0x0 0x800000>; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r1-lte.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r1-lte.dts index f1017809e5da..d71cc4bbc4b3 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r1-lte.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r1-lte.dts @@ -5,7 +5,9 @@ * Copyright 2022 Google LLC. */ -#include "sc7280-herobrine-villager-r1.dts" +/dts-v1/; + +#include "sc7280-herobrine-villager-r1.dtsi" #include "sc7280-herobrine-lte-sku.dtsi" / { diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r1.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r1.dts index cfc648726930..edb52f12f0ea 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r1.dts @@ -7,37 +7,10 @@ /dts-v1/; -#include "sc7280-herobrine-villager.dtsi" -#include "sc7280-herobrine-audio-wcd9385.dtsi" +#include "sc7280-herobrine-villager-r1.dtsi" +#include "sc7280-herobrine-wifi-sku.dtsi" / { model = "Google Villager (rev1+)"; compatible = "google,villager", "qcom,sc7280"; }; - -&lpass_va_macro { - vdd-micb-supply = <&pp1800_l2c>; -}; - -&sound { - audio-routing = - "IN1_HPHL", "HPHL_OUT", - "IN2_HPHR", "HPHR_OUT", - "AMIC1", "MIC BIAS1", - "AMIC2", "MIC BIAS2", - "VA DMIC0", "vdd-micb", - "VA DMIC1", "vdd-micb", - "VA DMIC2", "vdd-micb", - "VA DMIC3", "vdd-micb", - "TX SWR_ADC0", "ADC1_OUTPUT", - "TX SWR_ADC1", "ADC2_OUTPUT", - "TX SWR_ADC2", "ADC3_OUTPUT", - "TX SWR_DMIC0", "DMIC1_OUTPUT", - "TX SWR_DMIC1", "DMIC2_OUTPUT", - "TX SWR_DMIC2", "DMIC3_OUTPUT", - "TX SWR_DMIC3", "DMIC4_OUTPUT", - "TX SWR_DMIC4", "DMIC5_OUTPUT", - "TX SWR_DMIC5", "DMIC6_OUTPUT", - "TX SWR_DMIC6", "DMIC7_OUTPUT", - "TX SWR_DMIC7", "DMIC8_OUTPUT"; -}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r1.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r1.dtsi new file mode 100644 index 000000000000..b25df5a99161 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r1.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Villager board device tree source + * + * Copyright 2022 Google LLC. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "sc7280-herobrine-villager.dtsi" +#include "sc7280-herobrine-audio-wcd9385.dtsi" + +&lpass_va_macro { + vdd-micb-supply = <&pp1800_l2c>; +}; + +&sound { + audio-routing = + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC1", "MIC BIAS1", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "vdd-micb", + "VA DMIC1", "vdd-micb", + "VA DMIC2", "vdd-micb", + "VA DMIC3", "vdd-micb", + "TX SWR_ADC0", "ADC1_OUTPUT", + "TX SWR_ADC1", "ADC2_OUTPUT", + "TX SWR_ADC2", "ADC3_OUTPUT", + "TX SWR_DMIC0", "DMIC1_OUTPUT", + "TX SWR_DMIC1", "DMIC2_OUTPUT", + "TX SWR_DMIC2", "DMIC3_OUTPUT", + "TX SWR_DMIC3", "DMIC4_OUTPUT", + "TX SWR_DMIC4", "DMIC5_OUTPUT", + "TX SWR_DMIC5", "DMIC6_OUTPUT", + "TX SWR_DMIC6", "DMIC7_OUTPUT", + "TX SWR_DMIC7", "DMIC8_OUTPUT"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-wifi-sku.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-wifi-sku.dtsi new file mode 100644 index 000000000000..2febd6126d4c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-wifi-sku.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Google Herobrine dts fragment for WIFI SKUs + * + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/* WIFI SKUs save 256M by not having modem/mba/rmtfs memory regions defined. */ + +/delete-node/ &remoteproc_mpss; +/delete-node/ &rmtfs_mem; From 07c8ded6e373830aed55139b2030e755177e1611 Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Thu, 10 Nov 2022 19:18:19 -0500 Subject: [PATCH 245/261] arm64: dts: qcom: add sdm670 and pixel 3a device trees The Qualcomm Snapdragon 670 has been out for a while. Add a device tree for it and the Google Pixel 3a as the first device. The Pixel 3a has the same bootloader issue as the Pixel 3 and will not work on Android 10 bootloaders or later until it gets fixed for the Pixel 3. SoC Initial Features: - power management - clocks - pinctrl - eMMC - USB 2.0 - GENI I2C - IOMMU - RPMh - interrupts Device-Specific Initial Features: - side buttons (keys) - regulators - touchscreen Signed-off-by: Richard Acayan Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221111001818.124901-5-mailingradian@gmail.com --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sdm670-google-sargo.dts | 531 ++++++++ arch/arm64/boot/dts/qcom/sdm670.dtsi | 1160 +++++++++++++++++ 3 files changed, 1692 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts create mode 100644 arch/arm64/boot/dts/qcom/sdm670.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index d534888bcfe5..afe496a93f94 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -127,6 +127,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-voyager.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm632-fairphone-fp3.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm636-sony-xperia-ganges-mermaid.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-lavender.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm670-google-sargo.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb diff --git a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts new file mode 100644 index 000000000000..cf2ae540db12 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts @@ -0,0 +1,531 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device tree for Google Pixel 3a, adapted from google-blueline device tree, + * xiaomi-lavender device tree, and oneplus-common device tree. + * + * Copyright (c) 2022, Richard Acayan. All rights reserved. + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "sdm670.dtsi" +#include "pm660.dtsi" +#include "pm660l.dtsi" + +/delete-node/ &mpss_region; +/delete-node/ &venus_mem; +/delete-node/ &wlan_msa_mem; +/delete-node/ &cdsp_mem; +/delete-node/ &mba_region; +/delete-node/ &adsp_mem; +/delete-node/ &ipa_fw_mem; +/delete-node/ &ipa_gsi_mem; +/delete-node/ &gpu_mem; + +/ { + model = "Google Pixel 3a"; + compatible = "google,sargo", "qcom,sdm670"; + + aliases { }; + + chosen { + stdout-path = "serial0:115200n8"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer@9c000000 { + compatible = "simple-framebuffer"; + reg = <0 0x9c000000 0 (1080 * 2220 * 4)>; + width = <1080>; + height = <2220>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + }; + }; + + clocks { + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32764>; + }; + + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <38400000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&vol_up_pin>; + + key-vol-up { + label = "Volume Up"; + linux,code = ; + gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + + mpss_region: mpss@8b000000 { + reg = <0 0x8b000000 0 0x9800000>; + no-map; + }; + + venus_mem: venus@94800000 { + reg = <0 0x94800000 0 0x500000>; + no-map; + }; + + wlan_msa_mem: wlan-msa@94d00000 { + reg = <0 0x94d00000 0 0x100000>; + no-map; + }; + + cdsp_mem: cdsp@94e00000 { + reg = <0 0x94e00000 0 0x800000>; + no-map; + }; + + mba_region: mba@95600000 { + reg = <0 0x95600000 0 0x200000>; + no-map; + }; + + adsp_mem: adsp@95800000 { + reg = <0 0x95800000 0 0x2200000>; + no-map; + }; + + ipa_fw_mem: ipa-fw@97a00000 { + reg = <0 0x97a00000 0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi@97a10000 { + reg = <0 0x97a10000 0 0x5000>; + no-map; + }; + + gpu_mem: gpu@97a15000 { + reg = <0 0x97a15000 0 0x2000>; + no-map; + }; + + framebuffer-region@9c000000 { + reg = <0 0x9c000000 0 0x2400000>; + no-map; + }; + + /* Also includes ramoops regions */ + debug_info_mem: debug-info@a1800000 { + reg = <0 0xa1800000 0 0x411000>; + no-map; + }; + }; + + /* + * The touchscreen regulator seems to be controlled somehow by a gpio. + * Model it as a fixed regulator and keep it on. Without schematics we + * don't know how this is actually wired up... + */ + ts_1p8_supply: ts-1p8-regulator { + compatible = "regulator-fixed"; + regulator-name = "ts_1p8_supply"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&pm660_gpios 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3312000>; + + regulator-always-on; + regulator-boot-on; + }; + + /* + * Supply map from xiaomi-lavender specifies this as the supply for + * ldob1, ldob9, ldob10, ldoa2, and ldoa3, while downstream specifies + * this as a power domain. Set this as a fixed regulator with the same + * voltage as lavender until display is needed to avoid unneccessarily + * using a deprecated binding (regulator-fixed-domain). + */ + vreg_s2b_1p05: vreg-s2b-regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_s2b"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm660-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + + vdd-l1-l6-l7-supply = <&vreg_s6a_0p87>; + vdd-l2-l3-supply = <&vreg_s2b_1p05>; + vdd-l5-supply = <&vreg_s2b_1p05>; + vdd-l8-l9-l10-l11-l12-l13-l14-supply = <&vreg_s4a_2p04>; + vdd-l15-l16-l17-l18-l19-supply = <&vreg_bob>; + + /* + * S1A (FTAPC0), S2A (FTAPC1), S3A (HFAPC1) are managed + * by the Core Power Reduction hardened (CPRh) and the + * Operating State Manager (OSM) HW automatically. + */ + + vreg_s4a_2p04: smps4 { + regulator-min-microvolt = <1808000>; + regulator-max-microvolt = <2040000>; + regulator-enable-ramp-delay = <200>; + }; + + vreg_s6a_0p87: smps6 { + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1352000>; + regulator-enable-ramp-delay = <150>; + }; + + /* LDOs */ + vreg_l1a_1p225: ldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1250000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l2a_1p0: ldo2 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l3a_1p0: ldo3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l5a_0p848: ldo5 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l6a_1p3: ldo6 { + regulator-min-microvolt = <1248000>; + regulator-max-microvolt = <1304000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l7a_1p2: ldo7 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l8a_1p8: ldo8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l9a_1p8: ldo9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l10a_1p8: ldo10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l11a_1p8: ldo11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l13a_1p8: ldo13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l14a_1p8: ldo14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l15a_1p8: ldo15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l16a_2p7: ldo16 { + regulator-min-microvolt = <2696000>; + regulator-max-microvolt = <2696000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l17a_1p8: ldo17 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l19a_3p3: ldo19 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-enable-ramp-delay = <250>; + }; + }; + + regulators-1 { + compatible = "qcom,pm660l-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + + vdd-l1-l9-l10-supply = <&vreg_s2b_1p05>; + vdd-l2-supply = <&vreg_bob>; + vdd-l3-l5-l7-l8-supply = <&vreg_bob>; + vdd-l4-l6-supply = <&vreg_bob>; + vdd-bob-supply = <&vph_pwr>; + + /* LDOs */ + vreg_l1b_0p925: ldo1 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <900000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l2b_2p95: ldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l3b_3p0: ldo3 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3008000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l4b_2p95: ldo4 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l5b_2p95: ldo5 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l6b_3p3: ldo6 { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l7b_3p125: ldo7 { + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3100000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l8b_3p3: ldo8 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3312000>; + regulator-enable-ramp-delay = <250>; + }; + + /* + * Downstream specifies a fixed voltage of 3.312 V, but the + * PMIC4 BOB ranges don't support that. Widen the range a + * little to avoid adding a new BOB regulator type. + */ + vreg_bob: bob { + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3328000>; + regulator-enable-ramp-delay = <500>; + }; + }; + +}; + +&gcc { + protected-clocks = , + , + ; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&i2c9 { + clock-frequency = <100000>; + status = "okay"; + + synaptics-rmi4-i2c@20 { + compatible = "syna,rmi4-i2c"; + reg = <0x20>; + interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_default>; + + vio-supply = <&ts_1p8_supply>; + + syna,reset-delay-ms = <200>; + syna,startup-delay-ms = <200>; + + #address-cells = <1>; + #size-cells = <0>; + + rmi4-f01@1 { + reg = <0x01>; + syna,nosleep-mode = <1>; + }; + + rmi4-f12@12 { + reg = <0x12>; + touchscreen-x-mm = <62>; + touchscreen-y-mm = <127>; + syna,sensor-type = <1>; + }; + }; +}; + +&pm660l_gpios { + vol_up_pin: vol-up-state { + pins = "gpio7"; + function = "normal"; + qcom,drive-strength = ; + input-enable; + bias-pull-up; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&sdhc_1 { + supports-cqe; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-ddr-1_8v; + + qcom,ddr-config = <0xc3040873>; + + vmmc-supply = <&vreg_l4b_2p95>; + vqmmc-supply = <&vreg_l8a_1p8>; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <81 4>; + + touchscreen_default: ts-default-state { + ts-reset-pins { + pins = "gpio99"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + output-high; + }; + + ts-irq-pins { + pins = "gpio125"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + ts-switch-pins { + pins = "gpio135"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l1b_0p925>; + vdda-pll-supply = <&vreg_l10a_1p8>; + vdda-phy-dpdm-supply = <&vreg_l7b_3p125>; + + status = "okay"; +}; + +&usb_1 { + qcom,select-utmi-as-pipe-clk; + status = "okay"; +}; + +&usb_1_dwc3 { + /* Only peripheral works for now */ + dr_mode = "peripheral"; + + /* Do not assume that sdm670.dtsi will never support USB 3.0 */ + phys = <&usb_1_hsphy>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi new file mode 100644 index 000000000000..47363fde64ac --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -0,0 +1,1160 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SDM670 SoC device tree source, adapted from SDM845 SoC device tree + * + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Richard Acayan. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + aliases { }; + + chosen { }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo360"; + reg = <0x0 0x0>; + enable-method = "psci"; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo360"; + reg = <0x0 0x100>; + enable-method = "psci"; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + next-level-cache = <&L2_100>; + L2_100: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo360"; + reg = <0x0 0x200>; + enable-method = "psci"; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; + next-level-cache = <&L2_200>; + L2_200: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo360"; + reg = <0x0 0x300>; + enable-method = "psci"; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; + next-level-cache = <&L2_300>; + L2_300: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo360"; + reg = <0x0 0x400>; + enable-method = "psci"; + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; + next-level-cache = <&L2_400>; + L2_400: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo360"; + reg = <0x0 0x500>; + enable-method = "psci"; + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; + next-level-cache = <&L2_500>; + L2_500: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo360"; + reg = <0x0 0x600>; + enable-method = "psci"; + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; + next-level-cache = <&L2_600>; + L2_600: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo360"; + reg = <0x0 0x700>; + enable-method = "psci"; + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; + next-level-cache = <&L2_700>; + L2_700: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + + core4 { + cpu = <&CPU4>; + }; + + core5 { + cpu = <&CPU5>; + }; + + core6 { + cpu = <&CPU6>; + }; + + core7 { + cpu = <&CPU7>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "little-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <702>; + exit-latency-us = <915>; + min-residency-us = <1617>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "big-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <526>; + exit-latency-us = <1854>; + min-residency-us = <2380>; + local-timer-stop; + }; + }; + + domain-idle-states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x4100c244>; + entry-latency-us = <3263>; + exit-latency-us = <6562>; + min-residency-us = <9825>; + }; + }; + }; + + firmware { + scm { + compatible = "qcom,scm-sdm670", "qcom,scm"; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0x80000000 0x0 0x0>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD4: power-domain-cpu4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD5: power-domain-cpu5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD6: power-domain-cpu6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD7: power-domain-cpu7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CLUSTER_PD: power-domain-cluster { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_0>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp-mem@85700000 { + reg = <0 0x85700000 0 0x600000>; + no-map; + }; + + xbl_mem: xbl-mem@85e00000 { + reg = <0 0x85e00000 0 0x100000>; + no-map; + }; + + aop_mem: aop-mem@85fc0000 { + reg = <0 0x85fc0000 0 0x20000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 { + compatible = "qcom,cmd-db"; + reg = <0 0x85fe0000 0 0x20000>; + no-map; + }; + + camera_mem: camera-mem@8ab00000 { + reg = <0 0x8ab00000 0 0x500000>; + no-map; + }; + + mpss_region: mpss@8b000000 { + reg = <0 0x8b000000 0 0x7e00000>; + no-map; + }; + + venus_mem: venus@92e00000 { + reg = <0 0x92e00000 0 0x500000>; + no-map; + }; + + wlan_msa_mem: wlan-msa@93300000 { + reg = <0 0x93300000 0 0x100000>; + no-map; + }; + + cdsp_mem: cdsp@93400000 { + reg = <0 0x93400000 0 0x800000>; + no-map; + }; + + mba_region: mba@93c00000 { + reg = <0 0x93c00000 0 0x200000>; + no-map; + }; + + adsp_mem: adsp@93e00000 { + reg = <0 0x93e00000 0 0x1e00000>; + no-map; + }; + + ipa_fw_mem: ipa-fw@95c00000 { + reg = <0 0x95c00000 0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi@95c10000 { + reg = <0 0x95c10000 0 0x5000>; + no-map; + }; + + gpu_mem: gpu@95c15000 { + reg = <0 0x95c15000 0 0x2000>; + no-map; + }; + + spss_mem: spss@97b00000 { + reg = <0 0x97b00000 0 0x100000>; + no-map; + }; + + qseecom_mem: qseecom@9e400000 { + reg = <0 0x9e400000 0 0x1400000>; + no-map; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + soc: soc@0 { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + compatible = "simple-bus"; + + gcc: clock-controller@100000 { + compatible = "qcom,gcc-sdm670"; + reg = <0 0x00100000 0 0x1f0000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + clock-names = "bi_tcxo", + "bi_tcxo_ao", + "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + sdhc_1: mmc@7c4000 { + compatible = "qcom,sdm670-sdhci", "qcom,sdhci-msm-v5"; + reg = <0 0x007c4000 0 0x1000>, + <0 0x007c5000 0 0x1000>, + <0 0x007c8000 0 0x8000>; + reg-names = "hc", "cqhci", "ice"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; + clock-names = "iface", "core", "xo", "ice", "bus"; + + iommus = <&apps_smmu 0x140 0xf>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_state_on>; + pinctrl-1 = <&sdc1_state_off>; + power-domains = <&rpmhpd SDM670_CX>; + + bus-width = <8>; + non-removable; + + status = "disabled"; + }; + + gpi_dma0: dma-controller@800000 { + #dma-cells = <3>; + compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma"; + reg = <0 0x00800000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <13>; + dma-channel-mask = <0xfa>; + iommus = <&apps_smmu 0x16 0x0>; + status = "disabled"; + }; + + qupv3_id_0: geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0 0x008c0000 0 0x6000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + iommus = <&apps_smmu 0x3 0x0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + i2c0: i2c@880000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00880000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c0_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM670_CX>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c1: i2c@884000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00884000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c1_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM670_CX>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c2: i2c@888000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00888000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c2_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM670_CX>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c3: i2c@88c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x0088c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c3_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM670_CX>; + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c4: i2c@890000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00890000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c4_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM670_CX>; + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c5: i2c@894000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00894000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c5_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM670_CX>; + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c6: i2c@898000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00898000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c6_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM670_CX>; + dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, + <&gpi_dma0 1 6 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c7: i2c@89c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x0089c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c7_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM670_CX>; + dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, + <&gpi_dma0 1 7 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + }; + + gpi_dma1: dma-controller@a00000 { + #dma-cells = <3>; + compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma"; + reg = <0 0x00a00000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <13>; + dma-channel-mask = <0xfa>; + iommus = <&apps_smmu 0x6d6 0x0>; + status = "disabled"; + }; + + qupv3_id_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0 0x00ac0000 0 0x6000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0x6c3 0x0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + i2c8: i2c@a80000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a80000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c8_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM670_CX>; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c9: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a84000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c9_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM670_CX>; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c10: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a88000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c10_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM670_CX>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c11: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a8c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c11_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM670_CX>; + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c12: i2c@a90000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a90000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c12_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM670_CX>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c13: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a94000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c13_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM670_CX>; + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, + <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c14: i2c@a98000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a98000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c14_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM670_CX>; + dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, + <&gpi_dma1 1 6 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c15: i2c@a9c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a9c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c15_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SDM670_CX>; + dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, + <&gpi_dma1 1 7 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + }; + + tlmm: pinctrl@3400000 { + compatible = "qcom,sdm670-tlmm"; + reg = <0 0x03400000 0 0xc00000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 151>; + + qup_i2c0_default: qup-i2c0-default-state { + pins = "gpio0", "gpio1"; + function = "qup0"; + }; + + qup_i2c1_default: qup-i2c1-default-state { + pins = "gpio17", "gpio18"; + function = "qup1"; + }; + + qup_i2c2_default: qup-i2c2-default-state { + pins = "gpio27", "gpio28"; + function = "qup2"; + }; + + qup_i2c3_default: qup-i2c3-default-state { + pins = "gpio41", "gpio42"; + function = "qup3"; + }; + + qup_i2c4_default: qup-i2c4-default-state { + pins = "gpio89", "gpio90"; + function = "qup4"; + }; + + qup_i2c5_default: qup-i2c5-default-state { + pins = "gpio85", "gpio86"; + function = "qup5"; + }; + + qup_i2c6_default: qup-i2c6-default-state { + pins = "gpio45", "gpio46"; + function = "qup6"; + }; + + qup_i2c7_default: qup-i2c7-default-state { + pins = "gpio93", "gpio94"; + function = "qup7"; + }; + + qup_i2c8_default: qup-i2c8-default-state { + pins = "gpio65", "gpio66"; + function = "qup8"; + }; + + qup_i2c9_default: qup-i2c9-default-state { + pins = "gpio6", "gpio7"; + function = "qup9"; + }; + + qup_i2c10_default: qup-i2c10-default-state { + pins = "gpio55", "gpio56"; + function = "qup10"; + }; + + qup_i2c11_default: qup-i2c11-default-state { + pins = "gpio31", "gpio32"; + function = "qup11"; + }; + + qup_i2c12_default: qup-i2c12-default-state { + pins = "gpio49", "gpio50"; + function = "qup12"; + }; + + qup_i2c13_default: qup-i2c13-default-state { + pins = "gpio105", "gpio106"; + function = "qup13"; + }; + + qup_i2c14_default: qup-i2c14-default-state { + pins = "gpio33", "gpio34"; + function = "qup14"; + }; + + qup_i2c15_default: qup-i2c15-default-state { + pins = "gpio81", "gpio82"; + function = "qup15"; + }; + + sdc1_state_on: sdc1-on-state { + clk-pins { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd-pins { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data-pins { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_state_off: sdc1-off-state { + clk-pins { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd-pins { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data-pins { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + }; + + usb_1_hsphy: phy@88e2000 { + compatible = "qcom,sdm670-qusb2-phy", "qcom,qusb2-v2-phy"; + reg = <0 0x088e2000 0 0x400>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "cfg_ahb", "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + status = "disabled"; + }; + + usb_1: usb@a6f8800 { + compatible = "qcom,sdm670-dwc3", "qcom,dwc3"; + reg = <0 0x0a6f8800 0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <150000000>; + + interrupts = , + , + , + ; + interrupt-names = "hs_phy_irq", "ss_phy_irq", + "dm_hs_phy_irq", "dp_hs_phy_irq"; + + power-domains = <&gcc USB30_PRIM_GDSC>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + status = "disabled"; + + usb_1_dwc3: usb@a600000 { + compatible = "snps,dwc3"; + reg = <0 0x0a600000 0 0xcd00>; + interrupts = ; + iommus = <&apps_smmu 0x740 0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_1_hsphy>; + phy-names = "usb2-phy"; + }; + }; + + spmi_bus: spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0 0x0c440000 0 0x1100>, + <0 0x0c600000 0 0x2000000>, + <0 0x0e600000 0 0x100000>, + <0 0x0e700000 0 0xa0000>, + <0 0x0c40a000 0 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + apps_smmu: iommu@15000000 { + compatible = "qcom,sdm670-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0 0x15000000 0 0x80000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + apps_rsc: rsc@179c0000 { + compatible = "qcom,rpmh-rsc"; + reg = <0 0x179c0000 0 0x10000>, + <0 0x179d0000 0 0x10000>, + <0 0x179e0000 0 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = , + , + ; + label = "apps_rsc"; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,sdm670-rpmh-clk"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board>; + }; + + rpmhpd: power-controller { + compatible = "qcom,sdm670-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp4 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp6 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level = ; + }; + }; + }; + }; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + reg = <0 0x17a00000 0 0x10000>, /* GICD */ + <0 0x17a60000 0 0x100000>; /* GICR * 8 */ + interrupt-controller; + interrupts = ; + #interrupt-cells = <3>; + }; + }; +}; From 813e831570017bfbab8ccb898a46349c2df3f0f1 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Thu, 10 Nov 2022 11:35:50 +0100 Subject: [PATCH 246/261] arm64: dts: qcom: sc8280xp/sa8540p: add PCIe2-4 nodes The SC8280XP platform has seven PCIe controllers: PCIe0 USB4 PCIe1 USB4 PCIe2A 4-lane PCIe2B 2-lane PCIe3A 4-lane PCIe3B 2-lane PCIe4 1-lane while SA8540P only has five (PCIe2-4). Add devicetree nodes for the PCIe2-4 controllers and their PHYs. Signed-off-by: Johan Hovold Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221110103558.12690-2-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sa8540p.dtsi | 59 +++ arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 493 ++++++++++++++++++++++++- 2 files changed, 547 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8540p.dtsi b/arch/arm64/boot/dts/qcom/sa8540p.dtsi index 8ea2886fbab2..01a24b6a5e6d 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8540p.dtsi @@ -128,6 +128,65 @@ opp-2592000000 { }; }; +&pcie2a { + compatible = "qcom,pcie-sa8540p"; + + linux,pci-domain = <0>; + + interrupts = ; + interrupt-names = "msi"; +}; + +&pcie2b { + compatible = "qcom,pcie-sa8540p"; + + linux,pci-domain = <1>; + + interrupts = ; + interrupt-names = "msi"; +}; + +&pcie3a { + compatible = "qcom,pcie-sa8540p"; + reg = <0x0 0x01c10000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf1d>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x1000>, + <0x0 0x40100000 0x0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + + ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1d00000>; + + linux,pci-domain = <2>; + + interrupts = ; + interrupt-names = "msi"; + + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>; +}; + +&pcie3b { + compatible = "qcom,pcie-sa8540p"; + + linux,pci-domain = <3>; + + interrupts = ; + interrupt-names = "msi"; +}; + +&pcie4 { + compatible = "qcom,pcie-sa8540p"; + + linux,pci-domain = <4>; + + interrupts = ; + interrupt-names = "msi"; +}; + &rpmhpd { compatible = "qcom,sa8540p-rpmhpd"; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 700c6273df13..be72b1f7ad61 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -729,11 +729,11 @@ gcc: clock-controller@100000 { <0>, <0>, <0>, - <0>, - <0>, - <0>, - <0>, - <0>, + <&pcie2a_phy>, + <&pcie2b_phy>, + <&pcie3a_phy>, + <&pcie3b_phy>, + <&pcie4_phy>, <0>, <0>; power-domains = <&rpmhpd SC8280XP_CX>; @@ -839,6 +839,489 @@ qup1: geniqup@ac0000 { status = "disabled"; }; + pcie4: pcie@1c00000 { + device_type = "pci"; + compatible = "qcom,pcie-sc8280xp"; + reg = <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x30000000 0x0 0xf1d>, + <0x0 0x30000f20 0x0 0xa8>, + <0x0 0x30001000 0x0 0x1000>, + <0x0 0x30100000 0x0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x30200000 0x0 0x30200000 0x0 0x100000>, + <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>; + bus-range = <0x00 0xff>; + + linux,pci-domain = <6>; + num-lanes = <1>; + + interrupts = , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_4_AUX_CLK>, + <&gcc GCC_PCIE_4_CFG_AHB_CLK>, + <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_4_SLV_AXI_CLK>, + <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>, + <&gcc GCC_CNOC_PCIE4_QX_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "noc_aggr_4", + "noc_aggr_south_sf", + "cnoc_qx"; + + assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + resets = <&gcc GCC_PCIE_4_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_4_GDSC>; + + phys = <&pcie4_phy>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie4_phy: phy@1c06000 { + compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy"; + reg = <0x0 0x01c06000 0x0 0x2000>; + + clocks = <&gcc GCC_PCIE_4_AUX_CLK>, + <&gcc GCC_PCIE_4_CFG_AHB_CLK>, + <&gcc GCC_PCIE_4_CLKREF_CLK>, + <&gcc GCC_PCIE4_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_4_PIPE_CLK>, + <&gcc GCC_PCIE_4_PIPEDIV2_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "rchng", + "pipe", "pipediv2"; + + assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + power-domains = <&gcc PCIE_4_GDSC>; + + resets = <&gcc GCC_PCIE_4_PHY_BCR>; + reset-names = "phy"; + + #clock-cells = <0>; + clock-output-names = "pcie_4_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + pcie3b: pcie@1c08000 { + device_type = "pci"; + compatible = "qcom,pcie-sc8280xp"; + reg = <0x0 0x01c08000 0x0 0x3000>, + <0x0 0x32000000 0x0 0xf1d>, + <0x0 0x32000f20 0x0 0xa8>, + <0x0 0x32001000 0x0 0x1000>, + <0x0 0x32100000 0x0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x32200000 0x0 0x32200000 0x0 0x100000>, + <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>; + bus-range = <0x00 0xff>; + + linux,pci-domain = <5>; + num-lanes = <2>; + + interrupts = , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, + <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, + <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_3B_SLV_AXI_CLK>, + <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "noc_aggr_4", + "noc_aggr_south_sf"; + + assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + resets = <&gcc GCC_PCIE_3B_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_3B_GDSC>; + + phys = <&pcie3b_phy>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie3b_phy: phy@1c0e000 { + compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; + reg = <0x0 0x01c0e000 0x0 0x2000>; + + clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, + <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, + <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, + <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_3B_PIPE_CLK>, + <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "rchng", + "pipe", "pipediv2"; + + assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + power-domains = <&gcc PCIE_3B_GDSC>; + + resets = <&gcc GCC_PCIE_3B_PHY_BCR>; + reset-names = "phy"; + + #clock-cells = <0>; + clock-output-names = "pcie_3b_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + pcie3a: pcie@1c10000 { + device_type = "pci"; + compatible = "qcom,pcie-sc8280xp"; + reg = <0x0 0x01c10000 0x0 0x3000>, + <0x0 0x34000000 0x0 0xf1d>, + <0x0 0x34000f20 0x0 0xa8>, + <0x0 0x34001000 0x0 0x1000>, + <0x0 0x34100000 0x0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x34200000 0x0 0x34200000 0x0 0x100000>, + <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>; + bus-range = <0x00 0xff>; + + linux,pci-domain = <4>; + num-lanes = <4>; + + interrupts = , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, + <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, + <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_3A_SLV_AXI_CLK>, + <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "noc_aggr_4", + "noc_aggr_south_sf"; + + assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + resets = <&gcc GCC_PCIE_3A_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_3A_GDSC>; + + phys = <&pcie3a_phy>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie3a_phy: phy@1c14000 { + compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; + reg = <0x0 0x01c14000 0x0 0x2000>, + <0x0 0x01c16000 0x0 0x2000>; + + clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, + <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, + <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, + <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_3A_PIPE_CLK>, + <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "rchng", + "pipe", "pipediv2"; + + assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + power-domains = <&gcc PCIE_3A_GDSC>; + + resets = <&gcc GCC_PCIE_3A_PHY_BCR>; + reset-names = "phy"; + + qcom,4ln-config-sel = <&tcsr 0xa044 1>; + + #clock-cells = <0>; + clock-output-names = "pcie_3a_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + pcie2b: pcie@1c18000 { + device_type = "pci"; + compatible = "qcom,pcie-sc8280xp"; + reg = <0x0 0x01c18000 0x0 0x3000>, + <0x0 0x38000000 0x0 0xf1d>, + <0x0 0x38000f20 0x0 0xa8>, + <0x0 0x38001000 0x0 0x1000>, + <0x0 0x38100000 0x0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x38200000 0x0 0x38200000 0x0 0x100000>, + <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>; + bus-range = <0x00 0xff>; + + linux,pci-domain = <3>; + num-lanes = <2>; + + interrupts = , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, + <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, + <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_2B_SLV_AXI_CLK>, + <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "noc_aggr_4", + "noc_aggr_south_sf"; + + assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + resets = <&gcc GCC_PCIE_2B_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_2B_GDSC>; + + phys = <&pcie2b_phy>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie2b_phy: phy@1c1e000 { + compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; + reg = <0x0 0x01c1e000 0x0 0x2000>; + + clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, + <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, + <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, + <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_2B_PIPE_CLK>, + <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "rchng", + "pipe", "pipediv2"; + + assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + power-domains = <&gcc PCIE_2B_GDSC>; + + resets = <&gcc GCC_PCIE_2B_PHY_BCR>; + reset-names = "phy"; + + #clock-cells = <0>; + clock-output-names = "pcie_2b_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + pcie2a: pcie@1c20000 { + device_type = "pci"; + compatible = "qcom,pcie-sc8280xp"; + reg = <0x0 0x01c20000 0x0 0x3000>, + <0x0 0x3c000000 0x0 0xf1d>, + <0x0 0x3c000f20 0x0 0xa8>, + <0x0 0x3c001000 0x0 0x1000>, + <0x0 0x3c100000 0x0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x3c200000 0x0 0x3c200000 0x0 0x100000>, + <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>; + bus-range = <0x00 0xff>; + + linux,pci-domain = <2>; + num-lanes = <4>; + + interrupts = , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, + <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, + <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_2A_SLV_AXI_CLK>, + <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "noc_aggr_4", + "noc_aggr_south_sf"; + + assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + resets = <&gcc GCC_PCIE_2A_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_2A_GDSC>; + + phys = <&pcie2a_phy>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie2a_phy: phy@1c24000 { + compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; + reg = <0x0 0x01c24000 0x0 0x2000>, + <0x0 0x01c26000 0x0 0x2000>; + + clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, + <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, + <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, + <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_2A_PIPE_CLK>, + <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "rchng", + "pipe", "pipediv2"; + + assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + power-domains = <&gcc PCIE_2A_GDSC>; + + resets = <&gcc GCC_PCIE_2A_PHY_BCR>; + reset-names = "phy"; + + qcom,4ln-config-sel = <&tcsr 0xa044 0>; + + #clock-cells = <0>; + clock-output-names = "pcie_2a_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + ufs_mem_hc: ufs@1d84000 { compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; From c35d4d7128726e7c8160bedd9ed5b309978bdeb3 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Thu, 10 Nov 2022 11:35:51 +0100 Subject: [PATCH 247/261] arm64: dts: qcom: sa8295p-adp: enable PCIe The SA8295P-ADP has up to four PCIe interfaces implemented by three or four controllers: PCIe2A, PCIe3A/PCIe3B and PCIe4. PCIe2 is used in x4 mode, while PCIe3 can be used in either x2 or x4 mode. Enable both PCIe3A and PCI3B in x2 mode for now. Signed-off-by: Johan Hovold Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221110103558.12690-3-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 171 +++++++++++++++++++++++ 1 file changed, 171 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts index b608b82dff03..ff1e6a674913 100644 --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts @@ -57,6 +57,13 @@ vreg_l13a: ldo13 { regulator-max-microvolt = <3072000>; regulator-initial-mode = ; }; + + vreg_l11a: ldo11 { + regulator-name = "vreg_l11a"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; }; pmm8540-c-regulators { @@ -151,6 +158,76 @@ vreg_l8g: ldo8 { }; }; +&pcie2a { + perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie2a_default>; + + status = "okay"; +}; + +&pcie2a_phy { + vdda-phy-supply = <&vreg_l11a>; + vdda-pll-supply = <&vreg_l3a>; + + status = "okay"; +}; + +&pcie3a { + num-lanes = <2>; + + perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie3a_default>; + + status = "okay"; +}; + +&pcie3a_phy { + vdda-phy-supply = <&vreg_l11a>; + vdda-pll-supply = <&vreg_l3a>; + + status = "okay"; +}; + +&pcie3b { + perst-gpios = <&tlmm 153 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie3b_default>; + + status = "okay"; +}; + +&pcie3b_phy { + vdda-phy-supply = <&vreg_l11a>; + vdda-pll-supply = <&vreg_l3a>; + + status = "okay"; +}; + +&pcie4 { + perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie4_default>; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l11a>; + vdda-pll-supply = <&vreg_l3a>; + + status = "okay"; +}; + &qup2 { status = "okay"; }; @@ -380,3 +457,97 @@ &xo_board_clk { }; /* PINCTRL */ + +&tlmm { + pcie2a_default: pcie2a-default-state { + clkreq-n-pins { + pins = "gpio142"; + function = "pcie2a_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio143"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wake-n-pins { + pins = "gpio145"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie3a_default: pcie3a-default-state { + clkreq-n-pins { + pins = "gpio150"; + function = "pcie3a_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio151"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wake-n-pins { + pins = "gpio56"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie3b_default: pcie3b-default-state { + clkreq-n-pins { + pins = "gpio152"; + function = "pcie3b_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio153"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wake-n-pins { + pins = "gpio130"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio140"; + function = "pcie4_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio141"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wake-n-pins { + pins = "gpio139"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; From 5634c6d9771df48838384b14592a00a1e7da8fdf Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Thu, 10 Nov 2022 11:35:52 +0100 Subject: [PATCH 248/261] arm64: dts: qcom: sc8280xp-crd: rename backlight and misc regulators Rename the backlight and misc regulators according to the net names. Signed-off-by: Johan Hovold Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221110103558.12690-4-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index a2027f1d1d04..0801bd8c44fb 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -37,7 +37,7 @@ chosen { vreg_edp_bl: regulator-edp-bl { compatible = "regulator-fixed"; - regulator-name = "VREG_EDP_BL"; + regulator-name = "VBL9"; regulator-min-microvolt = <3600000>; regulator-max-microvolt = <3600000>; @@ -53,7 +53,7 @@ vreg_edp_bl: regulator-edp-bl { vreg_misc_3p3: regulator-misc-3p3 { compatible = "regulator-fixed"; - regulator-name = "VREG_MISC_3P3"; + regulator-name = "VCC3B"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; From 6a1ec5eca73c0ca8cdefd13426bf812c65a1e510 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Thu, 10 Nov 2022 11:35:53 +0100 Subject: [PATCH 249/261] arm64: dts: qcom: sc8280xp-crd: enable NVMe SSD Enable the NVMe SSD connected to PCIe2. Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221110103558.12690-5-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 63 +++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index 0801bd8c44fb..fd2bdfd1126b 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -50,6 +50,20 @@ vreg_edp_bl: regulator-edp-bl { regulator-boot-on; }; + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VCC3_SSD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 135 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&nvme_reg_en>; + }; + vreg_misc_3p3: regulator-misc-3p3 { compatible = "regulator-fixed"; @@ -178,6 +192,25 @@ vreg_l9d: ldo9 { }; }; +&pcie2a { + perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie2a_default>; + + status = "okay"; +}; + +&pcie2a_phy { + vdda-phy-supply = <&vreg_l6d>; + vdda-pll-supply = <&vreg_l4d>; + + status = "okay"; +}; + &pmc8280c_lpg { status = "okay"; }; @@ -393,6 +426,36 @@ reset-pins { }; }; + nvme_reg_en: nvme-reg-en-state { + pins = "gpio135"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie2a_default: pcie2a-default-state { + clkreq-n-pins { + pins = "gpio142"; + function = "pcie2a_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio143"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wake-n-pins { + pins = "gpio145"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + qup0_i2c4_default: qup0-i2c4-default-state { pins = "gpio171", "gpio172"; function = "qup4"; From 17e2ccaf65d16848b27793853af8f42ae524219f Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Thu, 10 Nov 2022 11:35:54 +0100 Subject: [PATCH 250/261] arm64: dts: qcom: sc8280xp-crd: enable SDX55 modem Enable the SDX55 modem connected to PCIe3. Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221110103558.12690-6-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 65 +++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index fd2bdfd1126b..5b9e37a16f9f 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -80,6 +80,22 @@ vreg_misc_3p3: regulator-misc-3p3 { regulator-boot-on; regulator-always-on; }; + + vreg_wwan: regulator-wwan { + compatible = "regulator-fixed"; + + regulator-name = "VCC3B_WAN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmc8280_2_gpios 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&wwan_sw_en>; + + regulator-boot-on; + }; }; &apps_rsc { @@ -211,6 +227,25 @@ &pcie2a_phy { status = "okay"; }; +&pcie3a { + perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply = <&vreg_wwan>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie3a_default>; + + status = "okay"; +}; + +&pcie3a_phy { + vdda-phy-supply = <&vreg_l6d>; + vdda-pll-supply = <&vreg_l4d>; + + status = "okay"; +}; + &pmc8280c_lpg { status = "okay"; }; @@ -396,6 +431,13 @@ misc_3p3_reg_en: misc-3p3-reg-en-state { }; }; +&pmc8280_2_gpios { + wwan_sw_en: wwan-sw-en-state { + pins = "gpio1"; + function = "normal"; + }; +}; + &pmc8280c_gpios { edp_bl_pwm: edp-bl-pwm-state { pins = "gpio8"; @@ -456,6 +498,29 @@ wake-n-pins { }; }; + pcie3a_default: pcie3a-default-state { + clkreq-n-pins { + pins = "gpio150"; + function = "pcie3a_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio151"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + qup0_i2c4_default: qup0-i2c4-default-state { pins = "gpio171", "gpio172"; function = "qup4"; From d907fe5acbf1061f86936485d604c229e68ae312 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Thu, 10 Nov 2022 11:35:55 +0100 Subject: [PATCH 251/261] arm64: dts: qcom: sc8280xp-crd: enable WiFi controller Enable the Qualcomm QCNFA765 Wireless Network Adapter connected to PCIe4. Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221110103558.12690-7-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 65 +++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index 5b9e37a16f9f..ab5b0aadeead 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -81,6 +81,22 @@ vreg_misc_3p3: regulator-misc-3p3 { regulator-always-on; }; + vreg_wlan: regulator-wlan { + compatible = "regulator-fixed"; + + regulator-name = "VCC_WLAN_3R9"; + regulator-min-microvolt = <3900000>; + regulator-max-microvolt = <3900000>; + + gpio = <&pmr735a_gpios 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&hastings_reg_en>; + + regulator-boot-on; + }; + vreg_wwan: regulator-wwan { compatible = "regulator-fixed"; @@ -246,6 +262,25 @@ &pcie3a_phy { status = "okay"; }; +&pcie4 { + perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply = <&vreg_wlan>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie4_default>; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l6d>; + vdda-pll-supply = <&vreg_l4d>; + + status = "okay"; +}; + &pmc8280c_lpg { status = "okay"; }; @@ -445,6 +480,13 @@ edp_bl_pwm: edp-bl-pwm-state { }; }; +&pmr735a_gpios { + hastings_reg_en: hastings-reg-en-state { + pins = "gpio1"; + function = "normal"; + }; +}; + &tlmm { gpio-reserved-ranges = <74 6>, <83 4>, <125 2>, <128 2>, <154 7>; @@ -521,6 +563,29 @@ wake-n-pins { }; }; + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio140"; + function = "pcie4_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio141"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wake-n-pins { + pins = "gpio139"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + qup0_i2c4_default: qup0-i2c4-default-state { pins = "gpio171", "gpio172"; function = "qup4"; From b4bb952e6cfc13f86b4b52c3039b199dd3f16020 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Thu, 10 Nov 2022 11:35:56 +0100 Subject: [PATCH 252/261] arm64: dts: qcom: sc8280xp-x13s: enable NVMe SSD Enable the NVMe SSD connected to PCIe2. Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221110103558.12690-8-johan+linaro@kernel.org --- .../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 72 +++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 02083342bfca..e212b5307f98 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -124,6 +124,22 @@ vreg_misc_3p3: regulator-misc-3p3 { regulator-boot-on; regulator-always-on; }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VCC3_SSD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 135 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&nvme_reg_en>; + + regulator-boot-on; + }; }; &apps_rsc { @@ -211,6 +227,13 @@ vreg_l4d: ldo4 { regulator-initial-mode = ; }; + vreg_l6d: ldo6 { + regulator-name = "vreg_l6d"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + vreg_l7d: ldo7 { regulator-name = "vreg_l7d"; regulator-min-microvolt = <3072000>; @@ -227,6 +250,25 @@ vreg_l9d: ldo9 { }; }; +&pcie2a { + perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie2a_default>; + + status = "okay"; +}; + +&pcie2a_phy { + vdda-phy-supply = <&vreg_l6d>; + vdda-pll-supply = <&vreg_l4d>; + + status = "okay"; +}; + &pmc8280c_lpg { status = "okay"; }; @@ -592,6 +634,36 @@ reset-pins { }; }; + nvme_reg_en: nvme-reg-en-state { + pins = "gpio135"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie2a_default: pcie2a-default-state { + clkreq-n-pins { + pins = "gpio142"; + function = "pcie2a_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio143"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wake-n-pins { + pins = "gpio145"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + qup0_i2c4_default: qup0-i2c4-default-state { pins = "gpio171", "gpio172"; function = "qup4"; From 176d54acd5d9c79bb6b51dbe2550a3b0441353bf Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Thu, 10 Nov 2022 11:35:57 +0100 Subject: [PATCH 253/261] arm64: dts: qcom: sc8280xp-x13s: enable modem Enable the modem connected to the PCIe3a M.2 connector. Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221110103558.12690-9-johan+linaro@kernel.org --- .../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 65 +++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index e212b5307f98..9a7e959f3825 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -140,6 +140,22 @@ vreg_nvme: regulator-nvme { regulator-boot-on; }; + + vreg_wwan: regulator-wwan { + compatible = "regulator-fixed"; + + regulator-name = "VCC3B_WAN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmc8280_2_gpios 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&wwan_sw_en>; + + regulator-boot-on; + }; }; &apps_rsc { @@ -269,6 +285,25 @@ &pcie2a_phy { status = "okay"; }; +&pcie3a { + perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply = <&vreg_wwan>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie3a_default>; + + status = "okay"; +}; + +&pcie3a_phy { + vdda-phy-supply = <&vreg_l6d>; + vdda-pll-supply = <&vreg_l4d>; + + status = "okay"; +}; + &pmc8280c_lpg { status = "okay"; }; @@ -597,6 +632,13 @@ misc_3p3_reg_en: misc-3p3-reg-en-state { }; }; +&pmc8280_2_gpios { + wwan_sw_en: wwan-sw-en-state { + pins = "gpio1"; + function = "normal"; + }; +}; + &pmc8280c_gpios { edp_bl_pwm: edp-bl-pwm-state { pins = "gpio8"; @@ -664,6 +706,29 @@ wake-n-pins { }; }; + pcie3a_default: pcie3a-default-state { + clkreq-n-pins { + pins = "gpio150"; + function = "pcie3a_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio151"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + qup0_i2c4_default: qup0-i2c4-default-state { pins = "gpio171", "gpio172"; function = "qup4"; From 123b30a75623f7131af0f0fa2bee330be65f1ead Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Thu, 10 Nov 2022 11:35:58 +0100 Subject: [PATCH 254/261] arm64: dts: qcom: sc8280xp-x13s: enable WiFi controller Enable the Qualcomm QCNFA765 Wireless Network Adapter connected to PCIe4. Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221110103558.12690-10-johan+linaro@kernel.org --- .../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 65 +++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 9a7e959f3825..568c6be1ceaa 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -141,6 +141,22 @@ vreg_nvme: regulator-nvme { regulator-boot-on; }; + vreg_wlan: regulator-wlan { + compatible = "regulator-fixed"; + + regulator-name = "VCC_WLAN_3R9"; + regulator-min-microvolt = <3900000>; + regulator-max-microvolt = <3900000>; + + gpio = <&pmr735a_gpios 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&hastings_reg_en>; + + regulator-boot-on; + }; + vreg_wwan: regulator-wwan { compatible = "regulator-fixed"; @@ -304,6 +320,25 @@ &pcie3a_phy { status = "okay"; }; +&pcie4 { + perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply = <&vreg_wlan>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie4_default>; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l6d>; + vdda-pll-supply = <&vreg_l4d>; + + status = "okay"; +}; + &pmc8280c_lpg { status = "okay"; }; @@ -646,6 +681,13 @@ edp_bl_pwm: edp-bl-pwm-state { }; }; +&pmr735a_gpios { + hastings_reg_en: hastings-reg-en-state { + pins = "gpio1"; + function = "normal"; + }; +}; + &tlmm { gpio-reserved-ranges = <70 2>, <74 6>, <83 4>, <125 2>, <128 2>, <154 7>; @@ -729,6 +771,29 @@ wake-n-pins { }; }; + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio140"; + function = "pcie4_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio141"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wake-n-pins { + pins = "gpio139"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + qup0_i2c4_default: qup0-i2c4-default-state { pins = "gpio171", "gpio172"; function = "qup4"; From 0d70d5f6614e15bdc269b630b7f884889568b1bb Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 15 Nov 2022 13:53:09 +0100 Subject: [PATCH 255/261] arm64: dts: msm8998: add MSM8998 specific compatible Add new compatible for MSM8998 (compatible with MSM8996) to allow further customizing if needed and to accurately describe the hardware. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221115125310.184012-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index da2dd87e3f4f..320a28232a32 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -900,7 +900,7 @@ anoc2_smmu: iommu@16c0000 { }; pcie0: pci@1c00000 { - compatible = "qcom,pcie-msm8996"; + compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996"; reg = <0x01c00000 0x2000>, <0x1b000000 0xf1d>, <0x1b000f20 0xa8>, From b132731bb936cfe0ee26790eeb51572d12dbf854 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 15 Nov 2022 13:53:10 +0100 Subject: [PATCH 256/261] arm64: dts: msm8998: unify PCIe clock order withMSM8996 PCIe on MSM8996 and MSM8998 use the same clocks, so use one order to make the binding simpler. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221115125310.184012-4-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 320a28232a32..539382dab0ad 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -929,11 +929,11 @@ pcie0: pci@1c00000 { <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, - <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_AUX_CLK>; - clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux"; + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>; + clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave"; power-domains = <&gcc PCIE_0_GDSC>; iommu-map = <0x100 &anoc1_smmu 0x1480 1>; From 22dbcfd6f4a9f7d4391f0aa66d3f46addea4bee9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 15 Nov 2022 11:50:46 +0100 Subject: [PATCH 257/261] arm64: dts: qcom: trim addresses to 8 digits Hex numbers in addresses and sizes should be rather eight digits, not nine. Drop leading zeros. No functional change (same DTB). Suggested-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221115105046.95254-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8450.dtsi | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 552c0da3c479..49db223a0777 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2222,7 +2222,7 @@ compute-cb@3 { cdsp: remoteproc@98900000 { compatible = "qcom,sm8350-cdsp-pas"; - reg = <0 0x098900000 0 0x1400000>; + reg = <0 0x98900000 0 0x1400000>; interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 19a0f5033cc9..f20db5456765 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2091,7 +2091,7 @@ compute-cb@3 { remoteproc_adsp: remoteproc@30000000 { compatible = "qcom,sm8450-adsp-pas"; - reg = <0 0x030000000 0 0x100>; + reg = <0 0x30000000 0 0x100>; interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, @@ -2157,7 +2157,7 @@ compute-cb@5 { remoteproc_cdsp: remoteproc@32300000 { compatible = "qcom,sm8450-cdsp-pas"; - reg = <0 0x032300000 0 0x1400000>; + reg = <0 0x32300000 0 0x1400000>; interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, From f98d1a3c653e7e6f540e680eb8fef046c21cb091 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Mon, 14 Nov 2022 16:28:28 -0800 Subject: [PATCH 258/261] arm64: dts: qcom: sc7280: Make herobrine-audio-rt5682 mic dtsi's match more The 1-mic and 3-mic dtsi still had two minor cosmetic differences after commit '3d11e7e120ee ("arm64: dts: qcom: sc7280: sort out the "Status" to last property with sc7280-herobrine-audio-rt5682.dtsi")'. Let's fix them so the two files diff better. This is expected to have no effect though it will slightly change the generated dtb by removing an unnecessary 'status = "okay"' from the sound node. Signed-off-by: Douglas Anderson Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221114162807.1.I0900b97128f9bb03e5f96fcb3068c227a33f143a@changeid --- arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682.dtsi index fc7a659dfe4a..af685bc35e10 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682.dtsi @@ -19,8 +19,6 @@ sound: sound { #address-cells = <1>; #size-cells = <0>; - status = "okay"; - dai-link@0 { link-name = "MAX98360"; reg = <0>; @@ -96,6 +94,8 @@ dai-link@1 { }; }; +/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */ + &mi2s0_data0 { drive-strength = <6>; bias-disable; From 5440c005dadc22ee132d59816ca51eb98aa59954 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 14 Nov 2022 15:36:41 +0100 Subject: [PATCH 259/261] arm64: dts: qcom: sm8350-sagami: Add most RPMh regulators Configure most RPMh-controlled regulators on SoMC Sagami. The missing ones (on pm8350b and pm8008[ij]) will be configured when driver support is added. Thankfully, it looks like PDX215 and PDX214 don't have any differences when it comes to PM8350/PM8350C/PMR735a. Signed-off-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221114143642.44839-1-konrad.dybcio@linaro.org --- .../dts/qcom/sm8350-sony-xperia-sagami.dtsi | 350 ++++++++++++++++++ 1 file changed, 350 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi index e73ea22bd142..f7eb30bc4f4d 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2021, Konrad Dybcio */ +#include #include "sm8350.dtsi" #include "pm8350.dtsi" #include "pm8350b.dtsi" @@ -73,6 +74,16 @@ ramoops@ffc00000 { no-map; }; }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; }; &adsp { @@ -80,6 +91,345 @@ &adsp { firmware-name = "qcom/sm8350/Sony/sagami/adsp.mbn"; }; +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8350-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-s11-supply = <&vph_pwr>; + vdd-s12-supply = <&vph_pwr>; + + vdd-l1-l4-supply = <&pm8350_s11>; + vdd-l2-l7-supply = <&vreg_bob>; + vdd-l3-l5-supply = <&vreg_bob>; + vdd-l6-l9-l10-supply = <&pm8350_s11>; + + /* + * ARC regulators: + * S5 - mx.lvl + * S6 - gfx.lvl + * S9 - mxc.lvl + */ + + pm8350_s10: smps10 { + regulator-name = "pm8350_s10"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + pm8350_s11: smps11 { + regulator-name = "pm8350_s11"; + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = ; + }; + + pm8350_s12: smps12 { + regulator-name = "pm8350_s12"; + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1360000>; + regulator-initial-mode = ; + }; + + pm8350_l1: ldo1 { + regulator-name = "pm8350_l1"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + pm8350_l2: ldo2 { + regulator-name = "pm8350_l2"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + pm8350_l3: ldo3 { + regulator-name = "pm8350_l3"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <904000>; + regulator-initial-mode = ; + }; + + /* L4 - lmx.lvl (ARC) */ + + pm8350_l5: ldo5 { + regulator-name = "pm8350_l5"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <888000>; + regulator-initial-mode = ; + regulator-allow-set-load; + }; + + pm8350_l6: ldo6 { + regulator-name = "pm8350_l6"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1208000>; + regulator-initial-mode = ; + regulator-allow-set-load; + }; + + pm8350_l7: ldo7 { + regulator-name = "pm8350_l7"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + regulator-allow-set-load; + }; + + /* L8 - lcx.lvl (ARC) */ + + pm8350_l9: ldo9 { + regulator-name = "pm8350_l9"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + }; + }; + + regulators-1 { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + + vdd-l1-l12-supply = <&pm8350c_s1>; + vdd-l2-l8-supply = <&pm8350c_s1>; + vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>; + vdd-l6-l9-l11-supply = <&vreg_bob>; + vdd-l10-supply = <&pm8350_s12>; + + vdd-bob-supply = <&vph_pwr>; + + pm8350c_s1: smps1 { + regulator-name = "pm8350c_s1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1952000>; + regulator-initial-mode = ; + }; + + /* S2 - ebi.lvl (ARC) */ + + pm8350c_s3: smps3 { + regulator-name = "pm8350c_s3"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <704000>; + regulator-initial-mode = ; + }; + + /* + * ARC regulators: + * S4 - mss.lvl + * S6 - cx.lvl + * S8 - mmcx.lvl + */ + + pm8350c_s10: smps10 { + regulator-name = "pm8350c_s10"; + regulator-min-microvolt = <1048000>; + regulator-max-microvolt = <1128000>; + regulator-initial-mode = ; + }; + + pm8350c_l1: ldo1 { + regulator-name = "pm8350c_l1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + pm8350c_l2: ldo2 { + regulator-name = "pm8350c_l2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + pm8350c_l3: ldo3 { + regulator-name = "pm8350c_l3"; + regulator-min-microvolt = <3304000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + pm8350c_l4: ldo4 { + regulator-name = "pm8350c_l4"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + pm8350c_l5: ldo5 { + regulator-name = "pm8350c_l5"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + pm8350c_l6: ldo6 { + regulator-name = "pm8350c_l6"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + pm8350c_l7: ldo7 { + regulator-name = "pm8350c_l7"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + pm8350c_l8: ldo8 { + regulator-name = "pm8350c_l8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + pm8350c_l9: ldo9 { + regulator-name = "pm8350c_l9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + pm8350c_l10: ldo10 { + regulator-name = "pm8350c_l10"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + pm8350c_l11: ldo11 { + regulator-name = "pm8350c_l11"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + pm8350c_l12: ldo12 { + regulator-name = "pm8350c_l12"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + pm8350c_l13: ldo13 { + regulator-name = "pm8350c_l13"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_bob: bob { + regulator-name = "vreg_bob"; + regulator-min-microvolt = <3400000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + }; + + /* TODO: Add pm8350b (just one ldo) once the driver part is in */ + + regulators-2 { + compatible = "qcom,pmr735a-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + + vdd-l1-l2-supply = <&pmr735a_s2>; + vdd-l3-supply = <&pmr735a_s1>; + vdd-l4-supply = <&pm8350c_s1>; + vdd-l5-l6-supply = <&pm8350c_s1>; + vdd-l7-bob-supply = <&vreg_bob>; + + pmr735a_s1: smps1 { + regulator-name = "pmr735a_s1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1280000>; + }; + + pmr735a_s2: smps2 { + regulator-name = "pmr735a_s2"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <976000>; + }; + + pmr735a_s3: smps3 { + regulator-name = "pmr735a_s3"; + regulator-min-microvolt = <2208000>; + regulator-max-microvolt = <2352000>; + }; + + pmr735a_l1: ldo1 { + regulator-name = "pmr735a_l1"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + }; + + pmr735a_l2: ldo2 { + regulator-name = "pmr735a_l2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pmr735a_l3: ldo3 { + regulator-name = "pmr735a_l3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pmr735a_l4: ldo4 { + regulator-name = "pmr735a_l4"; + regulator-min-microvolt = <1776000>; + regulator-max-microvolt = <1872000>; + }; + + pmr735a_l5: ldo5 { + regulator-name = "pmr735a_l5"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + }; + + pmr735a_l6: ldo6 { + regulator-name = "pmr735a_l6"; + regulator-min-microvolt = <480000>; + regulator-max-microvolt = <904000>; + }; + + pmr735a_l7: ldo7 { + regulator-name = "pmr735a_l7"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + }; +}; + &cdsp { status = "okay"; firmware-name = "qcom/sm8350/Sony/sagami/cdsp.mbn"; From 5a077120bcf6aacf97da75a0f925bfdbe2666815 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 14 Nov 2022 15:36:42 +0100 Subject: [PATCH 260/261] arm64: dts: qcom: sm8350-sagami: Wire up USB regulators and fix USB3 Wire up necessary supplies to USB PHYs to enable USB3 on Sagami and remove all the limit-to-USB2 properties. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221114143642.44839-2-konrad.dybcio@linaro.org --- .../boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi index f7eb30bc4f4d..3365903cb931 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi @@ -585,25 +585,25 @@ ts_int_default: ts-int-default-state { &ufs_mem_hc { status = "disabled"; }; &ufs_mem_phy { status = "disabled"; }; -/* TODO: Make USB3 work (perhaps needs regulators for higher-current operation?) */ &usb_1 { status = "okay"; - - qcom,select-utmi-as-pipe-clk; }; &usb_1_dwc3 { dr_mode = "peripheral"; - - maximum-speed = "high-speed"; - phys = <&usb_1_hsphy>; - phy-names = "usb2-phy"; }; &usb_1_hsphy { status = "okay"; + + vdda-pll-supply = <&pm8350_l5>; + vdda18-supply = <&pm8350c_l1>; + vdda33-supply = <&pm8350_l2>; }; &usb_1_qmpphy { status = "okay"; + + vdda-phy-supply = <&pm8350_l6>; + vdda-pll-supply = <&pm8350_l1>; }; From afcd946be11c937ed400b1d4727e2b5fe04ba693 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 14 Nov 2022 15:00:11 +0100 Subject: [PATCH 261/261] arm64: dts: qcom: sdm845-polaris: Don't duplicate DMA assignment The DMA properties in this DT are identical to the ones already defined in sdm845.dtsi. Remove them. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221114140011.43442-1-konrad.dybcio@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts index fc189f7caaa4..38ba809a95cd 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts @@ -456,9 +456,6 @@ &ipa { &i2c14 { clock-frequency = <400000>; - dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, - <&gpi_dma1 1 6 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; status = "okay"; touchscreen@20 {