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drm/i915: increase default latency constant (v2 w/comment)
Some i915/i945 platforms have a fairly high memory latency in certain situations, so increase our constant a bit to avoid FIFO underruns. The effect should be positive on other platforms as well; we'll have a bit more insurance against a busy memory subsystem due to the extra FIFO entries. Fixes fdo bug #23368. Needed for 2.6.31. Tested-by: Sven Arvidsson <sa@whiz.se> Tested-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
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1 changed files with 15 additions and 1 deletions
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@ -2005,7 +2005,21 @@ static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
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return;
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}
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const static int latency_ns = 3000; /* default for non-igd platforms */
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/*
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* Latency for FIFO fetches is dependent on several factors:
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* - memory configuration (speed, channels)
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* - chipset
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* - current MCH state
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* It can be fairly high in some situations, so here we assume a fairly
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* pessimal value. It's a tradeoff between extra memory fetches (if we
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* set this value too high, the FIFO will fetch frequently to stay full)
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* and power consumption (set it too low to save power and we might see
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* FIFO underruns and display "flicker").
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*
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* A value of 5us seems to be a good balance; safe for very low end
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* platforms but not overly aggressive on lower latency configs.
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*/
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const static int latency_ns = 5000;
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static int intel_get_fifo_size(struct drm_device *dev, int plane)
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{
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