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ASoC: Intel: bytcr_wm5102: Add BYT_WM5102_MCLK_19_2MHZ quirk
The Cherry Trail SoC only supports 19200000 as clk-frequency for the pmc_plt_clk used for the audio codec. Add a BYT_WM5102_MCLK_19_2MHZ quirk for this and enable this by default on Cherry Trail SoCs. Acked-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Link: https://lore.kernel.org/r/20231025143513.291753-3-hdegoede@redhat.com Signed-off-by: Mark Brown <broonie@kernel.org>
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95504218c6
commit
bce4b014cc
1 changed files with 13 additions and 5 deletions
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@ -27,8 +27,6 @@
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#include "../../codecs/wm5102.h"
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#include "../atom/sst-atom-controls.h"
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#define MCLK_FREQ 25000000
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#define WM5102_MAX_SYSCLK_4K 49152000 /* max sysclk for 4K family */
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#define WM5102_MAX_SYSCLK_11025 45158400 /* max sysclk for 11.025K family */
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@ -36,10 +34,12 @@ struct byt_wm5102_private {
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struct snd_soc_jack jack;
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struct clk *mclk;
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struct gpio_desc *spkvdd_en_gpio;
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int mclk_freq;
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};
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/* Bits 0-15 are reserved for things like an input-map */
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#define BYT_WM5102_SSP2 BIT(16)
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#define BYT_WM5102_MCLK_19_2MHZ BIT(17)
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static unsigned long quirk;
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@ -51,6 +51,8 @@ static void log_quirks(struct device *dev)
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{
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if (quirk & BYT_WM5102_SSP2)
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dev_info_once(dev, "quirk SSP2 enabled");
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if (quirk & BYT_WM5102_MCLK_19_2MHZ)
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dev_info_once(dev, "quirk MCLK 19.2MHz enabled");
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}
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static int byt_wm5102_spkvdd_power_event(struct snd_soc_dapm_widget *w,
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@ -68,6 +70,7 @@ static int byt_wm5102_spkvdd_power_event(struct snd_soc_dapm_widget *w,
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static int byt_wm5102_prepare_and_enable_pll1(struct snd_soc_dai *codec_dai, int rate)
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{
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struct snd_soc_component *codec_component = codec_dai->component;
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struct byt_wm5102_private *priv = snd_soc_card_get_drvdata(codec_component->card);
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int sr_mult = ((rate % 4000) == 0) ?
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(WM5102_MAX_SYSCLK_4K / rate) :
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(WM5102_MAX_SYSCLK_11025 / rate);
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@ -79,7 +82,7 @@ static int byt_wm5102_prepare_and_enable_pll1(struct snd_soc_dai *codec_dai, int
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/* Configure the FLL1 PLL before selecting it */
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ret = snd_soc_dai_set_pll(codec_dai, WM5102_FLL1, ARIZONA_CLK_SRC_MCLK1,
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MCLK_FREQ, rate * sr_mult);
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priv->mclk_freq, rate * sr_mult);
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if (ret) {
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dev_err(codec_component->dev, "Error setting PLL: %d\n", ret);
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return ret;
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@ -251,6 +254,11 @@ static int byt_wm5102_init(struct snd_soc_pcm_runtime *runtime)
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if (ret)
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return ret;
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if (quirk & BYT_WM5102_MCLK_19_2MHZ)
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priv->mclk_freq = 19200000;
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else
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priv->mclk_freq = 25000000;
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/*
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* The firmware might enable the clock at boot (this information
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* may or may not be reflected in the enable clock register).
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@ -263,7 +271,7 @@ static int byt_wm5102_init(struct snd_soc_pcm_runtime *runtime)
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if (!ret)
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clk_disable_unprepare(priv->mclk);
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ret = clk_set_rate(priv->mclk, MCLK_FREQ);
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ret = clk_set_rate(priv->mclk, priv->mclk_freq);
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if (ret) {
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dev_err(card->dev, "Error setting MCLK rate: %d\n", ret);
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return ret;
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@ -486,7 +494,7 @@ static int snd_byt_wm5102_mc_probe(struct platform_device *pdev)
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if (soc_intel_is_cht()) {
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/* On CHT default to SSP2 */
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quirk = BYT_WM5102_SSP2;
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quirk = BYT_WM5102_SSP2 | BYT_WM5102_MCLK_19_2MHZ;
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}
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if (quirk_override != -1) {
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dev_info_once(dev, "Overriding quirk 0x%lx => 0x%x\n",
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