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Here is the first set of FPGA changes for 5.5

Browse source 
The first patch from Stephen is a trivial cleanup patch.
 
 The following three patches add hwmon support to DFL FPGAs.
 
 All of this patches have been reviewed and been in the last couple
 of linux-next releases without issues.
 
 Signed-off-by: Moritz Fischer <mdf@kernel.org>
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Merge tag 'fpga-dfl-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/mdf/linux-fpga into char-misc-next

Moritz writes:

Here is the first set of FPGA changes for 5.5

The first patch from Stephen is a trivial cleanup patch.

The following three patches add hwmon support to DFL FPGAs.

All of this patches have been reviewed and been in the last couple
of linux-next releases without issues.

Signed-off-by: Moritz Fischer <mdf@kernel.org>

* tag 'fpga-dfl-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/mdf/linux-fpga:
  fpga: dfl: fme: add power management support
  fpga: dfl: fme: add thermal management support
  Documentation: fpga: dfl: add descriptions for thermal/power management interfaces
  fpga: Remove dev_err() usage after platform_get_irq()
This commit is contained in:
Greg Kroah-Hartman 2019-11-08 18:48:40 +01:00
commit bce92136c2
5 changed files with 529 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

132
Documentation/ABI/testing/sysfs-platform-dfl-fme
View file

@ -106,3 +106,135 @@ KernelVersion: 5.4
Contact: Wu Hao <hao.wu@intel.com>
Description: Read-only. Read this file to get the second error detected by
hardware.
What: /sys/bus/platform/devices/dfl-fme.0/hwmon/hwmonX/name
Date: October 2019
KernelVersion: 5.5
Contact: Wu Hao <hao.wu@intel.com>
Description: Read-Only. Read this file to get the name of hwmon device, it
supports values:
'dfl_fme_thermal' - thermal hwmon device name
'dfl_fme_power' - power hwmon device name
What: /sys/bus/platform/devices/dfl-fme.0/hwmon/hwmonX/temp1_input
Date: October 2019
KernelVersion: 5.5
Contact: Wu Hao <hao.wu@intel.com>
Description: Read-Only. It returns FPGA device temperature in millidegrees
Celsius.
What: /sys/bus/platform/devices/dfl-fme.0/hwmon/hwmonX/temp1_max
Date: October 2019
KernelVersion: 5.5
Contact: Wu Hao <hao.wu@intel.com>
Description: Read-Only. It returns hardware threshold1 temperature in
millidegrees Celsius. If temperature rises at or above this
threshold, hardware starts 50% or 90% throttling (see
'temp1_max_policy').
What: /sys/bus/platform/devices/dfl-fme.0/hwmon/hwmonX/temp1_crit
Date: October 2019
KernelVersion: 5.5
Contact: Wu Hao <hao.wu@intel.com>
Description: Read-Only. It returns hardware threshold2 temperature in
millidegrees Celsius. If temperature rises at or above this
threshold, hardware starts 100% throttling.
What: /sys/bus/platform/devices/dfl-fme.0/hwmon/hwmonX/temp1_emergency
Date: October 2019
KernelVersion: 5.5
Contact: Wu Hao <hao.wu@intel.com>
Description: Read-Only. It returns hardware trip threshold temperature in
millidegrees Celsius. If temperature rises at or above this
threshold, a fatal event will be triggered to board management
controller (BMC) to shutdown FPGA.
What: /sys/bus/platform/devices/dfl-fme.0/hwmon/hwmonX/temp1_max_alarm
Date: October 2019
KernelVersion: 5.5
Contact: Wu Hao <hao.wu@intel.com>
Description: Read-only. It returns 1 if temperature is currently at or above
hardware threshold1 (see 'temp1_max'), otherwise 0.
What: /sys/bus/platform/devices/dfl-fme.0/hwmon/hwmonX/temp1_crit_alarm
Date: October 2019
KernelVersion: 5.5
Contact: Wu Hao <hao.wu@intel.com>
Description: Read-only. It returns 1 if temperature is currently at or above
hardware threshold2 (see 'temp1_crit'), otherwise 0.
What: /sys/bus/platform/devices/dfl-fme.0/hwmon/hwmonX/temp1_max_policy
Date: October 2019
KernelVersion: 5.5
Contact: Wu Hao <hao.wu@intel.com>
Description: Read-Only. Read this file to get the policy of hardware threshold1
(see 'temp1_max'). It only supports two values (policies):
0 - AP2 state (90% throttling)
1 - AP1 state (50% throttling)
What: /sys/bus/platform/devices/dfl-fme.0/hwmon/hwmonX/power1_input
Date: October 2019
KernelVersion: 5.5
Contact: Wu Hao <hao.wu@intel.com>
Description: Read-Only. It returns current FPGA power consumption in uW.
What: /sys/bus/platform/devices/dfl-fme.0/hwmon/hwmonX/power1_max
Date: October 2019
KernelVersion: 5.5
Contact: Wu Hao <hao.wu@intel.com>
Description: Read-Write. Read this file to get current hardware power
threshold1 in uW. If power consumption rises at or above
this threshold, hardware starts 50% throttling.
Write this file to set current hardware power threshold1 in uW.
As hardware only accepts values in Watts, so input value will
be round down per Watts (< 1 watts part will be discarded) and
clamped within the range from 0 to 127 Watts. Write fails with
-EINVAL if input parsing fails.
What: /sys/bus/platform/devices/dfl-fme.0/hwmon/hwmonX/power1_crit
Date: October 2019
KernelVersion: 5.5
Contact: Wu Hao <hao.wu@intel.com>
Description: Read-Write. Read this file to get current hardware power
threshold2 in uW. If power consumption rises at or above
this threshold, hardware starts 90% throttling.
Write this file to set current hardware power threshold2 in uW.
As hardware only accepts values in Watts, so input value will
be round down per Watts (< 1 watts part will be discarded) and
clamped within the range from 0 to 127 Watts. Write fails with
-EINVAL if input parsing fails.
What: /sys/bus/platform/devices/dfl-fme.0/hwmon/hwmonX/power1_max_alarm
Date: October 2019
KernelVersion: 5.5
Contact: Wu Hao <hao.wu@intel.com>
Description: Read-only. It returns 1 if power consumption is currently at or
above hardware threshold1 (see 'power1_max'), otherwise 0.
What: /sys/bus/platform/devices/dfl-fme.0/hwmon/hwmonX/power1_crit_alarm
Date: October 2019
KernelVersion: 5.5
Contact: Wu Hao <hao.wu@intel.com>
Description: Read-only. It returns 1 if power consumption is currently at or
above hardware threshold2 (see 'power1_crit'), otherwise 0.
What: /sys/bus/platform/devices/dfl-fme.0/hwmon/hwmonX/power1_xeon_limit
Date: October 2019
KernelVersion: 5.5
Contact: Wu Hao <hao.wu@intel.com>
Description: Read-Only. It returns power limit for XEON in uW.
What: /sys/bus/platform/devices/dfl-fme.0/hwmon/hwmonX/power1_fpga_limit
Date: October 2019
KernelVersion: 5.5
Contact: Wu Hao <hao.wu@intel.com>
Description: Read-Only. It returns power limit for FPGA in uW.
What: /sys/bus/platform/devices/dfl-fme.0/hwmon/hwmonX/power1_ltr
Date: October 2019
KernelVersion: 5.5
Contact: Wu Hao <hao.wu@intel.com>
Description: Read-only. Read this file to get current Latency Tolerance
Reporting (ltr) value. It returns 1 if all Accelerated
Function Units (AFUs) can tolerate latency >= 40us for memory
access or 0 if any AFU is latency sensitive (< 40us).

10
Documentation/fpga/dfl.rst
View file

@ -108,6 +108,16 @@ More functions are exposed through sysfs
error reporting sysfs interfaces allow user to read errors detected by the
hardware, and clear the logged errors.
Power management (dfl_fme_power hwmon)
power management hwmon sysfs interfaces allow user to read power management
information (power consumption, thresholds, threshold status, limits, etc.)
and configure power thresholds for different throttling levels.
Thermal management (dfl_fme_thermal hwmon)
thermal management hwmon sysfs interfaces allow user to read thermal
management information (current temperature, thresholds, threshold status,
etc.).
FIU - PORT
==========

2
drivers/fpga/Kconfig
View file

@ -156,7 +156,7 @@ config FPGA_DFL
config FPGA_DFL_FME
tristate "FPGA DFL FME Driver"
depends on FPGA_DFL
depends on FPGA_DFL && HWMON
help
The FPGA Management Engine (FME) is a feature device implemented
under Device Feature List (DFL) framework. Select this option to

385
drivers/fpga/dfl-fme-main.c
View file

@ -14,6 +14,8 @@
* Henry Mitchel <henry.mitchel@intel.com>
*/
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/uaccess.h>
@ -181,6 +183,381 @@ static const struct dfl_feature_ops fme_hdr_ops = {
.ioctl = fme_hdr_ioctl,
};
#define FME_THERM_THRESHOLD 0x8
#define TEMP_THRESHOLD1 GENMASK_ULL(6, 0)
#define TEMP_THRESHOLD1_EN BIT_ULL(7)
#define TEMP_THRESHOLD2 GENMASK_ULL(14, 8)
#define TEMP_THRESHOLD2_EN BIT_ULL(15)
#define TRIP_THRESHOLD GENMASK_ULL(30, 24)
#define TEMP_THRESHOLD1_STATUS BIT_ULL(32) /* threshold1 reached */
#define TEMP_THRESHOLD2_STATUS BIT_ULL(33) /* threshold2 reached */
/* threshold1 policy: 0 - AP2 (90% throttle) / 1 - AP1 (50% throttle) */
#define TEMP_THRESHOLD1_POLICY BIT_ULL(44)
#define FME_THERM_RDSENSOR_FMT1 0x10
#define FPGA_TEMPERATURE GENMASK_ULL(6, 0)
#define FME_THERM_CAP 0x20
#define THERM_NO_THROTTLE BIT_ULL(0)
#define MD_PRE_DEG
static bool fme_thermal_throttle_support(void __iomem *base)
{
u64 v = readq(base + FME_THERM_CAP);
return FIELD_GET(THERM_NO_THROTTLE, v) ? false : true;
}
static umode_t thermal_hwmon_attrs_visible(const void *drvdata,
enum hwmon_sensor_types type,
u32 attr, int channel)
{
const struct dfl_feature *feature = drvdata;
/* temperature is always supported, and check hardware cap for others */
if (attr == hwmon_temp_input)
return 0444;
return fme_thermal_throttle_support(feature->ioaddr) ? 0444 : 0;
}
static int thermal_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long *val)
{
struct dfl_feature *feature = dev_get_drvdata(dev);
u64 v;
switch (attr) {
case hwmon_temp_input:
v = readq(feature->ioaddr + FME_THERM_RDSENSOR_FMT1);
*val = (long)(FIELD_GET(FPGA_TEMPERATURE, v) * 1000);
break;
case hwmon_temp_max:
v = readq(feature->ioaddr + FME_THERM_THRESHOLD);
*val = (long)(FIELD_GET(TEMP_THRESHOLD1, v) * 1000);
break;
case hwmon_temp_crit:
v = readq(feature->ioaddr + FME_THERM_THRESHOLD);
*val = (long)(FIELD_GET(TEMP_THRESHOLD2, v) * 1000);
break;
case hwmon_temp_emergency:
v = readq(feature->ioaddr + FME_THERM_THRESHOLD);
*val = (long)(FIELD_GET(TRIP_THRESHOLD, v) * 1000);
break;
case hwmon_temp_max_alarm:
v = readq(feature->ioaddr + FME_THERM_THRESHOLD);
*val = (long)FIELD_GET(TEMP_THRESHOLD1_STATUS, v);
break;
case hwmon_temp_crit_alarm:
v = readq(feature->ioaddr + FME_THERM_THRESHOLD);
*val = (long)FIELD_GET(TEMP_THRESHOLD2_STATUS, v);
break;
default:
return -EOPNOTSUPP;
}
return 0;
}
static const struct hwmon_ops thermal_hwmon_ops = {
.is_visible = thermal_hwmon_attrs_visible,
.read = thermal_hwmon_read,
};
static const struct hwmon_channel_info *thermal_hwmon_info[] = {
HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT | HWMON_T_EMERGENCY |
HWMON_T_MAX | HWMON_T_MAX_ALARM |
HWMON_T_CRIT | HWMON_T_CRIT_ALARM),
NULL
};
static const struct hwmon_chip_info thermal_hwmon_chip_info = {
.ops = &thermal_hwmon_ops,
.info = thermal_hwmon_info,
};
static ssize_t temp1_max_policy_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct dfl_feature *feature = dev_get_drvdata(dev);
u64 v;
v = readq(feature->ioaddr + FME_THERM_THRESHOLD);
return sprintf(buf, "%u\n",
(unsigned int)FIELD_GET(TEMP_THRESHOLD1_POLICY, v));
}
static DEVICE_ATTR_RO(temp1_max_policy);
static struct attribute *thermal_extra_attrs[] = {
&dev_attr_temp1_max_policy.attr,
NULL,
};
static umode_t thermal_extra_attrs_visible(struct kobject *kobj,
struct attribute *attr, int index)
{
struct device *dev = kobj_to_dev(kobj);
struct dfl_feature *feature = dev_get_drvdata(dev);
return fme_thermal_throttle_support(feature->ioaddr) ? attr->mode : 0;
}
static const struct attribute_group thermal_extra_group = {
.attrs = thermal_extra_attrs,
.is_visible = thermal_extra_attrs_visible,
};
__ATTRIBUTE_GROUPS(thermal_extra);
static int fme_thermal_mgmt_init(struct platform_device *pdev,
struct dfl_feature *feature)
{
struct device *hwmon;
/*
* create hwmon to allow userspace monitoring temperature and other
* threshold information.
*
* temp1_input -> FPGA device temperature
* temp1_max -> hardware threshold 1 -> 50% or 90% throttling
* temp1_crit -> hardware threshold 2 -> 100% throttling
* temp1_emergency -> hardware trip_threshold to shutdown FPGA
* temp1_max_alarm -> hardware threshold 1 alarm
* temp1_crit_alarm -> hardware threshold 2 alarm
*
* create device specific sysfs interfaces, e.g. read temp1_max_policy
* to understand the actual hardware throttling action (50% vs 90%).
*
* If hardware doesn't support automatic throttling per thresholds,
* then all above sysfs interfaces are not visible except temp1_input
* for temperature.
*/
hwmon = devm_hwmon_device_register_with_info(&pdev->dev,
"dfl_fme_thermal", feature,
&thermal_hwmon_chip_info,
thermal_extra_groups);
if (IS_ERR(hwmon)) {
dev_err(&pdev->dev, "Fail to register thermal hwmon\n");
return PTR_ERR(hwmon);
}
return 0;
}
static const struct dfl_feature_id fme_thermal_mgmt_id_table[] = {
{.id = FME_FEATURE_ID_THERMAL_MGMT,},
{0,}
};
static const struct dfl_feature_ops fme_thermal_mgmt_ops = {
.init = fme_thermal_mgmt_init,
};
#define FME_PWR_STATUS 0x8
#define FME_LATENCY_TOLERANCE BIT_ULL(18)
#define PWR_CONSUMED GENMASK_ULL(17, 0)
#define FME_PWR_THRESHOLD 0x10
#define PWR_THRESHOLD1 GENMASK_ULL(6, 0) /* in Watts */
#define PWR_THRESHOLD2 GENMASK_ULL(14, 8) /* in Watts */
#define PWR_THRESHOLD_MAX 0x7f /* in Watts */
#define PWR_THRESHOLD1_STATUS BIT_ULL(16)
#define PWR_THRESHOLD2_STATUS BIT_ULL(17)
#define FME_PWR_XEON_LIMIT 0x18
#define XEON_PWR_LIMIT GENMASK_ULL(14, 0) /* in 0.1 Watts */
#define XEON_PWR_EN BIT_ULL(15)
#define FME_PWR_FPGA_LIMIT 0x20
#define FPGA_PWR_LIMIT GENMASK_ULL(14, 0) /* in 0.1 Watts */
#define FPGA_PWR_EN BIT_ULL(15)
static int power_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long *val)
{
struct dfl_feature *feature = dev_get_drvdata(dev);
u64 v;
switch (attr) {
case hwmon_power_input:
v = readq(feature->ioaddr + FME_PWR_STATUS);
*val = (long)(FIELD_GET(PWR_CONSUMED, v) * 1000000);
break;
case hwmon_power_max:
v = readq(feature->ioaddr + FME_PWR_THRESHOLD);
*val = (long)(FIELD_GET(PWR_THRESHOLD1, v) * 1000000);
break;
case hwmon_power_crit:
v = readq(feature->ioaddr + FME_PWR_THRESHOLD);
*val = (long)(FIELD_GET(PWR_THRESHOLD2, v) * 1000000);
break;
case hwmon_power_max_alarm:
v = readq(feature->ioaddr + FME_PWR_THRESHOLD);
*val = (long)FIELD_GET(PWR_THRESHOLD1_STATUS, v);
break;
case hwmon_power_crit_alarm:
v = readq(feature->ioaddr + FME_PWR_THRESHOLD);
*val = (long)FIELD_GET(PWR_THRESHOLD2_STATUS, v);
break;
default:
return -EOPNOTSUPP;
}
return 0;
}
static int power_hwmon_write(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long val)
{
struct dfl_feature_platform_data *pdata = dev_get_platdata(dev->parent);
struct dfl_feature *feature = dev_get_drvdata(dev);
int ret = 0;
u64 v;
val = clamp_val(val / 1000000, 0, PWR_THRESHOLD_MAX);
mutex_lock(&pdata->lock);
switch (attr) {
case hwmon_power_max:
v = readq(feature->ioaddr + FME_PWR_THRESHOLD);
v &= ~PWR_THRESHOLD1;
v |= FIELD_PREP(PWR_THRESHOLD1, val);
writeq(v, feature->ioaddr + FME_PWR_THRESHOLD);
break;
case hwmon_power_crit:
v = readq(feature->ioaddr + FME_PWR_THRESHOLD);
v &= ~PWR_THRESHOLD2;
v |= FIELD_PREP(PWR_THRESHOLD2, val);
writeq(v, feature->ioaddr + FME_PWR_THRESHOLD);
break;
default:
ret = -EOPNOTSUPP;
break;
}
mutex_unlock(&pdata->lock);
return ret;
}
static umode_t power_hwmon_attrs_visible(const void *drvdata,
enum hwmon_sensor_types type,
u32 attr, int channel)
{
switch (attr) {
case hwmon_power_input:
case hwmon_power_max_alarm:
case hwmon_power_crit_alarm:
return 0444;
case hwmon_power_max:
case hwmon_power_crit:
return 0644;
}
return 0;
}
static const struct hwmon_ops power_hwmon_ops = {
.is_visible = power_hwmon_attrs_visible,
.read = power_hwmon_read,
.write = power_hwmon_write,
};
static const struct hwmon_channel_info *power_hwmon_info[] = {
HWMON_CHANNEL_INFO(power, HWMON_P_INPUT |
HWMON_P_MAX | HWMON_P_MAX_ALARM |
HWMON_P_CRIT | HWMON_P_CRIT_ALARM),
NULL
};
static const struct hwmon_chip_info power_hwmon_chip_info = {
.ops = &power_hwmon_ops,
.info = power_hwmon_info,
};
static ssize_t power1_xeon_limit_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct dfl_feature *feature = dev_get_drvdata(dev);
u16 xeon_limit = 0;
u64 v;
v = readq(feature->ioaddr + FME_PWR_XEON_LIMIT);
if (FIELD_GET(XEON_PWR_EN, v))
xeon_limit = FIELD_GET(XEON_PWR_LIMIT, v);
return sprintf(buf, "%u\n", xeon_limit * 100000);
}
static ssize_t power1_fpga_limit_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct dfl_feature *feature = dev_get_drvdata(dev);
u16 fpga_limit = 0;
u64 v;
v = readq(feature->ioaddr + FME_PWR_FPGA_LIMIT);
if (FIELD_GET(FPGA_PWR_EN, v))
fpga_limit = FIELD_GET(FPGA_PWR_LIMIT, v);
return sprintf(buf, "%u\n", fpga_limit * 100000);
}
static ssize_t power1_ltr_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct dfl_feature *feature = dev_get_drvdata(dev);
u64 v;
v = readq(feature->ioaddr + FME_PWR_STATUS);
return sprintf(buf, "%u\n",
(unsigned int)FIELD_GET(FME_LATENCY_TOLERANCE, v));
}
static DEVICE_ATTR_RO(power1_xeon_limit);
static DEVICE_ATTR_RO(power1_fpga_limit);
static DEVICE_ATTR_RO(power1_ltr);
static struct attribute *power_extra_attrs[] = {
&dev_attr_power1_xeon_limit.attr,
&dev_attr_power1_fpga_limit.attr,
&dev_attr_power1_ltr.attr,
NULL
};
ATTRIBUTE_GROUPS(power_extra);
static int fme_power_mgmt_init(struct platform_device *pdev,
struct dfl_feature *feature)
{
struct device *hwmon;
hwmon = devm_hwmon_device_register_with_info(&pdev->dev,
"dfl_fme_power", feature,
&power_hwmon_chip_info,
power_extra_groups);
if (IS_ERR(hwmon)) {
dev_err(&pdev->dev, "Fail to register power hwmon\n");
return PTR_ERR(hwmon);
}
return 0;
}
static const struct dfl_feature_id fme_power_mgmt_id_table[] = {
{.id = FME_FEATURE_ID_POWER_MGMT,},
{0,}
};
static const struct dfl_feature_ops fme_power_mgmt_ops = {
.init = fme_power_mgmt_init,
};
static struct dfl_feature_driver fme_feature_drvs[] = {
{
.id_table = fme_hdr_id_table,
@ -194,6 +571,14 @@ static struct dfl_feature_driver fme_feature_drvs[] = {
.id_table = fme_global_err_id_table,
.ops = &fme_global_err_ops,
},
{
.id_table = fme_thermal_mgmt_id_table,
.ops = &fme_thermal_mgmt_ops,
},
{
.id_table = fme_power_mgmt_id_table,
.ops = &fme_power_mgmt_ops,
},
{
.ops = NULL,
},

4
drivers/fpga/zynq-fpga.c
View file

@ -578,10 +578,8 @@ static int zynq_fpga_probe(struct platform_device *pdev)
init_completion(&priv->dma_done);
priv->irq = platform_get_irq(pdev, 0);
if (priv->irq < 0) {
dev_err(dev, "No IRQ available\n");
if (priv->irq < 0)
return priv->irq;
}
priv->clk = devm_clk_get(dev, "ref_clk");
if (IS_ERR(priv->clk)) {