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Merge branch 'icc-sdx75' into icc-next 

Add interconnect driver support for SDX75 platform.

* icc-sdx75
  dt-bindings: interconnect: Add compatibles for SDX75
  interconnect: qcom: Add SDX75 interconnect provider driver

 Link: https://lore.kernel.org/r/1694614256-24109-1-git-send-email-quic_rohiagar@quicinc.com
 Signed-off-by: Georgi Djakov <djakov@kernel.org>anter a commit message to explain why this merge is necessary,
This commit is contained in:
Georgi Djakov 2023-10-10 12:33:10 +03:00
parent 9ee5214138 3642b4e5cb
commit bd35cbd721
6 changed files with 1409 additions and 0 deletions
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92
Documentation/devicetree/bindings/interconnect/qcom,sdx75-rpmh.yaml Normal file
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@ -0,0 +1,92 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/qcom,sdx75-rpmh.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm RPMh Network-On-Chip Interconnect on SDX75
maintainers:
- Rohit Agarwal <quic_rohiagar@quicinc.com>
description:
RPMh interconnect providers support system bandwidth requirements through
RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
able to communicate with the BCM through the Resource State Coordinator (RSC)
associated with each execution environment. Provider nodes must point to at
least one RPMh device child node pertaining to their RSC and each provider
can map to multiple RPMh resources.
properties:
compatible:
enum:
- qcom,sdx75-clk-virt
- qcom,sdx75-dc-noc
- qcom,sdx75-gem-noc
- qcom,sdx75-mc-virt
- qcom,sdx75-pcie-anoc
- qcom,sdx75-system-noc
'#interconnect-cells': true
reg:
maxItems: 1
clocks:
maxItems: 1
required:
- compatible
allOf:
- $ref: qcom,rpmh-common.yaml#
- if:
properties:
compatible:
contains:
enum:
- qcom,sdx75-clk-virt
- qcom,sdx75-mc-virt
then:
properties:
reg: false
else:
required:
- reg
- if:
properties:
compatible:
contains:
enum:
- qcom,sdx75-clk-virt
then:
properties:
clocks:
items:
- description: RPMH CC QPIC Clock
required:
- clocks
else:
properties:
clocks: false
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clk_virt: interconnect-0 {
compatible = "qcom,sdx75-clk-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
clocks = <&rpmhcc RPMH_QPIC_CLK>;
};
system_noc: interconnect@1640000 {
compatible = "qcom,sdx75-system-noc";
reg = <0x1640000 0x4b400>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};

9
drivers/interconnect/qcom/Kconfig
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@ -182,6 +182,15 @@ config INTERCONNECT_QCOM_SDX65
This is a driver for the Qualcomm Network-on-Chip on sdx65-based
platforms.
config INTERCONNECT_QCOM_SDX75
tristate "Qualcomm SDX75 interconnect driver"
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
help
This is a driver for the Qualcomm Network-on-Chip on sdx75-based
platforms.
config INTERCONNECT_QCOM_SM6350
tristate "Qualcomm SM6350 interconnect driver"
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE

2
drivers/interconnect/qcom/Makefile
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@ -23,6 +23,7 @@ qnoc-sdm670-objs := sdm670.o
qnoc-sdm845-objs := sdm845.o
qnoc-sdx55-objs := sdx55.o
qnoc-sdx65-objs := sdx65.o
qnoc-sdx75-objs := sdx75.o
qnoc-sm6350-objs := sm6350.o
qnoc-sm8150-objs := sm8150.o
qnoc-sm8250-objs := sm8250.o
@ -51,6 +52,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_SDM670) += qnoc-sdm670.o
obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o
obj-$(CONFIG_INTERCONNECT_QCOM_SDX55) += qnoc-sdx55.o
obj-$(CONFIG_INTERCONNECT_QCOM_SDX65) += qnoc-sdx65.o
obj-$(CONFIG_INTERCONNECT_QCOM_SDX75) += qnoc-sdx75.o
obj-$(CONFIG_INTERCONNECT_QCOM_SM6350) += qnoc-sm6350.o
obj-$(CONFIG_INTERCONNECT_QCOM_SM8150) += qnoc-sm8150.o
obj-$(CONFIG_INTERCONNECT_QCOM_SM8250) += qnoc-sm8250.o

1107
drivers/interconnect/qcom/sdx75.c Normal file
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97
drivers/interconnect/qcom/sdx75.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_SDX75_H
#define __DRIVERS_INTERCONNECT_QCOM_SDX75_H
#define SDX75_MASTER_ANOC_PCIE_GEM_NOC 0
#define SDX75_MASTER_ANOC_SNOC 1
#define SDX75_MASTER_APPSS_PROC 2
#define SDX75_MASTER_AUDIO 3
#define SDX75_MASTER_CNOC_DC_NOC 4
#define SDX75_MASTER_CRYPTO 5
#define SDX75_MASTER_EMAC_0 6
#define SDX75_MASTER_EMAC_1 7
#define SDX75_MASTER_GEM_NOC_CFG 8
#define SDX75_MASTER_GEM_NOC_CNOC 9
#define SDX75_MASTER_GEM_NOC_PCIE_SNOC 10
#define SDX75_MASTER_GIC 11
#define SDX75_MASTER_GIC_AHB 12
#define SDX75_MASTER_IPA 13
#define SDX75_MASTER_IPA_PCIE 14
#define SDX75_MASTER_LLCC 15
#define SDX75_MASTER_MSS_PROC 16
#define SDX75_MASTER_MVMSS 17
#define SDX75_MASTER_PCIE_0 18
#define SDX75_MASTER_PCIE_1 19
#define SDX75_MASTER_PCIE_2 20
#define SDX75_MASTER_PCIE_ANOC_CFG 21
#define SDX75_MASTER_PCIE_RSCC 22
#define SDX75_MASTER_QDSS_BAM 23
#define SDX75_MASTER_QDSS_ETR 24
#define SDX75_MASTER_QDSS_ETR_1 25
#define SDX75_MASTER_QPIC 26
#define SDX75_MASTER_QPIC_CORE 27
#define SDX75_MASTER_QUP_0 28
#define SDX75_MASTER_QUP_CORE_0 29
#define SDX75_MASTER_SDCC_1 30
#define SDX75_MASTER_SDCC_4 31
#define SDX75_MASTER_SNOC_CFG 32
#define SDX75_MASTER_SNOC_SF_MEM_NOC 33
#define SDX75_MASTER_SYS_TCU 34
#define SDX75_MASTER_USB3_0 35
#define SDX75_SLAVE_A1NOC_CFG 36
#define SDX75_SLAVE_ANOC_PCIE_GEM_NOC 37
#define SDX75_SLAVE_AUDIO 38
#define SDX75_SLAVE_CLK_CTL 39
#define SDX75_SLAVE_CRYPTO_0_CFG 40
#define SDX75_SLAVE_CNOC_MSS 41
#define SDX75_SLAVE_DDRSS_CFG 42
#define SDX75_SLAVE_EBI1 43
#define SDX75_SLAVE_ETH0_CFG 44
#define SDX75_SLAVE_ETH1_CFG 45
#define SDX75_SLAVE_GEM_NOC_CFG 46
#define SDX75_SLAVE_GEM_NOC_CNOC 47
#define SDX75_SLAVE_ICBDI_MVMSS_CFG 48
#define SDX75_SLAVE_IMEM 49
#define SDX75_SLAVE_IMEM_CFG 50
#define SDX75_SLAVE_IPA_CFG 51
#define SDX75_SLAVE_IPC_ROUTER_CFG 52
#define SDX75_SLAVE_LAGG_CFG 53
#define SDX75_SLAVE_LLCC 54
#define SDX75_SLAVE_MCCC_MASTER 55
#define SDX75_SLAVE_MEM_NOC_PCIE_SNOC 56
#define SDX75_SLAVE_PCIE_0 57
#define SDX75_SLAVE_PCIE_1 58
#define SDX75_SLAVE_PCIE_2 59
#define SDX75_SLAVE_PCIE_0_CFG 60
#define SDX75_SLAVE_PCIE_1_CFG 61
#define SDX75_SLAVE_PCIE_2_CFG 62
#define SDX75_SLAVE_PCIE_ANOC_CFG 63
#define SDX75_SLAVE_PCIE_RSC_CFG 64
#define SDX75_SLAVE_PDM 65
#define SDX75_SLAVE_PRNG 66
#define SDX75_SLAVE_QDSS_CFG 67
#define SDX75_SLAVE_QDSS_STM 68
#define SDX75_SLAVE_QPIC 69
#define SDX75_SLAVE_QPIC_CORE 70
#define SDX75_SLAVE_QUP_0 71
#define SDX75_SLAVE_QUP_CORE_0 72
#define SDX75_SLAVE_SDCC_1 73
#define SDX75_SLAVE_SDCC_4 74
#define SDX75_SLAVE_SERVICE_GEM_NOC 75
#define SDX75_SLAVE_SERVICE_PCIE_ANOC 76
#define SDX75_SLAVE_SERVICE_SNOC 77
#define SDX75_SLAVE_SNOC_CFG 78
#define SDX75_SLAVE_SNOC_GEM_NOC_SF 79
#define SDX75_SLAVE_SNOOP_BWMON 80
#define SDX75_SLAVE_SPMI_VGI_COEX 81
#define SDX75_SLAVE_TCSR 82
#define SDX75_SLAVE_TCU 83
#define SDX75_SLAVE_TLMM 84
#define SDX75_SLAVE_USB3 85
#define SDX75_SLAVE_USB3_PHY_CFG 86
#endif

102
include/dt-bindings/interconnect/qcom,sdx75.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDX75_H
#define __DT_BINDINGS_INTERCONNECT_QCOM_SDX75_H
#define MASTER_QPIC_CORE 0
#define MASTER_QUP_CORE_0 1
#define SLAVE_QPIC_CORE 2
#define SLAVE_QUP_CORE_0 3
#define MASTER_LLCC 0
#define SLAVE_EBI1 1
#define MASTER_CNOC_DC_NOC 0
#define SLAVE_LAGG_CFG 1
#define SLAVE_MCCC_MASTER 2
#define SLAVE_GEM_NOC_CFG 3
#define SLAVE_SNOOP_BWMON 4
#define MASTER_SYS_TCU 0
#define MASTER_APPSS_PROC 1
#define MASTER_GEM_NOC_CFG 2
#define MASTER_MSS_PROC 3
#define MASTER_ANOC_PCIE_GEM_NOC 4
#define MASTER_SNOC_SF_MEM_NOC 5
#define MASTER_GIC 6
#define MASTER_IPA_PCIE 7
#define SLAVE_GEM_NOC_CNOC 8
#define SLAVE_LLCC 9
#define SLAVE_MEM_NOC_PCIE_SNOC 10
#define SLAVE_SERVICE_GEM_NOC 11
#define MASTER_PCIE_0 0
#define MASTER_PCIE_1 1
#define MASTER_PCIE_2 2
#define SLAVE_ANOC_PCIE_GEM_NOC 3
#define MASTER_AUDIO 0
#define MASTER_GIC_AHB 1
#define MASTER_PCIE_RSCC 2
#define MASTER_QDSS_BAM 3
#define MASTER_QPIC 4
#define MASTER_QUP_0 5
#define MASTER_ANOC_SNOC 6
#define MASTER_GEM_NOC_CNOC 7
#define MASTER_GEM_NOC_PCIE_SNOC 8
#define MASTER_SNOC_CFG 9
#define MASTER_PCIE_ANOC_CFG 10
#define MASTER_CRYPTO 11
#define MASTER_IPA 12
#define MASTER_MVMSS 13
#define MASTER_EMAC_0 14
#define MASTER_EMAC_1 15
#define MASTER_QDSS_ETR 16
#define MASTER_QDSS_ETR_1 17
#define MASTER_SDCC_1 18
#define MASTER_SDCC_4 19
#define MASTER_USB3_0 20
#define SLAVE_ETH0_CFG 21
#define SLAVE_ETH1_CFG 22
#define SLAVE_AUDIO 23
#define SLAVE_CLK_CTL 24
#define SLAVE_CRYPTO_0_CFG 25
#define SLAVE_IMEM_CFG 26
#define SLAVE_IPA_CFG 27
#define SLAVE_IPC_ROUTER_CFG 28
#define SLAVE_CNOC_MSS 29
#define SLAVE_ICBDI_MVMSS_CFG 30
#define SLAVE_PCIE_0_CFG 31
#define SLAVE_PCIE_1_CFG 32
#define SLAVE_PCIE_2_CFG 33
#define SLAVE_PCIE_RSC_CFG 34
#define SLAVE_PDM 35
#define SLAVE_PRNG 36
#define SLAVE_QDSS_CFG 37
#define SLAVE_QPIC 38
#define SLAVE_QUP_0 39
#define SLAVE_SDCC_1 40
#define SLAVE_SDCC_4 41
#define SLAVE_SPMI_VGI_COEX 42
#define SLAVE_TCSR 43
#define SLAVE_TLMM 44
#define SLAVE_USB3 45
#define SLAVE_USB3_PHY_CFG 46
#define SLAVE_A1NOC_CFG 47
#define SLAVE_DDRSS_CFG 48
#define SLAVE_SNOC_GEM_NOC_SF 49
#define SLAVE_SNOC_CFG 50
#define SLAVE_PCIE_ANOC_CFG 51
#define SLAVE_IMEM 52
#define SLAVE_SERVICE_PCIE_ANOC 53
#define SLAVE_SERVICE_SNOC 54
#define SLAVE_PCIE_0 55
#define SLAVE_PCIE_1 56
#define SLAVE_PCIE_2 57
#define SLAVE_QDSS_STM 58
#define SLAVE_TCU 59
#endif