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Merge branch 'icc-sdx75' into icc-next
Add interconnect driver support for SDX75 platform. * icc-sdx75 dt-bindings: interconnect: Add compatibles for SDX75 interconnect: qcom: Add SDX75 interconnect provider driver Link: https://lore.kernel.org/r/1694614256-24109-1-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Georgi Djakov <djakov@kernel.org>anter a commit message to explain why this merge is necessary,
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commit
bd35cbd721
6 changed files with 1409 additions and 0 deletions
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interconnect/qcom,sdx75-rpmh.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm RPMh Network-On-Chip Interconnect on SDX75
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maintainers:
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- Rohit Agarwal <quic_rohiagar@quicinc.com>
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description:
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RPMh interconnect providers support system bandwidth requirements through
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RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
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able to communicate with the BCM through the Resource State Coordinator (RSC)
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associated with each execution environment. Provider nodes must point to at
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least one RPMh device child node pertaining to their RSC and each provider
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can map to multiple RPMh resources.
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properties:
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compatible:
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enum:
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- qcom,sdx75-clk-virt
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- qcom,sdx75-dc-noc
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- qcom,sdx75-gem-noc
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- qcom,sdx75-mc-virt
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- qcom,sdx75-pcie-anoc
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- qcom,sdx75-system-noc
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'#interconnect-cells': true
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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required:
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- compatible
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allOf:
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- $ref: qcom,rpmh-common.yaml#
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sdx75-clk-virt
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- qcom,sdx75-mc-virt
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then:
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properties:
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reg: false
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else:
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required:
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- reg
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sdx75-clk-virt
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then:
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properties:
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clocks:
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items:
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- description: RPMH CC QPIC Clock
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required:
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- clocks
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else:
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properties:
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clocks: false
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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clk_virt: interconnect-0 {
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compatible = "qcom,sdx75-clk-virt";
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#interconnect-cells = <2>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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clocks = <&rpmhcc RPMH_QPIC_CLK>;
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};
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system_noc: interconnect@1640000 {
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compatible = "qcom,sdx75-system-noc";
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reg = <0x1640000 0x4b400>;
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#interconnect-cells = <2>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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@ -182,6 +182,15 @@ config INTERCONNECT_QCOM_SDX65
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This is a driver for the Qualcomm Network-on-Chip on sdx65-based
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platforms.
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config INTERCONNECT_QCOM_SDX75
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tristate "Qualcomm SDX75 interconnect driver"
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depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
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select INTERCONNECT_QCOM_RPMH
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select INTERCONNECT_QCOM_BCM_VOTER
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help
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This is a driver for the Qualcomm Network-on-Chip on sdx75-based
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platforms.
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config INTERCONNECT_QCOM_SM6350
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tristate "Qualcomm SM6350 interconnect driver"
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depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
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@ -23,6 +23,7 @@ qnoc-sdm670-objs := sdm670.o
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qnoc-sdm845-objs := sdm845.o
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qnoc-sdx55-objs := sdx55.o
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qnoc-sdx65-objs := sdx65.o
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qnoc-sdx75-objs := sdx75.o
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qnoc-sm6350-objs := sm6350.o
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qnoc-sm8150-objs := sm8150.o
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qnoc-sm8250-objs := sm8250.o
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@ -51,6 +52,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_SDM670) += qnoc-sdm670.o
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obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o
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obj-$(CONFIG_INTERCONNECT_QCOM_SDX55) += qnoc-sdx55.o
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obj-$(CONFIG_INTERCONNECT_QCOM_SDX65) += qnoc-sdx65.o
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obj-$(CONFIG_INTERCONNECT_QCOM_SDX75) += qnoc-sdx75.o
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obj-$(CONFIG_INTERCONNECT_QCOM_SM6350) += qnoc-sm6350.o
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obj-$(CONFIG_INTERCONNECT_QCOM_SM8150) += qnoc-sm8150.o
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obj-$(CONFIG_INTERCONNECT_QCOM_SM8250) += qnoc-sm8250.o
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1107
drivers/interconnect/qcom/sdx75.c
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1107
drivers/interconnect/qcom/sdx75.c
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File diff suppressed because it is too large
Load diff
97
drivers/interconnect/qcom/sdx75.h
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97
drivers/interconnect/qcom/sdx75.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef __DRIVERS_INTERCONNECT_QCOM_SDX75_H
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#define __DRIVERS_INTERCONNECT_QCOM_SDX75_H
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#define SDX75_MASTER_ANOC_PCIE_GEM_NOC 0
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#define SDX75_MASTER_ANOC_SNOC 1
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#define SDX75_MASTER_APPSS_PROC 2
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#define SDX75_MASTER_AUDIO 3
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#define SDX75_MASTER_CNOC_DC_NOC 4
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#define SDX75_MASTER_CRYPTO 5
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#define SDX75_MASTER_EMAC_0 6
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#define SDX75_MASTER_EMAC_1 7
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#define SDX75_MASTER_GEM_NOC_CFG 8
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#define SDX75_MASTER_GEM_NOC_CNOC 9
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#define SDX75_MASTER_GEM_NOC_PCIE_SNOC 10
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#define SDX75_MASTER_GIC 11
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#define SDX75_MASTER_GIC_AHB 12
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#define SDX75_MASTER_IPA 13
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#define SDX75_MASTER_IPA_PCIE 14
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#define SDX75_MASTER_LLCC 15
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#define SDX75_MASTER_MSS_PROC 16
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#define SDX75_MASTER_MVMSS 17
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#define SDX75_MASTER_PCIE_0 18
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#define SDX75_MASTER_PCIE_1 19
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#define SDX75_MASTER_PCIE_2 20
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#define SDX75_MASTER_PCIE_ANOC_CFG 21
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#define SDX75_MASTER_PCIE_RSCC 22
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#define SDX75_MASTER_QDSS_BAM 23
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#define SDX75_MASTER_QDSS_ETR 24
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#define SDX75_MASTER_QDSS_ETR_1 25
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#define SDX75_MASTER_QPIC 26
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#define SDX75_MASTER_QPIC_CORE 27
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#define SDX75_MASTER_QUP_0 28
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#define SDX75_MASTER_QUP_CORE_0 29
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#define SDX75_MASTER_SDCC_1 30
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#define SDX75_MASTER_SDCC_4 31
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#define SDX75_MASTER_SNOC_CFG 32
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#define SDX75_MASTER_SNOC_SF_MEM_NOC 33
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#define SDX75_MASTER_SYS_TCU 34
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#define SDX75_MASTER_USB3_0 35
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#define SDX75_SLAVE_A1NOC_CFG 36
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#define SDX75_SLAVE_ANOC_PCIE_GEM_NOC 37
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#define SDX75_SLAVE_AUDIO 38
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#define SDX75_SLAVE_CLK_CTL 39
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#define SDX75_SLAVE_CRYPTO_0_CFG 40
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#define SDX75_SLAVE_CNOC_MSS 41
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#define SDX75_SLAVE_DDRSS_CFG 42
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#define SDX75_SLAVE_EBI1 43
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#define SDX75_SLAVE_ETH0_CFG 44
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#define SDX75_SLAVE_ETH1_CFG 45
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#define SDX75_SLAVE_GEM_NOC_CFG 46
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#define SDX75_SLAVE_GEM_NOC_CNOC 47
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#define SDX75_SLAVE_ICBDI_MVMSS_CFG 48
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#define SDX75_SLAVE_IMEM 49
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#define SDX75_SLAVE_IMEM_CFG 50
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#define SDX75_SLAVE_IPA_CFG 51
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#define SDX75_SLAVE_IPC_ROUTER_CFG 52
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#define SDX75_SLAVE_LAGG_CFG 53
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#define SDX75_SLAVE_LLCC 54
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#define SDX75_SLAVE_MCCC_MASTER 55
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#define SDX75_SLAVE_MEM_NOC_PCIE_SNOC 56
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#define SDX75_SLAVE_PCIE_0 57
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#define SDX75_SLAVE_PCIE_1 58
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#define SDX75_SLAVE_PCIE_2 59
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#define SDX75_SLAVE_PCIE_0_CFG 60
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#define SDX75_SLAVE_PCIE_1_CFG 61
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#define SDX75_SLAVE_PCIE_2_CFG 62
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#define SDX75_SLAVE_PCIE_ANOC_CFG 63
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#define SDX75_SLAVE_PCIE_RSC_CFG 64
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#define SDX75_SLAVE_PDM 65
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#define SDX75_SLAVE_PRNG 66
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#define SDX75_SLAVE_QDSS_CFG 67
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#define SDX75_SLAVE_QDSS_STM 68
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#define SDX75_SLAVE_QPIC 69
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#define SDX75_SLAVE_QPIC_CORE 70
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#define SDX75_SLAVE_QUP_0 71
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#define SDX75_SLAVE_QUP_CORE_0 72
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#define SDX75_SLAVE_SDCC_1 73
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#define SDX75_SLAVE_SDCC_4 74
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#define SDX75_SLAVE_SERVICE_GEM_NOC 75
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#define SDX75_SLAVE_SERVICE_PCIE_ANOC 76
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#define SDX75_SLAVE_SERVICE_SNOC 77
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#define SDX75_SLAVE_SNOC_CFG 78
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#define SDX75_SLAVE_SNOC_GEM_NOC_SF 79
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#define SDX75_SLAVE_SNOOP_BWMON 80
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#define SDX75_SLAVE_SPMI_VGI_COEX 81
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#define SDX75_SLAVE_TCSR 82
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#define SDX75_SLAVE_TCU 83
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#define SDX75_SLAVE_TLMM 84
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#define SDX75_SLAVE_USB3 85
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#define SDX75_SLAVE_USB3_PHY_CFG 86
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#endif
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102
include/dt-bindings/interconnect/qcom,sdx75.h
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102
include/dt-bindings/interconnect/qcom,sdx75.h
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/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */
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/*
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* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDX75_H
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#define __DT_BINDINGS_INTERCONNECT_QCOM_SDX75_H
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#define MASTER_QPIC_CORE 0
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#define MASTER_QUP_CORE_0 1
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#define SLAVE_QPIC_CORE 2
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#define SLAVE_QUP_CORE_0 3
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#define MASTER_LLCC 0
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#define SLAVE_EBI1 1
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#define MASTER_CNOC_DC_NOC 0
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#define SLAVE_LAGG_CFG 1
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#define SLAVE_MCCC_MASTER 2
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#define SLAVE_GEM_NOC_CFG 3
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#define SLAVE_SNOOP_BWMON 4
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#define MASTER_SYS_TCU 0
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#define MASTER_APPSS_PROC 1
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#define MASTER_GEM_NOC_CFG 2
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#define MASTER_MSS_PROC 3
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#define MASTER_ANOC_PCIE_GEM_NOC 4
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#define MASTER_SNOC_SF_MEM_NOC 5
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#define MASTER_GIC 6
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#define MASTER_IPA_PCIE 7
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#define SLAVE_GEM_NOC_CNOC 8
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#define SLAVE_LLCC 9
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#define SLAVE_MEM_NOC_PCIE_SNOC 10
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#define SLAVE_SERVICE_GEM_NOC 11
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#define MASTER_PCIE_0 0
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#define MASTER_PCIE_1 1
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#define MASTER_PCIE_2 2
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#define SLAVE_ANOC_PCIE_GEM_NOC 3
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#define MASTER_AUDIO 0
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#define MASTER_GIC_AHB 1
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#define MASTER_PCIE_RSCC 2
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#define MASTER_QDSS_BAM 3
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#define MASTER_QPIC 4
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#define MASTER_QUP_0 5
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#define MASTER_ANOC_SNOC 6
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#define MASTER_GEM_NOC_CNOC 7
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#define MASTER_GEM_NOC_PCIE_SNOC 8
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#define MASTER_SNOC_CFG 9
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#define MASTER_PCIE_ANOC_CFG 10
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#define MASTER_CRYPTO 11
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#define MASTER_IPA 12
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#define MASTER_MVMSS 13
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#define MASTER_EMAC_0 14
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#define MASTER_EMAC_1 15
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#define MASTER_QDSS_ETR 16
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#define MASTER_QDSS_ETR_1 17
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#define MASTER_SDCC_1 18
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#define MASTER_SDCC_4 19
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#define MASTER_USB3_0 20
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#define SLAVE_ETH0_CFG 21
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#define SLAVE_ETH1_CFG 22
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#define SLAVE_AUDIO 23
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#define SLAVE_CLK_CTL 24
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#define SLAVE_CRYPTO_0_CFG 25
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#define SLAVE_IMEM_CFG 26
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#define SLAVE_IPA_CFG 27
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#define SLAVE_IPC_ROUTER_CFG 28
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#define SLAVE_CNOC_MSS 29
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#define SLAVE_ICBDI_MVMSS_CFG 30
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#define SLAVE_PCIE_0_CFG 31
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#define SLAVE_PCIE_1_CFG 32
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#define SLAVE_PCIE_2_CFG 33
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#define SLAVE_PCIE_RSC_CFG 34
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#define SLAVE_PDM 35
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#define SLAVE_PRNG 36
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#define SLAVE_QDSS_CFG 37
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#define SLAVE_QPIC 38
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#define SLAVE_QUP_0 39
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#define SLAVE_SDCC_1 40
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#define SLAVE_SDCC_4 41
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#define SLAVE_SPMI_VGI_COEX 42
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#define SLAVE_TCSR 43
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#define SLAVE_TLMM 44
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#define SLAVE_USB3 45
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#define SLAVE_USB3_PHY_CFG 46
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#define SLAVE_A1NOC_CFG 47
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#define SLAVE_DDRSS_CFG 48
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#define SLAVE_SNOC_GEM_NOC_SF 49
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#define SLAVE_SNOC_CFG 50
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#define SLAVE_PCIE_ANOC_CFG 51
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#define SLAVE_IMEM 52
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#define SLAVE_SERVICE_PCIE_ANOC 53
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#define SLAVE_SERVICE_SNOC 54
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#define SLAVE_PCIE_0 55
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#define SLAVE_PCIE_1 56
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#define SLAVE_PCIE_2 57
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#define SLAVE_QDSS_STM 58
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#define SLAVE_TCU 59
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#endif
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