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ASoC: rsnd: enable clk_i approximate rate usage
Basically Renesas sound ADG is assuming that it has accurately divisible input clock. But sometimes / some board might not have it. The clk_i from CPG is used for such case. It can't calculate accurate division, but can be used as approximate rate. This patch enable clk_i for such case. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Adnan Ali <adnan.ali@bp.renesas.com> Tested-by: Vincenzo De Michele <vincenzo.michele@davinci.de> Tested-by: Patrick Keil <patrick.keil@conti-engineering.com> Link: https://lore.kernel.org/r/87msyizlfd.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Mark Brown <broonie@kernel.org>
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1 changed files with 36 additions and 0 deletions
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@ -491,6 +491,7 @@ static int rsnd_adg_get_clkout(struct rsnd_priv *priv)
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unsigned long req_Hz[ADG_HZ_SIZE];
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int clkout_size;
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int i, req_size;
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int approximate = 0;
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const char *parent_clk_name = NULL;
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const char * const *clkout_name;
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int brg_table[] = {
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@ -537,6 +538,26 @@ static int rsnd_adg_get_clkout(struct rsnd_priv *priv)
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* rsnd_adg_ssi_clk_try_start()
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* rsnd_ssi_master_clk_start()
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*/
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/*
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* [APPROXIMATE]
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*
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* clk_i (internal clock) can't create accurate rate, it will be approximate rate.
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*
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* <Note>
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*
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* clk_i needs x2 of required maximum rate.
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* see
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* - Minimum division of BRRA/BRRB
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* - rsnd_ssi_clk_query()
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*
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* Sample Settings for TDM 8ch, 32bit width
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*
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* 8(ch) x 32(bit) x 44100(Hz) x 2<Note> = 22579200
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* 8(ch) x 32(bit) x 48000(Hz) x 2<Note> = 24576000
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*
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* clock-frequency = <22579200 24576000>;
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*/
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for_each_rsnd_clkin(clk, adg, i) {
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rate = clk_get_rate(clk);
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@ -544,6 +565,10 @@ static int rsnd_adg_get_clkout(struct rsnd_priv *priv)
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continue;
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/* BRGA */
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if (i == CLKI)
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/* see [APPROXIMATE] */
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rate = (clk_get_rate(clk) / req_Hz[ADG_HZ_441]) * req_Hz[ADG_HZ_441];
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if (!adg->brg_rate[ADG_HZ_441] && (0 == rate % 44100)) {
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div = 6;
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if (req_Hz[ADG_HZ_441])
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@ -555,10 +580,16 @@ static int rsnd_adg_get_clkout(struct rsnd_priv *priv)
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ckr |= brg_table[i] << 20;
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if (req_Hz[ADG_HZ_441])
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parent_clk_name = __clk_get_name(clk);
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if (i == CLKI)
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approximate = 1;
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}
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}
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/* BRGB */
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if (i == CLKI)
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/* see [APPROXIMATE] */
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rate = (clk_get_rate(clk) / req_Hz[ADG_HZ_48]) * req_Hz[ADG_HZ_48];
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if (!adg->brg_rate[ADG_HZ_48] && (0 == rate % 48000)) {
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div = 6;
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if (req_Hz[ADG_HZ_48])
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@ -570,10 +601,15 @@ static int rsnd_adg_get_clkout(struct rsnd_priv *priv)
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ckr |= brg_table[i] << 16;
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if (req_Hz[ADG_HZ_48])
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parent_clk_name = __clk_get_name(clk);
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if (i == CLKI)
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approximate = 1;
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}
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}
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}
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if (approximate)
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dev_info(dev, "It uses CLK_I as approximate rate");
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clkout_name = clkout_name_gen2;
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clkout_size = ARRAY_SIZE(clkout_name_gen2);
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if (rsnd_is_gen4(priv))
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