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nommu: Do not set PRRR and NMRR in proc-v7.S if !MMU

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ARMv7-R profile CPUs do not have these registers.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
Catalin Marinas 2009-07-24 12:35:06 +01:00
parent 8bdca0ac2b
commit bdaaaec397
1 changed files with 1 additions and 1 deletions
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2
arch/arm/mm/proc-v7.S
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@ -234,7 +234,6 @@ __v7_setup:
mcr p15, 0, r4, c2, c0, 1 @ load TTB1 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
mov r10, #0x1f @ domains 0, 1 = manager mov r10, #0x1f @ domains 0, 1 = manager
mcr p15, 0, r10, c3, c0, 0 @ load domain access register mcr p15, 0, r10, c3, c0, 0 @ load domain access register
#endif
/* /*
* Memory region attributes with SCTLR.TRE=1 * Memory region attributes with SCTLR.TRE=1
* *
@ -267,6 +266,7 @@ __v7_setup:
ldr r6, =0x40e040e0 @ NMRR ldr r6, =0x40e040e0 @ NMRR
mcr p15, 0, r5, c10, c2, 0 @ write PRRR mcr p15, 0, r5, c10, c2, 0 @ write PRRR
mcr p15, 0, r6, c10, c2, 1 @ write NMRR mcr p15, 0, r6, c10, c2, 1 @ write NMRR
#endif
adr r5, v7_crval adr r5, v7_crval
ldmia r5, {r5, r6} ldmia r5, {r5, r6}
#ifdef CONFIG_CPU_ENDIAN_BE8 #ifdef CONFIG_CPU_ENDIAN_BE8