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nommu: Do not set PRRR and NMRR in proc-v7.S if !MMU
ARMv7-R profile CPUs do not have these registers. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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1 changed files with 1 additions and 1 deletions
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@ -234,7 +234,6 @@ __v7_setup:
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mcr p15, 0, r4, c2, c0, 1 @ load TTB1
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mcr p15, 0, r4, c2, c0, 1 @ load TTB1
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mov r10, #0x1f @ domains 0, 1 = manager
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mov r10, #0x1f @ domains 0, 1 = manager
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mcr p15, 0, r10, c3, c0, 0 @ load domain access register
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mcr p15, 0, r10, c3, c0, 0 @ load domain access register
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#endif
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/*
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/*
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* Memory region attributes with SCTLR.TRE=1
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* Memory region attributes with SCTLR.TRE=1
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*
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*
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@ -267,6 +266,7 @@ __v7_setup:
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ldr r6, =0x40e040e0 @ NMRR
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ldr r6, =0x40e040e0 @ NMRR
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mcr p15, 0, r5, c10, c2, 0 @ write PRRR
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mcr p15, 0, r5, c10, c2, 0 @ write PRRR
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mcr p15, 0, r6, c10, c2, 1 @ write NMRR
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mcr p15, 0, r6, c10, c2, 1 @ write NMRR
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#endif
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adr r5, v7_crval
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adr r5, v7_crval
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ldmia r5, {r5, r6}
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ldmia r5, {r5, r6}
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#ifdef CONFIG_CPU_ENDIAN_BE8
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#ifdef CONFIG_CPU_ENDIAN_BE8
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