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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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platform/x86: mlx-platform: Add support for new system type
Add support for new Mellanox system types of basic class VMOD0009, containing Mellanox systems equipped with the switch devices Spectrum 1 (32x100GbE Ethernet switch) and Switch-IB/Switch-IB2 (36x100Gbe InfiniBand switch). These are the Top of the Rack system, equipped with Mellanox Comex card. Signed-off-by: Vadim Pasternak <vadimp@mellanox.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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1 changed files with 238 additions and 1 deletions
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@ -48,6 +48,8 @@
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#define MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET 0x41
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#define MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET 0x42
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#define MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET 0x43
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#define MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET 0x44
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#define MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET 0x45
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#define MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET 0x50
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#define MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET 0x51
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#define MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET 0x52
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@ -93,6 +95,7 @@
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#define MLXPLAT_CPLD_LPC_IO_RANGE 0x100
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#define MLXPLAT_CPLD_LPC_I2C_CH1_OFF 0xdb
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#define MLXPLAT_CPLD_LPC_I2C_CH2_OFF 0xda
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#define MLXPLAT_CPLD_LPC_I2C_CH3_OFF 0xdc
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#define MLXPLAT_CPLD_LPC_PIO_OFFSET 0x10000UL
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#define MLXPLAT_CPLD_LPC_REG1 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \
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@ -101,6 +104,9 @@
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#define MLXPLAT_CPLD_LPC_REG2 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \
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MLXPLAT_CPLD_LPC_I2C_CH2_OFF) | \
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MLXPLAT_CPLD_LPC_PIO_OFFSET)
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#define MLXPLAT_CPLD_LPC_REG3 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \
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MLXPLAT_CPLD_LPC_I2C_CH3_OFF) | \
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MLXPLAT_CPLD_LPC_PIO_OFFSET)
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/* Masks for aggregation, psu, pwr and fan event in CPLD related registers. */
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#define MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF 0x04
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@ -124,11 +130,18 @@
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#define MLXPLAT_CPLD_LED_HI_NIBBLE_MASK GENMASK(3, 0)
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#define MLXPLAT_CPLD_VOLTREG_UPD_MASK GENMASK(5, 4)
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/* Masks for aggregation for comex carriers */
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#define MLXPLAT_CPLD_AGGR_MASK_CARRIER BIT(1)
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#define MLXPLAT_CPLD_AGGR_MASK_CARR_DEF (MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF | \
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MLXPLAT_CPLD_AGGR_MASK_CARRIER)
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#define MLXPLAT_CPLD_LOW_AGGRCX_MASK 0xc1
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/* Default I2C parent bus number */
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#define MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR 1
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/* Maximum number of possible physical buses equipped on system */
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#define MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM 16
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#define MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM 24
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/* Number of channels in group */
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#define MLXPLAT_CPLD_GRP_CHNL_NUM 8
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@ -136,9 +149,10 @@
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/* Start channel numbers */
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#define MLXPLAT_CPLD_CH1 2
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#define MLXPLAT_CPLD_CH2 10
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#define MLXPLAT_CPLD_CH3 18
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/* Number of LPC attached MUX platform devices */
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#define MLXPLAT_CPLD_LPC_MUX_DEVS 2
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#define MLXPLAT_CPLD_LPC_MUX_DEVS 3
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/* Hotplug devices adapter numbers */
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#define MLXPLAT_CPLD_NR_NONE -1
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@ -244,6 +258,35 @@ static int mlxplat_max_adap_num;
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static int mlxplat_mux_num;
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static struct i2c_mux_reg_platform_data *mlxplat_mux_data;
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/* Platform extended mux data */
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static struct i2c_mux_reg_platform_data mlxplat_extended_mux_data[] = {
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{
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.parent = 1,
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.base_nr = MLXPLAT_CPLD_CH1,
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.write_only = 1,
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.reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1,
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.reg_size = 1,
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.idle_in_use = 1,
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},
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{
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.parent = 1,
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.base_nr = MLXPLAT_CPLD_CH2,
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.write_only = 1,
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.reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG3,
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.reg_size = 1,
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.idle_in_use = 1,
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},
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{
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.parent = 1,
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.base_nr = MLXPLAT_CPLD_CH3,
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.write_only = 1,
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.reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2,
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.reg_size = 1,
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.idle_in_use = 1,
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},
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};
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/* Platform hotplug devices */
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static struct i2c_board_info mlxplat_mlxcpld_psu[] = {
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{
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@ -287,6 +330,22 @@ static struct i2c_board_info mlxplat_mlxcpld_fan[] = {
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},
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};
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/* Platform hotplug comex carrier system family data */
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static struct mlxreg_core_data mlxplat_mlxcpld_comex_psu_items_data[] = {
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{
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.label = "psu1",
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.reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
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.mask = BIT(0),
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.hpdev.nr = MLXPLAT_CPLD_NR_NONE,
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},
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{
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.label = "psu2",
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.reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
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.mask = BIT(1),
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.hpdev.nr = MLXPLAT_CPLD_NR_NONE,
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},
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};
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/* Platform hotplug default data */
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static struct mlxreg_core_data mlxplat_mlxcpld_default_psu_items_data[] = {
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{
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@ -401,6 +460,45 @@ static struct mlxreg_core_item mlxplat_mlxcpld_default_items[] = {
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},
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};
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static struct mlxreg_core_item mlxplat_mlxcpld_comex_items[] = {
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{
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.data = mlxplat_mlxcpld_comex_psu_items_data,
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.aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER,
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.reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
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.mask = MLXPLAT_CPLD_PSU_MASK,
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.count = ARRAY_SIZE(mlxplat_mlxcpld_psu),
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.inversed = 1,
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.health = false,
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},
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{
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.data = mlxplat_mlxcpld_default_pwr_items_data,
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.aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER,
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.reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
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.mask = MLXPLAT_CPLD_PWR_MASK,
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.count = ARRAY_SIZE(mlxplat_mlxcpld_pwr),
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.inversed = 0,
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.health = false,
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},
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{
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.data = mlxplat_mlxcpld_default_fan_items_data,
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.aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER,
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.reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
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.mask = MLXPLAT_CPLD_FAN_MASK,
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.count = ARRAY_SIZE(mlxplat_mlxcpld_fan),
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.inversed = 1,
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.health = false,
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},
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{
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.data = mlxplat_mlxcpld_default_asic_items_data,
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.aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF,
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.reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
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.mask = MLXPLAT_CPLD_ASIC_MASK,
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.count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
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.inversed = 0,
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.health = true,
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},
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};
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static
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struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_data = {
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.items = mlxplat_mlxcpld_default_items,
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@ -411,6 +509,16 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_data = {
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.mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
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};
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static
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struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_comex_data = {
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.items = mlxplat_mlxcpld_comex_items,
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.counter = ARRAY_SIZE(mlxplat_mlxcpld_comex_items),
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.cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
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.mask = MLXPLAT_CPLD_AGGR_MASK_CARR_DEF,
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.cell_low = MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET,
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.mask_low = MLXPLAT_CPLD_LOW_AGGRCX_MASK,
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};
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static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_pwr_items_data[] = {
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{
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.label = "pwr1",
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@ -975,6 +1083,80 @@ static struct mlxreg_core_platform_data mlxplat_default_ng_led_data = {
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.counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_led_data),
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};
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/* Platform led for Comex based 100GbE systems */
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static struct mlxreg_core_data mlxplat_mlxcpld_comex_100G_led_data[] = {
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{
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.label = "status:green",
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.reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
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.mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
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},
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{
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.label = "status:red",
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.reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
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.mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK
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},
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{
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.label = "psu:green",
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.reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
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.mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
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},
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{
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.label = "psu:red",
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.reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
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.mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
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},
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{
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.label = "fan1:green",
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.reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
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.mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
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},
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{
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.label = "fan1:red",
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.reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
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.mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
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},
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{
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.label = "fan2:green",
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.reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
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.mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
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},
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{
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.label = "fan2:red",
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.reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
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.mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
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},
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{
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.label = "fan3:green",
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.reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
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.mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
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},
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{
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.label = "fan3:red",
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.reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
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.mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
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},
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{
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.label = "fan4:green",
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.reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
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.mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
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},
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{
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.label = "fan4:red",
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.reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
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.mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
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},
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{
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.label = "uid:blue",
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.reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET,
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.mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
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},
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};
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static struct mlxreg_core_platform_data mlxplat_comex_100G_led_data = {
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.data = mlxplat_mlxcpld_comex_100G_led_data,
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.counter = ARRAY_SIZE(mlxplat_mlxcpld_comex_100G_led_data),
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};
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/* Platform register access default */
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static struct mlxreg_core_data mlxplat_mlxcpld_default_regs_io_data[] = {
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{
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@ -1661,6 +1843,7 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
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case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:
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@ -1712,6 +1895,8 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
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case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET:
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@ -1786,6 +1971,8 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
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case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET:
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@ -1840,6 +2027,12 @@ static const struct reg_default mlxplat_mlxcpld_regmap_ng[] = {
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{ MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET, 0x00 },
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};
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static const struct reg_default mlxplat_mlxcpld_regmap_comex_default[] = {
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{ MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET,
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MLXPLAT_CPLD_LOW_AGGRCX_MASK },
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{ MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 },
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};
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struct mlxplat_mlxcpld_regmap_context {
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void __iomem *base;
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};
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@ -1892,6 +2085,20 @@ static const struct regmap_config mlxplat_mlxcpld_regmap_config_ng = {
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.reg_write = mlxplat_mlxcpld_reg_write,
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};
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static const struct regmap_config mlxplat_mlxcpld_regmap_config_comex = {
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.reg_bits = 8,
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.val_bits = 8,
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.max_register = 255,
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.cache_type = REGCACHE_FLAT,
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.writeable_reg = mlxplat_mlxcpld_writeable_reg,
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.readable_reg = mlxplat_mlxcpld_readable_reg,
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.volatile_reg = mlxplat_mlxcpld_volatile_reg,
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.reg_defaults = mlxplat_mlxcpld_regmap_comex_default,
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.num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_comex_default),
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.reg_read = mlxplat_mlxcpld_reg_read,
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.reg_write = mlxplat_mlxcpld_reg_write,
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};
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static struct resource mlxplat_mlxcpld_resources[] = {
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[0] = DEFINE_RES_IRQ_NAMED(17, "mlxreg-hotplug"),
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};
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@ -2020,6 +2227,30 @@ static int __init mlxplat_dmi_qmb7xx_matched(const struct dmi_system_id *dmi)
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return 1;
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}
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static int __init mlxplat_dmi_comex_matched(const struct dmi_system_id *dmi)
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{
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int i;
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mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM;
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mlxplat_mux_num = ARRAY_SIZE(mlxplat_extended_mux_data);
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mlxplat_mux_data = mlxplat_extended_mux_data;
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for (i = 0; i < mlxplat_mux_num; i++) {
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mlxplat_mux_data[i].values = mlxplat_msn21xx_channels;
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mlxplat_mux_data[i].n_values =
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ARRAY_SIZE(mlxplat_msn21xx_channels);
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}
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mlxplat_hotplug = &mlxplat_mlxcpld_comex_data;
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mlxplat_hotplug->deferred_nr = MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM;
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mlxplat_led = &mlxplat_comex_100G_led_data;
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mlxplat_regs_io = &mlxplat_default_ng_regs_io_data;
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mlxplat_fan = &mlxplat_default_fan_data;
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for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++)
|
||||
mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i];
|
||||
mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_comex;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static const struct dmi_system_id mlxplat_dmi_table[] __initconst = {
|
||||
{
|
||||
.callback = mlxplat_dmi_default_matched,
|
||||
|
@ -2057,6 +2288,12 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = {
|
|||
DMI_MATCH(DMI_BOARD_NAME, "VMOD0007"),
|
||||
},
|
||||
},
|
||||
{
|
||||
.callback = mlxplat_dmi_comex_matched,
|
||||
.matches = {
|
||||
DMI_MATCH(DMI_BOARD_NAME, "VMOD0009"),
|
||||
},
|
||||
},
|
||||
{
|
||||
.callback = mlxplat_dmi_msn274x_matched,
|
||||
.matches = {
|
||||
|
|
Loading…
Reference in a new issue