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drm/tegra: Changes for v5.14-rc1
The two major changes here are fixed YUV support as well as scaling on Tegra186 and later. This allows Tegra DRM to be used, for example, as a video sink for the kmssink gstreamer plugin. The remainder of the changes are minor fixes. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmDDk/4THHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zoaY3D/9mEpsfo71PkZGTKl51xh+y4BwyaPHd RTbBOUbtD3vTdDyxBV1yRvQ5x7ElN2wcR5VHriBPZXYjyxCSShQ0vswul3WYu5ms RbgLnLJQaLaNKw6AASeqGmWeUx9QElXznvRgx2OOtnYFEskwwC8YaDeUchbtZzD9 f7STJMWFuovROJmJcF/lc+/IIczNWingiHmE6IUGb28/Xtobsh1Rs1MohVJ9Ozn/ Zb0wSe+wy2I+KmDJr3/fyP/KV8ijKwch08MZGrEGYoJxYPcvj7ZIIGYUKcmYrTs0 5Iz4excpZjRCBCeeWHBnA+cMznzlbW2ky3i2BiEZQpz5X0b3PL7Vkd0pMw/Eisg1 hcvMmAU4JrvgALiQ3iWjnhrT1dBpQdEiVYikTV/L/WvSCveKKCO/EPQpWaJX/f5Q oL7dbxN0lD3zIYgtoC1vrgs4XUAalTiDrGcF6eDxHkPxpcAgxXhg1LErNpq7xc2J I8HpkvJaS9RiQ4XoJTb/orYvxLl3gY/q+fyRULQqylSFC9OPsLZnwyG0W6Vl4G7Y lrdzICJ3F1wNv4a+vVZ7Rk0wWDFqij7HOKg/nubPc7MZo4VZZu3e6VeMcYjlS6CH uqE+pfRAvVrvTSjaVFZhxq/6kcYQz6mY/lzoL2Sivp6yHx9/4NQcHzMYfdnBFFt7 aNAcftwbuTT0bw== =l2Ew -----END PGP SIGNATURE----- Merge tag 'drm/tegra/for-5.14-rc1' of ssh://git.freedesktop.org/git/tegra/linux into drm-next drm/tegra: Changes for v5.14-rc1 The two major changes here are fixed YUV support as well as scaling on Tegra186 and later. This allows Tegra DRM to be used, for example, as a video sink for the kmssink gstreamer plugin. The remainder of the changes are minor fixes. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Thierry Reding <thierry.reding@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210611165157.3569315-1-thierry.reding@gmail.com
This commit is contained in:
Dave Airlie
commit
bde431fbe8
8 changed files with 223 additions and 20 deletions
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@ -348,7 +348,7 @@ static void tegra_dc_setup_window(struct tegra_plane *plane,
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* For YUV planar modes, the number of bytes per pixel takes into
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* account only the luma component and therefore is 1.
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*/
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yuv = tegra_plane_format_is_yuv(window->format, &planar);
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yuv = tegra_plane_format_is_yuv(window->format, &planar, NULL);
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if (!yuv)
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bpp = window->bits_per_pixel / 8;
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else
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@ -696,6 +696,9 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc);
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#define DC_WINBUF_START_ADDR_HI 0x80d
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#define DC_WINBUF_START_ADDR_HI_U 0x80f
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#define DC_WINBUF_START_ADDR_HI_V 0x811
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#define DC_WINBUF_CDE_CONTROL 0x82f
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#define ENABLE_SURFACE (1 << 0)
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@ -711,15 +714,34 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc);
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#define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR 0x442
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#define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR 0x446
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#define DC_WINC_PRECOMP_WGRP_PIPE_CAPA 0x500
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#define DC_WINC_PRECOMP_WGRP_PIPE_CAPB 0x501
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#define DC_WINC_PRECOMP_WGRP_PIPE_CAPC 0x502
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#define MAX_PIXELS_5TAP444(x) ((x) & 0xffff)
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#define DC_WINC_PRECOMP_WGRP_PIPE_CAPD 0x503
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#define DC_WINC_PRECOMP_WGRP_PIPE_CAPE 0x504
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#define MAX_PIXELS_2TAP444(x) ((x) & 0xffff)
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#define DC_WINC_PRECOMP_WGRP_PIPE_CAPF 0x505
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#define DC_WIN_CORE_WINDOWGROUP_SET_CONTROL 0x702
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#define OWNER_MASK (0xf << 0)
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#define OWNER(x) (((x) & 0xf) << 0)
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#define DC_WIN_CROPPED_SIZE 0x706
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#define DC_WIN_SET_INPUT_SCALER_H_START_PHASE 0x707
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#define DC_WIN_SET_INPUT_SCALER_V_START_PHASE 0x708
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#define DC_WIN_PLANAR_STORAGE 0x709
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#define PITCH(x) (((x) >> 6) & 0x1fff)
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#define DC_WIN_PLANAR_STORAGE_UV 0x70a
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#define PITCH_U(x) ((((x) >> 6) & 0x1fff) << 0)
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#define PITCH_V(x) ((((x) >> 6) & 0x1fff) << 16)
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#define DC_WIN_SET_INPUT_SCALER_HPHASE_INCR 0x70b
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#define DC_WIN_SET_INPUT_SCALER_VPHASE_INCR 0x70c
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#define DC_WIN_SET_PARAMS 0x70d
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#define CLAMP_BEFORE_BLEND (1 << 15)
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#define DEGAMMA_NONE (0 << 13)
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@ -740,6 +762,10 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc);
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#define VERTICAL_TAPS_2 (1 << 0)
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#define VERTICAL_TAPS_5 (4 << 0)
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#define DC_WIN_WINDOWGROUP_SET_INPUT_SCALER_COEFF 0x70f
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#define COEFF_INDEX(x) (((x) & 0xff) << 15)
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#define COEFF_DATA(x) (((x) & 0x3ff) << 0)
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#define DC_WIN_WINDOWGROUP_SET_INPUT_SCALER_USAGE 0x711
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#define INPUT_SCALER_USE422 (1 << 2)
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#define INPUT_SCALER_VBYPASS (1 << 1)
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@ -467,10 +467,8 @@ static int tegra_dpaux_probe(struct platform_device *pdev)
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return PTR_ERR(dpaux->regs);
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dpaux->irq = platform_get_irq(pdev, 0);
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if (dpaux->irq < 0) {
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dev_err(&pdev->dev, "failed to get IRQ\n");
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if (dpaux->irq < 0)
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return -ENXIO;
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}
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if (!pdev->dev.pm_domain) {
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dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux");
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@ -23,6 +23,8 @@
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#include "dc.h"
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#include "plane.h"
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#define NFB 24
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static const u32 tegra_shared_plane_formats[] = {
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DRM_FORMAT_ARGB1555,
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DRM_FORMAT_RGB565,
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@ -292,6 +294,74 @@ static int tegra_shared_plane_set_owner(struct tegra_plane *plane,
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return 0;
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}
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static void tegra_shared_plane_setup_scaler(struct tegra_plane *plane)
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{
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static const unsigned int coeffs[192] = {
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0x00000000, 0x3c70e400, 0x3bb037e4, 0x0c51cc9c,
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0x00100001, 0x3bf0dbfa, 0x3d00f406, 0x3fe003ff,
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0x00300002, 0x3b80cbf5, 0x3da1040d, 0x3fb003fe,
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0x00400002, 0x3b20bff1, 0x3e511015, 0x3f9003fc,
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0x00500002, 0x3ad0b3ed, 0x3f21201d, 0x3f5003fb,
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0x00500003, 0x3aa0a3e9, 0x3ff13026, 0x3f2007f9,
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0x00500403, 0x3a7097e6, 0x00e1402f, 0x3ee007f7,
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0x00500403, 0x3a608be4, 0x01d14c38, 0x3ea00bf6,
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0x00500403, 0x3a507fe2, 0x02e15c42, 0x3e500ff4,
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0x00500402, 0x3a6073e1, 0x03f16c4d, 0x3e000ff2,
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0x00400402, 0x3a706be0, 0x05117858, 0x3db013f0,
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0x00300402, 0x3a905fe0, 0x06318863, 0x3d6017ee,
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0x00300402, 0x3ab057e0, 0x0771986e, 0x3d001beb,
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0x00200001, 0x3af04fe1, 0x08a1a47a, 0x3cb023e9,
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0x00100001, 0x3b2047e2, 0x09e1b485, 0x3c6027e7,
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0x00100000, 0x3b703fe2, 0x0b11c091, 0x3c002fe6,
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0x3f203800, 0x0391103f, 0x3ff0a014, 0x0811606c,
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0x3f2037ff, 0x0351083c, 0x03e11842, 0x3f203c00,
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0x3f302fff, 0x03010439, 0x04311c45, 0x3f104401,
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0x3f302fff, 0x02c0fc35, 0x04812448, 0x3f104802,
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0x3f4027ff, 0x0270f832, 0x04c1284b, 0x3f205003,
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0x3f4023ff, 0x0230f030, 0x0511304e, 0x3f205403,
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0x3f601fff, 0x01f0e82d, 0x05613451, 0x3f205c04,
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0x3f701bfe, 0x01b0e02a, 0x05a13c54, 0x3f306006,
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0x3f7017fe, 0x0170d827, 0x05f14057, 0x3f406807,
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0x3f8017ff, 0x0140d424, 0x0641445a, 0x3f406c08,
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0x3fa013ff, 0x0100cc22, 0x0681485d, 0x3f507409,
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0x3fa00fff, 0x00d0c41f, 0x06d14c60, 0x3f607c0b,
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0x3fc00fff, 0x0090bc1c, 0x07115063, 0x3f80840c,
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0x3fd00bff, 0x0070b41a, 0x07515465, 0x3f908c0e,
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0x3fe007ff, 0x0040b018, 0x07915868, 0x3fb0900f,
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0x3ff00400, 0x0010a816, 0x07d15c6a, 0x3fd09811,
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0x00a04c0e, 0x0460f442, 0x0240a827, 0x05c15859,
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0x0090440d, 0x0440f040, 0x0480fc43, 0x00b05010,
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0x0080400c, 0x0410ec3e, 0x04910044, 0x00d05411,
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0x0070380b, 0x03f0e83d, 0x04b10846, 0x00e05812,
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0x0060340a, 0x03d0e43b, 0x04d10c48, 0x00f06013,
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0x00503009, 0x03b0e039, 0x04e11449, 0x01106415,
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0x00402c08, 0x0390d838, 0x05011c4b, 0x01206c16,
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0x00302807, 0x0370d436, 0x0511204c, 0x01407018,
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0x00302406, 0x0340d034, 0x0531244e, 0x01507419,
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0x00202005, 0x0320cc32, 0x05412c50, 0x01707c1b,
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0x00101c04, 0x0300c431, 0x05613451, 0x0180801d,
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0x00101803, 0x02e0c02f, 0x05713853, 0x01a0881e,
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0x00101002, 0x02b0bc2d, 0x05814054, 0x01c08c20,
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0x00000c02, 0x02a0b82c, 0x05914455, 0x01e09421,
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0x00000801, 0x0280b02a, 0x05a14c57, 0x02009c23,
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0x00000400, 0x0260ac28, 0x05b15458, 0x0220a025,
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};
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unsigned int ratio, row, column;
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for (ratio = 0; ratio <= 2; ratio++) {
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for (row = 0; row <= 15; row++) {
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for (column = 0; column <= 3; column++) {
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unsigned int index = (ratio << 6) + (row << 2) + column;
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u32 value;
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value = COEFF_INDEX(index) | COEFF_DATA(coeffs[index]);
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tegra_plane_writel(plane, value,
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DC_WIN_WINDOWGROUP_SET_INPUT_SCALER_COEFF);
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}
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}
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}
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}
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static void tegra_dc_assign_shared_plane(struct tegra_dc *dc,
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struct tegra_plane *plane)
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{
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@ -337,6 +407,8 @@ static void tegra_dc_assign_shared_plane(struct tegra_dc *dc,
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value |= THREAD_GROUP_ENABLE;
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tegra_plane_writel(plane, value, DC_WIN_CORE_IHUB_THREAD_GROUP);
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tegra_shared_plane_setup_scaler(plane);
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tegra_shared_plane_update(plane);
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tegra_shared_plane_activate(plane);
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}
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@ -444,6 +516,18 @@ static void tegra_shared_plane_atomic_disable(struct drm_plane *plane,
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host1x_client_suspend(&dc->client);
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}
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static inline u32 compute_phase_incr(fixed20_12 in, unsigned int out)
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{
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u64 tmp, tmp1, tmp2;
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tmp = (u64)dfixed_trunc(in);
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tmp2 = (u64)out;
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tmp1 = (tmp << NFB) + (tmp2 >> 1);
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do_div(tmp1, tmp2);
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return lower_32_bits(tmp1);
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}
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static void tegra_shared_plane_atomic_update(struct drm_plane *plane,
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struct drm_atomic_state *state)
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{
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@ -454,8 +538,10 @@ static void tegra_shared_plane_atomic_update(struct drm_plane *plane,
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unsigned int zpos = new_state->normalized_zpos;
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struct drm_framebuffer *fb = new_state->fb;
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struct tegra_plane *p = to_tegra_plane(plane);
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dma_addr_t base;
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u32 value;
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u32 value, min_width, bypass = 0;
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dma_addr_t base, addr_flag = 0;
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unsigned int bpc;
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bool yuv, planar;
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int err;
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/* rien ne va plus */
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@ -473,6 +559,8 @@ static void tegra_shared_plane_atomic_update(struct drm_plane *plane,
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return;
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}
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yuv = tegra_plane_format_is_yuv(tegra_plane_state->format, &planar, &bpc);
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tegra_dc_assign_shared_plane(dc, p);
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tegra_plane_writel(p, VCOUNTER, DC_WIN_CORE_ACT_CONTROL);
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@ -491,18 +579,52 @@ static void tegra_shared_plane_atomic_update(struct drm_plane *plane,
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value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - zpos);
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tegra_plane_writel(p, value, DC_WIN_BLEND_LAYER_CONTROL);
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/* bypass scaling */
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/* scaling */
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min_width = min(new_state->src_w >> 16, new_state->crtc_w);
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value = tegra_plane_readl(p, DC_WINC_PRECOMP_WGRP_PIPE_CAPC);
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if (min_width < MAX_PIXELS_5TAP444(value)) {
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value = HORIZONTAL_TAPS_5 | VERTICAL_TAPS_5;
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} else {
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value = tegra_plane_readl(p, DC_WINC_PRECOMP_WGRP_PIPE_CAPE);
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if (min_width < MAX_PIXELS_2TAP444(value))
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value = HORIZONTAL_TAPS_2 | VERTICAL_TAPS_2;
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else
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dev_err(dc->dev, "invalid minimum width: %u\n", min_width);
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}
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value = HORIZONTAL_TAPS_5 | VERTICAL_TAPS_5;
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tegra_plane_writel(p, value, DC_WIN_WINDOWGROUP_SET_CONTROL_INPUT_SCALER);
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value = INPUT_SCALER_VBYPASS | INPUT_SCALER_HBYPASS;
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tegra_plane_writel(p, value, DC_WIN_WINDOWGROUP_SET_INPUT_SCALER_USAGE);
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if (new_state->src_w != new_state->crtc_w << 16) {
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fixed20_12 width = dfixed_init(new_state->src_w >> 16);
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u32 incr = compute_phase_incr(width, new_state->crtc_w) & ~0x1;
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u32 init = (1 << (NFB - 1)) + (incr >> 1);
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tegra_plane_writel(p, incr, DC_WIN_SET_INPUT_SCALER_HPHASE_INCR);
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tegra_plane_writel(p, init, DC_WIN_SET_INPUT_SCALER_H_START_PHASE);
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} else {
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bypass |= INPUT_SCALER_HBYPASS;
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}
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if (new_state->src_h != new_state->crtc_h << 16) {
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fixed20_12 height = dfixed_init(new_state->src_h >> 16);
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u32 incr = compute_phase_incr(height, new_state->crtc_h) & ~0x1;
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u32 init = (1 << (NFB - 1)) + (incr >> 1);
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tegra_plane_writel(p, incr, DC_WIN_SET_INPUT_SCALER_VPHASE_INCR);
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tegra_plane_writel(p, init, DC_WIN_SET_INPUT_SCALER_V_START_PHASE);
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} else {
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bypass |= INPUT_SCALER_VBYPASS;
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}
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tegra_plane_writel(p, bypass, DC_WIN_WINDOWGROUP_SET_INPUT_SCALER_USAGE);
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/* disable compression */
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tegra_plane_writel(p, 0, DC_WINBUF_CDE_CONTROL);
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base = tegra_plane_state->iova[0] + fb->offsets[0];
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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/*
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* Physical address bit 39 in Tegra194 is used as a switch for special
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@ -510,9 +632,12 @@ static void tegra_shared_plane_atomic_update(struct drm_plane *plane,
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* dGPU sector layout.
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*/
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if (tegra_plane_state->tiling.sector_layout == TEGRA_BO_SECTOR_LAYOUT_GPU)
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base |= BIT_ULL(39);
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addr_flag = BIT_ULL(39);
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#endif
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base = tegra_plane_state->iova[0] + fb->offsets[0];
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base |= addr_flag;
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tegra_plane_writel(p, tegra_plane_state->format, DC_WIN_COLOR_DEPTH);
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tegra_plane_writel(p, 0, DC_WIN_PRECOMP_WGRP_PARAMS);
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@ -526,7 +651,7 @@ static void tegra_shared_plane_atomic_update(struct drm_plane *plane,
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value = WIN_ENABLE | COLOR_EXPAND;
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tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS);
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value = V_SIZE(new_state->crtc_h) | H_SIZE(new_state->crtc_w);
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value = V_SIZE(new_state->src_h >> 16) | H_SIZE(new_state->src_w >> 16);
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tegra_plane_writel(p, value, DC_WIN_CROPPED_SIZE);
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tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI);
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@ -535,7 +660,44 @@ static void tegra_shared_plane_atomic_update(struct drm_plane *plane,
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value = PITCH(fb->pitches[0]);
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||||
tegra_plane_writel(p, value, DC_WIN_PLANAR_STORAGE);
|
||||
|
||||
value = CLAMP_BEFORE_BLEND | DEGAMMA_SRGB | INPUT_RANGE_FULL;
|
||||
if (yuv && planar) {
|
||||
base = tegra_plane_state->iova[1] + fb->offsets[1];
|
||||
base |= addr_flag;
|
||||
|
||||
tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI_U);
|
||||
tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR_U);
|
||||
|
||||
base = tegra_plane_state->iova[2] + fb->offsets[2];
|
||||
base |= addr_flag;
|
||||
|
||||
tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI_V);
|
||||
tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR_V);
|
||||
|
||||
value = PITCH_U(fb->pitches[2]) | PITCH_V(fb->pitches[2]);
|
||||
tegra_plane_writel(p, value, DC_WIN_PLANAR_STORAGE_UV);
|
||||
} else {
|
||||
tegra_plane_writel(p, 0, DC_WINBUF_START_ADDR_U);
|
||||
tegra_plane_writel(p, 0, DC_WINBUF_START_ADDR_HI_U);
|
||||
tegra_plane_writel(p, 0, DC_WINBUF_START_ADDR_V);
|
||||
tegra_plane_writel(p, 0, DC_WINBUF_START_ADDR_HI_V);
|
||||
tegra_plane_writel(p, 0, DC_WIN_PLANAR_STORAGE_UV);
|
||||
}
|
||||
|
||||
value = CLAMP_BEFORE_BLEND | INPUT_RANGE_FULL;
|
||||
|
||||
if (yuv) {
|
||||
if (bpc < 12)
|
||||
value |= DEGAMMA_YUV8_10;
|
||||
else
|
||||
value |= DEGAMMA_YUV12;
|
||||
|
||||
/* XXX parameterize */
|
||||
value |= COLOR_SPACE_YUV_2020;
|
||||
} else {
|
||||
if (!tegra_plane_format_is_indexed(tegra_plane_state->format))
|
||||
value |= DEGAMMA_SRGB;
|
||||
}
|
||||
|
||||
tegra_plane_writel(p, value, DC_WIN_SET_PARAMS);
|
||||
|
||||
value = OFFSET_X(new_state->src_y >> 16) |
|
||||
|
|
|
|||
|
|
@ -375,7 +375,20 @@ int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap)
|
|||
return 0;
|
||||
}
|
||||
|
||||
bool tegra_plane_format_is_yuv(unsigned int format, bool *planar)
|
||||
bool tegra_plane_format_is_indexed(unsigned int format)
|
||||
{
|
||||
switch (format) {
|
||||
case WIN_COLOR_DEPTH_P1:
|
||||
case WIN_COLOR_DEPTH_P2:
|
||||
case WIN_COLOR_DEPTH_P4:
|
||||
case WIN_COLOR_DEPTH_P8:
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
bool tegra_plane_format_is_yuv(unsigned int format, bool *planar, unsigned int *bpc)
|
||||
{
|
||||
switch (format) {
|
||||
case WIN_COLOR_DEPTH_YCbCr422:
|
||||
|
|
@ -383,6 +396,9 @@ bool tegra_plane_format_is_yuv(unsigned int format, bool *planar)
|
|||
if (planar)
|
||||
*planar = false;
|
||||
|
||||
if (bpc)
|
||||
*bpc = 8;
|
||||
|
||||
return true;
|
||||
|
||||
case WIN_COLOR_DEPTH_YCbCr420P:
|
||||
|
|
@ -396,6 +412,9 @@ bool tegra_plane_format_is_yuv(unsigned int format, bool *planar)
|
|||
if (planar)
|
||||
*planar = true;
|
||||
|
||||
if (bpc)
|
||||
*bpc = 8;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
@ -421,7 +440,7 @@ static bool __drm_format_has_alpha(u32 format)
|
|||
static int tegra_plane_format_get_alpha(unsigned int opaque,
|
||||
unsigned int *alpha)
|
||||
{
|
||||
if (tegra_plane_format_is_yuv(opaque, NULL)) {
|
||||
if (tegra_plane_format_is_yuv(opaque, NULL, NULL)) {
|
||||
*alpha = opaque;
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -74,7 +74,8 @@ int tegra_plane_state_add(struct tegra_plane *plane,
|
|||
struct drm_plane_state *state);
|
||||
|
||||
int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap);
|
||||
bool tegra_plane_format_is_yuv(unsigned int format, bool *planar);
|
||||
bool tegra_plane_format_is_indexed(unsigned int format);
|
||||
bool tegra_plane_format_is_yuv(unsigned int format, bool *planar, unsigned int *bpc);
|
||||
int tegra_plane_setup_legacy_state(struct tegra_plane *tegra,
|
||||
struct tegra_plane_state *state);
|
||||
|
||||
|
|
|
|||
|
|
@ -148,8 +148,6 @@ static int vic_boot(struct vic *vic)
|
|||
hdr = vic->falcon.firmware.virt;
|
||||
fce_bin_data_offset = *(u32 *)(hdr + VIC_UCODE_FCE_DATA_OFFSET);
|
||||
|
||||
falcon_execute_method(&vic->falcon, VIC_SET_APPLICATION_ID, 1);
|
||||
|
||||
/* Old VIC firmware needs kernel help with setting up FCE microcode. */
|
||||
if (fce_bin_data_offset != 0x0 && fce_bin_data_offset != 0xa5a5a5a5) {
|
||||
hdr = vic->falcon.firmware.virt +
|
||||
|
|
|
|||
|
|
@ -8,7 +8,6 @@
|
|||
|
||||
/* VIC methods */
|
||||
|
||||
#define VIC_SET_APPLICATION_ID 0x00000200
|
||||
#define VIC_SET_FCE_UCODE_SIZE 0x0000071C
|
||||
#define VIC_SET_FCE_UCODE_OFFSET 0x0000072C
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue