From feaea1fe8b36b2e5b12b2f9e6e050db28dfee789 Mon Sep 17 00:00:00 2001 From: "Michael J. Ruhl" Date: Wed, 9 Feb 2022 11:28:01 -0500 Subject: [PATCH] PCI/P2PDMA: Add Intel 3rd Gen Intel Xeon Scalable Processors to whitelist In order to do P2P communication the bridge ID of the platform must be in the P2P device table. Update the P2P device table with a device ID for the 3rd Gen Intel Xeon Scalable Processors. Link: https://lore.kernel.org/r/20220209162801.7647-1-michael.j.ruhl@intel.com Signed-off-by: Michael J. Ruhl Signed-off-by: Bjorn Helgaas Reviewed-by: Dan Williams --- drivers/pci/p2pdma.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/p2pdma.c b/drivers/pci/p2pdma.c index 1015274bd2fe..30b1df3c9d2f 100644 --- a/drivers/pci/p2pdma.c +++ b/drivers/pci/p2pdma.c @@ -321,6 +321,7 @@ static const struct pci_p2pdma_whitelist_entry { {PCI_VENDOR_ID_INTEL, 0x2032, 0}, {PCI_VENDOR_ID_INTEL, 0x2033, 0}, {PCI_VENDOR_ID_INTEL, 0x2020, 0}, + {PCI_VENDOR_ID_INTEL, 0x09a2, 0}, {} };