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media: atomisp: fix several coding style issues 

Use checkpatch.pl --fix-inplace --strict to solve several
coding style issues, manually reviewing the produced code and
fixing some troubles caused by checkpatch.

Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
This commit is contained in:
Mauro Carvalho Chehab 2020-04-19 16:06:45 +02:00
parent 4636a85cff
commit bdfe0beb95
586 changed files with 8831 additions and 9526 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
drivers/staging/media/atomisp/i2c/atomisp-gc0310.c
View File

@ -239,6 +239,7 @@ static int gc0310_write_reg_array(struct i2c_client *client,
return __gc0310_flush_reg_array(client, &ctrl);
}
static int gc0310_g_focal(struct v4l2_subdev *sd, s32 *val)
{
*val = (GC0310_FOCAL_LENGTH_NUM << 16) | GC0310_FOCAL_LENGTH_DEM;
@ -499,6 +500,7 @@ static long gc0310_s_exposure(struct v4l2_subdev *sd,
/* we should not accept the invalid value below. */
if (gain == 0) {
struct i2c_client *client = v4l2_get_subdevdata(sd);
v4l2_err(client, "%s: invalid value\n", __func__);
return -EINVAL;
}
@ -520,7 +522,6 @@ static int gc0310_h_flip(struct v4l2_subdev *sd, s32 value)
static long gc0310_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
{
switch (cmd) {
case ATOMISP_IOC_S_EXPOSURE:
return gc0310_s_exposure(sd, arg);
@ -734,6 +735,7 @@ static int power_ctrl(struct v4l2_subdev *sd, bool flag)
{
int ret = 0;
struct gc0310_device *dev = to_gc0310_sensor(sd);
if (!dev || !dev->platform_data)
return -ENODEV;
@ -783,7 +785,6 @@ static int gpio_ctrl(struct v4l2_subdev *sd, bool flag)
return ret;
}
static int power_down(struct v4l2_subdev *sd);
static int power_up(struct v4l2_subdev *sd)
@ -867,6 +868,7 @@ static int power_down(struct v4l2_subdev *sd)
static int gc0310_s_power(struct v4l2_subdev *sd, int on)
{
int ret;
if (on == 0)
return power_down(sd);
else {
@ -899,9 +901,9 @@ static int distance(struct gc0310_resolution *res, u32 w, u32 h)
h_ratio = (res->height << 13) / h;
if (h_ratio == 0)
return -1;
match = abs(((w_ratio << 13) / h_ratio) - ((int)8192));
match = abs(((w_ratio << 13) / h_ratio) - 8192);
if ((w_ratio < (int)8192) || (h_ratio < (int)8192) ||
if ((w_ratio < 8192) || (h_ratio < 8192) ||
(match > LARGEST_ALLOWED_RATIO_MISMATCH))
return -1;
@ -947,7 +949,6 @@ static int get_resolution_index(int w, int h)
return -1;
}
/* TODO: remove it. */
static int startup(struct v4l2_subdev *sd)
{
@ -977,6 +978,7 @@ static int gc0310_set_fmt(struct v4l2_subdev *sd,
struct camera_mipi_info *gc0310_info = NULL;
int ret = 0;
int idx = 0;
pr_info("%s S\n", __func__);
if (format->pad)
@ -1015,7 +1017,7 @@ static int gc0310_set_fmt(struct v4l2_subdev *sd,
return -EINVAL;
}
printk("%s: before gc0310_write_reg_array %s\n", __FUNCTION__,
printk("%s: before gc0310_write_reg_array %s\n", __func__,
gc0310_res[dev->fmt_idx].desc);
ret = startup(sd);
if (ret) {
@ -1079,7 +1081,7 @@ static int gc0310_detect(struct i2c_client *client)
dev_err(&client->dev, "read sensor_id_low failed\n");
return -ENODEV;
}
id = ((((u16) high) << 8) | (u16) low);
id = ((((u16)high) << 8) | (u16)low);
pr_info("sensor ID = 0x%x\n", id);
if (id != GC0310_ID) {
@ -1140,7 +1142,6 @@ static int gc0310_s_stream(struct v4l2_subdev *sd, int enable)
return ret;
}
static int gc0310_s_config(struct v4l2_subdev *sd,
int irq, void *platform_data)
{
@ -1241,10 +1242,8 @@ static int gc0310_enum_frame_size(struct v4l2_subdev *sd,
fse->max_height = gc0310_res[index].height;
return 0;
}
static int gc0310_g_skip_frames(struct v4l2_subdev *sd, u32 *frames)
{
struct gc0310_device *dev = to_gc0310_sensor(sd);
@ -1288,6 +1287,7 @@ static int gc0310_remove(struct i2c_client *client)
{
struct v4l2_subdev *sd = i2c_get_clientdata(client);
struct gc0310_device *dev = to_gc0310_sensor(sd);
dev_dbg(&client->dev, "gc0310_remove...\n");
dev->platform_data->csi_cfg(sd, 0);
@ -1315,7 +1315,7 @@ static int gc0310_probe(struct i2c_client *client)
mutex_init(&dev->input_lock);
dev->fmt_idx = 0;
v4l2_i2c_subdev_init(&(dev->sd), client, &gc0310_ops);
v4l2_i2c_subdev_init(&dev->sd, client, &gc0310_ops);
pdata = gmin_camera_platform_data(&dev->sd,
ATOMISP_INPUT_FORMAT_RAW_8,

16
drivers/staging/media/atomisp/i2c/atomisp-gc2235.c
View File

@ -168,6 +168,7 @@ static int __gc2235_buf_reg_array(struct i2c_client *client,
return 0;
}
static int __gc2235_write_reg_is_consecutive(struct i2c_client *client,
struct gc2235_write_ctrl *ctrl,
const struct gc2235_reg *next)
@ -177,6 +178,7 @@ static int __gc2235_write_reg_is_consecutive(struct i2c_client *client,
return ctrl->buffer.addr + ctrl->index == next->reg;
}
static int gc2235_write_reg_array(struct i2c_client *client,
const struct gc2235_reg *reglist)
{
@ -238,7 +240,6 @@ static int gc2235_g_fnumber_range(struct v4l2_subdev *sd, s32 *val)
return 0;
}
static int gc2235_get_intg_factor(struct i2c_client *client,
struct camera_mipi_info *info,
const struct gc2235_resolution *res)
@ -355,6 +356,7 @@ static long __gc2235_set_exposure(struct v4l2_subdev *sd, int coarse_itg,
u16 coarse_integration = (u16)coarse_itg;
int ret = 0;
u16 expo_coarse_h, expo_coarse_l, gain_val = 0xF0, gain_val2 = 0xF0;
expo_coarse_h = coarse_integration >> 8;
expo_coarse_l = coarse_integration & 0xff;
@ -382,7 +384,6 @@ static long __gc2235_set_exposure(struct v4l2_subdev *sd, int coarse_itg,
return ret;
}
static int gc2235_set_exposure(struct v4l2_subdev *sd, int exposure,
int gain, int digitgain)
{
@ -406,12 +407,14 @@ static long gc2235_s_exposure(struct v4l2_subdev *sd,
/* we should not accept the invalid value below. */
if (gain == 0) {
struct i2c_client *client = v4l2_get_subdevdata(sd);
v4l2_err(client, "%s: invalid value\n", __func__);
return -EINVAL;
}
return gc2235_set_exposure(sd, exp, gain, digitgain);
}
static long gc2235_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
{
switch (cmd) {
@ -422,6 +425,7 @@ static long gc2235_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
}
return 0;
}
/* This returns the exposure time being used. This should only be used
* for filling in EXIF data, not for actual image processing.
*/
@ -739,6 +743,7 @@ static int startup(struct v4l2_subdev *sd)
struct gc2235_device *dev = to_gc2235_sensor(sd);
struct i2c_client *client = v4l2_get_subdevdata(sd);
int ret = 0;
if (is_init == 0) {
/* force gc2235 to do a reset in res change, otherwise it
* can not output normal after switching res. and it is not
@ -764,7 +769,6 @@ static int gc2235_set_fmt(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_format *format)
{
struct v4l2_mbus_framefmt *fmt = &format->format;
struct gc2235_device *dev = to_gc2235_sensor(sd);
struct i2c_client *client = v4l2_get_subdevdata(sd);
@ -873,6 +877,7 @@ static int gc2235_s_stream(struct v4l2_subdev *sd, int enable)
struct gc2235_device *dev = to_gc2235_sensor(sd);
struct i2c_client *client = v4l2_get_subdevdata(sd);
int ret;
mutex_lock(&dev->input_lock);
if (enable)
@ -884,7 +889,6 @@ static int gc2235_s_stream(struct v4l2_subdev *sd, int enable)
return ret;
}
static int gc2235_s_config(struct v4l2_subdev *sd,
int irq, void *platform_data)
{
@ -983,7 +987,6 @@ static int gc2235_enum_frame_size(struct v4l2_subdev *sd,
fse->max_height = gc2235_res[index].height;
return 0;
}
static int gc2235_g_skip_frames(struct v4l2_subdev *sd, u32 *frames)
@ -1029,6 +1032,7 @@ static int gc2235_remove(struct i2c_client *client)
{
struct v4l2_subdev *sd = i2c_get_clientdata(client);
struct gc2235_device *dev = to_gc2235_sensor(sd);
dev_dbg(&client->dev, "gc2235_remove...\n");
dev->platform_data->csi_cfg(sd, 0);
@ -1055,7 +1059,7 @@ static int gc2235_probe(struct i2c_client *client)
mutex_init(&dev->input_lock);
dev->fmt_idx = 0;
v4l2_i2c_subdev_init(&(dev->sd), client, &gc2235_ops);
v4l2_i2c_subdev_init(&dev->sd, client, &gc2235_ops);
gcpdev = gmin_camera_platform_data(&dev->sd,
ATOMISP_INPUT_FORMAT_RAW_10,

34
drivers/staging/media/atomisp/i2c/atomisp-libmsrlisthelper.c
View File

@ -22,26 +22,26 @@
/* Tagged binary data container structure definitions. */
struct tbd_header {
uint32_t tag; /*!< Tag identifier, also checks endianness */
uint32_t size; /*!< Container size including this header */
uint32_t version; /*!< Version, format 0xYYMMDDVV */
uint32_t revision; /*!< Revision, format 0xYYMMDDVV */
uint32_t config_bits; /*!< Configuration flag bits set */
uint32_t checksum; /*!< Global checksum, header included */
u32 tag; /*!< Tag identifier, also checks endianness */
u32 size; /*!< Container size including this header */
u32 version; /*!< Version, format 0xYYMMDDVV */
u32 revision; /*!< Revision, format 0xYYMMDDVV */
u32 config_bits; /*!< Configuration flag bits set */
u32 checksum; /*!< Global checksum, header included */
} __packed;
struct tbd_record_header {
uint32_t size; /*!< Size of record including header */
uint8_t format_id; /*!< tbd_format_t enumeration values used */
uint8_t packing_key; /*!< Packing method; 0 = no packing */
uint16_t class_id; /*!< tbd_class_t enumeration values used */
u32 size; /*!< Size of record including header */
u8 format_id; /*!< tbd_format_t enumeration values used */
u8 packing_key; /*!< Packing method; 0 = no packing */
u16 class_id; /*!< tbd_class_t enumeration values used */
} __packed;
struct tbd_data_record_header {
uint16_t next_offset;
uint16_t flags;
uint16_t data_offset;
uint16_t data_size;
u16 next_offset;
u16 flags;
u16 data_offset;
u16 data_size;
} __packed;
#define TBD_CLASS_DRV_ID 2
@ -58,7 +58,8 @@ static int set_msr_configuration(struct i2c_client *client, uint8_t *bufptr,
* followed by lobyte) where the remaining data in the sequence
* will be written. */
uint8_t *ptr = bufptr;
u8 *ptr = bufptr;
while (ptr < bufptr + size) {
struct i2c_msg msg = {
.addr = client->addr,
@ -88,7 +89,7 @@ static int set_msr_configuration(struct i2c_client *client, uint8_t *bufptr,
static int parse_and_apply(struct i2c_client *client, uint8_t *buffer,
unsigned int size)
{
uint8_t *endptr8 = buffer + size;
u8 *endptr8 = buffer + size;
struct tbd_data_record_header *header =
(struct tbd_data_record_header *)buffer;
@ -170,6 +171,7 @@ int load_msr_list(struct i2c_client *client, char *name,
const struct firmware **fw)
{
int ret = request_firmware(fw, name, &client->dev);
if (ret) {
dev_err(&client->dev,
"Error %d while requesting firmware %s\n",

17
drivers/staging/media/atomisp/i2c/atomisp-lm3554.c
View File

@ -46,14 +46,14 @@
#define LM3554_CURRENT_LIMIT_SHIFT 5
#define LM3554_FLAGS_REG 0xD0
#define LM3554_FLAG_TIMEOUT (1 << 0)
#define LM3554_FLAG_THERMAL_SHUTDOWN (1 << 1)
#define LM3554_FLAG_LED_FAULT (1 << 2)
#define LM3554_FLAG_TX1_INTERRUPT (1 << 3)
#define LM3554_FLAG_TX2_INTERRUPT (1 << 4)
#define LM3554_FLAG_LED_THERMAL_FAULT (1 << 5)
#define LM3554_FLAG_UNUSED (1 << 6)
#define LM3554_FLAG_INPUT_VOLTAGE_LOW (1 << 7)
#define LM3554_FLAG_TIMEOUT BIT(0)
#define LM3554_FLAG_THERMAL_SHUTDOWN BIT(1)
#define LM3554_FLAG_LED_FAULT BIT(2)
#define LM3554_FLAG_TX1_INTERRUPT BIT(3)
#define LM3554_FLAG_TX2_INTERRUPT BIT(4)
#define LM3554_FLAG_LED_THERMAL_FAULT BIT(5)
#define LM3554_FLAG_UNUSED BIT(6)
#define LM3554_FLAG_INPUT_VOLTAGE_LOW BIT(7)
#define LM3554_CONFIG_REG_1 0xE0
#define LM3554_ENVM_TX2_SHIFT 5
@ -881,7 +881,6 @@ static int lm3554_probe(struct i2c_client *client)
NULL);
if (flash->ctrl_handler.error) {
dev_err(&client->dev, "ctrl_handler error.\n");
goto fail2;
}

29
drivers/staging/media/atomisp/i2c/atomisp-mt9m114.c
View File

@ -73,8 +73,8 @@ mt9m114_read_reg(struct i2c_client *client, u16 data_length, u32 reg, u32 *val)
msg[0].buf = data;
/* high byte goes out first */
data[0] = (u16) (reg >> 8);
data[1] = (u16) (reg & 0xff);
data[0] = (u16)(reg >> 8);
data[1] = (u16)(reg & 0xff);
msg[1].addr = client->addr;
msg[1].len = data_length;
@ -239,7 +239,6 @@ misensor_rmw_reg(struct i2c_client *client, u16 data_length, u16 reg,
return 0;
}
static int __mt9m114_flush_reg_array(struct i2c_client *client,
struct mt9m114_write_ctrl *ctrl)
{
@ -428,12 +427,12 @@ static int mt9m114_wait_state(struct i2c_client *client, int timeout)
}
return -EINVAL;
}
static int mt9m114_set_suspend(struct v4l2_subdev *sd)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
return mt9m114_write_reg_array(client,
mt9m114_standby_reg, POST_POLLING);
}
@ -499,7 +498,7 @@ static int power_up(struct v4l2_subdev *sd)
struct i2c_client *client = v4l2_get_subdevdata(sd);
int ret;
if (NULL == dev->platform_data) {
if (!dev->platform_data) {
dev_err(&client->dev, "no camera_sensor_platform_data");
return -ENODEV;
}
@ -541,7 +540,7 @@ static int power_down(struct v4l2_subdev *sd)
struct i2c_client *client = v4l2_get_subdevdata(sd);
int ret;
if (NULL == dev->platform_data) {
if (!dev->platform_data) {
dev_err(&client->dev, "no camera_sensor_platform_data");
return -ENODEV;
}
@ -704,9 +703,9 @@ static int mt9m114_res2size(struct v4l2_subdev *sd, int *h_size, int *v_size)
return -EINVAL;
}
if (h_size != NULL)
if (h_size)
*h_size = hsize;
if (v_size != NULL)
if (v_size)
*v_size = vsize;
return 0;
@ -720,7 +719,7 @@ static int mt9m114_get_intg_factor(struct i2c_client *client,
u32 reg_val;
int ret;
if (info == NULL)
if (!info)
return -EINVAL;
ret = mt9m114_read_reg(client, MISENSOR_32BIT,
@ -807,6 +806,7 @@ static int mt9m114_get_fmt(struct v4l2_subdev *sd,
struct v4l2_mbus_framefmt *fmt = &format->format;
int width, height;
int ret;
if (format->pad)
return -EINVAL;
fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
@ -833,13 +833,14 @@ static int mt9m114_set_fmt(struct v4l2_subdev *sd,
struct camera_mipi_info *mt9m114_info = NULL;
int ret;
if (format->pad)
return -EINVAL;
dev->streamon = 0;
dev->first_exp = MT9M114_DEFAULT_FIRST_EXP;
mt9m114_info = v4l2_get_subdev_hostdata(sd);
if (mt9m114_info == NULL)
if (!mt9m114_info)
return -EINVAL;
mt9m114_try_res(&width, &height);
@ -964,6 +965,7 @@ static int mt9m114_g_hflip(struct v4l2_subdev *sd, s32 *val)
struct i2c_client *c = v4l2_get_subdevdata(sd);
int ret;
u32 data;
ret = mt9m114_read_reg(c, MISENSOR_16BIT,
(u32)MISENSOR_READ_MODE, &data);
if (ret)
@ -1082,7 +1084,6 @@ static long mt9m114_s_exposure(struct v4l2_subdev *sd,
static long mt9m114_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
{
switch (cmd) {
case ATOMISP_IOC_S_EXPOSURE:
return mt9m114_s_exposure(sd, arg);
@ -1110,6 +1111,7 @@ static int mt9m114_g_exposure(struct v4l2_subdev *sd, s32 *value)
*value = coarse;
return 0;
}
#ifndef CSS15
/*
* This function will return the sensor supported max exposure zone number.
@ -1563,7 +1565,7 @@ mt9m114_s_config(struct v4l2_subdev *sd, int irq, void *platform_data)
struct i2c_client *client = v4l2_get_subdevdata(sd);
int ret;
if (NULL == platform_data)
if (!platform_data)
return -ENODEV;
dev->platform_data =
@ -1738,7 +1740,6 @@ static int mt9m114_enum_frame_size(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_frame_size_enum *fse)
{
unsigned int index = fse->index;
if (index >= N_RES)
@ -1757,7 +1758,7 @@ static int mt9m114_g_skip_frames(struct v4l2_subdev *sd, u32 *frames)
int index;
struct mt9m114_device *snr = to_mt9m114_sensor(sd);
if (frames == NULL)
if (!frames)
return -EINVAL;
for (index = 0; index < N_RES; index++) {

64
drivers/staging/media/atomisp/i2c/atomisp-ov2680.c
View File

@ -34,8 +34,8 @@
#include "ov2680.h"
static int h_flag = 0;
static int v_flag = 0;
static int h_flag;
static int v_flag;
static enum atomisp_bayer_order ov2680_bayer_order_mapping[] = {
atomisp_bayer_order_bggr,
atomisp_bayer_order_grbg,
@ -64,7 +64,7 @@ static int ov2680_read_reg(struct i2c_client *client,
return -EINVAL;
}
memset(msg, 0 , sizeof(msg));
memset(msg, 0, sizeof(msg));
msg[0].addr = client->addr;
msg[0].flags = 0;
@ -235,6 +235,7 @@ static int ov2680_write_reg_array(struct i2c_client *client,
const struct ov2680_reg *next = reglist;
struct ov2680_write_ctrl ctrl;
int err;
dev_dbg(&client->dev, "++++write reg array\n");
ctrl.index = 0;
for (; next->type != OV2680_TOK_TERM; next++) {
@ -250,7 +251,7 @@ static int ov2680_write_reg_array(struct i2c_client *client,
* If next address is not consecutive, data needs to be
* flushed before proceed.
*/
dev_dbg(&client->dev, "+++ov2680_write_reg_array reg=%x->%x\n", next->reg,next->val);
dev_dbg(&client->dev, "+++ov2680_write_reg_array reg=%x->%x\n", next->reg, next->val);
if (!__ov2680_write_reg_is_consecutive(client, &ctrl,
next)) {
err = __ov2680_flush_reg_array(client, &ctrl);
@ -269,9 +270,9 @@ static int ov2680_write_reg_array(struct i2c_client *client,
return __ov2680_flush_reg_array(client, &ctrl);
}
static int ov2680_g_focal(struct v4l2_subdev *sd, s32 *val)
{
*val = (OV2680_FOCAL_LENGTH_NUM << 16) | OV2680_FOCAL_LENGTH_DEM;
return 0;
}
@ -296,6 +297,7 @@ static int ov2680_g_bin_factor_x(struct v4l2_subdev *sd, s32 *val)
{
struct ov2680_device *dev = to_ov2680_sensor(sd);
struct i2c_client *client = v4l2_get_subdevdata(sd);
dev_dbg(&client->dev, "++++ov2680_g_bin_factor_x\n");
*val = ov2680_res[dev->fmt_idx].bin_factor_x;
@ -312,7 +314,6 @@ static int ov2680_g_bin_factor_y(struct v4l2_subdev *sd, s32 *val)
return 0;
}
static int ov2680_get_intg_factor(struct i2c_client *client,
struct camera_mipi_info *info,
const struct ov2680_resolution *res)
@ -323,6 +324,7 @@ static int ov2680_get_intg_factor(struct i2c_client *client,
unsigned int pix_clk_freq_hz;
u16 reg_val;
int ret;
dev_dbg(&client->dev, "++++ov2680_get_intg_factor\n");
if (!info)
return -EINVAL;
@ -398,7 +400,7 @@ static long __ov2680_set_exposure(struct v4l2_subdev *sd, int coarse_itg,
struct i2c_client *client = v4l2_get_subdevdata(sd);
struct ov2680_device *dev = to_ov2680_sensor(sd);
u16 vts;
int ret,exp_val;
int ret, exp_val;
dev_dbg(&client->dev,
"+++++++__ov2680_set_exposure coarse_itg %d, gain %d, digitgain %d++\n",
@ -408,7 +410,7 @@ static long __ov2680_set_exposure(struct v4l2_subdev *sd, int coarse_itg,
/* group hold */
ret = ov2680_write_reg(client, OV2680_8BIT,
OV2680_GROUP_ACCESS, 0x00);
OV2680_GROUP_ACCESS, 0x00);
if (ret) {
dev_err(&client->dev, "%s: write %x error, aborted\n",
__func__, OV2680_GROUP_ACCESS);
@ -417,7 +419,7 @@ static long __ov2680_set_exposure(struct v4l2_subdev *sd, int coarse_itg,
/* Increase the VTS to match exposure + MARGIN */
if (coarse_itg > vts - OV2680_INTEGRATION_TIME_MARGIN)
vts = (u16) coarse_itg + OV2680_INTEGRATION_TIME_MARGIN;
vts = (u16)coarse_itg + OV2680_INTEGRATION_TIME_MARGIN;
ret = ov2680_write_reg(client, OV2680_16BIT, OV2680_TIMING_VTS_H, vts);
if (ret) {
@ -525,6 +527,7 @@ static long ov2680_s_exposure(struct v4l2_subdev *sd,
/* we should not accept the invalid value below */
if (analog_gain == 0) {
struct i2c_client *client = v4l2_get_subdevdata(sd);
v4l2_err(client, "%s: invalid value\n", __func__);
return -EINVAL;
}
@ -533,13 +536,8 @@ static long ov2680_s_exposure(struct v4l2_subdev *sd,
return ov2680_set_exposure(sd, coarse_itg, analog_gain, digital_gain);
}
static long ov2680_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
{
switch (cmd) {
case ATOMISP_IOC_S_EXPOSURE:
return ov2680_s_exposure(sd, arg);
@ -607,6 +605,7 @@ static int ov2680_v_flip(struct v4l2_subdev *sd, s32 value)
int ret;
u16 val;
u8 index;
dev_dbg(&client->dev, "@%s: value:%d\n", __func__, value);
ret = ov2680_read_reg(client, OV2680_8BIT, OV2680_FLIP_REG, &val);
if (ret)
@ -620,7 +619,7 @@ static int ov2680_v_flip(struct v4l2_subdev *sd, s32 value)
OV2680_FLIP_REG, val);
if (ret)
return ret;
index = (v_flag>0?OV2680_FLIP_BIT:0) | (h_flag>0?OV2680_MIRROR_BIT:0);
index = (v_flag > 0 ? OV2680_FLIP_BIT : 0) | (h_flag > 0 ? OV2680_MIRROR_BIT : 0);
ov2680_info = v4l2_get_subdev_hostdata(sd);
if (ov2680_info) {
ov2680_info->raw_bayer_order = ov2680_bayer_order_mapping[index];
@ -638,6 +637,7 @@ static int ov2680_h_flip(struct v4l2_subdev *sd, s32 value)
int ret;
u16 val;
u8 index;
dev_dbg(&client->dev, "@%s: value:%d\n", __func__, value);
ret = ov2680_read_reg(client, OV2680_8BIT, OV2680_MIRROR_REG, &val);
@ -652,7 +652,7 @@ static int ov2680_h_flip(struct v4l2_subdev *sd, s32 value)
OV2680_MIRROR_REG, val);
if (ret)
return ret;
index = (v_flag>0?OV2680_FLIP_BIT:0) | (h_flag>0?OV2680_MIRROR_BIT:0);
index = (v_flag > 0 ? OV2680_FLIP_BIT : 0) | (h_flag > 0 ? OV2680_MIRROR_BIT : 0);
ov2680_info = v4l2_get_subdev_hostdata(sd);
if (ov2680_info) {
ov2680_info->raw_bayer_order = ov2680_bayer_order_mapping[index];
@ -846,6 +846,7 @@ static int power_ctrl(struct v4l2_subdev *sd, bool flag)
{
int ret = 0;
struct ov2680_device *dev = to_ov2680_sensor(sd);
if (!dev || !dev->platform_data)
return -ENODEV;
@ -973,7 +974,7 @@ static int ov2680_s_power(struct v4l2_subdev *sd, int on)
{
int ret;
if (on == 0){
if (on == 0) {
ret = power_down(sd);
} else {
ret = power_up(sd);
@ -1005,10 +1006,9 @@ static int distance(struct ov2680_resolution *res, u32 w, u32 h)
h_ratio = (res->height << 13) / h;
if (h_ratio == 0)
return -1;
match = abs(((w_ratio << 13) / h_ratio) - ((int)8192));
match = abs(((w_ratio << 13) / h_ratio) - 8192);
if ((w_ratio < (int)8192) || (h_ratio < (int)8192) ||
if ((w_ratio < 8192) || (h_ratio < 8192) ||
(match > LARGEST_ALLOWED_RATIO_MISMATCH))
return -1;
@ -1064,6 +1064,7 @@ static int ov2680_set_fmt(struct v4l2_subdev *sd,
struct camera_mipi_info *ov2680_info = NULL;
int ret = 0;
int idx = 0;
dev_dbg(&client->dev, "+++++ov2680_s_mbus_fmt+++++l\n");
if (format->pad)
return -EINVAL;
@ -1123,7 +1124,7 @@ static int ov2680_set_fmt(struct v4l2_subdev *sd,
if (v_flag)
ov2680_v_flip(sd, v_flag);
v4l2_info(client, "\n%s idx %d \n", __func__, dev->fmt_idx);
v4l2_info(client, "\n%s idx %d\n", __func__, dev->fmt_idx);
/*ret = startup(sd);
* if (ret)
@ -1173,7 +1174,7 @@ static int ov2680_detect(struct i2c_client *client)
}
ret = ov2680_read_reg(client, OV2680_8BIT,
OV2680_SC_CMMN_CHIP_ID_L, &low);
id = ((((u16) high) << 8) | (u16) low);
id = ((((u16)high) << 8) | (u16)low);
if (id != OV2680_ID) {
dev_err(&client->dev, "sensor ID error 0x%x\n", id);
@ -1182,7 +1183,7 @@ static int ov2680_detect(struct i2c_client *client)
ret = ov2680_read_reg(client, OV2680_8BIT,
OV2680_SC_CMMN_SUB_ID, &high);
revision = (u8) high & 0x0f;
revision = (u8)high & 0x0f;
dev_info(&client->dev, "sensor_revision id = 0x%x, rev= %d\n",
id, revision);
@ -1197,10 +1198,10 @@ static int ov2680_s_stream(struct v4l2_subdev *sd, int enable)
int ret;
mutex_lock(&dev->input_lock);
if(enable )
dev_dbg(&client->dev, "ov2680_s_stream one \n");
if (enable)
dev_dbg(&client->dev, "ov2680_s_stream one\n");
else
dev_dbg(&client->dev, "ov2680_s_stream off \n");
dev_dbg(&client->dev, "ov2680_s_stream off\n");
ret = ov2680_write_reg(client, OV2680_8BIT, OV2680_SW_STREAM,
enable ? OV2680_START_STREAMING :
@ -1220,7 +1221,6 @@ static int ov2680_s_stream(struct v4l2_subdev *sd, int enable)
return ret;
}
static int ov2680_s_config(struct v4l2_subdev *sd,
int irq, void *platform_data)
{
@ -1319,7 +1319,6 @@ static int ov2680_enum_frame_size(struct v4l2_subdev *sd,
fse->max_height = ov2680_res[index].height;
return 0;
}
static int ov2680_g_skip_frames(struct v4l2_subdev *sd, u32 *frames)
@ -1365,6 +1364,7 @@ static int ov2680_remove(struct i2c_client *client)
{
struct v4l2_subdev *sd = i2c_get_clientdata(client);
struct ov2680_device *dev = to_ov2680_sensor(sd);
dev_dbg(&client->dev, "ov2680_remove...\n");
dev->platform_data->csi_cfg(sd, 0);
@ -1391,7 +1391,7 @@ static int ov2680_probe(struct i2c_client *client)
mutex_init(&dev->input_lock);
dev->fmt_idx = 0;
v4l2_i2c_subdev_init(&(dev->sd), client, &ov2680_ops);
v4l2_i2c_subdev_init(&dev->sd, client, &ov2680_ops);
pdata = gmin_camera_platform_data(&dev->sd,
ATOMISP_INPUT_FORMAT_RAW_10,
@ -1399,7 +1399,7 @@ static int ov2680_probe(struct i2c_client *client)
if (!pdata) {
ret = -EINVAL;
goto out_free;
}
}
ret = ov2680_s_config(&dev->sd, client->irq, pdata);
if (ret)
@ -1438,11 +1438,11 @@ static int ov2680_probe(struct i2c_client *client)
if (ret)
{
ov2680_remove(client);
dev_dbg(&client->dev, "+++ remove ov2680 \n");
dev_dbg(&client->dev, "+++ remove ov2680\n");
}
return ret;
out_free:
dev_dbg(&client->dev, "+++ out free \n");
dev_dbg(&client->dev, "+++ out free\n");
v4l2_device_unregister_subdev(&dev->sd);
kfree(dev);
return ret;

20
drivers/staging/media/atomisp/i2c/atomisp-ov2722.c
View File

@ -55,7 +55,7 @@ static int ov2722_read_reg(struct i2c_client *client,
return -EINVAL;
}
memset(msg, 0 , sizeof(msg));
memset(msg, 0, sizeof(msg));
msg[0].addr = client->addr;
msg[0].flags = 0;
@ -259,6 +259,7 @@ static int ov2722_write_reg_array(struct i2c_client *client,
return __ov2722_flush_reg_array(client, &ctrl);
}
static int ov2722_g_focal(struct v4l2_subdev *sd, s32 *val)
{
*val = (OV2722_FOCAL_LENGTH_NUM << 16) | OV2722_FOCAL_LENGTH_DEM;
@ -318,7 +319,7 @@ static int ov2722_get_intg_factor(struct i2c_client *client,
return ret;
pre_pll_clk_div = (pre_pll_clk_div & 0x70) >> 4;
if (0 == pre_pll_clk_div)
if (!pre_pll_clk_div)
return -EINVAL;
pll_multiplier = pll_multiplier & 0x7f;
@ -481,6 +482,7 @@ static long ov2722_s_exposure(struct v4l2_subdev *sd,
/* we should not accept the invalid value below. */
if (gain == 0) {
struct i2c_client *client = v4l2_get_subdevdata(sd);
v4l2_err(client, "%s: invalid value\n", __func__);
return -EINVAL;
}
@ -490,7 +492,6 @@ static long ov2722_s_exposure(struct v4l2_subdev *sd,
static long ov2722_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
{
switch (cmd) {
case ATOMISP_IOC_S_EXPOSURE:
return ov2722_s_exposure(sd, arg);
@ -540,6 +541,7 @@ static int ov2722_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
container_of(ctrl->handler, struct ov2722_device, ctrl_handler);
int ret = 0;
unsigned int val;
switch (ctrl->id) {
case V4L2_CID_EXPOSURE_ABSOLUTE:
ret = ov2722_q_exposure(&dev->sd, &ctrl->val);
@ -768,6 +770,7 @@ static int power_down(struct v4l2_subdev *sd)
static int ov2722_s_power(struct v4l2_subdev *sd, int on)
{
int ret;
if (on == 0)
return power_down(sd);
else {
@ -881,6 +884,7 @@ static int ov2722_set_fmt(struct v4l2_subdev *sd,
struct camera_mipi_info *ov2722_info = NULL;
int ret = 0;
int idx;
if (format->pad)
return -EINVAL;
if (!fmt)
@ -919,6 +923,7 @@ static int ov2722_set_fmt(struct v4l2_subdev *sd,
ret = startup(sd);
if (ret) {
int i = 0;
dev_err(&client->dev, "ov2722 startup err, retry to power up\n");
for (i = 0; i < OV2722_POWER_UP_RETRY_NUM; i++) {
dev_err(&client->dev,
@ -953,6 +958,7 @@ err:
mutex_unlock(&dev->input_lock);
return ret;
}
static int ov2722_get_fmt(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_format *format)
@ -1000,7 +1006,7 @@ static int ov2722_detect(struct i2c_client *client)
ret = ov2722_read_reg(client, OV2722_8BIT,
OV2722_SC_CMMN_SUB_ID, &high);
revision = (u8) high & 0x0f;
revision = (u8)high & 0x0f;
dev_dbg(&client->dev, "sensor_revision = 0x%x\n", revision);
dev_dbg(&client->dev, "detect ov2722 success\n");
@ -1122,10 +1128,8 @@ static int ov2722_enum_frame_size(struct v4l2_subdev *sd,
fse->max_height = ov2722_res[index].height;
return 0;
}
static int ov2722_g_skip_frames(struct v4l2_subdev *sd, u32 *frames)
{
struct ov2722_device *dev = to_ov2722_sensor(sd);
@ -1169,6 +1173,7 @@ static int ov2722_remove(struct i2c_client *client)
{
struct v4l2_subdev *sd = i2c_get_clientdata(client);
struct ov2722_device *dev = to_ov2722_sensor(sd);
dev_dbg(&client->dev, "ov2722_remove...\n");
dev->platform_data->csi_cfg(sd, 0);
@ -1187,6 +1192,7 @@ static int __ov2722_init_ctrl_handler(struct ov2722_device *dev)
{
struct v4l2_ctrl_handler *hdl;
unsigned int i;
hdl = &dev->ctrl_handler;
v4l2_ctrl_handler_init(&dev->ctrl_handler, ARRAY_SIZE(ov2722_controls));
for (i = 0; i < ARRAY_SIZE(ov2722_controls); i++)
@ -1216,7 +1222,7 @@ static int ov2722_probe(struct i2c_client *client)
mutex_init(&dev->input_lock);
dev->fmt_idx = 0;
v4l2_i2c_subdev_init(&(dev->sd), client, &ov2722_ops);
v4l2_i2c_subdev_init(&dev->sd, client, &ov2722_ops);
ovpdev = gmin_camera_platform_data(&dev->sd,
ATOMISP_INPUT_FORMAT_RAW_10,

2
drivers/staging/media/atomisp/i2c/gc0310.h
View File

@ -396,9 +396,9 @@ static struct gc0310_resolution gc0310_res_preview[] = {
.regs = gc0310_VGA_30fps,
},
};
#define N_RES_PREVIEW (ARRAY_SIZE(gc0310_res_preview))
static struct gc0310_resolution *gc0310_res = gc0310_res_preview;
static unsigned long N_RES = N_RES_PREVIEW;
#endif

5
drivers/staging/media/atomisp/i2c/gc2235.h
View File

@ -286,6 +286,7 @@ static struct gc2235_reg const gc2235_init_settings[] = {
{ GC2235_8BIT, 0xfe, 0x00 }, /* switch to P0 */
{ GC2235_TOK_TERM, 0, 0 }
};
/*
* Register settings for various resolution
*/
@ -530,7 +531,6 @@ static struct gc2235_reg const gc2235_1616_1216_30fps[] = {
};
static struct gc2235_resolution gc2235_res_preview[] = {
{
.desc = "gc2235_1600_900_30fps",
.width = 1600,
@ -579,6 +579,7 @@ static struct gc2235_resolution gc2235_res_preview[] = {
},
};
#define N_RES_PREVIEW (ARRAY_SIZE(gc2235_res_preview))
/*
@ -634,6 +635,7 @@ static struct gc2235_resolution gc2235_res_still[] = {
},
};
#define N_RES_STILL (ARRAY_SIZE(gc2235_res_still))
static struct gc2235_resolution gc2235_res_video[] = {
@ -669,6 +671,7 @@ static struct gc2235_resolution gc2235_res_video[] = {
},
};
#define N_RES_VIDEO (ARRAY_SIZE(gc2235_res_video))
#endif

17
drivers/staging/media/atomisp/i2c/mt9m114.h
View File

@ -53,8 +53,8 @@
#define MISENSOR_TOK_POLL 0xfc00 /* token indicating poll instruction */
#define MISENSOR_TOK_RMW 0x0010 /* RMW operation */
#define MISENSOR_TOK_MASK 0xfff0
#define MISENSOR_AWB_STEADY (1<<0) /* awb steady */
#define MISENSOR_AE_READY (1<<3) /* ae status ready */
#define MISENSOR_AWB_STEADY BIT(0) /* awb steady */
#define MISENSOR_AE_READY BIT(3) /* ae status ready */
/* mask to set sensor read_mode via misensor_rmw_reg */
#define MISENSOR_R_MODE_MASK 0x0330
@ -127,13 +127,12 @@
#define MT9M114_COARSE_INTG_TIME_MIN 1
#define MT9M114_COARSE_INTG_TIME_MAX_MARGIN 6
/* ulBPat; */
#define MT9M114_BPAT_RGRGGBGB (1 << 0)
#define MT9M114_BPAT_GRGRBGBG (1 << 1)
#define MT9M114_BPAT_GBGBRGRG (1 << 2)
#define MT9M114_BPAT_BGBGGRGR (1 << 3)
#define MT9M114_BPAT_RGRGGBGB BIT(0)
#define MT9M114_BPAT_GRGRBGBG BIT(1)
#define MT9M114_BPAT_GBGBRGRG BIT(2)
#define MT9M114_BPAT_BGBGGRGR BIT(3)
#define MT9M114_FOCAL_LENGTH_NUM 208 /*2.08mm*/
#define MT9M114_FOCAL_LENGTH_DEM 100
@ -169,6 +168,7 @@ enum {
MT9M114_RES_864P,
MT9M114_RES_960P,
};
#define MT9M114_RES_960P_SIZE_H 1296
#define MT9M114_RES_960P_SIZE_V 976
#define MT9M114_RES_720P_SIZE_H 1280
@ -204,6 +204,7 @@ enum poll_reg {
PRE_POLLING,
POST_POLLING,
};
/*
* struct misensor_reg - MI sensor register format
* @length: length of the register
@ -388,6 +389,7 @@ static struct mt9m114_res_struct mt9m114_res[] = {
.bin_mode = 0,
},
};
#define N_RES (ARRAY_SIZE(mt9m114_res))
#if 0 /* Currently unused */
@ -795,6 +797,7 @@ static struct misensor_reg const mt9m114_common[] = {
{MISENSOR_TOK_TERM, 0, 0},
};
#if 0 /* Currently unused */
static struct misensor_reg const mt9m114_antiflicker_50hz[] = {
{MISENSOR_16BIT, 0x098E, 0xC88B},

15
drivers/staging/media/atomisp/i2c/ov2680.h
View File

@ -132,10 +132,8 @@
#define OV2680_START_STREAMING 0x01
#define OV2680_STOP_STREAMING 0x00
#define OV2680_INVALID_CONFIG 0xffffffff
struct regval_list {
u16 reg_num;
u8 value;
@ -294,7 +292,6 @@ struct ov2680_format {
{OV2680_TOK_TERM, 0, 0}
};
#if 0 /* None of the definitions below are used currently */
/*
* 176x144 30fps VBlanking 1lane 10Bit (binning)
@ -427,7 +424,6 @@ struct ov2680_format {
{OV2680_TOK_TERM, 0, 0}
};
/*
* 656x496 30fps VBlanking 1lane 10Bit (binning)
*/
@ -641,12 +637,12 @@ struct ov2680_format {
{OV2680_8BIT, 0x3821, 0x00}, //miror/flip
// {OV2680_8BIT, 0x5090, 0x0c},
{OV2680_TOK_TERM, 0, 0}
};
};
/*
* 1456*1096 30fps VBlanking 1lane 10bit(no-scaling)
*/
static struct ov2680_reg const ov2680_1456x1096_30fps[]= {
static struct ov2680_reg const ov2680_1456x1096_30fps[] = {
{OV2680_8BIT, 0x3086, 0x00},
{OV2680_8BIT, 0x3501, 0x48},
{OV2680_8BIT, 0x3502, 0xe0},
@ -773,7 +769,7 @@ struct ov2680_format {
{OV2680_8BIT, 0x4009, 0x09},
{OV2680_8BIT, 0x5081, 0x41},
{OV2680_TOK_TERM, 0, 0}
};
};
#endif
/*
* 1616x1216 30fps VBlanking 1lane 10Bit
@ -821,7 +817,7 @@ struct ov2680_format {
static struct ov2680_resolution ov2680_res_preview[] = {
{
.desc = "ov2680_1616x1216_30fps",
.width = 1616,
.width = 1616,
.height = 1216,
.pix_clk_freq = 66,
.fps = 30,
@ -834,7 +830,7 @@ struct ov2680_format {
.skip_frames = 3,
.regs = ov2680_1616x1216_30fps,
},
{
{
.desc = "ov2680_1616x916_30fps",
.width = 1616,
.height = 916,
@ -850,6 +846,7 @@ struct ov2680_format {
.regs = ov2680_1616x916_30fps,
},
};
#define N_RES_PREVIEW (ARRAY_SIZE(ov2680_res_preview))
static struct ov2680_resolution *ov2680_res = ov2680_res_preview;

4
drivers/staging/media/atomisp/i2c/ov2722.h
View File

@ -786,6 +786,7 @@ static struct ov2722_reg const ov2722_1452_1092_30fps[] = {
{OV2722_8BIT, 0x3509, 0x00},
{OV2722_TOK_TERM, 0, 0}
};
#if 0
static struct ov2722_reg const ov2722_1M3_30fps[] = {
{OV2722_8BIT, 0x3718, 0x10},
@ -1152,6 +1153,7 @@ static struct ov2722_resolution ov2722_res_preview[] = {
.mipi_freq = 345600,
},
};
#define N_RES_PREVIEW (ARRAY_SIZE(ov2722_res_preview))
/*
@ -1209,6 +1211,7 @@ struct ov2722_resolution ov2722_res_still[] = {
.mipi_freq = 345600,
},
};
#define N_RES_STILL (ARRAY_SIZE(ov2722_res_still))
struct ov2722_resolution ov2722_res_video[] = {
@ -1260,6 +1263,7 @@ struct ov2722_resolution ov2722_res_video[] = {
.mipi_freq = 345600,
},
};
#define N_RES_VIDEO (ARRAY_SIZE(ov2722_res_video))
#endif

1
drivers/staging/media/atomisp/i2c/ov5693/ad5823.h
View File

@ -20,7 +20,6 @@
#include <linux/types.h>
#define AD5823_VCM_ADDR 0x0c
#define AD5823_REG_RESET 0x01

27
drivers/staging/media/atomisp/i2c/ov5693/atomisp-ov5693.c
View File

@ -119,8 +119,7 @@ static int ad5823_i2c_read(struct i2c_client *client, u8 reg, u8 *val)
return 0;
}
static const uint32_t ov5693_embedded_effective_size = 28;
static const u32 ov5693_embedded_effective_size = 28;
/* i2c read/write stuff */
static int ov5693_read_reg(struct i2c_client *client,
@ -413,6 +412,7 @@ static int ov5693_write_reg_array(struct i2c_client *client,
return __ov5693_flush_reg_array(client, &ctrl);
}
static int ov5693_g_focal(struct v4l2_subdev *sd, s32 *val)
{
*val = (OV5693_FOCAL_LENGTH_NUM << 16) | OV5693_FOCAL_LENGTH_DEM;
@ -463,7 +463,7 @@ static int ov5693_get_intg_factor(struct i2c_client *client,
u16 reg_val;
int ret;
if (info == NULL)
if (!info)
return -EINVAL;
/* pixel clock */
@ -576,7 +576,7 @@ static long __ov5693_set_exposure(struct v4l2_subdev *sd, int coarse_itg,
}
/* Increase the VTS to match exposure + MARGIN */
if (coarse_itg > vts - OV5693_INTEGRATION_TIME_MARGIN)
vts = (u16) coarse_itg + OV5693_INTEGRATION_TIME_MARGIN;
vts = (u16)coarse_itg + OV5693_INTEGRATION_TIME_MARGIN;
ret = ov5693_write_reg(client, OV5693_8BIT,
OV5693_TIMING_VTS_H, (vts >> 8) & 0xFF);
@ -718,7 +718,7 @@ static int ov5693_read_otp_reg_array(struct i2c_client *client, u16 size,
u16 *pVal = NULL;
for (index = 0; index <= size; index++) {
pVal = (u16 *) (buf + index);
pVal = (u16 *)(buf + index);
ret =
ov5693_read_reg(client, OV5693_8BIT, addr + index,
pVal);
@ -873,12 +873,10 @@ out:
priv->size = dev->otp_size;
return 0;
}
static long ov5693_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
{
switch (cmd) {
case ATOMISP_IOC_S_EXPOSURE:
return ov5693_s_exposure(sd, arg);
@ -1588,7 +1586,7 @@ static int ov5693_set_fmt(struct v4l2_subdev *sd,
if (!fmt)
return -EINVAL;
ov5693_info = v4l2_get_subdev_hostdata(sd);
if (ov5693_info == NULL)
if (!ov5693_info)
return -EINVAL;
mutex_lock(&dev->input_lock);
@ -1624,7 +1622,7 @@ static int ov5693_set_fmt(struct v4l2_subdev *sd,
for (i = 0; i < OV5693_POWER_UP_RETRY_NUM; i++) {
dev_err(&client->dev,
"ov5693 retry to power up %d/%d times, result: ",
i+1, OV5693_POWER_UP_RETRY_NUM);
i + 1, OV5693_POWER_UP_RETRY_NUM);
power_down(sd);
ret = power_up(sd);
if (!ret) {
@ -1670,6 +1668,7 @@ err:
mutex_unlock(&dev->input_lock);
return ret;
}
static int ov5693_get_fmt(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_format *format)
@ -1709,7 +1708,7 @@ static int ov5693_detect(struct i2c_client *client)
}
ret = ov5693_read_reg(client, OV5693_8BIT,
OV5693_SC_CMMN_CHIP_ID_L, &low);
id = ((((u16) high) << 8) | (u16) low);
id = ((((u16)high) << 8) | (u16)low);
if (id != OV5693_ID) {
dev_err(&client->dev, "sensor ID error 0x%x\n", id);
@ -1718,7 +1717,7 @@ static int ov5693_detect(struct i2c_client *client)
ret = ov5693_read_reg(client, OV5693_8BIT,
OV5693_SC_CMMN_SUB_ID, &high);
revision = (u8) high & 0x0f;
revision = (u8)high & 0x0f;
dev_dbg(&client->dev, "sensor_revision = 0x%x\n", revision);
dev_dbg(&client->dev, "detect ov5693 success\n");
@ -1742,7 +1741,6 @@ static int ov5693_s_stream(struct v4l2_subdev *sd, int enable)
return ret;
}
static int ov5693_s_config(struct v4l2_subdev *sd,
int irq, void *platform_data)
{
@ -1750,7 +1748,7 @@ static int ov5693_s_config(struct v4l2_subdev *sd,
struct i2c_client *client = v4l2_get_subdevdata(sd);
int ret = 0;
if (platform_data == NULL)
if (!platform_data)
return -ENODEV;
dev->platform_data =
@ -1846,7 +1844,6 @@ static int ov5693_enum_frame_size(struct v4l2_subdev *sd,
fse->max_height = ov5693_res[index].height;
return 0;
}
static const struct v4l2_subdev_video_ops ov5693_video_ops = {
@ -1921,7 +1918,7 @@ static int ov5693_probe(struct i2c_client *client)
mutex_init(&dev->input_lock);
dev->fmt_idx = 0;
v4l2_i2c_subdev_init(&(dev->sd), client, &ov5693_ops);
v4l2_i2c_subdev_init(&dev->sd, client, &ov5693_ops);
pdata = gmin_camera_platform_data(&dev->sd,
ATOMISP_INPUT_FORMAT_RAW_10,

9
drivers/staging/media/atomisp/i2c/ov5693/ov5693.h
View File

@ -36,7 +36,6 @@
*/
#define ENABLE_NON_PREVIEW 0
#define OV5693_POWER_UP_RETRY_NUM 5
/* Defines for register writes and register array processing */
@ -174,7 +173,7 @@
#define OV5693_OTP_START_ADDR 0x3D00
#define OV5693_OTP_END_ADDR 0x3D0F
#define OV5693_OTP_DATA_SIZE 320
#define OV5693_OTP_PROGRAM_REG 0x3D80
#define OV5693_OTP_PROGRAM_REG 0x3D80
#define OV5693_OTP_READ_REG 0x3D81 // 1:Enable 0:disable
#define OV5693_OTP_BANK_REG 0x3D84 //otp bank and mode
#define OV5693_OTP_READY_REG_DONE 1
@ -586,7 +585,6 @@ static struct ov5693_reg const ov5693_1296x976[] = {
};
/*
* 336x256 30fps 17ms VBlanking 2lane 10Bit (Scaling)
DS from 2564x1956
@ -675,7 +673,6 @@ static struct ov5693_reg const ov5693_192x160[] = {
{OV5693_TOK_TERM, 0, 0}
};
static struct ov5693_reg const ov5693_736x496[] = {
{OV5693_8BIT, 0x3501, 0x3d},
{OV5693_8BIT, 0x3502, 0x00},
@ -865,7 +862,6 @@ static struct ov5693_reg const ov5693_1616x1216_30fps[] = {
{OV5693_TOK_TERM, 0, 0}
};
/*
* 1940x1096 30fps 8.8ms VBlanking 2lane 10bit (Scaling)
*/
@ -1161,6 +1157,7 @@ static struct ov5693_resolution ov5693_res_preview[] = {
.regs = ov5693_2576x1936_30fps,
},
};
#define N_RES_PREVIEW (ARRAY_SIZE(ov5693_res_preview))
/*
@ -1240,6 +1237,7 @@ struct ov5693_resolution ov5693_res_still[] = {
.regs = ov5693_2592x1944_30fps,
},
};
#define N_RES_STILL (ARRAY_SIZE(ov5693_res_still))
struct ov5693_resolution ov5693_res_video[] = {
@ -1384,6 +1382,7 @@ struct ov5693_resolution ov5693_res_video[] = {
.regs = ov5693_2592x1944_30fps,
},
};
#define N_RES_VIDEO (ARRAY_SIZE(ov5693_res_video))
#endif

144
drivers/staging/media/atomisp/include/linux/atomisp.h
View File

@ -176,14 +176,14 @@ struct atomisp_3a_config {
};
struct atomisp_dvs_grid_info {
uint32_t enable;
uint32_t width;
uint32_t aligned_width;
uint32_t height;
uint32_t aligned_height;
uint32_t bqs_per_grid_cell;
uint32_t num_hor_coefs;
uint32_t num_ver_coefs;
u32 enable;
u32 width;
u32 aligned_width;
u32 height;
u32 aligned_height;
u32 bqs_per_grid_cell;
u32 num_hor_coefs;
u32 num_ver_coefs;
};
struct atomisp_dvs_envelop {
@ -192,16 +192,16 @@ struct atomisp_dvs_envelop {
};
struct atomisp_grid_info {
uint32_t enable;
uint32_t use_dmem;
uint32_t has_histogram;
uint32_t s3a_width;
uint32_t s3a_height;
uint32_t aligned_width;
uint32_t aligned_height;
uint32_t s3a_bqs_per_grid_cell;
uint32_t deci_factor_log2;
uint32_t elem_bit_depth;
u32 enable;
u32 use_dmem;
u32 has_histogram;
u32 s3a_width;
u32 s3a_height;
u32 aligned_width;
u32 aligned_height;
u32 s3a_bqs_per_grid_cell;
u32 deci_factor_log2;
u32 elem_bit_depth;
};
struct atomisp_dis_vector {
@ -209,7 +209,6 @@ struct atomisp_dis_vector {
int y;
};
/* DVS 2.0 Coefficient types. This structure contains 4 pointers to
* arrays that contain the coeffients for each type.
*/
@ -245,14 +244,14 @@ struct atomisp_dvs2_statistics {
struct atomisp_dis_statistics {
struct atomisp_dvs2_statistics dvs2_stat;
uint32_t exp_id;
u32 exp_id;
};
struct atomisp_3a_rgby_output {
uint32_t r;
uint32_t g;
uint32_t b;
uint32_t y;
u32 r;
u32 g;
u32 b;
u32 y;
};
/*
@ -273,33 +272,33 @@ struct atomisp_metadata_with_type {
/* to specify which type of metadata to get */
enum atomisp_metadata_type type;
void __user *data;
uint32_t width;
uint32_t height;
uint32_t stride; /* in bytes */
uint32_t exp_id; /* exposure ID */
uint32_t *effective_width; /* mipi packets valid data size */
u32 width;
u32 height;
u32 stride; /* in bytes */
u32 exp_id; /* exposure ID */
u32 *effective_width; /* mipi packets valid data size */
};
struct atomisp_metadata {
void __user *data;
uint32_t width;
uint32_t height;
uint32_t stride; /* in bytes */
uint32_t exp_id; /* exposure ID */
uint32_t *effective_width; /* mipi packets valid data size */
u32 width;
u32 height;
u32 stride; /* in bytes */
u32 exp_id; /* exposure ID */
u32 *effective_width; /* mipi packets valid data size */
};
struct atomisp_ext_isp_ctrl {
uint32_t id;
uint32_t data;
u32 id;
u32 data;
};
struct atomisp_3a_statistics {
struct atomisp_grid_info grid_info;
struct atomisp_3a_output __user *data;
struct atomisp_3a_rgby_output __user *rgby_data;
uint32_t exp_id; /* exposure ID */
uint32_t isp_config_id; /* isp config ID */
u32 exp_id; /* exposure ID */
u32 isp_config_id; /* isp config ID */
};
/**
@ -384,24 +383,24 @@ struct atomisp_xnr_config {
/* metadata config */
struct atomisp_metadata_config {
uint32_t metadata_height;
uint32_t metadata_stride;
u32 metadata_height;
u32 metadata_stride;
};
/*
* Generic resolution structure.
*/
struct atomisp_resolution {
uint32_t width; /** Width */
uint32_t height; /** Height */
u32 width; /** Width */
u32 height; /** Height */
};
/*
* This specifies the coordinates (x,y)
*/
struct atomisp_zoom_point {
int32_t x; /** x coordinate */
int32_t y; /** y coordinate */
s32 x; /** x coordinate */
s32 y; /** y coordinate */
};
/*
@ -413,8 +412,8 @@ struct atomisp_zoom_region {
};
struct atomisp_dz_config {
uint32_t dx; /** Horizontal zoom factor */
uint32_t dy; /** Vertical zoom factor */
u32 dx; /** Horizontal zoom factor */
u32 dy; /** Vertical zoom factor */
struct atomisp_zoom_region zoom_region; /** region for zoom */
};
@ -454,19 +453,19 @@ struct atomisp_dvs2_bq_resolutions {
};
struct atomisp_dvs_6axis_config {
uint32_t exp_id;
uint32_t width_y;
uint32_t height_y;
uint32_t width_uv;
uint32_t height_uv;
uint32_t *xcoords_y;
uint32_t *ycoords_y;
uint32_t *xcoords_uv;
uint32_t *ycoords_uv;
u32 exp_id;
u32 width_y;
u32 height_y;
u32 width_uv;
u32 height_uv;
u32 *xcoords_y;
u32 *ycoords_y;
u32 *xcoords_uv;
u32 *ycoords_uv;
};
struct atomisp_formats_config {
uint32_t video_full_range_flag;
u32 video_full_range_flag;
};
struct atomisp_parameters {
@ -543,7 +542,7 @@ struct atomisp_parameters {
* Unique ID to track which config was actually applied to a particular
* frame, driver will send this id back with output frame together.
*/
uint32_t isp_config_id;
u32 isp_config_id;
/*
* Switch to control per_frame setting:
@ -551,7 +550,7 @@ struct atomisp_parameters {
* 1: this is a per_frame setting
* PLEASE KEEP THIS AT THE END OF THE STRUCTURE!!
*/
uint32_t per_frame_setting;
u32 per_frame_setting;
};
#define ATOMISP_GAMMA_TABLE_SIZE 1024
@ -574,7 +573,7 @@ struct atomisp_morph_table {
};
#define ATOMISP_NUM_SC_COLORS 4
#define ATOMISP_SC_FLAG_QUERY (1 << 0)
#define ATOMISP_SC_FLAG_QUERY BIT(0)
struct atomisp_shading_table {
__u32 enable;
@ -669,9 +668,9 @@ struct atomisp_sensor_mode_data {
unsigned int crop_vertical_end;
unsigned int output_width; /* input size to ISP after binning/scaling */
unsigned int output_height;
uint8_t binning_factor_x; /* horizontal binning factor used */
uint8_t binning_factor_y; /* vertical binning factor used */
uint16_t hts;
u8 binning_factor_x; /* horizontal binning factor used */
u8 binning_factor_y; /* vertical binning factor used */
u16 hts;
};
struct atomisp_exposure {
@ -696,8 +695,8 @@ enum atomisp_focus_hp {
};
/* Masks */
#define ATOMISP_FOCUS_STATUS_MOVING (1U << 0)
#define ATOMISP_FOCUS_STATUS_ACCEPTS_NEW_MOVE (1U << 1)
#define ATOMISP_FOCUS_STATUS_MOVING BIT(0)
#define ATOMISP_FOCUS_STATUS_ACCEPTS_NEW_MOVE BIT(1)
#define ATOMISP_FOCUS_STATUS_HOME_POSITION (3U << 2)
enum atomisp_camera_port {
@ -887,6 +886,7 @@ struct atomisp_acc_fw_load_to_pipe {
__u32 type; /* Binary type */
__u32 reserved[3]; /* Set to zero */
};
/*
* Set Senor run mode
*/
@ -894,12 +894,12 @@ struct atomisp_s_runmode {
__u32 mode;
};
#define ATOMISP_ACC_FW_LOAD_FL_PREVIEW (1 << 0)
#define ATOMISP_ACC_FW_LOAD_FL_COPY (1 << 1)
#define ATOMISP_ACC_FW_LOAD_FL_VIDEO (1 << 2)
#define ATOMISP_ACC_FW_LOAD_FL_CAPTURE (1 << 3)
#define ATOMISP_ACC_FW_LOAD_FL_ACC (1 << 4)
#define ATOMISP_ACC_FW_LOAD_FL_ENABLE (1 << 16)
#define ATOMISP_ACC_FW_LOAD_FL_PREVIEW BIT(0)
#define ATOMISP_ACC_FW_LOAD_FL_COPY BIT(1)
#define ATOMISP_ACC_FW_LOAD_FL_VIDEO BIT(2)
#define ATOMISP_ACC_FW_LOAD_FL_CAPTURE BIT(3)
#define ATOMISP_ACC_FW_LOAD_FL_ACC BIT(4)
#define ATOMISP_ACC_FW_LOAD_FL_ENABLE BIT(16)
#define ATOMISP_ACC_FW_LOAD_TYPE_NONE 0 /* Normal binary: don't use */
#define ATOMISP_ACC_FW_LOAD_TYPE_OUTPUT 1 /* Stage on output */
@ -1285,8 +1285,8 @@ struct atomisp_sensor_ae_bracketing_lut {
/* Query sensor's 2A status */
#define V4L2_CID_2A_STATUS (V4L2_CID_CAMERA_LASTP1 + 18)
#define V4L2_2A_STATUS_AE_READY (1 << 0)
#define V4L2_2A_STATUS_AWB_READY (1 << 1)
#define V4L2_2A_STATUS_AE_READY BIT(0)
#define V4L2_2A_STATUS_AWB_READY BIT(1)
#define V4L2_CID_FMT_AUTO (V4L2_CID_CAMERA_LASTP1 + 19)

6
drivers/staging/media/atomisp/include/linux/atomisp_gmin_platform.h
View File

@ -18,14 +18,14 @@
#include "atomisp_platform.h"
int atomisp_register_i2c_module(struct v4l2_subdev *subdev,
struct camera_sensor_platform_data *plat_data,
enum intel_v4l2_subdev_type type);
struct camera_sensor_platform_data *plat_data,
enum intel_v4l2_subdev_type type);
struct v4l2_subdev *atomisp_gmin_find_subdev(struct i2c_adapter *adapter,
struct i2c_board_info *board_info);
int atomisp_gmin_remove_subdev(struct v4l2_subdev *sd);
int gmin_get_var_int(struct device *dev, const char *var, int def);
int camera_sensor_csi(struct v4l2_subdev *sd, u32 port,
u32 lanes, u32 format, u32 bayer_order, int flag);
u32 lanes, u32 format, u32 bayer_order, int flag);
struct camera_sensor_platform_data *gmin_camera_platform_data(
struct v4l2_subdev *subdev,
enum atomisp_input_format csi_format,

12
drivers/staging/media/atomisp/include/linux/atomisp_platform.h
View File

@ -106,8 +106,6 @@ enum atomisp_input_format {
#define N_ATOMISP_INPUT_FORMAT (ATOMISP_INPUT_FORMAT_USER_DEF8 + 1)
enum intel_v4l2_subdev_type {
RAW_CAMERA = 1,
SOC_CAMERA = 2,
@ -228,13 +226,13 @@ struct camera_mipi_info {
enum atomisp_bayer_order raw_bayer_order;
struct atomisp_sensor_mode_data data;
enum atomisp_input_format metadata_format;
uint32_t metadata_width;
uint32_t metadata_height;
const uint32_t *metadata_effective_width;
u32 metadata_width;
u32 metadata_height;
const u32 *metadata_effective_width;
};
extern const struct atomisp_platform_data *atomisp_get_platform_data(void);
extern const struct atomisp_camera_caps *atomisp_get_default_camera_caps(void);
const struct atomisp_platform_data *atomisp_get_platform_data(void);
const struct atomisp_camera_caps *atomisp_get_default_camera_caps(void);
/* API from old platform_camera.h, new CPUID implementation */
#define __IS_SOC(x) (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && \

7
drivers/staging/media/atomisp/include/linux/libmsrlisthelper.h
View File

@ -18,11 +18,10 @@
struct i2c_client;
struct firmware;
extern int load_msr_list(struct i2c_client *client, char *path,
int load_msr_list(struct i2c_client *client, char *path,
const struct firmware **fw);
extern int apply_msr_data(struct i2c_client *client, const struct firmware *fw);
extern void release_msr_list(struct i2c_client *client,
int apply_msr_data(struct i2c_client *client, const struct firmware *fw);
void release_msr_list(struct i2c_client *client,
const struct firmware *fw);
#endif /* ifndef __LIBMSRLISTHELPER_H__ */

7
drivers/staging/media/atomisp/include/media/lm3554.h
View File

@ -91,8 +91,8 @@
#define LM3554_CLAMP_PERCENTAGE(val) \
clamp(val, LM3554_MIN_PERCENT, LM3554_MAX_PERCENT)
#define LM3554_VALUE_TO_PERCENT(v, step) (((((unsigned long)(v))*(step))+50)/100)
#define LM3554_PERCENT_TO_VALUE(p, step) (((((unsigned long)(p))*100)+(step>>1))/(step))
#define LM3554_VALUE_TO_PERCENT(v, step) (((((unsigned long)(v)) * (step)) + 50) / 100)
#define LM3554_PERCENT_TO_VALUE(p, step) (((((unsigned long)(p)) * 100) + (step >> 1)) / (step))
/* Product specific limits
* TODO: get these from platform data */
@ -100,7 +100,7 @@
/* Flash brightness, input is percentage, output is [0..15] */
#define LM3554_FLASH_STEP \
((100ul*(LM3554_MAX_PERCENT)+((LM3554_FLASH_MAX_LVL)>>1))/((LM3554_FLASH_MAX_LVL)))
((100ul * (LM3554_MAX_PERCENT) + ((LM3554_FLASH_MAX_LVL) >> 1)) / ((LM3554_FLASH_MAX_LVL)))
#define LM3554_FLASH_DEFAULT_BRIGHTNESS \
LM3554_VALUE_TO_PERCENT(13, LM3554_FLASH_STEP)
@ -128,4 +128,3 @@ struct lm3554_platform_data {
};
#endif /* _LM3554_H_ */

1
drivers/staging/media/atomisp/pci/atomisp2/atomisp_acc.h
View File

@ -70,7 +70,6 @@ int atomisp_acc_unmap(struct atomisp_sub_device *asd,
int atomisp_acc_s_mapped_arg(struct atomisp_sub_device *asd,
struct atomisp_acc_s_mapped_arg *arg);
/*
* Start acceleration.
* Return immediately, acceleration is left running in background.

169
drivers/staging/media/atomisp/pci/atomisp2/atomisp_cmd.c
View File

@ -60,7 +60,6 @@
#include "error_support.h"
#include "hrt/bits.h"
/* We should never need to run the flash for more than 2 frames.
* At 15fps this means 133ms. We set the timeout a bit longer.
* Each flash driver is supposed to set its own timeout, but
@ -200,6 +199,7 @@ static int write_target_freq_to_hw(struct atomisp_device *isp,
return 0;
}
int atomisp_freq_scaling(struct atomisp_device *isp,
enum atomisp_dfs_mode mode,
bool force)
@ -436,7 +436,6 @@ static void atomisp_reset_event(struct atomisp_sub_device *asd)
v4l2_event_queue(asd->subdev.devnode, &event);
}
static void print_csi_rx_errors(enum mipi_port_id port,
struct atomisp_device *isp)
{
@ -475,6 +474,7 @@ static void print_csi_rx_errors(enum mipi_port_id port,
static void clear_irq_reg(struct atomisp_device *isp)
{
u32 msg_ret;
pci_read_config_dword(isp->pdev, PCI_INTERRUPT_CTRL, &msg_ret);
msg_ret |= 1 << INTR_IIR;
pci_write_config_dword(isp->pdev, PCI_INTERRUPT_CTRL, msg_ret);
@ -581,7 +581,7 @@ irqreturn_t atomisp_isr(int irq, void *dev)
}
if (irq_infos & IA_CSS_IRQ_INFO_ISYS_EVENTS_READY) {
while (ia_css_dequeue_isys_event(&(eof_event.event)) ==
while (ia_css_dequeue_isys_event(&eof_event.event) ==
IA_CSS_SUCCESS) {
/* EOF Event does not have the css_pipe returned */
asd = __get_asd_from_port(isp, eof_event.event.port);
@ -614,6 +614,7 @@ out_nowake:
void atomisp_clear_css_buffer_counters(struct atomisp_sub_device *asd)
{
int i;
memset(asd->s3a_bufs_in_css, 0, sizeof(asd->s3a_bufs_in_css));
for (i = 0; i < ATOMISP_INPUT_STREAM_NUM; i++)
memset(asd->metadata_bufs_in_css[i], 0,
@ -915,7 +916,7 @@ void atomisp_buf_done(struct atomisp_sub_device *asd, int error,
/* need to know the atomisp pipe for frame buffers */
pipe = __atomisp_get_pipe(asd, stream_id, css_pipe_id, buf_type);
if (pipe == NULL) {
if (!pipe) {
dev_err(isp->dev, "error getting atomisp pipe\n");
return;
}
@ -1296,13 +1297,15 @@ static void __atomisp_css_recover(struct atomisp_device *isp, bool isp_timeout)
* HAL will be unblocked.
*/
acc_pipe = asd->stream_env[i].pipes[CSS_PIPE_ID_ACC];
if (acc_pipe != NULL) {
if (acc_pipe) {
acc_pipeline = ia_css_pipe_get_pipeline(acc_pipe);
if (acc_pipeline) {
struct ia_css_pipeline_stage *stage;
for (stage = acc_pipeline->stages; stage;
stage = stage->next) {
const struct ia_css_fw_info *fw;
fw = stage->firmware;
atomisp_acc_done(asd, fw->handle);
}
@ -1435,7 +1438,6 @@ static void __atomisp_css_recover(struct atomisp_device *isp, bool isp_timeout)
if (ret)
dev_warn(isp->dev,
"can't start streaming on sensor!\n");
}
if (depth_mode) {
@ -1469,6 +1471,7 @@ void atomisp_wdt_work(struct work_struct *work)
#else
for (i = 0; i < isp->num_of_streams; i++) {
struct atomisp_sub_device *asd = &isp->asd[i];
pipe_wdt_cnt[i][0] +=
atomic_read(&asd->video_out_capture.wdt_count);
pipe_wdt_cnt[i][1] +=
@ -1497,6 +1500,7 @@ void atomisp_wdt_work(struct work_struct *work)
if (css_recover) {
#endif
unsigned int old_dbglevel = dbg_level;
atomisp_css_debug_dump_sp_sw_debug_info();
atomisp_css_debug_dump_debug_info(__func__);
dbg_level = old_dbglevel;
@ -1566,7 +1570,7 @@ void atomisp_wdt_work(struct work_struct *work)
dev_err(isp->dev, "%s, raw_buffer_locked_count %d\n",
__func__, asd->raw_buffer_locked_count);
for (j = 0; j <= ATOMISP_MAX_EXP_ID/32; j++)
for (j = 0; j <= ATOMISP_MAX_EXP_ID / 32; j++)
dev_err(isp->dev, "%s, raw_buffer_bitmap[%d]: 0x%x\n",
__func__, j,
asd->raw_buffer_bitmap[j]);
@ -1578,6 +1582,7 @@ void atomisp_wdt_work(struct work_struct *work)
} else {
for (i = 0; i < isp->num_of_streams; i++) {
struct atomisp_sub_device *asd = &isp->asd[i];
if (asd->streaming ==
ATOMISP_DEVICE_STREAMING_ENABLED) {
atomisp_clear_css_buffer_counters(asd);
@ -1603,6 +1608,7 @@ void atomisp_wdt_work(struct work_struct *work)
#ifdef ISP2401
for (i = 0; i < isp->num_of_streams; i++) {
struct atomisp_sub_device *asd = &isp->asd[i];
if (asd->streaming ==
ATOMISP_DEVICE_STREAMING_ENABLED) {
atomisp_wdt_refresh(asd,
@ -1628,6 +1634,7 @@ void atomisp_css_flush(struct atomisp_device *isp)
/* Disable wdt */
for (i = 0; i < isp->num_of_streams; i++) {
struct atomisp_sub_device *asd = &isp->asd[i];
atomisp_wdt_stop(asd, true);
}
@ -1753,7 +1760,6 @@ void atomisp_wdt_refresh(struct atomisp_sub_device *asd, unsigned int delay)
atomisp_wdt_refresh_pipe(&asd->video_out_video_capture, delay);
}
void atomisp_wdt_stop_pipe(struct atomisp_video_pipe *pipe, bool sync)
#endif
{
@ -1811,7 +1817,7 @@ void atomisp_setup_flash(struct atomisp_sub_device *asd)
struct atomisp_device *isp = asd->isp;
struct v4l2_control ctrl;
if (isp->flash == NULL)
if (!isp->flash)
return;
if (asd->params.flash_state != ATOMISP_FLASH_REQUESTED &&
@ -1889,7 +1895,6 @@ irqreturn_t atomisp_isr_thread(int irq, void *isp_ptr)
if (asd->streaming != ATOMISP_DEVICE_STREAMING_ENABLED)
continue;
atomisp_setup_flash(asd);
}
out:
rt_mutex_unlock(&isp->mutex);
@ -1979,6 +1984,7 @@ v4l2_fmt_to_sh_fmt(u32 fmt)
return -EINVAL;
}
}
/*
* raw format match between SH format and V4L2 format
*/
@ -2343,7 +2349,7 @@ static void atomisp_update_grid_info(struct atomisp_sub_device *asd,
{
struct atomisp_device *isp = asd->isp;
int err;
uint16_t stream_id = atomisp_source_pad_to_stream_id(asd, source_pad);
u16 stream_id = atomisp_source_pad_to_stream_id(asd, source_pad);
if (atomisp_css_get_grid_info(asd, pipe_id, source_pad))
return;
@ -2415,6 +2421,7 @@ int atomisp_gdc_cac_table(struct atomisp_sub_device *asd, int flag,
if (flag == 0) {
/* Get gdc table from current setup */
struct atomisp_css_morph_table tab = {0};
atomisp_css_get_morph_table(asd, &tab);
config->width = tab.width;
@ -2643,7 +2650,6 @@ int atomisp_get_dvs2_bq_resolutions(struct atomisp_sub_device *asd,
pipe_cfg->bayer_ds_out_res.height /
input_config->effective_res.height + 1) / 2;
if (!asd->params.video_dis_en) {
/*
* We adjust the ispfilter_bq to:
@ -2681,7 +2687,7 @@ int atomisp_get_dvs2_bq_resolutions(struct atomisp_sub_device *asd,
w_padding = w_padding *
pipe_cfg->bayer_ds_out_res.width /
input_config->effective_res.width + 1;
w_padding = roundup(w_padding/2, 1);
w_padding = roundup(w_padding / 2, 1);
bq_res->gdc_shift_bq.width_bq = bq_res->ispfilter_bq.width_bq / 2
+ w_padding;
@ -2842,10 +2848,10 @@ int atomisp_get_metadata(struct atomisp_sub_device *asd, int flag,
mipi_info = atomisp_to_sensor_mipi_info(
isp->inputs[asd->input_curr].camera);
if (mipi_info == NULL)
if (!mipi_info)
return -EINVAL;
if (mipi_info->metadata_effective_width != NULL) {
if (mipi_info->metadata_effective_width) {
for (i = 0; i < md->height; i++)
md->effective_width[i] =
mipi_info->metadata_effective_width[i];
@ -2925,10 +2931,10 @@ int atomisp_get_metadata_by_type(struct atomisp_sub_device *asd, int flag,
mipi_info = atomisp_to_sensor_mipi_info(
isp->inputs[asd->input_curr].camera);
if (mipi_info == NULL)
if (!mipi_info)
return -EINVAL;
if (mipi_info->metadata_effective_width != NULL) {
if (mipi_info->metadata_effective_width) {
for (i = 0; i < md->height; i++)
md->effective_width[i] =
mipi_info->metadata_effective_width[i];
@ -3127,7 +3133,6 @@ int atomisp_calculate_real_zoom_region(struct atomisp_sub_device *asd,
asd->sensor_array_res.height,
out_res.width, out_res.height);
if ((dz_config->zoom_region.origin.x +
dz_config->zoom_region.resolution.width
> eff_res.width) ||
@ -3139,7 +3144,6 @@ int atomisp_calculate_real_zoom_region(struct atomisp_sub_device *asd,
return 0;
}
/*
* Function to check the zoom region whether is effective
*/
@ -3149,7 +3153,7 @@ static bool atomisp_check_zoom_region(
{
struct atomisp_resolution config;
bool flag = false;
unsigned int w , h;
unsigned int w, h;
memset(&config, 0, sizeof(struct atomisp_resolution));
@ -3313,7 +3317,7 @@ int atomisp_cp_general_isp_parameters(struct atomisp_sub_device *asd,
from_user))
return -EFAULT;
css_param->update_flag.wb_config =
(struct atomisp_wb_config *) &css_param->wb_config;
(struct atomisp_wb_config *)&css_param->wb_config;
}
if (arg->ob_config && (from_user || !cur_config->ob_config)) {
@ -3322,7 +3326,7 @@ int atomisp_cp_general_isp_parameters(struct atomisp_sub_device *asd,
from_user))
return -EFAULT;
css_param->update_flag.ob_config =
(struct atomisp_ob_config *) &css_param->ob_config;
(struct atomisp_ob_config *)&css_param->ob_config;
}
if (arg->dp_config && (from_user || !cur_config->dp_config)) {
@ -3331,7 +3335,7 @@ int atomisp_cp_general_isp_parameters(struct atomisp_sub_device *asd,
from_user))
return -EFAULT;
css_param->update_flag.dp_config =
(struct atomisp_dp_config *) &css_param->dp_config;
(struct atomisp_dp_config *)&css_param->dp_config;
}
if (asd->run_mode->val != ATOMISP_RUN_MODE_VIDEO) {
@ -3358,7 +3362,7 @@ int atomisp_cp_general_isp_parameters(struct atomisp_sub_device *asd,
from_user))
return -EFAULT;
css_param->update_flag.nr_config =
(struct atomisp_nr_config *) &css_param->nr_config;
(struct atomisp_nr_config *)&css_param->nr_config;
}
if (arg->ee_config && (from_user || !cur_config->ee_config)) {
@ -3367,7 +3371,7 @@ int atomisp_cp_general_isp_parameters(struct atomisp_sub_device *asd,
from_user))
return -EFAULT;
css_param->update_flag.ee_config =
(struct atomisp_ee_config *) &css_param->ee_config;
(struct atomisp_ee_config *)&css_param->ee_config;
}
if (arg->tnr_config && (from_user || !cur_config->tnr_config)) {
@ -3388,7 +3392,7 @@ int atomisp_cp_general_isp_parameters(struct atomisp_sub_device *asd,
from_user))
return -EFAULT;
css_param->update_flag.a3a_config =
(struct atomisp_3a_config *) &css_param->s3a_config;
(struct atomisp_3a_config *)&css_param->s3a_config;
}
if (arg->ctc_config && (from_user || !cur_config->ctc_config)) {
@ -3442,7 +3446,7 @@ int atomisp_cp_general_isp_parameters(struct atomisp_sub_device *asd,
from_user))
return -EFAULT;
css_param->update_flag.fc_config =
(struct atomisp_fc_config *) &css_param->fc_config;
(struct atomisp_fc_config *)&css_param->fc_config;
}
if (arg->macc_config && (from_user || !cur_config->macc_config)) {
@ -3462,7 +3466,7 @@ int atomisp_cp_general_isp_parameters(struct atomisp_sub_device *asd,
from_user))
return -EFAULT;
css_param->update_flag.aa_config =
(struct atomisp_aa_config *) &css_param->aa_config;
(struct atomisp_aa_config *)&css_param->aa_config;
}
if (arg->anr_config && (from_user || !cur_config->anr_config)) {
@ -3529,7 +3533,7 @@ int atomisp_cp_general_isp_parameters(struct atomisp_sub_device *asd,
from_user))
return -EFAULT;
css_param->update_flag.xnr_table =
(struct atomisp_xnr_table *) &css_param->xnr_table;
(struct atomisp_xnr_table *)&css_param->xnr_table;
}
if (arg->r_gamma_table && (from_user || !cur_config->r_gamma_table)) {
@ -3571,7 +3575,7 @@ int atomisp_cp_general_isp_parameters(struct atomisp_sub_device *asd,
from_user))
return -EFAULT;
css_param->update_flag.anr_thres =
(struct atomisp_anr_thres *) &css_param->anr_thres;
(struct atomisp_anr_thres *)&css_param->anr_thres;
}
if (from_user)
@ -3697,7 +3701,6 @@ int atomisp_cp_lsc_table(struct atomisp_sub_device *asd,
atomisp_css_shading_table_free(shading_table);
return -EFAULT;
}
}
#ifndef ISP2401
shading_table->sensor_width = source_st->sensor_width;
@ -3712,7 +3715,7 @@ int atomisp_cp_lsc_table(struct atomisp_sub_device *asd,
#endif
/* No need to update shading table if it is the same */
if (old_table != NULL &&
if (old_table &&
old_table->sensor_width == shading_table->sensor_width &&
old_table->sensor_height == shading_table->sensor_height &&
old_table->width == shading_table->width &&
@ -3739,8 +3742,8 @@ set_lsc:
/* set LSC to CSS */
css_param->shading_table = shading_table;
css_param->update_flag.shading_table =
(struct atomisp_shading_table *) shading_table;
asd->params.sc_en = shading_table != NULL;
(struct atomisp_shading_table *)shading_table;
asd->params.sc_en = shading_table;
if (old_table)
atomisp_css_shading_table_free(old_table);
@ -3788,23 +3791,23 @@ int atomisp_css_cp_dvs2_coefs(struct atomisp_sub_device *asd,
}
#ifndef ISP2401
if (coefs->hor_coefs.odd_real == NULL ||
coefs->hor_coefs.odd_imag == NULL ||
coefs->hor_coefs.even_real == NULL ||
coefs->hor_coefs.even_imag == NULL ||
coefs->ver_coefs.odd_real == NULL ||
coefs->ver_coefs.odd_imag == NULL ||
coefs->ver_coefs.even_real == NULL ||
coefs->ver_coefs.even_imag == NULL)
if (!coefs->hor_coefs.odd_real ||
!coefs->hor_coefs.odd_imag ||
!coefs->hor_coefs.even_real ||
!coefs->hor_coefs.even_imag ||
!coefs->ver_coefs.odd_real ||
!coefs->ver_coefs.odd_imag ||
!coefs->ver_coefs.even_real ||
!coefs->ver_coefs.even_imag)
#else
if (dvs2_coefs.hor_coefs.odd_real == NULL ||
dvs2_coefs.hor_coefs.odd_imag == NULL ||
dvs2_coefs.hor_coefs.even_real == NULL ||
dvs2_coefs.hor_coefs.even_imag == NULL ||
dvs2_coefs.ver_coefs.odd_real == NULL ||
dvs2_coefs.ver_coefs.odd_imag == NULL ||
dvs2_coefs.ver_coefs.even_real == NULL ||
dvs2_coefs.ver_coefs.even_imag == NULL)
if (!dvs2_coefs.hor_coefs.odd_real ||
!dvs2_coefs.hor_coefs.odd_imag ||
!dvs2_coefs.hor_coefs.even_real ||
!dvs2_coefs.hor_coefs.even_imag ||
!dvs2_coefs.ver_coefs.odd_real ||
!dvs2_coefs.ver_coefs.odd_imag ||
!dvs2_coefs.ver_coefs.even_real ||
!dvs2_coefs.ver_coefs.even_imag)
#endif
return -EINVAL;
@ -3891,7 +3894,7 @@ int atomisp_cp_dvs_6axis_config(struct atomisp_sub_device *asd,
atomisp_css_get_dvs_grid_info(&asd->params.curr_grid_info);
int ret = -EFAULT;
if (stream == NULL) {
if (!stream) {
dev_err(asd->isp->dev, "%s: internal error!", __func__);
return -EINVAL;
}
@ -4007,7 +4010,7 @@ int atomisp_cp_dvs_6axis_config(struct atomisp_sub_device *asd,
css_param->dvs_6axis = dvs_6axis_config;
css_param->update_flag.dvs_6axis_config =
(struct atomisp_dvs_6axis_config *) dvs_6axis_config;
(struct atomisp_dvs_6axis_config *)dvs_6axis_config;
return 0;
error:
@ -4087,7 +4090,7 @@ int atomisp_cp_morph_table(struct atomisp_sub_device *asd,
if (old_morph_table)
atomisp_css_morph_table_free(old_morph_table);
css_param->update_flag.morph_table =
(struct atomisp_morph_table *) morph_table;
(struct atomisp_morph_table *)morph_table;
return 0;
error:
@ -4112,7 +4115,7 @@ int atomisp_makeup_css_parameters(struct atomisp_sub_device *asd,
if (ret)
return ret;
ret = atomisp_css_cp_dvs2_coefs(asd,
(struct ia_css_dvs2_coefficients *) arg->dvs2_coefs,
(struct ia_css_dvs2_coefficients *)arg->dvs2_coefs,
css_param, false);
if (ret)
return ret;
@ -4242,7 +4245,7 @@ int atomisp_set_parameters(struct video_device *vdev,
struct atomisp_css_params *css_param = &asd->params.css_param;
int ret;
if (asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream == NULL) {
if (!asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream) {
dev_err(asd->isp->dev, "%s: internal error!\n", __func__);
return -EINVAL;
}
@ -4288,7 +4291,7 @@ int atomisp_set_parameters(struct video_device *vdev,
goto apply_parameter_failed;
ret = atomisp_css_cp_dvs2_coefs(asd,
(struct ia_css_dvs2_coefficients *) arg->dvs2_coefs,
(struct ia_css_dvs2_coefficients *)arg->dvs2_coefs,
css_param, true);
if (ret)
goto apply_parameter_failed;
@ -4334,7 +4337,7 @@ int atomisp_param(struct atomisp_sub_device *asd, int flag,
atomisp_css_get_dvs_grid_info(
&asd->params.curr_grid_info);
if (&config->info == NULL) {
if (!&config->info) {
dev_err(isp->dev, "ERROR: NULL pointer in grid_info\n");
return -EINVAL;
}
@ -4455,7 +4458,6 @@ int atomisp_color_effect(struct atomisp_sub_device *asd, int flag,
return 0;
}
control.id = V4L2_CID_COLORFX;
control.value = *effect;
ret =
@ -4537,7 +4539,6 @@ int atomisp_color_effect(struct atomisp_sub_device *asd, int flag,
int atomisp_bad_pixel(struct atomisp_sub_device *asd, int flag,
__s32 *value)
{
if (flag == 0) {
*value = asd->params.bad_pixel_en;
return 0;
@ -4588,7 +4589,6 @@ int atomisp_video_stable(struct atomisp_sub_device *asd, int flag,
int atomisp_fixed_pattern(struct atomisp_sub_device *asd, int flag,
__s32 *value)
{
if (flag == 0) {
*value = asd->params.fpn_en;
return 0;
@ -4612,9 +4612,9 @@ atomisp_bytesperline_to_padded_width(unsigned int bytesperline,
case CSS_FRAME_FORMAT_YUYV:
case CSS_FRAME_FORMAT_RAW:
case CSS_FRAME_FORMAT_RGB565:
return bytesperline/2;
return bytesperline / 2;
case CSS_FRAME_FORMAT_RGBA888:
return bytesperline/4;
return bytesperline / 4;
/* The following cases could be removed, but we leave them
in to document the formats that are included. */
case CSS_FRAME_FORMAT_NV11:
@ -4696,7 +4696,7 @@ int atomisp_fixed_pattern_table(struct atomisp_sub_device *asd,
struct atomisp_css_frame *raw_black_frame = NULL;
int ret;
if (arg == NULL)
if (!arg)
return -EINVAL;
ret = atomisp_v4l2_framebuffer_to_css_frame(arg, &raw_black_frame);
@ -4838,7 +4838,7 @@ int atomisp_get_sensor_mode_data(struct atomisp_sub_device *asd,
mipi_info = atomisp_to_sensor_mipi_info(
isp->inputs[asd->input_curr].camera);
if (mipi_info == NULL)
if (!mipi_info)
return -EINVAL;
memcpy(config, &mipi_info->data, sizeof(*config));
@ -4855,7 +4855,7 @@ int atomisp_get_fmt(struct video_device *vdev, struct v4l2_format *f)
}
static void __atomisp_update_stream_env(struct atomisp_sub_device *asd,
uint16_t stream_index, struct atomisp_input_stream_info *stream_info)
u16 stream_index, struct atomisp_input_stream_info *stream_info)
{
int i;
@ -4874,7 +4874,7 @@ static void __atomisp_update_stream_env(struct atomisp_sub_device *asd,
}
}
static void __atomisp_init_stream_info(uint16_t stream_index,
static void __atomisp_init_stream_info(u16 stream_index,
struct atomisp_input_stream_info *stream_info)
{
int i;
@ -4905,16 +4905,16 @@ int atomisp_try_fmt(struct video_device *vdev, struct v4l2_format *f,
const struct atomisp_format_bridge *fmt;
struct atomisp_input_stream_info *stream_info =
(struct atomisp_input_stream_info *)snr_mbus_fmt->reserved;
uint16_t stream_index;
u16 stream_index;
int source_pad = atomisp_subdev_source_pad(vdev);
int ret;
if (isp->inputs[asd->input_curr].camera == NULL)
if (!isp->inputs[asd->input_curr].camera)
return -EINVAL;
stream_index = atomisp_source_pad_to_stream_id(asd, source_pad);
fmt = atomisp_get_format_bridge(f->fmt.pix.pixelformat);
if (fmt == NULL) {
if (!fmt) {
dev_err(isp->dev, "unsupported pixelformat!\n");
fmt = atomisp_output_fmts;
}
@ -4942,7 +4942,7 @@ int atomisp_try_fmt(struct video_device *vdev, struct v4l2_format *f,
snr_mbus_fmt->width, snr_mbus_fmt->height);
fmt = atomisp_get_format_bridge_from_mbus(snr_mbus_fmt->code);
if (fmt == NULL) {
if (!fmt) {
dev_err(isp->dev, "unknown sensor format 0x%8.8x\n",
snr_mbus_fmt->code);
return -EINVAL;
@ -4970,7 +4970,7 @@ int atomisp_try_fmt(struct video_device *vdev, struct v4l2_format *f,
/* Set the flag when resolution requested is
* beyond the max value supported by sensor
*/
if (res_overflow != NULL)
if (res_overflow)
*res_overflow = true;
}
@ -5087,6 +5087,7 @@ static inline int atomisp_set_sensor_mipi_to_isp(
input_format = fc->css_stream_fmt;
} else {
struct v4l2_mbus_framefmt *sink;
sink = atomisp_subdev_get_ffmt(&asd->subdev, NULL,
V4L2_SUBDEV_FORMAT_ACTIVE,
ATOMISP_SUBDEV_PAD_SINK);
@ -5251,7 +5252,7 @@ static int atomisp_set_fmt_to_isp(struct video_device *vdev,
int (*configure_pp_input)(struct atomisp_sub_device *asd,
unsigned int width, unsigned int height) =
configure_pp_input_nop;
uint16_t stream_index = atomisp_source_pad_to_stream_id(asd, source_pad);
u16 stream_index = atomisp_source_pad_to_stream_id(asd, source_pad);
const struct atomisp_in_fmt_conv *fc;
int ret;
@ -5262,7 +5263,7 @@ static int atomisp_set_fmt_to_isp(struct video_device *vdev,
ATOMISP_SUBDEV_PAD_SINK, V4L2_SEL_TGT_CROP);
format = atomisp_get_format_bridge(pix->pixelformat);
if (format == NULL)
if (!format)
return -EINVAL;
if (isp->inputs[asd->input_curr].type != TEST_PATTERN &&
@ -5557,7 +5558,6 @@ static void atomisp_check_copy_mode(struct atomisp_sub_device *asd,
asd->copy_mode = false;
dev_dbg(asd->isp->dev, "copy_mode: %d\n", asd->copy_mode);
}
static int atomisp_set_fmt_to_snr(struct video_device *vdev,
@ -5576,7 +5576,7 @@ static int atomisp_set_fmt_to_snr(struct video_device *vdev,
struct atomisp_device *isp = asd->isp;
struct atomisp_input_stream_info *stream_info =
(struct atomisp_input_stream_info *)ffmt->reserved;
uint16_t stream_index = ATOMISP_INPUT_STREAM_GENERAL;
u16 stream_index = ATOMISP_INPUT_STREAM_GENERAL;
int source_pad = atomisp_subdev_source_pad(vdev);
struct v4l2_subdev_fh fh;
int ret;
@ -5586,7 +5586,7 @@ static int atomisp_set_fmt_to_snr(struct video_device *vdev,
stream_index = atomisp_source_pad_to_stream_id(asd, source_pad);
format = atomisp_get_format_bridge(pixelformat);
if (format == NULL)
if (!format)
return -EINVAL;
v4l2_fill_mbus_format(ffmt, &f->fmt.pix, format->mbus_code);
@ -5667,7 +5667,7 @@ int atomisp_set_fmt(struct video_device *vdev, struct v4l2_format *f)
struct v4l2_mbus_framefmt isp_sink_fmt;
struct v4l2_mbus_framefmt isp_source_fmt = {0};
struct v4l2_rect isp_sink_crop;
uint16_t source_pad = atomisp_subdev_source_pad(vdev);
u16 source_pad = atomisp_subdev_source_pad(vdev);
struct v4l2_subdev_fh fh;
int ret;
@ -5687,7 +5687,7 @@ int atomisp_set_fmt(struct video_device *vdev, struct v4l2_format *f)
v4l2_fh_init(&fh.vfh, vdev);
format_bridge = atomisp_get_format_bridge(f->fmt.pix.pixelformat);
if (format_bridge == NULL)
if (!format_bridge)
return -EINVAL;
pipe->sh_fmt = format_bridge->sh_fmt;
@ -5736,7 +5736,7 @@ int atomisp_set_fmt(struct video_device *vdev, struct v4l2_format *f)
(asd->isp->inputs[asd->input_curr].camera_caps->
sensor[asd->sensor_curr].stream_num > 1)) {
/* For M10MO outputing YUV preview images. */
uint16_t video_index =
u16 video_index =
atomisp_source_pad_to_stream_id(asd,
ATOMISP_SUBDEV_PAD_SOURCE_VIDEO);
@ -6064,7 +6064,6 @@ done:
output_info.padded_width, 8);
pipe->pix.sizeimage =
PAGE_ALIGN(f->fmt.pix.height * pipe->pix.bytesperline);
}
if (f->fmt.pix.field == V4L2_FIELD_ANY)
f->fmt.pix.field = V4L2_FIELD_NONE;
@ -6109,7 +6108,7 @@ int atomisp_set_fmt_file(struct video_device *vdev, struct v4l2_format *f)
}
format_bridge = atomisp_get_format_bridge(f->fmt.pix.pixelformat);
if (format_bridge == NULL) {
if (!format_bridge) {
dev_dbg(isp->dev, "atomisp_get_format_bridge err! fmt:0x%x\n",
f->fmt.pix.pixelformat);
return -EINVAL;
@ -6186,7 +6185,7 @@ int atomisp_set_shading_table(struct atomisp_sub_device *asd,
asd->params.sc_en = true;
out:
if (free_table != NULL)
if (free_table)
atomisp_css_shading_table_free(free_table);
return ret;
@ -6226,6 +6225,7 @@ done:
int atomisp_ospm_dphy_up(struct atomisp_device *isp)
{
unsigned long flags;
dev_dbg(isp->dev, "%s\n", __func__);
spin_lock_irqsave(&isp->lock, flags);
@ -6235,7 +6235,6 @@ int atomisp_ospm_dphy_up(struct atomisp_device *isp)
return 0;
}
int atomisp_exif_makernote(struct atomisp_sub_device *asd,
struct atomisp_makernote_info *config)
{
@ -6286,6 +6285,7 @@ int atomisp_offline_capture_configure(struct atomisp_sub_device *asd,
V4L2_CID_START_ZSL_CAPTURE);
if (c) {
int ret;
dev_dbg(asd->isp->dev, "%s trigger ZSL capture request\n",
__func__);
/* TODO: use the cvf_config */
@ -6447,6 +6447,7 @@ static int __checking_exp_id(struct atomisp_sub_device *asd, int exp_id)
void atomisp_init_raw_buffer_bitmap(struct atomisp_sub_device *asd)
{
unsigned long flags;
spin_lock_irqsave(&asd->raw_buffer_bitmap_lock, flags);
memset(asd->raw_buffer_bitmap, 0, sizeof(asd->raw_buffer_bitmap));
asd->raw_buffer_locked_count = 0;
@ -6582,7 +6583,7 @@ int atomisp_enable_dz_capt_pipe(struct atomisp_sub_device *asd,
{
bool value;
if (enable == NULL)
if (!enable)
return -EINVAL;
value = *enable > 0 ? true : false;

1
drivers/staging/media/atomisp/pci/atomisp2/atomisp_cmd.h
View File

@ -344,7 +344,6 @@ int atomisp_get_sensor_mode_data(struct atomisp_sub_device *asd,
int atomisp_get_fmt(struct video_device *vdev, struct v4l2_format *f);
/* This function looks up the closest available resolution. */
int atomisp_try_fmt(struct video_device *vdev, struct v4l2_format *f,
bool *res_overflow);

4
drivers/staging/media/atomisp/pci/atomisp2/atomisp_compat.h
View File

@ -202,7 +202,7 @@ int atomisp_css_dequeue_buffer(struct atomisp_sub_device *asd,
struct atomisp_css_buffer *isp_css_buffer);
int atomisp_css_allocate_stat_buffers(struct atomisp_sub_device *asd,
uint16_t stream_id,
u16 stream_id,
struct atomisp_s3a_buf *s3a_buf,
struct atomisp_dis_buf *dis_buf,
struct atomisp_metadata_buf *md_buf);
@ -422,7 +422,7 @@ int atomisp_css_video_configure_output(struct atomisp_sub_device *asd,
enum atomisp_css_frame_format format);
int atomisp_get_css_frame_info(struct atomisp_sub_device *asd,
uint16_t source_pad,
u16 source_pad,
struct atomisp_css_frame_info *frame_info);
int atomisp_css_video_configure_viewfinder(struct atomisp_sub_device *asd,

86
drivers/staging/media/atomisp/pci/atomisp2/atomisp_compat_css20.c
View File

@ -118,7 +118,7 @@ static void atomisp_css2_hw_store_32(hrt_address addr, uint32_t data)
static uint8_t atomisp_css2_hw_load_8(hrt_address addr)
{
unsigned long flags;
uint8_t ret;
u8 ret;
spin_lock_irqsave(&mmio_lock, flags);
ret = _hrt_master_port_load_8(addr);
@ -129,7 +129,7 @@ static uint8_t atomisp_css2_hw_load_8(hrt_address addr)
static uint16_t atomisp_css2_hw_load_16(hrt_address addr)
{
unsigned long flags;
uint16_t ret;
u16 ret;
spin_lock_irqsave(&mmio_lock, flags);
ret = _hrt_master_port_load_16(addr);
@ -140,7 +140,7 @@ static uint16_t atomisp_css2_hw_load_16(hrt_address addr)
static uint32_t atomisp_css2_hw_load_32(hrt_address addr)
{
unsigned long flags;
uint32_t ret;
u32 ret;
spin_lock_irqsave(&mmio_lock, flags);
ret = _hrt_master_port_load_32(addr);
@ -158,7 +158,7 @@ static void atomisp_css2_hw_store(hrt_address addr,
spin_lock_irqsave(&mmio_lock, flags);
for (i = 0; i < n; i++, _to++, _from++)
_hrt_master_port_store_8(_to , *_from);
_hrt_master_port_store_8(_to, *_from);
spin_unlock_irqrestore(&mmio_lock, flags);
}
@ -202,9 +202,10 @@ void atomisp_load_uint32(hrt_address addr, uint32_t *data)
{
*data = atomisp_css2_hw_load_32(addr);
}
static int hmm_get_mmu_base_addr(unsigned int *mmu_base_addr)
{
if (sh_mmu_mrfld.get_pd_base == NULL) {
if (!sh_mmu_mrfld.get_pd_base) {
dev_err(atomisp_dev, "get mmu base address failed.\n");
return -EINVAL;
}
@ -515,6 +516,7 @@ static int __destroy_streams(struct atomisp_sub_device *asd, bool force)
asd->stream_prepared = false;
return 0;
}
static int __create_stream(struct atomisp_sub_device *asd,
struct atomisp_stream_env *stream_env)
{
@ -598,7 +600,6 @@ static int __destroy_pipes(struct atomisp_sub_device *asd, bool force)
for (i = 0; i < ATOMISP_INPUT_STREAM_NUM; i++) {
if (asd->stream_env[i].stream) {
dev_err(isp->dev,
"cannot destroy css pipes for stream[%d].\n",
i);
@ -1286,7 +1287,6 @@ void atomisp_css_update_isp_params(struct atomisp_sub_device *asd)
atomisp_isp_parameters_clean_up(&asd->params.config);
}
void atomisp_css_update_isp_params_on_pipe(struct atomisp_sub_device *asd,
struct ia_css_pipe *pipe)
{
@ -1347,7 +1347,7 @@ int atomisp_css_dequeue_buffer(struct atomisp_sub_device *asd,
}
int atomisp_css_allocate_stat_buffers(struct atomisp_sub_device *asd,
uint16_t stream_id,
u16 stream_id,
struct atomisp_s3a_buf *s3a_buf,
struct atomisp_dis_buf *dis_buf,
struct atomisp_metadata_buf *md_buf)
@ -1566,8 +1566,7 @@ int atomisp_css_get_grid_info(struct atomisp_sub_device *asd,
|| asd->params.curr_grid_info.s3a_grid.height == 0)
&& asd->params.metadata_width_size == md_width) {
dev_dbg(isp->dev,
"grid info change escape. memcmp=%d, s3a_user_stat=%d,"
"dvs_stat=%d, s3a.width=%d, s3a.height=%d, metadata width =%d\n",
"grid info change escape. memcmp=%d, s3a_user_stat=%d,dvs_stat=%d, s3a.width=%d, s3a.height=%d, metadata width =%d\n",
!memcmp(&old_info, &asd->params.curr_grid_info,
sizeof(old_info)),
!!asd->params.s3a_user_stat, !!asd->params.dvs_stat,
@ -1687,7 +1686,6 @@ void atomisp_css_get_dis_statistics(struct atomisp_sub_device *asd,
else
ia_css_get_dvs2_statistics(asd->params.dvs_stat,
isp_css_buffer->css_buffer.data.stats_dvs);
}
}
@ -1787,7 +1785,6 @@ void atomisp_css_isys_set_format(struct atomisp_sub_device *asd,
enum atomisp_input_format format,
int isys_stream)
{
struct ia_css_stream_config *s_config =
&asd->stream_env[stream_id].stream_config;
@ -1798,7 +1795,6 @@ void atomisp_css_input_set_format(struct atomisp_sub_device *asd,
enum atomisp_input_stream_id stream_id,
enum atomisp_input_format format)
{
struct ia_css_stream_config *s_config =
&asd->stream_env[stream_id].stream_config;
@ -2026,8 +2022,7 @@ void atomisp_css_input_set_mode(struct atomisp_sub_device *asd,
else
size_mem_words = CSS_MIPI_FRAME_BUFFER_SIZE_1;
dev_warn(asd->isp->dev,
"ia_css_mipi_frame_calculate_size failed,"
"applying pre-defined MIPI buffer size %u.\n",
"ia_css_mipi_frame_calculate_size failed,applying pre-defined MIPI buffer size %u.\n",
size_mem_words);
}
s_config->mipi_buffer_config.size_mem_words = size_mem_words;
@ -2390,7 +2385,6 @@ static enum ia_css_pipe_mode __pipe_id_to_pipe_mode(
WARN_ON(1);
return IA_CSS_PIPE_MODE_PREVIEW;
}
}
static void __configure_output(struct atomisp_sub_device *asd,
@ -2912,7 +2906,7 @@ static unsigned int atomisp_get_pipe_index(struct atomisp_sub_device *asd,
}
int atomisp_get_css_frame_info(struct atomisp_sub_device *asd,
uint16_t source_pad,
u16 source_pad,
struct atomisp_css_frame_info *frame_info)
{
struct ia_css_pipe_info info;
@ -3555,7 +3549,7 @@ void atomisp_css_set_ctc_table(struct atomisp_sub_device *asd,
struct atomisp_css_ctc_table *ctc_table)
{
int i;
uint16_t *vamem_ptr = ctc_table->data.vamem_1;
u16 *vamem_ptr = ctc_table->data.vamem_1;
int data_size = IA_CSS_VAMEM_1_CTC_TABLE_SIZE;
bool valid = false;
@ -3653,22 +3647,22 @@ int atomisp_css_set_dis_coefs(struct atomisp_sub_device *asd,
try again. */
return -EAGAIN;
if (coefs->hor_coefs.odd_real == NULL ||
coefs->hor_coefs.odd_imag == NULL ||
coefs->hor_coefs.even_real == NULL ||
coefs->hor_coefs.even_imag == NULL ||
coefs->ver_coefs.odd_real == NULL ||
coefs->ver_coefs.odd_imag == NULL ||
coefs->ver_coefs.even_real == NULL ||
coefs->ver_coefs.even_imag == NULL ||
asd->params.css_param.dvs2_coeff->hor_coefs.odd_real == NULL ||
asd->params.css_param.dvs2_coeff->hor_coefs.odd_imag == NULL ||
asd->params.css_param.dvs2_coeff->hor_coefs.even_real == NULL ||
asd->params.css_param.dvs2_coeff->hor_coefs.even_imag == NULL ||
asd->params.css_param.dvs2_coeff->ver_coefs.odd_real == NULL ||
asd->params.css_param.dvs2_coeff->ver_coefs.odd_imag == NULL ||
asd->params.css_param.dvs2_coeff->ver_coefs.even_real == NULL ||
asd->params.css_param.dvs2_coeff->ver_coefs.even_imag == NULL)
if (!coefs->hor_coefs.odd_real ||
!coefs->hor_coefs.odd_imag ||
!coefs->hor_coefs.even_real ||
!coefs->hor_coefs.even_imag ||
!coefs->ver_coefs.odd_real ||
!coefs->ver_coefs.odd_imag ||
!coefs->ver_coefs.even_real ||
!coefs->ver_coefs.even_imag ||
!asd->params.css_param.dvs2_coeff->hor_coefs.odd_real ||
!asd->params.css_param.dvs2_coeff->hor_coefs.odd_imag ||
!asd->params.css_param.dvs2_coeff->hor_coefs.even_real ||
!asd->params.css_param.dvs2_coeff->hor_coefs.even_imag ||
!asd->params.css_param.dvs2_coeff->ver_coefs.odd_real ||
!asd->params.css_param.dvs2_coeff->ver_coefs.odd_imag ||
!asd->params.css_param.dvs2_coeff->ver_coefs.even_real ||
!asd->params.css_param.dvs2_coeff->ver_coefs.even_imag)
return -EINVAL;
if (copy_from_user(asd->params.css_param.dvs2_coeff->hor_coefs.odd_real,
@ -3724,7 +3718,7 @@ void atomisp_css_set_zoom_factor(struct atomisp_sub_device *asd,
asd->params.css_param.dz_config.dy = zoom;
asd->params.css_param.update_flag.dz_config =
(struct atomisp_dz_config *) &asd->params.css_param.dz_config;
(struct atomisp_dz_config *)&asd->params.css_param.dz_config;
asd->params.css_update_params_needed = true;
}
@ -4047,7 +4041,6 @@ int atomisp_css_get_zoom_factor(struct atomisp_sub_device *asd,
return 0;
}
/*
* Function to set/get image stablization statistics
*/
@ -4058,14 +4051,14 @@ int atomisp_css_get_dis_stat(struct atomisp_sub_device *asd,
struct atomisp_dis_buf *dis_buf;
unsigned long flags;
if (asd->params.dvs_stat->hor_prod.odd_real == NULL ||
asd->params.dvs_stat->hor_prod.odd_imag == NULL ||
asd->params.dvs_stat->hor_prod.even_real == NULL ||
asd->params.dvs_stat->hor_prod.even_imag == NULL ||
asd->params.dvs_stat->ver_prod.odd_real == NULL ||
asd->params.dvs_stat->ver_prod.odd_imag == NULL ||
asd->params.dvs_stat->ver_prod.even_real == NULL ||
asd->params.dvs_stat->ver_prod.even_imag == NULL)
if (!asd->params.dvs_stat->hor_prod.odd_real ||
!asd->params.dvs_stat->hor_prod.odd_imag ||
!asd->params.dvs_stat->hor_prod.even_real ||
!asd->params.dvs_stat->hor_prod.even_imag ||
!asd->params.dvs_stat->ver_prod.odd_real ||
!asd->params.dvs_stat->ver_prod.odd_imag ||
!asd->params.dvs_stat->ver_prod.even_real ||
!asd->params.dvs_stat->ver_prod.even_imag)
return -EINVAL;
/* isp needs to be streaming to get DIS statistics */
@ -4646,12 +4639,12 @@ int atomisp_css_dump_blob_infor(void)
if (nm == 0)
return -EPERM;
if (bd == NULL)
if (!bd)
return -EPERM;
for (i = 1; i < sh_css_num_binaries; i++)
dev_dbg(atomisp_dev, "Num%d binary id is %d, name is %s\n", i,
bd[i-1].header.info.isp.sp.id, bd[i-1].name);
bd[i - 1].header.info.isp.sp.id, bd[i - 1].name);
return 0;
}
@ -4683,6 +4676,7 @@ int atomisp_set_css_dbgfunc(struct atomisp_device *isp, int opt)
return ret;
}
void atomisp_en_dz_capt_pipe(struct atomisp_sub_device *asd, bool enable)
{
ia_css_en_dz_capt_pipe(

7
drivers/staging/media/atomisp/pci/atomisp2/atomisp_compat_ioctl32.c
View File

@ -253,7 +253,6 @@ static int put_atomisp_3a_statistics32(struct atomisp_3a_statistics *kp,
return 0;
}
static int get_atomisp_metadata_stat32(struct atomisp_metadata *kp,
struct atomisp_metadata32 __user *up)
{
@ -274,7 +273,6 @@ static int get_atomisp_metadata_stat32(struct atomisp_metadata *kp,
return 0;
}
static int put_atomisp_metadata_stat32(struct atomisp_metadata *kp,
struct atomisp_metadata32 __user *up)
{
@ -387,6 +385,7 @@ static int get_atomisp_overlay32(struct atomisp_overlay *kp,
struct atomisp_overlay32 __user *up)
{
compat_uptr_t frame;
if (!access_ok(up, sizeof(struct atomisp_overlay32)) ||
get_user(frame, &up->frame) ||
get_user(kp->bg_y, &up->bg_y) ||
@ -761,6 +760,7 @@ static int get_atomisp_acc_fw_load_to_pipe32(
struct atomisp_acc_fw_load_to_pipe32 __user *up)
{
compat_uptr_t data;
if (!access_ok(up, sizeof(struct atomisp_acc_fw_load_to_pipe32)) ||
get_user(kp->flags, &up->flags) ||
get_user(kp->fw_handle, &up->fw_handle) ||
@ -781,6 +781,7 @@ static int put_atomisp_acc_fw_load_to_pipe32(
struct atomisp_acc_fw_load_to_pipe32 __user *up)
{
compat_uptr_t data = (compat_uptr_t)((uintptr_t)kp->data);
if (!access_ok(up, sizeof(struct atomisp_acc_fw_load_to_pipe32)) ||
put_user(kp->flags, &up->flags) ||
put_user(kp->fw_handle, &up->fw_handle) ||
@ -800,6 +801,7 @@ static int get_atomisp_sensor_ae_bracketing_lut(
struct atomisp_sensor_ae_bracketing_lut32 __user *up)
{
compat_uptr_t lut;
if (!access_ok(up, sizeof(struct atomisp_sensor_ae_bracketing_lut32)) ||
get_user(kp->lut_size, &up->lut_size) ||
get_user(lut, &up->lut))
@ -1066,7 +1068,6 @@ static long atomisp_do_compat_ioctl(struct file *file,
long atomisp_compat_ioctl32(struct file *file,
unsigned int cmd, unsigned long arg)
{
struct video_device *vdev = video_devdata(file);
struct atomisp_device *isp = video_get_drvdata(vdev);
long ret = -ENOIOCTLCMD;

36
drivers/staging/media/atomisp/pci/atomisp2/atomisp_compat_ioctl32.h
View File

@ -49,7 +49,7 @@ struct atomisp_dvs2_statistics32 {
struct atomisp_dis_statistics32 {
struct atomisp_dvs2_statistics32 dvs2_stat;
uint32_t exp_id;
u32 exp_id;
};
struct atomisp_dis_coefficients32 {
@ -62,27 +62,27 @@ struct atomisp_3a_statistics32 {
struct atomisp_grid_info grid_info;
compat_uptr_t data;
compat_uptr_t rgby_data;
uint32_t exp_id;
uint32_t isp_config_id;
u32 exp_id;
u32 isp_config_id;
};
struct atomisp_metadata_with_type32 {
/* to specify which type of metadata to get */
enum atomisp_metadata_type type;
compat_uptr_t data;
uint32_t width;
uint32_t height;
uint32_t stride; /* in bytes */
uint32_t exp_id; /* exposure ID */
u32 width;
u32 height;
u32 stride; /* in bytes */
u32 exp_id; /* exposure ID */
compat_uptr_t effective_width;
};
struct atomisp_metadata32 {
compat_uptr_t data;
uint32_t width;
uint32_t height;
uint32_t stride;
uint32_t exp_id;
u32 width;
u32 height;
u32 stride;
u32 exp_id;
compat_uptr_t effective_width;
};
@ -258,8 +258,8 @@ struct atomisp_parameters32 {
* Unique ID to track which config was actually applied to a particular
* frame, driver will send this id back with output frame together.
*/
uint32_t isp_config_id;
uint32_t per_frame_setting;
u32 isp_config_id;
u32 per_frame_setting;
};
struct atomisp_acc_fw_load_to_pipe32 {
@ -272,11 +272,11 @@ struct atomisp_acc_fw_load_to_pipe32 {
};
struct atomisp_dvs_6axis_config32 {
uint32_t exp_id;
uint32_t width_y;
uint32_t height_y;
uint32_t width_uv;
uint32_t height_uv;
u32 exp_id;
u32 width_y;
u32 height_y;
u32 width_uv;
u32 height_uv;
compat_uptr_t xcoords_y;
compat_uptr_t ycoords_y;
compat_uptr_t xcoords_uv;

9
drivers/staging/media/atomisp/pci/atomisp2/atomisp_csi2.c
View File

@ -23,9 +23,9 @@
static struct v4l2_mbus_framefmt *__csi2_get_format(struct
atomisp_mipi_csi2_device
*csi2,
* csi2,
struct
v4l2_subdev_pad_config *cfg,
v4l2_subdev_pad_config * cfg,
enum
v4l2_subdev_format_whence
which, unsigned int pad)
@ -155,7 +155,7 @@ static int csi2_set_format(struct v4l2_subdev *sd,
*/
static int csi2_set_stream(struct v4l2_subdev *sd, int enable)
{
return 0;
return 0;
}
/* subdev core operations */
@ -345,6 +345,7 @@ static void atomisp_csi2_configure_isp2401(struct atomisp_sub_device *asd)
static const short int coeff_dat_settle[] = { 85, -2 };
static const int TERMEN_DEFAULT = 0 * 0;
static const int SETTLE_DEFAULT = 0x480;
static const hrt_address csi2_port_base[] = {
[ATOMISP_CAMERA_PORT_PRIMARY] = CSI2_PORT_A_BASE,
[ATOMISP_CAMERA_PORT_SECONDARY] = CSI2_PORT_B_BASE,
@ -396,6 +397,7 @@ static void atomisp_csi2_configure_isp2401(struct atomisp_sub_device *asd)
mipi_freq, SETTLE_DEFAULT);
for (n = 0; n < csi2_port_lanes[port] + 1; n++) {
hrt_address base = csi2_port_base[port] + csi2_lane_base[n];
atomisp_store_uint32(base + CSI2_REG_RX_CSI_DLY_CNT_TERMEN,
n == 0 ? clk_termen : dat_termen);
atomisp_store_uint32(base + CSI2_REG_RX_CSI_DLY_CNT_SETTLE,
@ -439,4 +441,3 @@ fail:
atomisp_mipi_csi2_cleanup(isp);
return ret;
}

4
drivers/staging/media/atomisp/pci/atomisp2/atomisp_csi2.h
View File

@ -24,8 +24,8 @@
#define CSI2_PAD_SOURCE 1
#define CSI2_PADS_NUM 2
#define CSI2_OUTPUT_ISP_SUBDEV (1 << 0)
#define CSI2_OUTPUT_MEMORY (1 << 1)
#define CSI2_OUTPUT_ISP_SUBDEV BIT(0)
#define CSI2_OUTPUT_MEMORY BIT(1)
struct atomisp_device;
struct v4l2_device;

1
drivers/staging/media/atomisp/pci/atomisp2/atomisp_dfs_tables.h
View File

@ -27,7 +27,6 @@ struct atomisp_freq_scaling_rule {
unsigned int run_mode;
};
struct atomisp_dfs_config {
unsigned int lowest_freq;
unsigned int max_freq_at_vmin;

6
drivers/staging/media/atomisp/pci/atomisp2/atomisp_drvfs.c
View File

@ -41,9 +41,9 @@ struct _iunit_debug {
unsigned int dbgopt;
};
#define OPTION_BIN_LIST (1<<0)
#define OPTION_BIN_RUN (1<<1)
#define OPTION_MEM_STAT (1<<2)
#define OPTION_BIN_LIST BIT(0)
#define OPTION_BIN_RUN BIT(1)
#define OPTION_MEM_STAT BIT(2)
#define OPTION_VALID (OPTION_BIN_LIST \
| OPTION_BIN_RUN \
| OPTION_MEM_STAT)

4
drivers/staging/media/atomisp/pci/atomisp2/atomisp_file.c
View File

@ -87,6 +87,7 @@ static int file_input_get_fmt(struct v4l2_subdev *sd,
/* only support file injection on subdev0 */
struct atomisp_sub_device *asd = &isp->asd[0];
struct v4l2_mbus_framefmt *isp_sink_fmt;
if (format->pad)
return -EINVAL;
isp_sink_fmt = atomisp_subdev_get_ffmt(&asd->subdev, NULL,
@ -105,6 +106,7 @@ static int file_input_set_fmt(struct v4l2_subdev *sd,
struct v4l2_subdev_format *format)
{
struct v4l2_mbus_framefmt *fmt = &format->format;
if (format->pad)
return -EINVAL;
file_input_get_fmt(sd, cfg, format);
@ -206,7 +208,7 @@ int atomisp_file_input_init(struct atomisp_device *isp)
file_dev->isp = isp;
file_dev->work_queue = alloc_workqueue(isp->v4l2_dev.name, 0, 1);
if (file_dev->work_queue == NULL) {
if (!file_dev->work_queue) {
dev_err(isp->dev, "Failed to initialize file inject workq\n");
return -ENOMEM;
}

23
drivers/staging/media/atomisp/pci/atomisp2/atomisp_fops.c
View File

@ -410,7 +410,6 @@ static int atomisp_qbuffers_to_css_for_all_pipes(struct atomisp_sub_device *asd)
return 0;
}
/* queue all available buffers to css */
int atomisp_qbuffers_to_css(struct atomisp_sub_device *asd)
{
@ -737,6 +736,7 @@ static void atomisp_subdev_init_struct(struct atomisp_sub_device *asd)
asd->sensor_array_res.width = 0;
atomisp_css_init_struct(asd);
}
/*
* file operation functions
*/
@ -753,6 +753,7 @@ static unsigned int atomisp_subdev_users(struct atomisp_sub_device *asd)
unsigned int atomisp_dev_users(struct atomisp_device *isp)
{
unsigned int i, sum;
for (i = 0, sum = 0; i < isp->num_of_streams; i++)
sum += atomisp_subdev_users(&isp->asd[i]);
@ -902,7 +903,7 @@ static int atomisp_release(struct file *file)
v4l2_fh_init(&fh.vfh, vdev);
req.count = 0;
if (isp == NULL)
if (!isp)
return -EBADF;
mutex_lock(&isp->streamoff_mutex);
@ -960,6 +961,7 @@ static int atomisp_release(struct file *file)
*/
if (!isp->sw_contex.file_input && asd->fmt_auto->val) {
struct v4l2_mbus_framefmt isp_sink_fmt = { 0 };
atomisp_subdev_set_ffmt(&asd->subdev, fh.pad,
V4L2_SUBDEV_FORMAT_ACTIVE,
ATOMISP_SUBDEV_PAD_SINK, &isp_sink_fmt);
@ -971,6 +973,7 @@ subdev_uninit:
/* clear the sink pad for file input */
if (isp->sw_contex.file_input && asd->fmt_auto->val) {
struct v4l2_mbus_framefmt isp_sink_fmt = { 0 };
atomisp_subdev_set_ffmt(&asd->subdev, fh.pad,
V4L2_SUBDEV_FORMAT_ACTIVE,
ATOMISP_SUBDEV_PAD_SINK, &isp_sink_fmt);
@ -1090,7 +1093,8 @@ int atomisp_videobuf_mmap_mapper(struct videobuf_queue *q,
mutex_lock(&q->vb_lock);
for (i = 0; i < VIDEO_MAX_FRAME; i++) {
struct videobuf_buffer *buf = q->bufs[i];
if (buf == NULL)
if (!buf)
continue;
map = kzalloc(sizeof(struct videobuf_mapping), GFP_KERNEL);
@ -1108,7 +1112,7 @@ int atomisp_videobuf_mmap_mapper(struct videobuf_queue *q,
buf->boff == offset) {
vm_mem = buf->priv;
ret = frame_mmap(isp, vm_mem->vaddr, vma);
vma->vm_flags |= VM_IO|VM_DONTEXPAND|VM_DONTDUMP;
vma->vm_flags |= VM_IO | VM_DONTEXPAND | VM_DONTDUMP;
break;
}
}
@ -1130,17 +1134,17 @@ static int remove_pad_from_frame(struct atomisp_device *isp,
ia_css_ptr load = in_frame->data;
ia_css_ptr store = load;
buffer = kmalloc(width*sizeof(load), GFP_KERNEL);
buffer = kmalloc_array(width, sizeof(load), GFP_KERNEL);
if (!buffer)
return -ENOMEM;
load += ISP_LEFT_PAD;
for (i = 0; i < height; i++) {
ret = hmm_load(load, buffer, width*sizeof(load));
ret = hmm_load(load, buffer, width * sizeof(load));
if (ret < 0)
goto remove_pad_error;
ret = hmm_store(store, buffer, width*sizeof(store));
ret = hmm_store(store, buffer, width * sizeof(store));
if (ret < 0)
goto remove_pad_error;
@ -1194,7 +1198,7 @@ static int atomisp_mmap(struct file *file, struct vm_area_struct *vma)
goto error;
}
raw_virt_addr = asd->raw_output_frame;
if (raw_virt_addr == NULL) {
if (!raw_virt_addr) {
dev_err(isp->dev, "Failed to request RAW frame\n");
ret = -EINVAL;
goto error;
@ -1222,7 +1226,7 @@ static int atomisp_mmap(struct file *file, struct vm_area_struct *vma)
goto error;
}
raw_virt_addr->data_bytes = origin_size;
vma->vm_flags |= VM_IO|VM_DONTEXPAND|VM_DONTDUMP;
vma->vm_flags |= VM_IO | VM_DONTEXPAND | VM_DONTDUMP;
rt_mutex_unlock(&isp->mutex);
return 0;
}
@ -1299,4 +1303,3 @@ const struct v4l2_file_operations atomisp_file_fops = {
#endif
.poll = atomisp_poll,
};

1
drivers/staging/media/atomisp/pci/atomisp2/atomisp_helper.h
View File

@ -26,4 +26,3 @@ static inline void __iomem *atomisp_get_io_virt_addr(unsigned int address)
return ret;
}
#endif

15
drivers/staging/media/atomisp/pci/atomisp2/atomisp_internal.h
View File

@ -156,7 +156,7 @@
#endif
#define DIV_NEAREST_STEP(n, d, step) \
round_down((2 * (n) + (d) * (step))/(2 * (d)), (step))
round_down((2 * (n) + (d) * (step)) / (2 * (d)), (step))
struct atomisp_input_subdev {
unsigned int type;
@ -212,7 +212,6 @@ struct atomisp_sw_contex {
int running_freq;
};
#define ATOMISP_DEVICE_STREAMING_DISABLED 0
#define ATOMISP_DEVICE_STREAMING_ENABLED 1
#define ATOMISP_DEVICE_STREAMING_STOPPING 2
@ -295,16 +294,16 @@ extern struct device *atomisp_dev;
#define atomisp_is_wdt_running(a) timer_pending(&(a)->wdt)
#ifdef ISP2401
extern void atomisp_wdt_refresh_pipe(struct atomisp_video_pipe *pipe,
void atomisp_wdt_refresh_pipe(struct atomisp_video_pipe *pipe,
unsigned int delay);
#endif
extern void atomisp_wdt_refresh(struct atomisp_sub_device *asd, unsigned int delay);
void atomisp_wdt_refresh(struct atomisp_sub_device *asd, unsigned int delay);
#ifndef ISP2401
extern void atomisp_wdt_start(struct atomisp_sub_device *asd);
void atomisp_wdt_start(struct atomisp_sub_device *asd);
#else
extern void atomisp_wdt_start(struct atomisp_video_pipe *pipe);
extern void atomisp_wdt_stop_pipe(struct atomisp_video_pipe *pipe, bool sync);
void atomisp_wdt_start(struct atomisp_video_pipe *pipe);
void atomisp_wdt_stop_pipe(struct atomisp_video_pipe *pipe, bool sync);
#endif
extern void atomisp_wdt_stop(struct atomisp_sub_device *asd, bool sync);
void atomisp_wdt_stop(struct atomisp_sub_device *asd, bool sync);
#endif /* __ATOMISP_INTERNAL_H__ */

30
drivers/staging/media/atomisp/pci/atomisp2/atomisp_ioctl.c
View File

@ -20,7 +20,6 @@
#include <linux/delay.h>
#include <linux/pci.h>
#include <media/v4l2-ioctl.h>
#include <media/v4l2-event.h>
#include <media/videobuf-vmalloc.h>
@ -333,6 +332,7 @@ static struct v4l2_queryctrl ci_v4l2_controls[] = {
.default_value = 0,
},
};
static const u32 ctrls_num = ARRAY_SIZE(ci_v4l2_controls);
/*
@ -651,6 +651,7 @@ unsigned int atomisp_is_acc_enabled(struct atomisp_device *isp)
return 0;
}
/*
* get input are used to get current primary/secondary camera
*/
@ -666,6 +667,7 @@ static int atomisp_g_input(struct file *file, void *fh, unsigned int *input)
return 0;
}
/*
* set input are used to set current primary/secondary camera
*/
@ -689,7 +691,7 @@ static int atomisp_s_input(struct file *file, void *fh, unsigned int input)
* 1: already in use
* 2: if in use, whether it is used by other streams
*/
if (isp->inputs[input].asd != NULL && isp->inputs[input].asd != asd) {
if (isp->inputs[input].asd && isp->inputs[input].asd != asd) {
dev_err(isp->dev,
"%s, camera is already used by stream: %d\n", __func__,
isp->inputs[input].asd->index);
@ -898,7 +900,7 @@ void atomisp_videobuf_free_buf(struct videobuf_buffer *vb)
{
struct videobuf_vmalloc_memory *vm_mem;
if (vb == NULL)
if (!vb)
return;
vm_mem = vb->priv;
@ -1037,8 +1039,8 @@ int __atomisp_reqbufs(struct file *file, void *fh,
struct atomisp_css_frame_info frame_info;
struct atomisp_css_frame *frame;
struct videobuf_vmalloc_memory *vm_mem;
uint16_t source_pad = atomisp_subdev_source_pad(vdev);
uint16_t stream_id = atomisp_source_pad_to_stream_id(asd, source_pad);
u16 source_pad = atomisp_subdev_source_pad(vdev);
u16 stream_id = atomisp_source_pad_to_stream_id(asd, source_pad);
int ret = 0, i = 0;
if (req->count == 0) {
@ -1194,6 +1196,7 @@ static int atomisp_qbuf(struct file *file, void *fh, struct v4l2_buffer *buf)
*/
if (buf->memory == V4L2_MEMORY_USERPTR) {
struct hrt_userbuffer_attr attributes;
vb = pipe->capq.bufs[buf->index];
vm_mem = vb->priv;
if (!vm_mem) {
@ -1338,7 +1341,7 @@ done:
asd->pending_capture_request++;
dev_dbg(isp->dev, "Add one pending capture request.\n");
#else
if (asd->re_trigger_capture) {
if (asd->re_trigger_capture) {
ret = atomisp_css_offline_capture_configure(asd,
asd->params.offline_parm.num_captures,
asd->params.offline_parm.skip_frames,
@ -1347,11 +1350,11 @@ done:
dev_dbg(isp->dev, "%s Trigger capture again ret=%d\n",
__func__, ret);
} else {
} else {
asd->pending_capture_request++;
asd->re_trigger_capture = false;
dev_dbg(isp->dev, "Add one pending capture request.\n");
}
}
#endif
}
rt_mutex_unlock(&isp->mutex);
@ -1557,6 +1560,7 @@ int atomisp_stream_on_master_slave_sensor(struct atomisp_device *isp,
*/
for (i = 0; i < isp->num_of_streams; i++) {
int sensor_index = isp->asd[i].input_curr;
if (isp->inputs[sensor_index].camera_caps->
sensor[isp->asd[i].sensor_curr].is_slave)
slave = sensor_index;
@ -1643,6 +1647,7 @@ static void atomisp_pause_buffer_event(struct atomisp_device *isp)
for (i = 0; i < isp->num_of_streams; i++) {
int sensor_index = isp->asd[i].input_curr;
if (isp->inputs[sensor_index].camera_caps->
sensor[isp->asd[i].sensor_curr].is_slave) {
v4l2_event_queue(isp->asd[i].subdev.devnode, &event);
@ -1657,13 +1662,13 @@ static void atomisp_pause_buffer_event(struct atomisp_device *isp)
/* manually to 128 in case of 13MPx snapshot and to 1 otherwise. */
static void atomisp_dma_burst_len_cfg(struct atomisp_sub_device *asd)
{
struct v4l2_mbus_framefmt *sink;
sink = atomisp_subdev_get_ffmt(&asd->subdev, NULL,
V4L2_SUBDEV_FORMAT_ACTIVE,
ATOMISP_SUBDEV_PAD_SINK);
if (sink->width * sink->height >= 4096*3072)
if (sink->width * sink->height >= 4096 * 3072)
atomisp_store_uint32(DMA_BURST_SIZE_REG, 0x7F);
else
atomisp_store_uint32(DMA_BURST_SIZE_REG, 0x00);
@ -1717,7 +1722,7 @@ static int atomisp_streamon(struct file *file, void *fh,
sensor_start_stream = atomisp_sensor_start_stream(asd);
spin_lock_irqsave(&pipe->irq_lock, irqflags);
if (list_empty(&(pipe->capq.stream))) {
if (list_empty(&pipe->capq.stream)) {
spin_unlock_irqrestore(&pipe->irq_lock, irqflags);
dev_dbg(isp->dev, "no buffer in the queue\n");
ret = -EINVAL;
@ -1971,7 +1976,6 @@ int __atomisp_streamoff(struct file *file, void *fh, enum v4l2_buf_type type)
ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW &&
atomisp_subdev_source_pad(vdev) !=
ATOMISP_SUBDEV_PAD_SOURCE_VIDEO) {
if (isp->inputs[asd->input_curr].camera_caps->multi_stream_ctrl) {
v4l2_subdev_call(isp->inputs[asd->input_curr].camera,
video, s_stream, 0);
@ -2138,6 +2142,7 @@ stopsensor:
if (isp->sw_contex.power_state == ATOM_ISP_POWER_UP) {
unsigned int i;
bool recreate_streams[MAX_STREAM_NUM] = {0};
if (isp->isp_timeout)
dev_err(isp->dev, "%s: Resetting with WA activated",
__func__);
@ -2345,6 +2350,7 @@ static int atomisp_s_ctrl(struct file *file, void *fh,
rt_mutex_unlock(&isp->mutex);
return ret;
}
/*
* To query the attributes of a control.
* applications set the id field of a struct v4l2_queryctrl and call the

21
drivers/staging/media/atomisp/pci/atomisp2/atomisp_subdev.c
View File

@ -127,10 +127,11 @@ bool atomisp_subdev_format_conversion(struct atomisp_sub_device *asd,
&& !atomisp_is_mbuscode_raw(src->code);
}
uint16_t atomisp_subdev_source_pad(struct video_device * vdev)
uint16_t atomisp_subdev_source_pad(struct video_device *vdev)
{
struct media_link *link;
uint16_t ret = 0;
u16 ret = 0;
list_for_each_entry(link, &vdev->entity.links, list) {
if (link->source) {
ret = link->source->index;
@ -243,7 +244,7 @@ static int isp_subdev_validate_rect(struct v4l2_subdev *sd, uint32_t pad,
struct v4l2_rect *atomisp_subdev_get_rect(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
uint32_t which, uint32_t pad,
u32 which, uint32_t pad,
uint32_t target)
{
struct atomisp_sub_device *isp_sd = v4l2_get_subdevdata(sd);
@ -299,7 +300,7 @@ static void isp_get_fmt_rect(struct v4l2_subdev *sd,
static void isp_subdev_propagate(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
uint32_t which, uint32_t pad, uint32_t target,
u32 which, uint32_t pad, uint32_t target,
uint32_t flags)
{
struct v4l2_mbus_framefmt *ffmt[ATOMISP_SUBDEV_PADS_NUM];
@ -353,13 +354,13 @@ static char *atomisp_pad_str[] = { "ATOMISP_SUBDEV_PAD_SINK",
int atomisp_subdev_set_selection(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
uint32_t which, uint32_t pad, uint32_t target,
uint32_t flags, struct v4l2_rect *r)
u32 which, uint32_t pad, uint32_t target,
u32 flags, struct v4l2_rect *r)
{
struct atomisp_sub_device *isp_sd = v4l2_get_subdevdata(sd);
struct atomisp_device *isp = isp_sd->isp;
struct v4l2_mbus_framefmt *ffmt[ATOMISP_SUBDEV_PADS_NUM];
uint16_t vdev_pad = atomisp_subdev_source_pad(sd->devnode);
u16 vdev_pad = atomisp_subdev_source_pad(sd->devnode);
struct v4l2_rect *crop[ATOMISP_SUBDEV_PADS_NUM],
*comp[ATOMISP_SUBDEV_PADS_NUM];
enum atomisp_input_stream_id stream_id;
@ -551,6 +552,7 @@ static int isp_subdev_set_selection(struct v4l2_subdev *sd,
struct v4l2_subdev_selection *sel)
{
int rval = isp_subdev_validate_rect(sd, sel->pad, sel->target);
if (rval)
return rval;
@ -594,13 +596,13 @@ static int atomisp_get_sensor_bin_factor(struct atomisp_sub_device *asd)
void atomisp_subdev_set_ffmt(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg, uint32_t which,
uint32_t pad, struct v4l2_mbus_framefmt *ffmt)
u32 pad, struct v4l2_mbus_framefmt *ffmt)
{
struct atomisp_sub_device *isp_sd = v4l2_get_subdevdata(sd);
struct atomisp_device *isp = isp_sd->isp;
struct v4l2_mbus_framefmt *__ffmt =
atomisp_subdev_get_ffmt(sd, cfg, which, pad);
uint16_t vdev_pad = atomisp_subdev_source_pad(sd->devnode);
u16 vdev_pad = atomisp_subdev_source_pad(sd->devnode);
enum atomisp_input_stream_id stream_id;
dev_dbg(isp->dev, "ffmt: pad %s w %d h %d code 0x%8.8x which %s\n",
@ -1240,6 +1242,7 @@ int atomisp_create_pads_links(struct atomisp_device *isp)
{
struct atomisp_sub_device *asd;
int i, j, ret = 0;
isp->num_of_streams = 2;
for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) {
for (j = 0; j < isp->num_of_streams; j++) {

24
drivers/staging/media/atomisp/pci/atomisp2/atomisp_subdev.h
View File

@ -56,8 +56,8 @@ enum atomisp_subdev_input_entity {
struct atomisp_in_fmt_conv {
u32 code;
uint8_t bpp; /* bits per pixel */
uint8_t depth; /* uncompressed */
u8 bpp; /* bits per pixel */
u8 depth; /* uncompressed */
enum atomisp_input_format atomisp_in_fmt;
enum atomisp_css_bayer_order bayer_order;
enum atomisp_input_format css_stream_fmt;
@ -91,7 +91,7 @@ struct atomisp_video_pipe {
struct atomisp_device *isp;
struct v4l2_pix_format pix;
uint32_t sh_fmt;
u32 sh_fmt;
struct atomisp_sub_device *asd;
@ -192,7 +192,7 @@ struct atomisp_css_params {
* translate to ia_css_frame * and then set to CSS.
*/
void *output_frame;
uint32_t isp_config_id;
u32 isp_config_id;
/* Indicates which parameters need to be updated. */
struct atomisp_parameters update_flag;
@ -238,11 +238,11 @@ struct atomisp_subdev_params {
struct ia_css_3a_statistics *s3a_user_stat;
void *metadata_user[ATOMISP_METADATA_TYPE_NUM];
uint32_t metadata_width_size;
u32 metadata_width_size;
struct ia_css_dvs2_statistics *dvs_stat;
struct atomisp_css_dvs_6axis *dvs_6axis;
uint32_t exp_id;
u32 exp_id;
int dvs_hor_coef_bytes;
int dvs_ver_coef_bytes;
int dvs_ver_proj_bytes;
@ -291,7 +291,7 @@ struct atomisp_sub_device {
struct v4l2_subdev subdev;
struct media_pad pads[ATOMISP_SUBDEV_PADS_NUM];
struct atomisp_pad_format fmt[ATOMISP_SUBDEV_PADS_NUM];
uint16_t capture_pad; /* main capture pad; defines much of isp config */
u16 capture_pad; /* main capture pad; defines much of isp config */
enum atomisp_subdev_input_entity input;
unsigned int output;
@ -395,7 +395,7 @@ struct atomisp_sub_device {
bool copy_mode; /* CSI2+ use copy mode */
bool yuvpp_mode; /* CSI2+ yuvpp pipe */
int raw_buffer_bitmap[ATOMISP_MAX_EXP_ID/32 + 1]; /* Record each Raw Buffer lock status */
int raw_buffer_bitmap[ATOMISP_MAX_EXP_ID / 32 + 1]; /* Record each Raw Buffer lock status */
int raw_buffer_locked_count;
spinlock_t raw_buffer_bitmap_lock;
@ -442,16 +442,16 @@ struct v4l2_mbus_framefmt
uint32_t pad);
struct v4l2_rect *atomisp_subdev_get_rect(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
uint32_t which, uint32_t pad,
u32 which, uint32_t pad,
uint32_t target);
int atomisp_subdev_set_selection(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
uint32_t which, uint32_t pad, uint32_t target,
uint32_t flags, struct v4l2_rect *r);
u32 which, uint32_t pad, uint32_t target,
u32 flags, struct v4l2_rect *r);
/* Actually set the format */
void atomisp_subdev_set_ffmt(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg, uint32_t which,
uint32_t pad, struct v4l2_mbus_framefmt *ffmt);
u32 pad, struct v4l2_mbus_framefmt *ffmt);
int atomisp_update_run_mode(struct atomisp_sub_device *asd);

1
drivers/staging/media/atomisp/pci/atomisp2/atomisp_tpg.c
View File

@ -134,7 +134,6 @@ error:
void atomisp_tpg_cleanup(struct atomisp_device *isp)
{
}
int atomisp_tpg_init(struct atomisp_device *isp)

4
drivers/staging/media/atomisp/pci/atomisp2/atomisp_trace_event.h
View File

@ -54,9 +54,7 @@ TRACE_EVENT(camera_meminfo,
),
TP_printk(
"<%s> User ptr memory:%d pages,\tISP private memory used:%d"
" pages:\tsysFP system size:%d,\treserved size:%d"
"\tcamFP sysUse:%d,\tdycUse:%d,\tresUse:%d.\n",
"<%s> User ptr memory:%d pages,\tISP private memory used:%d pages:\tsysFP system size:%d,\treserved size:%d\tcamFP sysUse:%d,\tdycUse:%d,\tresUse:%d.\n",
__entry->name, __entry->uptr_size, __entry->counter,
__entry->sys_size, __entry->sys_res_size, __entry->cam_sys_use,
__entry->cam_dyc_use, __entry->cam_res_use)

20
drivers/staging/media/atomisp/pci/atomisp2/atomisp_v4l2.c
View File

@ -376,7 +376,6 @@ done:
return 0;
}
/*
* WA for DDR DVFS enable/disable
* By default, ISP will force DDR DVFS 1600MHz before disable DVFS
@ -448,7 +447,6 @@ int atomisp_mrfld_power_down(struct atomisp_device *isp)
}
}
/* Workaround for pmu_nc_set_power_state not ready in MRFLD */
int atomisp_mrfld_power_up(struct atomisp_device *isp)
{
@ -735,7 +733,7 @@ static int atomisp_subdev_probe(struct atomisp_device *isp)
int ret, raw_index = -1;
pdata = atomisp_get_platform_data();
if (pdata == NULL) {
if (!pdata) {
dev_err(isp->dev, "no platform data available\n");
return 0;
}
@ -748,7 +746,7 @@ static int atomisp_subdev_probe(struct atomisp_device *isp)
i2c_get_adapter(subdevs->v4l2_subdev.i2c_adapter_id);
int sensor_num, i;
if (adapter == NULL) {
if (!adapter) {
dev_err(isp->dev,
"Failed to find i2c adapter for subdev %s\n",
board_info->type);
@ -766,7 +764,7 @@ static int atomisp_subdev_probe(struct atomisp_device *isp)
continue;
}
if (subdev == NULL) {
if (!subdev) {
dev_warn(isp->dev, "Subdev %s detection fail\n",
board_info->type);
continue;
@ -825,7 +823,6 @@ static int atomisp_subdev_probe(struct atomisp_device *isp)
dev_dbg(isp->dev, "unknown subdev probed\n");
break;
}
}
/*
@ -937,7 +934,7 @@ static int atomisp_register_entities(struct atomisp_device *isp)
asd->delayed_init_workq =
alloc_workqueue(isp->v4l2_dev.name, WQ_CPU_INTENSIVE,
1);
if (asd->delayed_init_workq == NULL) {
if (!asd->delayed_init_workq) {
dev_err(isp->dev,
"Failed to initialize delayed init workq\n");
ret = -ENOMEM;
@ -1037,7 +1034,6 @@ static int atomisp_initialize_modules(struct atomisp_device *isp)
goto error_isp_subdev;
}
return 0;
error_isp_subdev:
@ -1128,7 +1124,7 @@ static int init_atomisp_wdts(struct atomisp_device *isp)
atomic_set(&isp->wdt_work_queued, 0);
isp->wdt_work_queue = alloc_workqueue(isp->v4l2_dev.name, 0, 1);
if (isp->wdt_work_queue == NULL) {
if (!isp->wdt_work_queue) {
dev_err(isp->dev, "Failed to initialize wdt work queue\n");
err = -ENOMEM;
goto alloc_fail;
@ -1174,7 +1170,7 @@ static int atomisp_pci_probe(struct pci_dev *dev,
atomisp_dev = &dev->dev;
pdata = atomisp_get_platform_data();
if (pdata == NULL)
if (!pdata)
dev_warn(&dev->dev, "no platform data available\n");
err = pcim_enable_device(dev);
@ -1243,13 +1239,13 @@ static int atomisp_pci_probe(struct pci_dev *dev,
(ATOMISP_HW_REVISION_ISP2400
<< ATOMISP_HW_REVISION_SHIFT) |
ATOMISP_HW_STEPPING_B0;
#ifdef FIXME
#ifdef FIXME
if (INTEL_MID_BOARD(3, TABLET, BYT, BLK, PRO, CRV2) ||
INTEL_MID_BOARD(3, TABLET, BYT, BLK, ENG, CRV2)) {
isp->dfs = &dfs_config_byt_cr;
isp->hpll_freq = HPLL_FREQ_2000MHZ;
} else
#endif
#endif
{
isp->dfs = &dfs_config_byt;
isp->hpll_freq = HPLL_FREQ_1600MHZ;

68
drivers/staging/media/atomisp/pci/atomisp2/css2400/base/circbuf/interface/ia_css_circbuf.h
View File

@ -44,7 +44,7 @@ struct ia_css_circbuf_s {
* @param elems An array of elements.
* @param desc The descriptor set to the size using ia_css_circbuf_desc_init().
*/
extern void ia_css_circbuf_create(
void ia_css_circbuf_create(
ia_css_circbuf_t *cb,
ia_css_circbuf_elem_t *elems,
ia_css_circbuf_desc_t *desc);
@ -54,7 +54,7 @@ extern void ia_css_circbuf_create(
*
* @param cb The pointer to the circular buffer.
*/
extern void ia_css_circbuf_destroy(
void ia_css_circbuf_destroy(
ia_css_circbuf_t *cb);
/**
@ -67,7 +67,7 @@ extern void ia_css_circbuf_destroy(
*
* @return the pop-out value.
*/
extern uint32_t ia_css_circbuf_pop(
uint32_t ia_css_circbuf_pop(
ia_css_circbuf_t *cb);
/**
@ -81,7 +81,7 @@ extern uint32_t ia_css_circbuf_pop(
*
* @return the extracted value.
*/
extern uint32_t ia_css_circbuf_extract(
uint32_t ia_css_circbuf_extract(
ia_css_circbuf_t *cb,
int offset);
@ -100,7 +100,7 @@ static inline void ia_css_circbuf_elem_set_val(
ia_css_circbuf_elem_t *elem,
uint32_t val)
{
OP___assert(elem != NULL);
OP___assert(elem);
elem->val = val;
}
@ -113,7 +113,7 @@ static inline void ia_css_circbuf_elem_set_val(
static inline void ia_css_circbuf_elem_init(
ia_css_circbuf_elem_t *elem)
{
OP___assert(elem != NULL);
OP___assert(elem);
ia_css_circbuf_elem_set_val(elem, 0);
}
@ -127,8 +127,8 @@ static inline void ia_css_circbuf_elem_cpy(
ia_css_circbuf_elem_t *src,
ia_css_circbuf_elem_t *dest)
{
OP___assert(src != NULL);
OP___assert(dest != NULL);
OP___assert(src);
OP___assert(dest);
ia_css_circbuf_elem_set_val(dest, src->val);
}
@ -144,13 +144,13 @@ static inline void ia_css_circbuf_elem_cpy(
*/
static inline uint8_t ia_css_circbuf_get_pos_at_offset(
ia_css_circbuf_t *cb,
uint32_t base,
u32 base,
int offset)
{
uint8_t dest;
u8 dest;
OP___assert(cb != NULL);
OP___assert(cb->desc != NULL);
OP___assert(cb);
OP___assert(cb->desc);
OP___assert(cb->desc->size > 0);
/* step 1: adjudst the offset */
@ -177,13 +177,13 @@ static inline uint8_t ia_css_circbuf_get_pos_at_offset(
*/
static inline int ia_css_circbuf_get_offset(
ia_css_circbuf_t *cb,
uint32_t src_pos,
u32 src_pos,
uint32_t dest_pos)
{
int offset;
OP___assert(cb != NULL);
OP___assert(cb->desc != NULL);
OP___assert(cb);
OP___assert(cb->desc);
offset = (int)(dest_pos - src_pos);
offset += (offset < 0) ? cb->desc->size : 0;
@ -203,8 +203,8 @@ static inline int ia_css_circbuf_get_offset(
static inline uint32_t ia_css_circbuf_get_size(
ia_css_circbuf_t *cb)
{
OP___assert(cb != NULL);
OP___assert(cb->desc != NULL);
OP___assert(cb);
OP___assert(cb->desc);
return cb->desc->size;
}
@ -221,8 +221,8 @@ static inline uint32_t ia_css_circbuf_get_num_elems(
{
int num;
OP___assert(cb != NULL);
OP___assert(cb->desc != NULL);
OP___assert(cb);
OP___assert(cb->desc);
num = ia_css_circbuf_get_offset(cb, cb->desc->start, cb->desc->end);
@ -241,8 +241,8 @@ static inline uint32_t ia_css_circbuf_get_num_elems(
static inline bool ia_css_circbuf_is_empty(
ia_css_circbuf_t *cb)
{
OP___assert(cb != NULL);
OP___assert(cb->desc != NULL);
OP___assert(cb);
OP___assert(cb->desc);
return ia_css_circbuf_desc_is_empty(cb->desc);
}
@ -258,8 +258,8 @@ static inline bool ia_css_circbuf_is_empty(
*/
static inline bool ia_css_circbuf_is_full(ia_css_circbuf_t *cb)
{
OP___assert(cb != NULL);
OP___assert(cb->desc != NULL);
OP___assert(cb);
OP___assert(cb->desc);
return ia_css_circbuf_desc_is_full(cb->desc);
}
@ -277,8 +277,8 @@ static inline void ia_css_circbuf_write(
ia_css_circbuf_t *cb,
ia_css_circbuf_elem_t elem)
{
OP___assert(cb != NULL);
OP___assert(cb->desc != NULL);
OP___assert(cb);
OP___assert(cb->desc);
/* Cannot continue as the queue is full*/
assert(!ia_css_circbuf_is_full(cb));
@ -303,7 +303,7 @@ static inline void ia_css_circbuf_push(
{
ia_css_circbuf_elem_t elem;
OP___assert(cb != NULL);
OP___assert(cb);
/* set up an element */
ia_css_circbuf_elem_init(&elem);
@ -323,8 +323,8 @@ static inline void ia_css_circbuf_push(
static inline uint32_t ia_css_circbuf_get_free_elems(
ia_css_circbuf_t *cb)
{
OP___assert(cb != NULL);
OP___assert(cb->desc != NULL);
OP___assert(cb);
OP___assert(cb->desc);
return ia_css_circbuf_desc_get_free_elems(cb->desc);
}
@ -337,7 +337,7 @@ static inline uint32_t ia_css_circbuf_get_free_elems(
*
* @return the elements value.
*/
extern uint32_t ia_css_circbuf_peek(
uint32_t ia_css_circbuf_peek(
ia_css_circbuf_t *cb,
int offset);
@ -349,7 +349,7 @@ extern uint32_t ia_css_circbuf_peek(
*
* @return the elements value.
*/
extern uint32_t ia_css_circbuf_peek_from_start(
uint32_t ia_css_circbuf_peek_from_start(
ia_css_circbuf_t *cb,
int offset);
@ -362,13 +362,13 @@ extern uint32_t ia_css_circbuf_peek_from_start(
* @param sz_delta delta increase for new size
* @param elems (optional) pointers to new additional elements
* cb element array size will not be increased dynamically,
* but new elements should be added at the end to existing
* cb element array which if of max_size >= new size
* but new elements should be added at the end to existing
* cb element array which if of max_size >= new size
*
* @return true on successfully increasing the size
* false on failure
* false on failure
*/
extern bool ia_css_circbuf_increase_size(
bool ia_css_circbuf_increase_size(
ia_css_circbuf_t *cb,
unsigned int sz_delta,
ia_css_circbuf_elem_t *elems);

12
drivers/staging/media/atomisp/pci/atomisp2/css2400/base/circbuf/interface/ia_css_circbuf_comm.h
View File

@ -35,11 +35,12 @@
*/
typedef struct ia_css_circbuf_desc_s ia_css_circbuf_desc_t;
struct ia_css_circbuf_desc_s {
uint8_t size; /* the maximum number of elements*/
uint8_t step; /* number of bytes per element */
uint8_t start; /* index of the oldest element */
uint8_t end; /* index at which to write the new element */
u8 size; /* the maximum number of elements*/
u8 step; /* number of bytes per element */
u8 start; /* index of the oldest element */
u8 end; /* index at which to write the new element */
};
#define SIZE_OF_IA_CSS_CIRCBUF_DESC_S_STRUCT \
(4 * sizeof(uint8_t))
@ -48,8 +49,9 @@ struct ia_css_circbuf_desc_s {
*/
typedef struct ia_css_circbuf_elem_s ia_css_circbuf_elem_t;
struct ia_css_circbuf_elem_s {
uint32_t val; /* the value stored in the element */
u32 val; /* the value stored in the element */
};
#define SIZE_OF_IA_CSS_CIRCBUF_ELEM_S_STRUCT \
(sizeof(uint32_t))

26
drivers/staging/media/atomisp/pci/atomisp2/css2400/base/circbuf/interface/ia_css_circbuf_desc.h
View File

@ -37,7 +37,7 @@
static inline bool ia_css_circbuf_desc_is_empty(
ia_css_circbuf_desc_t *cb_desc)
{
OP___assert(cb_desc != NULL);
OP___assert(cb_desc);
return (cb_desc->end == cb_desc->start);
}
@ -54,7 +54,7 @@ static inline bool ia_css_circbuf_desc_is_empty(
static inline bool ia_css_circbuf_desc_is_full(
ia_css_circbuf_desc_t *cb_desc)
{
OP___assert(cb_desc != NULL);
OP___assert(cb_desc);
return (OP_std_modadd(cb_desc->end, 1, cb_desc->size) == cb_desc->start);
}
@ -68,7 +68,7 @@ static inline void ia_css_circbuf_desc_init(
ia_css_circbuf_desc_t *cb_desc,
int8_t size)
{
OP___assert(cb_desc != NULL);
OP___assert(cb_desc);
cb_desc->size = size;
}
@ -83,11 +83,12 @@ static inline void ia_css_circbuf_desc_init(
*/
static inline uint8_t ia_css_circbuf_desc_get_pos_at_offset(
ia_css_circbuf_desc_t *cb_desc,
uint32_t base,
u32 base,
int offset)
{
uint8_t dest;
OP___assert(cb_desc != NULL);
u8 dest;
OP___assert(cb_desc);
OP___assert(cb_desc->size > 0);
/* step 1: adjust the offset */
@ -115,11 +116,12 @@ static inline uint8_t ia_css_circbuf_desc_get_pos_at_offset(
*/
static inline int ia_css_circbuf_desc_get_offset(
ia_css_circbuf_desc_t *cb_desc,
uint32_t src_pos,
u32 src_pos,
uint32_t dest_pos)
{
int offset;
OP___assert(cb_desc != NULL);
OP___assert(cb_desc);
offset = (int)(dest_pos - src_pos);
offset += (offset < 0) ? cb_desc->size : 0;
@ -138,7 +140,8 @@ static inline uint32_t ia_css_circbuf_desc_get_num_elems(
ia_css_circbuf_desc_t *cb_desc)
{
int num;
OP___assert(cb_desc != NULL);
OP___assert(cb_desc);
num = ia_css_circbuf_desc_get_offset(cb_desc,
cb_desc->start,
@ -157,8 +160,9 @@ static inline uint32_t ia_css_circbuf_desc_get_num_elems(
static inline uint32_t ia_css_circbuf_desc_get_free_elems(
ia_css_circbuf_desc_t *cb_desc)
{
uint32_t num;
OP___assert(cb_desc != NULL);
u32 num;
OP___assert(cb_desc);
num = ia_css_circbuf_desc_get_offset(cb_desc,
cb_desc->start,

23
drivers/staging/media/atomisp/pci/atomisp2/css2400/base/circbuf/src/circbuf.c
View File

@ -45,7 +45,7 @@ ia_css_circbuf_read(ia_css_circbuf_t *cb);
* @param chunk_dest The position to which the first element in the chunk would be shift.
*/
static inline void ia_css_circbuf_shift_chunk(ia_css_circbuf_t *cb,
uint32_t chunk_src,
u32 chunk_src,
uint32_t chunk_dest);
/*
@ -72,7 +72,7 @@ ia_css_circbuf_create(ia_css_circbuf_t *cb,
ia_css_circbuf_elem_t *elems,
ia_css_circbuf_desc_t *desc)
{
uint32_t i;
u32 i;
OP___assert(desc);
@ -105,7 +105,7 @@ void ia_css_circbuf_destroy(ia_css_circbuf_t *cb)
*/
uint32_t ia_css_circbuf_pop(ia_css_circbuf_t *cb)
{
uint32_t ret;
u32 ret;
ia_css_circbuf_elem_t elem;
assert(!ia_css_circbuf_is_empty(cb));
@ -123,10 +123,10 @@ uint32_t ia_css_circbuf_pop(ia_css_circbuf_t *cb)
uint32_t ia_css_circbuf_extract(ia_css_circbuf_t *cb, int offset)
{
int max_offset;
uint32_t val;
uint32_t pos;
uint32_t src_pos;
uint32_t dest_pos;
u32 val;
u32 pos;
u32 src_pos;
u32 dest_pos;
/* get the maximum offest */
max_offset = ia_css_circbuf_get_offset(cb, cb->desc->start, cb->desc->end);
@ -204,8 +204,8 @@ bool ia_css_circbuf_increase_size(
unsigned int sz_delta,
ia_css_circbuf_elem_t *elems)
{
uint8_t curr_size;
uint8_t curr_end;
u8 curr_size;
u8 curr_end;
unsigned int i = 0;
if (!cb || sz_delta == 0)
@ -288,7 +288,7 @@ ia_css_circbuf_read(ia_css_circbuf_t *cb)
*/
static inline void
ia_css_circbuf_shift_chunk(ia_css_circbuf_t *cb,
uint32_t chunk_src, uint32_t chunk_dest)
u32 chunk_src, uint32_t chunk_dest)
{
int chunk_offset;
int chunk_sz;
@ -301,7 +301,6 @@ ia_css_circbuf_shift_chunk(ia_css_circbuf_t *cb,
/* shift each element to its terminal position */
for (i = 0; i < chunk_sz; i++) {
/* copy the element from the source to the destination */
ia_css_circbuf_elem_cpy(&cb->elems[chunk_src],
&cb->elems[chunk_dest]);
@ -312,10 +311,8 @@ ia_css_circbuf_shift_chunk(ia_css_circbuf_t *cb,
/* adjust the source/terminal positions */
chunk_src = ia_css_circbuf_get_pos_at_offset(cb, chunk_src, -1);
chunk_dest = ia_css_circbuf_get_pos_at_offset(cb, chunk_dest, -1);
}
/* adjust the index "start" */
cb->desc->start = ia_css_circbuf_get_pos_at_offset(cb, cb->desc->start, chunk_offset);
}

14
drivers/staging/media/atomisp/pci/atomisp2/css2400/base/refcount/interface/ia_css_refcount.h
View File

@ -26,13 +26,13 @@ typedef void (*clear_func)(hrt_vaddress ptr);
* \param[in] size Size of the refcount list.
* \return ia_css_err
*/
extern enum ia_css_err ia_css_refcount_init(uint32_t size);
enum ia_css_err ia_css_refcount_init(uint32_t size);
/*! \brief Function for de-initializing refcount list
*
* \return None
*/
extern void ia_css_refcount_uninit(void);
void ia_css_refcount_uninit(void);
/*! \brief Function for increasing reference by 1.
*
@ -40,7 +40,7 @@ extern void ia_css_refcount_uninit(void);
* \param[in] ptr Data of the object (ptr).
* \return hrt_vaddress (saved address)
*/
extern hrt_vaddress ia_css_refcount_increment(int32_t id, hrt_vaddress ptr);
hrt_vaddress ia_css_refcount_increment(s32 id, hrt_vaddress ptr);
/*! \brief Function for decrease reference by 1.
*
@ -50,7 +50,7 @@ extern hrt_vaddress ia_css_refcount_increment(int32_t id, hrt_vaddress ptr);
* - true, if it is successful.
* - false, otherwise.
*/
extern bool ia_css_refcount_decrement(int32_t id, hrt_vaddress ptr);
bool ia_css_refcount_decrement(s32 id, hrt_vaddress ptr);
/*! \brief Function to check if reference count is 1.
*
@ -59,7 +59,7 @@ extern bool ia_css_refcount_decrement(int32_t id, hrt_vaddress ptr);
* - true, if it is successful.
* - false, otherwise.
*/
extern bool ia_css_refcount_is_single(hrt_vaddress ptr);
bool ia_css_refcount_is_single(hrt_vaddress ptr);
/*! \brief Function to clear reference list objects.
*
@ -68,7 +68,7 @@ extern bool ia_css_refcount_is_single(hrt_vaddress ptr);
*
* return None
*/
extern void ia_css_refcount_clear(int32_t id,
void ia_css_refcount_clear(s32 id,
clear_func clear_func_ptr);
/*! \brief Function to verify if object is valid
@ -78,6 +78,6 @@ extern void ia_css_refcount_clear(int32_t id,
* - true, if valid
* - false, if invalid
*/
extern bool ia_css_refcount_is_valid(hrt_vaddress ptr);
bool ia_css_refcount_is_valid(hrt_vaddress ptr);
#endif /* _IA_CSS_REFCOUNT_H_ */

43
drivers/staging/media/atomisp/pci/atomisp2/css2400/base/refcount/src/refcount.c
View File

@ -25,13 +25,13 @@
/* TODO: enable for other memory aswell
now only for hrt_vaddress */
struct ia_css_refcount_entry {
uint32_t count;
u32 count;
hrt_vaddress data;
int32_t id;
s32 id;
};
struct ia_css_refcount_list {
uint32_t size;
u32 size;
struct ia_css_refcount_entry *items;
};
@ -40,18 +40,17 @@ static struct ia_css_refcount_list myrefcount;
static struct ia_css_refcount_entry *refcount_find_entry(hrt_vaddress ptr,
bool firstfree)
{
uint32_t i;
u32 i;
if (ptr == 0)
return NULL;
if (myrefcount.items == NULL) {
if (!myrefcount.items) {
ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR,
"refcount_find_entry(): Ref count not initiliazed!\n");
return NULL;
}
for (i = 0; i < myrefcount.size; i++) {
if ((&myrefcount.items[i])->data == 0) {
if (firstfree) {
/* for new entry */
@ -75,7 +74,7 @@ enum ia_css_err ia_css_refcount_init(uint32_t size)
"ia_css_refcount_init(): Size of 0 for Ref count init!\n");
return IA_CSS_ERR_INVALID_ARGUMENTS;
}
if (myrefcount.items != NULL) {
if (myrefcount.items) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_refcount_init(): Ref count is already initialized\n");
return IA_CSS_ERR_INTERNAL_ERROR;
@ -95,7 +94,8 @@ enum ia_css_err ia_css_refcount_init(uint32_t size)
void ia_css_refcount_uninit(void)
{
struct ia_css_refcount_entry *entry;
uint32_t i;
u32 i;
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_refcount_uninit() entry\n");
for (i = 0; i < myrefcount.size; i++) {
@ -121,7 +121,7 @@ void ia_css_refcount_uninit(void)
"ia_css_refcount_uninit() leave\n");
}
hrt_vaddress ia_css_refcount_increment(int32_t id, hrt_vaddress ptr)
hrt_vaddress ia_css_refcount_increment(s32 id, hrt_vaddress ptr)
{
struct ia_css_refcount_entry *entry;
@ -135,8 +135,8 @@ hrt_vaddress ia_css_refcount_increment(int32_t id, hrt_vaddress ptr)
if (!entry) {
entry = refcount_find_entry(ptr, true);
assert(entry != NULL);
if (entry == NULL)
assert(entry);
if (!entry)
return mmgr_NULL;
entry->id = id;
}
@ -158,7 +158,7 @@ hrt_vaddress ia_css_refcount_increment(int32_t id, hrt_vaddress ptr)
return ptr;
}
bool ia_css_refcount_decrement(int32_t id, hrt_vaddress ptr)
bool ia_css_refcount_decrement(s32 id, hrt_vaddress ptr)
{
struct ia_css_refcount_entry *entry;
@ -218,13 +218,13 @@ bool ia_css_refcount_is_single(hrt_vaddress ptr)
return true;
}
void ia_css_refcount_clear(int32_t id, clear_func clear_func_ptr)
void ia_css_refcount_clear(s32 id, clear_func clear_func_ptr)
{
struct ia_css_refcount_entry *entry;
uint32_t i;
uint32_t count = 0;
u32 i;
u32 count = 0;
assert(clear_func_ptr != NULL);
assert(clear_func_ptr);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_refcount_clear(%x)\n",
id);
@ -236,16 +236,14 @@ void ia_css_refcount_clear(int32_t id, clear_func clear_func_ptr)
entry = myrefcount.items + i;
if ((entry->data != mmgr_NULL) && (entry->id == id)) {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_refcount_clear:"
" %x: 0x%x\n", id, entry->data);
"ia_css_refcount_clear: %x: 0x%x\n",
id, entry->data);
if (clear_func_ptr) {
/* clear using provided function */
clear_func_ptr(entry->data);
} else {
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"ia_css_refcount_clear: "
"using hmm_free: "
"no clear_func\n");
"ia_css_refcount_clear: using hmm_free: no clear_func\n");
hmm_free(entry->data);
}
#ifndef ISP2401
@ -276,6 +274,5 @@ bool ia_css_refcount_is_valid(hrt_vaddress ptr)
entry = refcount_find_entry(ptr, false);
return entry != NULL;
return entry;
}

30
drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/pipe/interface/ia_css_pipe_binarydesc.h
View File

@ -29,7 +29,7 @@
* @return None
*
*/
extern void ia_css_pipe_get_copy_binarydesc(
void ia_css_pipe_get_copy_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *copy_descr,
struct ia_css_frame_info *in_info,
@ -45,7 +45,7 @@ extern void ia_css_pipe_get_copy_binarydesc(
* @return None
*
*/
extern void ia_css_pipe_get_vfpp_binarydesc(
void ia_css_pipe_get_vfpp_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *vf_pp_descr,
struct ia_css_frame_info *in_info,
@ -62,7 +62,7 @@ extern void ia_css_pipe_get_vfpp_binarydesc(
* @return IA_CSS_SUCCESS or error code upon error.
*
*/
extern enum ia_css_err sh_css_bds_factor_get_numerator_denominator(
enum ia_css_err sh_css_bds_factor_get_numerator_denominator(
unsigned int bds_factor,
unsigned int *bds_factor_numerator,
unsigned int *bds_factor_denominator);
@ -78,7 +78,7 @@ extern enum ia_css_err sh_css_bds_factor_get_numerator_denominator(
* @return IA_CSS_SUCCESS or error code upon error.
*
*/
extern enum ia_css_err ia_css_pipe_get_preview_binarydesc(
enum ia_css_err ia_css_pipe_get_preview_binarydesc(
struct ia_css_pipe * const pipe,
struct ia_css_binary_descr *preview_descr,
struct ia_css_frame_info *in_info,
@ -96,7 +96,7 @@ extern enum ia_css_err ia_css_pipe_get_preview_binarydesc(
* @return IA_CSS_SUCCESS or error code upon error.
*
*/
extern enum ia_css_err ia_css_pipe_get_video_binarydesc(
enum ia_css_err ia_css_pipe_get_video_binarydesc(
struct ia_css_pipe * const pipe,
struct ia_css_binary_descr *video_descr,
struct ia_css_frame_info *in_info,
@ -133,7 +133,7 @@ void ia_css_pipe_get_yuvscaler_binarydesc(
* @return None
*
*/
extern void ia_css_pipe_get_capturepp_binarydesc(
void ia_css_pipe_get_capturepp_binarydesc(
struct ia_css_pipe * const pipe,
struct ia_css_binary_descr *capture_pp_descr,
struct ia_css_frame_info *in_info,
@ -150,7 +150,7 @@ extern void ia_css_pipe_get_capturepp_binarydesc(
* @return None
*
*/
extern void ia_css_pipe_get_primary_binarydesc(
void ia_css_pipe_get_primary_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *prim_descr,
struct ia_css_frame_info *in_info,
@ -167,7 +167,7 @@ extern void ia_css_pipe_get_primary_binarydesc(
* @return None
*
*/
extern void ia_css_pipe_get_pre_gdc_binarydesc(
void ia_css_pipe_get_pre_gdc_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *gdc_descr,
struct ia_css_frame_info *in_info,
@ -182,7 +182,7 @@ extern void ia_css_pipe_get_pre_gdc_binarydesc(
* @return None
*
*/
extern void ia_css_pipe_get_gdc_binarydesc(
void ia_css_pipe_get_gdc_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *gdc_descr,
struct ia_css_frame_info *in_info,
@ -198,7 +198,7 @@ extern void ia_css_pipe_get_gdc_binarydesc(
* @return None
*
*/
extern void ia_css_pipe_get_post_gdc_binarydesc(
void ia_css_pipe_get_post_gdc_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *post_gdc_descr,
struct ia_css_frame_info *in_info,
@ -214,7 +214,7 @@ extern void ia_css_pipe_get_post_gdc_binarydesc(
* @return None
*
*/
extern void ia_css_pipe_get_pre_de_binarydesc(
void ia_css_pipe_get_pre_de_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *pre_de_descr,
struct ia_css_frame_info *in_info,
@ -229,7 +229,7 @@ extern void ia_css_pipe_get_pre_de_binarydesc(
* @return None
*
*/
extern void ia_css_pipe_get_pre_anr_binarydesc(
void ia_css_pipe_get_pre_anr_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *pre_anr_descr,
struct ia_css_frame_info *in_info,
@ -244,7 +244,7 @@ extern void ia_css_pipe_get_pre_anr_binarydesc(
* @return None
*
*/
extern void ia_css_pipe_get_anr_binarydesc(
void ia_css_pipe_get_anr_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *anr_descr,
struct ia_css_frame_info *in_info,
@ -260,7 +260,7 @@ extern void ia_css_pipe_get_anr_binarydesc(
* @return None
*
*/
extern void ia_css_pipe_get_post_anr_binarydesc(
void ia_css_pipe_get_post_anr_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *post_anr_descr,
struct ia_css_frame_info *in_info,
@ -276,7 +276,7 @@ extern void ia_css_pipe_get_post_anr_binarydesc(
* @return None
*
*/
extern void ia_css_pipe_get_ldc_binarydesc(
void ia_css_pipe_get_ldc_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *ldc_descr,
struct ia_css_frame_info *in_info,

11
drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/pipe/interface/ia_css_pipe_stagedesc.h
View File

@ -21,14 +21,14 @@
#include "ia_css_pipeline.h"
#include "ia_css_pipeline_common.h"
extern void ia_css_pipe_get_generic_stage_desc(
void ia_css_pipe_get_generic_stage_desc(
struct ia_css_pipeline_stage_desc *stage_desc,
struct ia_css_binary *binary,
struct ia_css_frame *out_frame[],
struct ia_css_frame *in_frame,
struct ia_css_frame *vf_frame);
extern void ia_css_pipe_get_firmwares_stage_desc(
void ia_css_pipe_get_firmwares_stage_desc(
struct ia_css_pipeline_stage_desc *stage_desc,
struct ia_css_binary *binary,
struct ia_css_frame *out_frame[],
@ -37,16 +37,15 @@ extern void ia_css_pipe_get_firmwares_stage_desc(
const struct ia_css_fw_info *fw,
unsigned int mode);
extern void ia_css_pipe_get_acc_stage_desc(
void ia_css_pipe_get_acc_stage_desc(
struct ia_css_pipeline_stage_desc *stage_desc,
struct ia_css_binary *binary,
struct ia_css_fw_info *fw);
extern void ia_css_pipe_get_sp_func_stage_desc(
void ia_css_pipe_get_sp_func_stage_desc(
struct ia_css_pipeline_stage_desc *stage_desc,
struct ia_css_frame *out_frame,
enum ia_css_pipeline_stage_sp_func sp_func,
unsigned max_input_width);
unsigned int max_input_width);
#endif /*__IA_CSS_PIPE_STAGEDESC__H__ */

6
drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/pipe/interface/ia_css_pipe_util.h
View File

@ -25,13 +25,13 @@
* @return bits per pixel for the underlying stream
*
*/
extern unsigned int ia_css_pipe_util_pipe_input_format_bpp(
unsigned int ia_css_pipe_util_pipe_input_format_bpp(
const struct ia_css_pipe * const pipe);
extern void ia_css_pipe_util_create_output_frames(
void ia_css_pipe_util_create_output_frames(
struct ia_css_frame *frames[]);
extern void ia_css_pipe_util_set_output_frames(
void ia_css_pipe_util_set_output_frames(
struct ia_css_frame *frames[],
unsigned int idx,
struct ia_css_frame *frame);

102
drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/pipe/src/pipe_binarydesc.c
View File

@ -40,8 +40,8 @@ static void pipe_binarydesc_get_offline(
{
unsigned int i;
/* in_info, out_info, vf_info can be NULL */
assert(pipe != NULL);
assert(descr != NULL);
assert(pipe);
assert(descr);
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
"pipe_binarydesc_get_offline() enter:\n");
@ -86,8 +86,8 @@ void ia_css_pipe_get_copy_binarydesc(
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
unsigned int i;
/* out_info can be NULL */
assert(pipe != NULL);
assert(in_info != NULL);
assert(pipe);
assert(in_info);
IA_CSS_ENTER_PRIVATE("");
*in_info = *out_info;
@ -103,6 +103,7 @@ void ia_css_pipe_get_copy_binarydesc(
copy_descr->isp_pipe_version = IA_CSS_PIPE_VERSION_1;
IA_CSS_LEAVE_PRIVATE("");
}
void ia_css_pipe_get_vfpp_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *vf_pp_descr,
@ -112,8 +113,8 @@ void ia_css_pipe_get_vfpp_binarydesc(
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
unsigned int i;
/* out_info can be NULL ??? */
assert(pipe != NULL);
assert(in_info != NULL);
assert(pipe);
assert(in_info);
IA_CSS_ENTER_PRIVATE("");
in_info->raw_bit_depth = 0;
@ -184,8 +185,8 @@ enum ia_css_err binarydesc_calculate_bds_factor(
/* Loop over all bds factors until a match is found */
for (i = 0; i < ARRAY_SIZE(bds_factors_list); i++) {
unsigned num = bds_factors_list[i].numerator;
unsigned den = bds_factors_list[i].denominator;
unsigned int num = bds_factors_list[i].numerator;
unsigned int den = bds_factors_list[i].denominator;
/* See width-wise and height-wise if this bds_factor
* satisfies the condition */
@ -217,10 +218,10 @@ enum ia_css_err ia_css_pipe_get_preview_binarydesc(
int mode = IA_CSS_BINARY_MODE_PREVIEW;
unsigned int i;
assert(pipe != NULL);
assert(in_info != NULL);
assert(out_info != NULL);
assert(vf_info != NULL);
assert(pipe);
assert(in_info);
assert(out_info);
assert(vf_info);
IA_CSS_ENTER_PRIVATE("");
/*
@ -339,8 +340,8 @@ enum ia_css_err ia_css_pipe_get_video_binarydesc(
bool stream_dz_config = false;
/* vf_info can be NULL */
assert(pipe != NULL);
assert(in_info != NULL);
assert(pipe);
assert(in_info);
/* assert(vf_info != NULL); */
IA_CSS_ENTER_PRIVATE("");
@ -459,8 +460,8 @@ void ia_css_pipe_get_yuvscaler_binarydesc(
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
struct ia_css_frame_info *this_vf_info = NULL;
assert(pipe != NULL);
assert(in_info != NULL);
assert(pipe);
assert(in_info);
/* Note: if the following assert fails, the number of ports has been
* changed; in that case an additional initializer must be added
* a few lines below after which this assert can be updated.
@ -502,12 +503,11 @@ void ia_css_pipe_get_capturepp_binarydesc(
unsigned int i;
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
assert(pipe != NULL);
assert(in_info != NULL);
assert(vf_info != NULL);
assert(pipe);
assert(in_info);
assert(vf_info);
IA_CSS_ENTER_PRIVATE("");
/* the in_info is only used for resolution to enable
bayer down scaling. */
if (pipe->out_yuv_ds_input_info.res.width)
@ -536,8 +536,7 @@ void ia_css_pipe_get_capturepp_binarydesc(
}
/* lookup table for high quality primary binaries */
static unsigned int primary_hq_binary_modes[NUM_PRIMARY_HQ_STAGES] =
{
static unsigned int primary_hq_binary_modes[NUM_PRIMARY_HQ_STAGES] = {
IA_CSS_BINARY_MODE_PRIMARY_HQ_STAGE0,
IA_CSS_BINARY_MODE_PRIMARY_HQ_STAGE1,
IA_CSS_BINARY_MODE_PRIMARY_HQ_STAGE2,
@ -559,9 +558,9 @@ void ia_css_pipe_get_primary_binarydesc(
unsigned int i;
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
assert(pipe != NULL);
assert(in_info != NULL);
assert(out_info != NULL);
assert(pipe);
assert(in_info);
assert(out_info);
assert(stage_idx < NUM_PRIMARY_HQ_STAGES);
/* vf_info can be NULL - example video_binarydescr */
/*assert(vf_info != NULL);*/
@ -637,9 +636,9 @@ void ia_css_pipe_get_pre_gdc_binarydesc(
unsigned int i;
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
assert(pipe != NULL);
assert(in_info != NULL);
assert(out_info != NULL);
assert(pipe);
assert(in_info);
assert(out_info);
IA_CSS_ENTER_PRIVATE("");
*in_info = *out_info;
@ -664,9 +663,9 @@ void ia_css_pipe_get_gdc_binarydesc(
unsigned int i;
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
assert(pipe != NULL);
assert(in_info != NULL);
assert(out_info != NULL);
assert(pipe);
assert(in_info);
assert(out_info);
IA_CSS_ENTER_PRIVATE("");
*in_info = *out_info;
@ -690,10 +689,10 @@ void ia_css_pipe_get_post_gdc_binarydesc(
unsigned int i;
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
assert(pipe != NULL);
assert(in_info != NULL);
assert(out_info != NULL);
assert(vf_info != NULL);
assert(pipe);
assert(in_info);
assert(out_info);
assert(vf_info);
IA_CSS_ENTER_PRIVATE("");
*in_info = *out_info;
@ -719,9 +718,9 @@ void ia_css_pipe_get_pre_de_binarydesc(
unsigned int i;
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
assert(pipe != NULL);
assert(in_info != NULL);
assert(out_info != NULL);
assert(pipe);
assert(in_info);
assert(out_info);
IA_CSS_ENTER_PRIVATE("");
*in_info = *out_info;
@ -758,9 +757,9 @@ void ia_css_pipe_get_pre_anr_binarydesc(
unsigned int i;
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
assert(pipe != NULL);
assert(in_info != NULL);
assert(out_info != NULL);
assert(pipe);
assert(in_info);
assert(out_info);
IA_CSS_ENTER_PRIVATE("");
*in_info = *out_info;
@ -792,9 +791,9 @@ void ia_css_pipe_get_anr_binarydesc(
unsigned int i;
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
assert(pipe != NULL);
assert(in_info != NULL);
assert(out_info != NULL);
assert(pipe);
assert(in_info);
assert(out_info);
IA_CSS_ENTER_PRIVATE("");
*in_info = *out_info;
@ -811,7 +810,6 @@ void ia_css_pipe_get_anr_binarydesc(
IA_CSS_LEAVE_PRIVATE("");
}
void ia_css_pipe_get_post_anr_binarydesc(
struct ia_css_pipe const * const pipe,
struct ia_css_binary_descr *post_anr_descr,
@ -822,10 +820,10 @@ void ia_css_pipe_get_post_anr_binarydesc(
unsigned int i;
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
assert(pipe != NULL);
assert(in_info != NULL);
assert(out_info != NULL);
assert(vf_info != NULL);
assert(pipe);
assert(in_info);
assert(out_info);
assert(vf_info);
IA_CSS_ENTER_PRIVATE("");
*in_info = *out_info;
@ -851,9 +849,9 @@ void ia_css_pipe_get_ldc_binarydesc(
unsigned int i;
struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
assert(pipe != NULL);
assert(in_info != NULL);
assert(out_info != NULL);
assert(pipe);
assert(in_info);
assert(out_info);
IA_CSS_ENTER_PRIVATE("");
#ifndef ISP2401

8
drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/pipe/src/pipe_stagedesc.c
View File

@ -24,11 +24,12 @@ void ia_css_pipe_get_generic_stage_desc(
struct ia_css_frame *vf_frame)
{
unsigned int i;
IA_CSS_ENTER_PRIVATE("stage_desc = %p, binary = %p, out_frame = %p, in_frame = %p, vf_frame = %p",
stage_desc, binary, out_frame, in_frame, vf_frame);
assert(stage_desc != NULL && binary != NULL && binary->info != NULL);
if (stage_desc == NULL || binary == NULL || binary->info == NULL) {
assert(stage_desc && binary && binary->info);
if (!stage_desc || !binary || !binary->info) {
IA_CSS_ERROR("invalid arguments");
goto ERR;
}
@ -95,7 +96,7 @@ void ia_css_pipe_get_sp_func_stage_desc(
struct ia_css_pipeline_stage_desc *stage_desc,
struct ia_css_frame *out_frame,
enum ia_css_pipeline_stage_sp_func sp_func,
unsigned max_input_width)
unsigned int max_input_width)
{
unsigned int i;
@ -112,4 +113,3 @@ void ia_css_pipe_get_sp_func_stage_desc(
}
stage_desc->vf_frame = NULL;
}

7
drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/pipe/src/pipe_util.c
View File

@ -21,8 +21,8 @@
unsigned int ia_css_pipe_util_pipe_input_format_bpp(
const struct ia_css_pipe * const pipe)
{
assert(pipe != NULL);
assert(pipe->stream != NULL);
assert(pipe);
assert(pipe->stream);
return ia_css_util_input_format_bpp(pipe->stream->config.input_config.format,
pipe->stream->config.pixels_per_clock == 2);
@ -33,7 +33,7 @@ void ia_css_pipe_util_create_output_frames(
{
unsigned int i;
assert(frames != NULL);
assert(frames);
for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) {
frames[i] = NULL;
}
@ -48,4 +48,3 @@ void ia_css_pipe_util_set_output_frames(
frames[idx] = frame;
}

21
drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/util/interface/ia_css_util.h
View File

@ -37,7 +37,7 @@ enum ia_css_err ia_css_convert_errno(
* @return IA_CSS_SUCCESS or error code upon error.
*
*/
extern enum ia_css_err ia_css_util_check_vf_info(
enum ia_css_err ia_css_util_check_vf_info(
const struct ia_css_frame_info * const info);
/* @brief check input configuration.
@ -47,7 +47,7 @@ extern enum ia_css_err ia_css_util_check_vf_info(
* @return IA_CSS_SUCCESS or error code upon error.
*
*/
extern enum ia_css_err ia_css_util_check_input(
enum ia_css_err ia_css_util_check_input(
const struct ia_css_stream_config * const stream_config,
bool must_be_raw,
bool must_be_yuv);
@ -59,7 +59,7 @@ extern enum ia_css_err ia_css_util_check_input(
* @return IA_CSS_SUCCESS or error code upon error.
*
*/
extern enum ia_css_err ia_css_util_check_vf_out_info(
enum ia_css_err ia_css_util_check_vf_out_info(
const struct ia_css_frame_info * const out_info,
const struct ia_css_frame_info * const vf_info);
@ -70,7 +70,7 @@ extern enum ia_css_err ia_css_util_check_vf_out_info(
* @return IA_CSS_SUCCESS or error code upon error.
*
*/
extern enum ia_css_err ia_css_util_check_res(
enum ia_css_err ia_css_util_check_res(
unsigned int width,
unsigned int height);
@ -83,7 +83,7 @@ extern enum ia_css_err ia_css_util_check_res(
* equal than those of b, false otherwise
*
*/
extern bool ia_css_util_res_leq(
bool ia_css_util_res_leq(
struct ia_css_resolution a,
struct ia_css_resolution b);
@ -94,7 +94,7 @@ extern bool ia_css_util_res_leq(
*
* @returns true if resolution is zero
*/
extern bool ia_css_util_resolution_is_zero(
bool ia_css_util_resolution_is_zero(
const struct ia_css_resolution resolution);
/**
@ -104,7 +104,7 @@ extern bool ia_css_util_resolution_is_zero(
*
* @returns true if resolution is even
*/
extern bool ia_css_util_resolution_is_even(
bool ia_css_util_resolution_is_even(
const struct ia_css_resolution resolution);
#endif
@ -115,7 +115,7 @@ extern bool ia_css_util_resolution_is_even(
* @return bits per pixel based on given parameters.
*
*/
extern unsigned int ia_css_util_input_format_bpp(
unsigned int ia_css_util_input_format_bpp(
enum atomisp_input_format stream_format,
bool two_ppc);
@ -125,7 +125,7 @@ extern unsigned int ia_css_util_input_format_bpp(
* @return true if the input format is raw or false otherwise
*
*/
extern bool ia_css_util_is_input_format_raw(
bool ia_css_util_is_input_format_raw(
enum atomisp_input_format stream_format);
/* @brief check if input format it yuv
@ -134,8 +134,7 @@ extern bool ia_css_util_is_input_format_raw(
* @return true if the input format is yuv or false otherwise
*
*/
extern bool ia_css_util_is_input_format_yuv(
bool ia_css_util_is_input_format_yuv(
enum atomisp_input_format stream_format);
#endif /* __IA_CSS_UTIL_H__ */

17
drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/util/src/util.c
View File

@ -20,7 +20,6 @@
/* for ia_css_binary_max_vf_width() */
#include "ia_css_binary.h"
enum ia_css_err ia_css_convert_errno(
int in_err)
{
@ -56,6 +55,7 @@ unsigned int ia_css_util_input_format_bpp(
bool two_ppc)
{
unsigned int rval = 0;
switch (format) {
case ATOMISP_INPUT_FORMAT_YUV420_8_LEGACY:
case ATOMISP_INPUT_FORMAT_YUV420_8:
@ -109,7 +109,6 @@ unsigned int ia_css_util_input_format_bpp(
default:
rval = 0;
break;
}
return rval;
}
@ -119,12 +118,13 @@ enum ia_css_err ia_css_util_check_vf_info(
{
enum ia_css_err err;
unsigned int max_vf_width;
assert(info != NULL);
assert(info);
err = ia_css_frame_check_info(info);
if (err != IA_CSS_SUCCESS)
return err;
max_vf_width = ia_css_binary_max_vf_width();
if (max_vf_width != 0 && info->res.width > max_vf_width*2)
if (max_vf_width != 0 && info->res.width > max_vf_width * 2)
return IA_CSS_ERR_INVALID_ARGUMENTS;
return IA_CSS_SUCCESS;
}
@ -135,8 +135,8 @@ enum ia_css_err ia_css_util_check_vf_out_info(
{
enum ia_css_err err;
assert(out_info != NULL);
assert(vf_info != NULL);
assert(out_info);
assert(vf_info);
err = ia_css_frame_check_info(out_info);
if (err != IA_CSS_SUCCESS)
@ -204,9 +204,9 @@ enum ia_css_err ia_css_util_check_input(
bool must_be_raw,
bool must_be_yuv)
{
assert(stream_config != NULL);
assert(stream_config);
if (stream_config == NULL)
if (!stream_config)
return IA_CSS_ERR_INVALID_ARGUMENTS;
#ifdef IS_ISP_2400_SYSTEM
@ -224,4 +224,3 @@ enum ia_css_err ia_css_util_check_input(
return IA_CSS_SUCCESS;
}

71
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_configs.c
View File

@ -30,8 +30,9 @@ ia_css_configure_iterator(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_iterator() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
unsigned int offset = 0;
unsigned int size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.iterator.size;
offset = binary->info->mem_offsets.offsets.config->dmem.iterator.offset;
@ -54,8 +55,9 @@ ia_css_configure_copy_output(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_copy_output() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
unsigned int offset = 0;
unsigned int size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.copy_output.size;
offset = binary->info->mem_offsets.offsets.config->dmem.copy_output.offset;
@ -78,8 +80,9 @@ ia_css_configure_crop(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_crop() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
unsigned int offset = 0;
unsigned int size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.crop.size;
offset = binary->info->mem_offsets.offsets.config->dmem.crop.offset;
@ -102,8 +105,9 @@ ia_css_configure_fpn(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_fpn() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
unsigned int offset = 0;
unsigned int size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.fpn.size;
offset = binary->info->mem_offsets.offsets.config->dmem.fpn.offset;
@ -126,8 +130,9 @@ ia_css_configure_dvs(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_dvs() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
unsigned int offset = 0;
unsigned int size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.dvs.size;
offset = binary->info->mem_offsets.offsets.config->dmem.dvs.offset;
@ -150,8 +155,9 @@ ia_css_configure_qplane(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_qplane() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
unsigned int offset = 0;
unsigned int size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.qplane.size;
offset = binary->info->mem_offsets.offsets.config->dmem.qplane.offset;
@ -174,8 +180,9 @@ ia_css_configure_output0(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output0() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
unsigned int offset = 0;
unsigned int size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.output0.size;
offset = binary->info->mem_offsets.offsets.config->dmem.output0.offset;
@ -198,8 +205,9 @@ ia_css_configure_output1(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output1() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
unsigned int offset = 0;
unsigned int size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.output1.size;
offset = binary->info->mem_offsets.offsets.config->dmem.output1.offset;
@ -222,8 +230,9 @@ ia_css_configure_output(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
unsigned int offset = 0;
unsigned int size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.output.size;
offset = binary->info->mem_offsets.offsets.config->dmem.output.offset;
@ -247,8 +256,9 @@ ia_css_configure_sc(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_sc() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
unsigned int offset = 0;
unsigned int size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.sc.size;
offset = binary->info->mem_offsets.offsets.config->dmem.sc.offset;
@ -272,8 +282,9 @@ ia_css_configure_raw(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_raw() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
unsigned int offset = 0;
unsigned int size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.raw.size;
offset = binary->info->mem_offsets.offsets.config->dmem.raw.offset;
@ -296,8 +307,9 @@ ia_css_configure_tnr(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_tnr() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
unsigned int offset = 0;
unsigned int size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.tnr.size;
offset = binary->info->mem_offsets.offsets.config->dmem.tnr.offset;
@ -320,8 +332,9 @@ ia_css_configure_ref(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_ref() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
unsigned int offset = 0;
unsigned int size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.ref.size;
offset = binary->info->mem_offsets.offsets.config->dmem.ref.offset;
@ -344,8 +357,9 @@ ia_css_configure_vf(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_vf() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
unsigned int offset = 0;
unsigned int size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.vf.size;
offset = binary->info->mem_offsets.offsets.config->dmem.vf.offset;
@ -357,4 +371,3 @@ ia_css_configure_vf(
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_vf() leave:\n");
}

996
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_params.c
View File

File diff suppressed because it is too large Load Diff

4
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_params.h
View File

@ -149,8 +149,8 @@ struct ia_css_memory_offsets {
struct ia_css_pipeline_stage; /* forward declaration */
extern void (* ia_css_kernel_process_param[IA_CSS_NUM_PARAMETER_IDS])(
unsigned pipe_id,
extern void (*ia_css_kernel_process_param[IA_CSS_NUM_PARAMETER_IDS])(
unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params);

41
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_states.c
View File

@ -27,13 +27,12 @@ ia_css_initialize_aa_state(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_aa_state() enter:\n");
{
unsigned size = binary->info->mem_offsets.offsets.state->vmem.aa.size;
unsigned int size = binary->info->mem_offsets.offsets.state->vmem.aa.size;
unsigned offset = binary->info->mem_offsets.offsets.state->vmem.aa.offset;
unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.aa.offset;
if (size)
memset(&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset], 0, size);
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_aa_state() leave:\n");
}
@ -47,16 +46,15 @@ ia_css_initialize_cnr_state(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr_state() enter:\n");
{
unsigned size = binary->info->mem_offsets.offsets.state->vmem.cnr.size;
unsigned int size = binary->info->mem_offsets.offsets.state->vmem.cnr.size;
unsigned offset = binary->info->mem_offsets.offsets.state->vmem.cnr.offset;
unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.cnr.offset;
if (size) {
ia_css_init_cnr_state(
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset],
size);
}
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr_state() leave:\n");
}
@ -70,16 +68,15 @@ ia_css_initialize_cnr2_state(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr2_state() enter:\n");
{
unsigned size = binary->info->mem_offsets.offsets.state->vmem.cnr2.size;
unsigned int size = binary->info->mem_offsets.offsets.state->vmem.cnr2.size;
unsigned offset = binary->info->mem_offsets.offsets.state->vmem.cnr2.offset;
unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.cnr2.offset;
if (size) {
ia_css_init_cnr2_state(
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset],
size);
}
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr2_state() leave:\n");
}
@ -93,16 +90,15 @@ ia_css_initialize_dp_state(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_dp_state() enter:\n");
{
unsigned size = binary->info->mem_offsets.offsets.state->vmem.dp.size;
unsigned int size = binary->info->mem_offsets.offsets.state->vmem.dp.size;
unsigned offset = binary->info->mem_offsets.offsets.state->vmem.dp.offset;
unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.dp.offset;
if (size) {
ia_css_init_dp_state(
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset],
size);
}
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_dp_state() leave:\n");
}
@ -116,16 +112,15 @@ ia_css_initialize_de_state(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_de_state() enter:\n");
{
unsigned size = binary->info->mem_offsets.offsets.state->vmem.de.size;
unsigned int size = binary->info->mem_offsets.offsets.state->vmem.de.size;
unsigned offset = binary->info->mem_offsets.offsets.state->vmem.de.offset;
unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.de.offset;
if (size) {
ia_css_init_de_state(
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset],
size);
}
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_de_state() leave:\n");
}
@ -139,16 +134,15 @@ ia_css_initialize_tnr_state(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_tnr_state() enter:\n");
{
unsigned size = binary->info->mem_offsets.offsets.state->dmem.tnr.size;
unsigned int size = binary->info->mem_offsets.offsets.state->dmem.tnr.size;
unsigned offset = binary->info->mem_offsets.offsets.state->dmem.tnr.offset;
unsigned int offset = binary->info->mem_offsets.offsets.state->dmem.tnr.offset;
if (size) {
ia_css_init_tnr_state((struct sh_css_isp_tnr_dmem_state *)
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_DMEM].address[offset],
size);
}
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_tnr_state() leave:\n");
}
@ -162,16 +156,15 @@ ia_css_initialize_ref_state(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ref_state() enter:\n");
{
unsigned size = binary->info->mem_offsets.offsets.state->dmem.ref.size;
unsigned int size = binary->info->mem_offsets.offsets.state->dmem.ref.size;
unsigned offset = binary->info->mem_offsets.offsets.state->dmem.ref.offset;
unsigned int offset = binary->info->mem_offsets.offsets.state->dmem.ref.offset;
if (size) {
ia_css_init_ref_state((struct sh_css_isp_ref_dmem_state *)
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_DMEM].address[offset],
size);
}
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ref_state() leave:\n");
}
@ -185,16 +178,15 @@ ia_css_initialize_ynr_state(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ynr_state() enter:\n");
{
unsigned size = binary->info->mem_offsets.offsets.state->vmem.ynr.size;
unsigned int size = binary->info->mem_offsets.offsets.state->vmem.ynr.size;
unsigned offset = binary->info->mem_offsets.offsets.state->vmem.ynr.offset;
unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.ynr.offset;
if (size) {
ia_css_init_ynr_state(
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset],
size);
}
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ynr_state() leave:\n");
}
@ -211,4 +203,3 @@ void (* ia_css_kernel_init_state[IA_CSS_NUM_STATE_IDS])(const struct ia_css_bina
ia_css_initialize_ref_state,
ia_css_initialize_ynr_state,
};

2
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/bits.h
View File

@ -95,7 +95,7 @@
#define _hrt_get_bit(w, b) \
(((w) >> (b)) & 1)
#define _hrt_set_bit(w, b, v) \
(((w) & (~(1 << (b)))) | (((v)&1) << (b)))
(((w) & (~(1 << (b)))) | (((v) & 1) << (b)))
#define _hrt_set_lower_half(w, v) \
_hrt_set_bits(w, 0, 16, v)
#define _hrt_set_upper_half(w, v) \

6
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/cell_params.h
View File

@ -22,9 +22,9 @@
#define SP_ICACHE_BLOCK_ADDRESS_BITS 11 /* 2048 lines capacity*/
#define SP_ICACHE_ADDRESS_BITS \
(SP_ICACHE_TAG_BITS+SP_ICACHE_BLOCK_ADDRESS_BITS)
(SP_ICACHE_TAG_BITS + SP_ICACHE_BLOCK_ADDRESS_BITS)
#define SP_PMEM_DEPTH (1<<SP_ICACHE_ADDRESS_BITS)
#define SP_PMEM_DEPTH BIT(SP_ICACHE_ADDRESS_BITS)
#define SP_FIFO_0_DEPTH 0
#define SP_FIFO_1_DEPTH 0
@ -35,8 +35,6 @@
#define SP_FIFO_6_DEPTH 0
#define SP_FIFO_7_DEPTH 0
#define SP_SLV_BUS_MAXBURSTSIZE 1
#endif /* _cell_params_h */

40
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/css_receiver_2400_common_defs.h
View File

@ -21,7 +21,7 @@
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_CH_ID_WIDTH 2
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_FMT_TYPE_WIDTH 3
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_REAL_WIDTH (_HRT_CSS_RECEIVER_2400_GEN_SHORT_DATA_WIDTH + _HRT_CSS_RECEIVER_2400_GEN_SHORT_CH_ID_WIDTH + _HRT_CSS_RECEIVER_2400_GEN_SHORT_FMT_TYPE_WIDTH)
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_WIDTH 32 /* use 32 to be compatibel with streaming monitor !, MSB's of interface are tied to '0' */
#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_WIDTH 32 /* use 32 to be compatibel with streaming monitor !, MSB's of interface are tied to '0' */
/* Definition of data format ID at the interface CSS_receiver capture/acquisition units */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8 24 /* 01 1000 YUV420 8-bit */
@ -64,10 +64,10 @@
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8_CSPS 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_10_CSPS 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */
/* used reserved mipi positions for these */
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW16 46
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18 47
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_2 37
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_3 38
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW16 46
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18 47
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_2 37
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_3 38
#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_WIDTH 6
@ -78,7 +78,7 @@
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB444 2 // 32
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB565 3 // 34
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB666 4 // 35
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW8 5 // 42
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW8 5 // 42
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW10 6 // 43
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW6 7 // 40
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW7 8 // 41
@ -104,24 +104,24 @@
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18 28 // ?
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18_2 29 // ? Option 2 for depacketiser
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18_3 30 // ? Option 3 for depacketiser
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_CUSTOM 31 // to signal custom decoding
#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_CUSTOM 31 // to signal custom decoding
/* definition for state machine of data FIFO for decode different type of data */
#define _HRT_CSS_RECEIVER_2400_YUV420_8_REPEAT_PTN 1
#define _HRT_CSS_RECEIVER_2400_YUV420_8_REPEAT_PTN 1
#define _HRT_CSS_RECEIVER_2400_YUV420_10_REPEAT_PTN 5
#define _HRT_CSS_RECEIVER_2400_YUV420_8L_REPEAT_PTN 1
#define _HRT_CSS_RECEIVER_2400_YUV422_8_REPEAT_PTN 1
#define _HRT_CSS_RECEIVER_2400_YUV422_10_REPEAT_PTN 5
#define _HRT_CSS_RECEIVER_2400_RGB444_REPEAT_PTN 2
#define _HRT_CSS_RECEIVER_2400_RGB444_REPEAT_PTN 2
#define _HRT_CSS_RECEIVER_2400_RGB555_REPEAT_PTN 2
#define _HRT_CSS_RECEIVER_2400_RGB565_REPEAT_PTN 2
#define _HRT_CSS_RECEIVER_2400_RGB666_REPEAT_PTN 9
#define _HRT_CSS_RECEIVER_2400_RGB666_REPEAT_PTN 9
#define _HRT_CSS_RECEIVER_2400_RGB888_REPEAT_PTN 3
#define _HRT_CSS_RECEIVER_2400_RAW6_REPEAT_PTN 3
#define _HRT_CSS_RECEIVER_2400_RAW7_REPEAT_PTN 7
#define _HRT_CSS_RECEIVER_2400_RAW8_REPEAT_PTN 1
#define _HRT_CSS_RECEIVER_2400_RAW10_REPEAT_PTN 5
#define _HRT_CSS_RECEIVER_2400_RAW12_REPEAT_PTN 3
#define _HRT_CSS_RECEIVER_2400_RAW12_REPEAT_PTN 3
#define _HRT_CSS_RECEIVER_2400_RAW14_REPEAT_PTN 7
#define _HRT_CSS_RECEIVER_2400_MAX_REPEAT_PTN _HRT_CSS_RECEIVER_2400_RGB666_REPEAT_PTN
@ -146,7 +146,6 @@
#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_7_12 5
#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_8_12 6
/* packet bit definition */
#define _HRT_CSS_RECEIVER_2400_PKT_SOP_IDX 32
#define _HRT_CSS_RECEIVER_2400_PKT_SOP_BITS 1
@ -159,22 +158,21 @@
#define _HRT_CSS_RECEIVER_2400_PKT_PAYLOAD_IDX 0
#define _HRT_CSS_RECEIVER_2400_PKT_PAYLOAD_BITS 32
/*************************************************************************************************/
/* Custom Decoding */
/* These Custom Defs are defined based on design-time config in "csi_be_pixel_formatter.chdl" !! */
/*************************************************************************************************/
#define BE_CUST_EN_IDX 0 /* 2bits */
#define BE_CUST_EN_DATAID_IDX 2 /* 6bits MIPI DATA ID */
#define BE_CUST_EN_WIDTH 8
#define BE_CUST_EN_DATAID_IDX 2 /* 6bits MIPI DATA ID */
#define BE_CUST_EN_WIDTH 8
#define BE_CUST_MODE_ALL 1 /* Enable Custom Decoding for all DATA IDs */
#define BE_CUST_MODE_ONE 3 /* Enable Custom Decoding for ONE DATA ID, programmed in CUST_EN_DATA_ID */
/* Data State config = {get_bits(6bits), valid(1bit)} */
#define BE_CUST_DATA_STATE_S0_IDX 0 /* 7bits */
#define BE_CUST_DATA_STATE_S1_IDX 7 /* 7bits */
#define BE_CUST_DATA_STATE_S0_IDX 0 /* 7bits */
#define BE_CUST_DATA_STATE_S1_IDX 7 /* 7bits */
#define BE_CUST_DATA_STATE_S2_IDX 14 /* 7bits */
#define BE_CUST_DATA_STATE_WIDTH 21
#define BE_CUST_DATA_STATE_WIDTH 21
#define BE_CUST_DATA_STATE_VALID_IDX 0 /* 1bits */
#define BE_CUST_DATA_STATE_GETBITS_IDX 1 /* 6bits */
@ -183,18 +181,18 @@
#define BE_CUST_PIX_EXT_PIX_ALIGN_IDX 5 /* 5bits */
#define BE_CUST_PIX_EXT_PIX_MASK_IDX 10 /* 18bits */
#define BE_CUST_PIX_EXT_PIX_EN_IDX 28 /* 1bits */
#define BE_CUST_PIX_EXT_WIDTH 29
#define BE_CUST_PIX_EXT_WIDTH 29
/* Pixel Valid & EoP config = {[eop,valid](especial), [eop,valid](normal)} */
#define BE_CUST_PIX_VALID_EOP_P0_IDX 0 /* 4bits */
#define BE_CUST_PIX_VALID_EOP_P1_IDX 4 /* 4bits */
#define BE_CUST_PIX_VALID_EOP_P2_IDX 8 /* 4bits */
#define BE_CUST_PIX_VALID_EOP_P3_IDX 12 /* 4bits */
#define BE_CUST_PIX_VALID_EOP_WIDTH 16
#define BE_CUST_PIX_VALID_EOP_WIDTH 16
#define BE_CUST_PIX_VALID_EOP_NOR_VALID_IDX 0 /* Normal (NO less get_bits case) Valid - 1bits */
#define BE_CUST_PIX_VALID_EOP_NOR_EOP_IDX 1 /* Normal (NO less get_bits case) EoP - 1bits */
#define BE_CUST_PIX_VALID_EOP_ESP_VALID_IDX 2 /* Especial (less get_bits case) Valid - 1bits */
#define BE_CUST_PIX_VALID_EOP_ESP_EOP_IDX 3 /* Especial (less get_bits case) EoP - 1bits */
#endif /* _mipi_backend_common_defs_h_ */
#endif /* _css_receiver_2400_common_defs_h_ */
#endif /* _css_receiver_2400_common_defs_h_ */

6
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/css_receiver_2400_defs.h
View File

@ -132,7 +132,6 @@
#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_ECC_TWO_BIT_ERR_IDX 6
#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_DATA_ID_ERR_IDX 7
/* Bits for CSI2_FUNC_PROG register */
#define _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_IDX 0
#define _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_BITS 19
@ -182,7 +181,6 @@
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_PRED_BITS_IDX 3
#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_PRED_BITS_BITS 2
/* BITS for backend RAW16 and RAW 18 registers */
#define _HRT_CSS_RECEIVER_2400_RAW18_DATAID_IDX 0
@ -200,8 +198,8 @@
#define _HRT_CSS_RECEIVER_2400_RAW16_EN_BITS 1
/* These hsync and vsync values are for HSS simulation only */
#define _HRT_CSS_RECEIVER_2400_HSYNC_VAL (1<<16)
#define _HRT_CSS_RECEIVER_2400_VSYNC_VAL (1<<17)
#define _HRT_CSS_RECEIVER_2400_HSYNC_VAL BIT(16)
#define _HRT_CSS_RECEIVER_2400_VSYNC_VAL BIT(17)
#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_WIDTH 28
#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_LSB 0

80
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/dma_v2_defs.h
View File

@ -51,7 +51,7 @@
#define _DMA_V2_SPEC_DEV_B_XB_IDX (_DMA_V2_SPEC_DEV_A_XB_IDX + _DMA_V2_SPEC_DEV_A_XB_BITS)
#define _DMA_V2_SPEC_DEV_B_XB_BITS 8
#define _DMA_V2_SPEC_YB_IDX (_DMA_V2_SPEC_DEV_B_XB_IDX + _DMA_V2_SPEC_DEV_B_XB_BITS)
#define _DMA_V2_SPEC_YB_BITS (32-_DMA_V2_SPEC_DEV_B_XB_BITS-_DMA_V2_SPEC_DEV_A_XB_BITS-_DMA_V2_CMD_BITS-_DMA_V2_CHANNEL_BITS)
#define _DMA_V2_SPEC_YB_BITS (32 - _DMA_V2_SPEC_DEV_B_XB_BITS - _DMA_V2_SPEC_DEV_A_XB_BITS - _DMA_V2_CMD_BITS - _DMA_V2_CHANNEL_BITS)
/* */
#define _DMA_V2_CMD_CTRL_IDX 4
@ -79,44 +79,44 @@
#define _DMA_V2_STRIDE_BITS 32
/* Command IDs */
#define _DMA_V2_MOVE_B2A_COMMAND 0
#define _DMA_V2_MOVE_B2A_BLOCK_COMMAND 1
#define _DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND 2
#define _DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND 3
#define _DMA_V2_MOVE_A2B_COMMAND 4
#define _DMA_V2_MOVE_A2B_BLOCK_COMMAND 5
#define _DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND 6
#define _DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND 7
#define _DMA_V2_INIT_A_COMMAND 8
#define _DMA_V2_INIT_A_BLOCK_COMMAND 9
#define _DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND 10
#define _DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND 11
#define _DMA_V2_INIT_B_COMMAND 12
#define _DMA_V2_INIT_B_BLOCK_COMMAND 13
#define _DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND 14
#define _DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND 15
#define _DMA_V2_NO_ACK_MOVE_B2A_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_MOVE_A2B_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_INIT_A_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_INIT_B_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_CONFIG_CHANNEL_COMMAND 32
#define _DMA_V2_SET_CHANNEL_PARAM_COMMAND 33
#define _DMA_V2_SET_CRUN_COMMAND 62
#define _DMA_V2_MOVE_B2A_COMMAND 0
#define _DMA_V2_MOVE_B2A_BLOCK_COMMAND 1
#define _DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND 2
#define _DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND 3
#define _DMA_V2_MOVE_A2B_COMMAND 4
#define _DMA_V2_MOVE_A2B_BLOCK_COMMAND 5
#define _DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND 6
#define _DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND 7
#define _DMA_V2_INIT_A_COMMAND 8
#define _DMA_V2_INIT_A_BLOCK_COMMAND 9
#define _DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND 10
#define _DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND 11
#define _DMA_V2_INIT_B_COMMAND 12
#define _DMA_V2_INIT_B_BLOCK_COMMAND 13
#define _DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND 14
#define _DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND 15
#define _DMA_V2_NO_ACK_MOVE_B2A_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_MOVE_A2B_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_INIT_A_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_INIT_B_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_NO_ACK_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND + 16)
#define _DMA_V2_CONFIG_CHANNEL_COMMAND 32
#define _DMA_V2_SET_CHANNEL_PARAM_COMMAND 33
#define _DMA_V2_SET_CRUN_COMMAND 62
/* Channel Parameter IDs */
#define _DMA_V2_PACKING_SETUP_PARAM 0
#define _DMA_V2_STRIDE_A_PARAM 1
#define _DMA_V2_ELEM_CROPPING_A_PARAM 2
#define _DMA_V2_WIDTH_A_PARAM 3
#define _DMA_V2_STRIDE_B_PARAM 4
#define _DMA_V2_ELEM_CROPPING_B_PARAM 5
#define _DMA_V2_WIDTH_B_PARAM 6
#define _DMA_V2_HEIGHT_PARAM 7
#define _DMA_V2_QUEUED_CMDS 8
#define _DMA_V2_PACKING_SETUP_PARAM 0
#define _DMA_V2_STRIDE_A_PARAM 1
#define _DMA_V2_ELEM_CROPPING_A_PARAM 2
#define _DMA_V2_WIDTH_A_PARAM 3
#define _DMA_V2_STRIDE_B_PARAM 4
#define _DMA_V2_ELEM_CROPPING_B_PARAM 5
#define _DMA_V2_WIDTH_B_PARAM 6
#define _DMA_V2_HEIGHT_PARAM 7
#define _DMA_V2_QUEUED_CMDS 8
/* Parameter Constants */
#define _DMA_V2_ZERO_EXTEND 0
@ -132,7 +132,7 @@
#define _DMA_V2_ADDR_SEL_COMP_BITS 4
#define _DMA_V2_ADDR_SEL_CH_REG_IDX 2
#define _DMA_V2_ADDR_SEL_CH_REG_BITS 6
#define _DMA_V2_ADDR_SEL_PARAM_IDX (_DMA_V2_ADDR_SEL_CH_REG_BITS+_DMA_V2_ADDR_SEL_CH_REG_IDX)
#define _DMA_V2_ADDR_SEL_PARAM_IDX (_DMA_V2_ADDR_SEL_CH_REG_BITS + _DMA_V2_ADDR_SEL_CH_REG_IDX)
#define _DMA_V2_ADDR_SEL_PARAM_BITS 4
#define _DMA_V2_ADDR_SEL_GROUP_COMP_IDX 2
@ -142,7 +142,7 @@
#define _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX 2
#define _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS 6
#define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_IDX (_DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX+_DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS)
#define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_IDX (_DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX + _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS)
#define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_BITS 4
#define _DMA_V2_FSM_GROUP_CMD_IDX 0
@ -153,7 +153,7 @@
#define _DMA_V2_FSM_GROUP_FSM_PACK_IDX 5
#define _DMA_V2_FSM_GROUP_FSM_REQ_IDX 6
#define _DMA_V2_FSM_GROUP_FSM_WR_IDX 7
#define _DMA_V2_FSM_GROUP_FSM_CTRL_STATE_IDX 0
#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_DEV_IDX 1
#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_ADDR_IDX 2

63
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/gdc_v2_defs.h
View File

@ -21,53 +21,51 @@
#define HRT_GDC_FRAC_BITS 10 /* Number of fractional bits in the GDC block, driven by the size of the LUT */
#define HRT_GDC_BLI_FRAC_BITS 4 /* Number of fractional bits for the bi-linear interpolation type */
#define HRT_GDC_BLI_COEF_ONE (1 << HRT_GDC_BLI_FRAC_BITS)
#define HRT_GDC_BLI_COEF_ONE BIT(HRT_GDC_BLI_FRAC_BITS)
#define HRT_GDC_BCI_COEF_BITS 14 /* 14 bits per coefficient */
#define HRT_GDC_BCI_COEF_ONE (1 << (HRT_GDC_BCI_COEF_BITS-2)) /* We represent signed 10 bit coefficients. */
/* The supported range is [-256, .., +256] */
/* in 14-bit signed notation, */
/* We need all ten bits (MSB must be zero). */
/* -s is inserted to solve this issue, and */
/* therefore "1" is equal to +256. */
#define HRT_GDC_BCI_COEF_MASK ((1 << HRT_GDC_BCI_COEF_BITS) - 1)
#define HRT_GDC_BCI_COEF_ONE (1 << (HRT_GDC_BCI_COEF_BITS - 2)) /* We represent signed 10 bit coefficients. */
/* The supported range is [-256, .., +256] */
/* in 14-bit signed notation, */
/* We need all ten bits (MSB must be zero). */
/* -s is inserted to solve this issue, and */
/* therefore "1" is equal to +256. */
#define HRT_GDC_BCI_COEF_MASK ((1 << HRT_GDC_BCI_COEF_BITS) - 1)
#define HRT_GDC_LUT_BYTES (HRT_GDC_N*4*2) /* 1024 addresses, 4 coefficients per address, */
/* 2 bytes per coefficient */
#define HRT_GDC_LUT_BYTES (HRT_GDC_N * 4 * 2) /* 1024 addresses, 4 coefficients per address, */
/* 2 bytes per coefficient */
#define _HRT_GDC_REG_ALIGN 4
#define _HRT_GDC_REG_ALIGN 4
// 31 30 29 25 24 0
// |-----|---|--------|------------------------|
// | CMD | C | Reg_ID | Value |
// There are just two commands possible for the GDC block:
// 1 - Configure reg
// 0 - Data token
// 1 - Configure reg
// 0 - Data token
// C - Reserved bit
// Used in protocol to indicate whether it is C-run or other type of runs
// In case of C-run, this bit has a value of 1, for all the other runs, it is 0.
// Reg_ID - Address of the register to be configured
// Value - Value to store to the addressed register, maximum of 24 bits
// Configure reg command is not followed by any other token.
// The address of the register and the data to be filled in is contained in the same token
// Configure reg command is not followed by any other token.
// The address of the register and the data to be filled in is contained in the same token
// When the first data token is received, it must be:
// 1. FRX and FRY (device configured in one of the scaling modes) ***DEFAULT MODE***, or,
// 2. P0'X (device configured in one of the tetragon modes)
// After the first data token is received, pre-defined number of tokens with the following meaning follow:
// 1. two tokens: SRC address ; DST address
// 2. nine tokens: P0'Y, .., P3'Y ; SRC address ; DST address
#define HRT_GDC_CONFIG_CMD 1
#define HRT_GDC_DATA_CMD 0
#define HRT_GDC_CMD_POS 31
#define HRT_GDC_CMD_BITS 1
#define HRT_GDC_CRUN_POS 30
@ -79,16 +77,14 @@
#define HRT_GDC_FRYIPXFRX_BITS 26
#define HRT_GDC_P0X_BITS 23
#define HRT_GDC_MAX_OXDIM (8192-64)
#define HRT_GDC_MAX_OXDIM (8192 - 64)
#define HRT_GDC_MAX_OYDIM 4095
#define HRT_GDC_MAX_IXDIM (8192-64)
#define HRT_GDC_MAX_IXDIM (8192 - 64)
#define HRT_GDC_MAX_IYDIM 4095
#define HRT_GDC_MAX_DS_FAC 16
#define HRT_GDC_MAX_DX (HRT_GDC_MAX_DS_FAC*HRT_GDC_N - 1)
#define HRT_GDC_MAX_DX (HRT_GDC_MAX_DS_FAC * HRT_GDC_N - 1)
#define HRT_GDC_MAX_DY HRT_GDC_MAX_DX
/* GDC lookup tables entries are 10 bits values, but they're
stored 2 by 2 as 32 bit values, yielding 16 bits per entry.
A GDC lookup table contains 64 * 4 elements */
@ -109,18 +105,17 @@
#define HRT_GDC_MODE_SCALING 0
#define HRT_GDC_MODE_TETRAGON 1
#define HRT_GDC_LUT_COEFF_OFFSET 16
#define HRT_GDC_FRY_BIT_OFFSET 16
// FRYIPXFRX is the only register where we store two values in one field,
// to save one token in the scaling protocol.
// Like this, we have three tokens in the scaling protocol,
#define HRT_GDC_LUT_COEFF_OFFSET 16
#define HRT_GDC_FRY_BIT_OFFSET 16
// FRYIPXFRX is the only register where we store two values in one field,
// to save one token in the scaling protocol.
// Like this, we have three tokens in the scaling protocol,
// Otherwise, we would have had four.
// The register bit-map is:
// 31 26 25 16 15 10 9 0
// |------|----------|------|----------|
// | XXXX | FRY | IPX | FRX |
#define HRT_GDC_CE_FSM0_POS 0
#define HRT_GDC_CE_FSM0_LEN 2
#define HRT_GDC_CE_OPY_POS 2
@ -131,11 +126,10 @@
// 31 16 15 2 1 0
// |----------------|-----------|----|
// | OPX | OPY |FSM0|
// However, for the time being at least,
// However, for the time being at least,
// this implementation is meaningless in hss model,
// So, we just return 0
#define HRT_GDC_CHK_ENGINE_IDX 0
#define HRT_GDC_WOIX_IDX 1
#define HRT_GDC_WOIY_IDX 2
@ -166,5 +160,4 @@
#define HRT_GDC_LUT_IDX 32
#endif /* HRT_GDC_v2_defs_h_ */

14
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/gp_timer_defs.h
View File

@ -20,12 +20,12 @@
#define HIVE_GP_TIMER_RESET_REG_IDX 0
#define HIVE_GP_TIMER_OVERALL_ENABLE_REG_IDX 1
#define HIVE_GP_TIMER_ENABLE_REG_IDX(timer) (HIVE_GP_TIMER_OVERALL_ENABLE_REG_IDX + 1 + timer)
#define HIVE_GP_TIMER_VALUE_REG_IDX(timer,timers) (HIVE_GP_TIMER_ENABLE_REG_IDX(timers) + timer)
#define HIVE_GP_TIMER_COUNT_TYPE_REG_IDX(timer,timers) (HIVE_GP_TIMER_VALUE_REG_IDX(timers, timers) + timer)
#define HIVE_GP_TIMER_SIGNAL_SELECT_REG_IDX(timer,timers) (HIVE_GP_TIMER_COUNT_TYPE_REG_IDX(timers, timers) + timer)
#define HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(irq,timers) (HIVE_GP_TIMER_SIGNAL_SELECT_REG_IDX(timers, timers) + irq)
#define HIVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irq,timers,irqs) (HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(irqs, timers) + irq)
#define HIVE_GP_TIMER_IRQ_ENABLE_REG_IDX(irq,timers,irqs) (HIVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irqs, timers, irqs) + irq)
#define HIVE_GP_TIMER_VALUE_REG_IDX(timer, timers) (HIVE_GP_TIMER_ENABLE_REG_IDX(timers) + timer)
#define HIVE_GP_TIMER_COUNT_TYPE_REG_IDX(timer, timers) (HIVE_GP_TIMER_VALUE_REG_IDX(timers, timers) + timer)
#define HIVE_GP_TIMER_SIGNAL_SELECT_REG_IDX(timer, timers) (HIVE_GP_TIMER_COUNT_TYPE_REG_IDX(timers, timers) + timer)
#define HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(irq, timers) (HIVE_GP_TIMER_SIGNAL_SELECT_REG_IDX(timers, timers) + irq)
#define HIVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irq, timers, irqs) (HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(irqs, timers) + irq)
#define HIVE_GP_TIMER_IRQ_ENABLE_REG_IDX(irq, timers, irqs) (HIVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irqs, timers, irqs) + irq)
#define HIVE_GP_TIMER_COUNT_TYPE_HIGH 0
#define HIVE_GP_TIMER_COUNT_TYPE_LOW 1
@ -33,4 +33,4 @@
#define HIVE_GP_TIMER_COUNT_TYPE_NEGEDGE 3
#define HIVE_GP_TIMER_COUNT_TYPES 4
#endif /* _gp_timer_defs_h */
#endif /* _gp_timer_defs_h */

1
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/gpio_block_defs.h
View File

@ -35,7 +35,6 @@
#define _gpio_block_reg_di_debounce_cnt_3 14
#define _gpio_block_reg_di_active_level 15
/* read-only registers */
#define _gpio_block_reg_di 16

41
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/hive_isp_css_defs.h
View File

@ -29,12 +29,12 @@
and in the DMA parameter list */
#define HIVE_ISP_DDR_DMA_SPECS {{32, 8}, {16, 16}, {18, 14}, {25, 10}, {21, 12}}
#define HIVE_ISP_DDR_WORD_BITS 256
#define HIVE_ISP_DDR_WORD_BYTES (HIVE_ISP_DDR_WORD_BITS/8)
#define HIVE_ISP_DDR_WORD_BYTES (HIVE_ISP_DDR_WORD_BITS / 8)
#define HIVE_ISP_DDR_BYTES (512 * 1024 * 1024) /* hss only */
#define HIVE_ISP_DDR_BYTES_RTL (127 * 1024 * 1024) /* RTL only */
#define HIVE_ISP_DDR_SMALL_BYTES (128 * 256 / 8)
#define HIVE_ISP_PAGE_SHIFT 12
#define HIVE_ISP_PAGE_SIZE (1<<HIVE_ISP_PAGE_SHIFT)
#define HIVE_ISP_PAGE_SIZE BIT(HIVE_ISP_PAGE_SHIFT)
#define CSS_DDR_WORD_BITS HIVE_ISP_DDR_WORD_BITS
#define CSS_DDR_WORD_BYTES HIVE_ISP_DDR_WORD_BYTES
@ -257,7 +257,7 @@
#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I4_I0 51
#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I5_I0 52
#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I6_I0 53
#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I7_I0 54
#define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I7_I0 54
#define HIVE_GP_TIMER_MIPI_SOL_BIT_ID 55
#define HIVE_GP_TIMER_MIPI_EOL_BIT_ID 56
#define HIVE_GP_TIMER_MIPI_SOF_BIT_ID 57
@ -268,15 +268,15 @@
/* port definititions SP streaming monitor, monitors the status of streaming ports at the SP side of the streaming FIFO's */
#define SP_STR_MON_PORT_SP2SIF 0
#define SP_STR_MON_PORT_SIF2SP 1
#define SP_STR_MON_PORT_SP2MC 2
#define SP_STR_MON_PORT_SP2MC 2
#define SP_STR_MON_PORT_MC2SP 3
#define SP_STR_MON_PORT_SP2DMA 4
#define SP_STR_MON_PORT_SP2DMA 4
#define SP_STR_MON_PORT_DMA2SP 5
#define SP_STR_MON_PORT_SP2ISP 6
#define SP_STR_MON_PORT_SP2ISP 6
#define SP_STR_MON_PORT_ISP2SP 7
#define SP_STR_MON_PORT_SP2GPD 8
#define SP_STR_MON_PORT_FA2SP 9
#define SP_STR_MON_PORT_SP2ISYS 10
#define SP_STR_MON_PORT_SP2ISYS 10
#define SP_STR_MON_PORT_ISYS2SP 11
#define SP_STR_MON_PORT_SP2PIFA 12
#define SP_STR_MON_PORT_PIFA2SP 13
@ -313,33 +313,33 @@
/* port definititions ISP streaming monitor, monitors the status of streaming ports at the ISP side of the streaming FIFO's */
#define ISP_STR_MON_PORT_ISP2PIFA 0
#define ISP_STR_MON_PORT_PIFA2ISP 1
#define ISP_STR_MON_PORT_ISP2PIFB 2
#define ISP_STR_MON_PORT_ISP2PIFB 2
#define ISP_STR_MON_PORT_PIFB2ISP 3
#define ISP_STR_MON_PORT_ISP2DMA 4
#define ISP_STR_MON_PORT_ISP2DMA 4
#define ISP_STR_MON_PORT_DMA2ISP 5
#define ISP_STR_MON_PORT_ISP2GDC1 6
#define ISP_STR_MON_PORT_ISP2GDC1 6
#define ISP_STR_MON_PORT_GDC12ISP 7
#define ISP_STR_MON_PORT_ISP2GDC2 8
#define ISP_STR_MON_PORT_ISP2GDC2 8
#define ISP_STR_MON_PORT_GDC22ISP 9
#define ISP_STR_MON_PORT_ISP2GPD 10
#define ISP_STR_MON_PORT_ISP2GPD 10
#define ISP_STR_MON_PORT_FA2ISP 11
#define ISP_STR_MON_PORT_ISP2SP 12
#define ISP_STR_MON_PORT_ISP2SP 12
#define ISP_STR_MON_PORT_SP2ISP 13
/* previously used ISP streaming monitor port identifiers, kept for backward compatibility */
#define ISP_STR_MON_PORT_SND_PIF_A ISP_STR_MON_PORT_ISP2PIFA
#define ISP_STR_MON_PORT_RCV_PIF_A ISP_STR_MON_PORT_PIFA2ISP
#define ISP_STR_MON_PORT_SND_PIF_B ISP_STR_MON_PORT_ISP2PIFB
#define ISP_STR_MON_PORT_SND_PIF_B ISP_STR_MON_PORT_ISP2PIFB
#define ISP_STR_MON_PORT_RCV_PIF_B ISP_STR_MON_PORT_PIFB2ISP
#define ISP_STR_MON_PORT_SND_DMA ISP_STR_MON_PORT_ISP2DMA
#define ISP_STR_MON_PORT_RCV_DMA ISP_STR_MON_PORT_DMA2ISP
#define ISP_STR_MON_PORT_SND_GDC ISP_STR_MON_PORT_ISP2GDC1
#define ISP_STR_MON_PORT_SND_DMA ISP_STR_MON_PORT_ISP2DMA
#define ISP_STR_MON_PORT_RCV_DMA ISP_STR_MON_PORT_DMA2ISP
#define ISP_STR_MON_PORT_SND_GDC ISP_STR_MON_PORT_ISP2GDC1
#define ISP_STR_MON_PORT_RCV_GDC ISP_STR_MON_PORT_GDC12ISP
#define ISP_STR_MON_PORT_SND_GPD ISP_STR_MON_PORT_ISP2GPD
#define ISP_STR_MON_PORT_SND_GPD ISP_STR_MON_PORT_ISP2GPD
#define ISP_STR_MON_PORT_RCV_GPD ISP_STR_MON_PORT_FA2ISP
#define ISP_STR_MON_PORT_SND_SP ISP_STR_MON_PORT_ISP2SP
#define ISP_STR_MON_PORT_RCV_SP ISP_STR_MON_PORT_SP2ISP
/* port definititions MOD streaming monitor, monitors the status of streaming ports at the module side of the streaming FIFO's */
#define MOD_STR_MON_PORT_PIFA2CELLS 0
@ -374,7 +374,6 @@
#define MOD_STR_MON_PORT_SND_GDC 12
#define MOD_STR_MON_PORT_RCV_GDC 13
/* testbench signals: */
/* testbench GP adapter register ids */
@ -385,7 +384,7 @@
#define HIVE_TESTBENCH_IDLE_REG_IDX 4
#define HIVE_TESTBENCH_GPIO_DATA_IN_REG_IDX 5
#define HIVE_TESTBENCH_MIPI_BFM_EN_REG_IDX 6
#define HIVE_TESTBENCH_CSI_CONFIG_REG_IDX 7
#define HIVE_TESTBENCH_CSI_CONFIG_REG_IDX 7
#define HIVE_TESTBENCH_DDR_STALL_EN_REG_IDX 8
#define HIVE_TESTBENCH_ISP_PMEM_ERROR_IRQ_REG_IDX 9

2
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/hive_isp_css_host_ids_hrt.h
View File

@ -29,7 +29,7 @@
#define ISP testbench_isp_isp
#define SP testbench_isp_scp
#define IF_PRIM testbench_isp_ifmt_ift_prim
#define IF_PRIM testbench_isp_ifmt_ift_prim
#define IF_PRIM_B testbench_isp_ifmt_ift_prim_b
#define IF_SEC testbench_isp_ifmt_ift_sec
#define IF_SEC_MASTER testbench_isp_ifmt_ift_sec_mt_out

66
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/hive_isp_css_irq_types_hrt.h
View File

@ -23,42 +23,42 @@
* The definitions are taken from <system>_defs.h
*/
typedef enum hrt_isp_css_irq {
hrt_isp_css_irq_gpio_pin_0 = HIVE_GP_DEV_IRQ_GPIO_PIN_0_BIT_ID ,
hrt_isp_css_irq_gpio_pin_1 = HIVE_GP_DEV_IRQ_GPIO_PIN_1_BIT_ID ,
hrt_isp_css_irq_gpio_pin_2 = HIVE_GP_DEV_IRQ_GPIO_PIN_2_BIT_ID ,
hrt_isp_css_irq_gpio_pin_3 = HIVE_GP_DEV_IRQ_GPIO_PIN_3_BIT_ID ,
hrt_isp_css_irq_gpio_pin_4 = HIVE_GP_DEV_IRQ_GPIO_PIN_4_BIT_ID ,
hrt_isp_css_irq_gpio_pin_5 = HIVE_GP_DEV_IRQ_GPIO_PIN_5_BIT_ID ,
hrt_isp_css_irq_gpio_pin_6 = HIVE_GP_DEV_IRQ_GPIO_PIN_6_BIT_ID ,
hrt_isp_css_irq_gpio_pin_7 = HIVE_GP_DEV_IRQ_GPIO_PIN_7_BIT_ID ,
hrt_isp_css_irq_gpio_pin_8 = HIVE_GP_DEV_IRQ_GPIO_PIN_8_BIT_ID ,
hrt_isp_css_irq_gpio_pin_9 = HIVE_GP_DEV_IRQ_GPIO_PIN_9_BIT_ID ,
hrt_isp_css_irq_gpio_pin_10 = HIVE_GP_DEV_IRQ_GPIO_PIN_10_BIT_ID ,
hrt_isp_css_irq_gpio_pin_11 = HIVE_GP_DEV_IRQ_GPIO_PIN_11_BIT_ID ,
hrt_isp_css_irq_sp = HIVE_GP_DEV_IRQ_SP_BIT_ID ,
hrt_isp_css_irq_isp = HIVE_GP_DEV_IRQ_ISP_BIT_ID ,
hrt_isp_css_irq_isys = HIVE_GP_DEV_IRQ_ISYS_BIT_ID ,
hrt_isp_css_irq_isel = HIVE_GP_DEV_IRQ_ISEL_BIT_ID ,
hrt_isp_css_irq_ifmt = HIVE_GP_DEV_IRQ_IFMT_BIT_ID ,
hrt_isp_css_irq_sp_stream_mon = HIVE_GP_DEV_IRQ_SP_STREAM_MON_BIT_ID ,
hrt_isp_css_irq_isp_stream_mon = HIVE_GP_DEV_IRQ_ISP_STREAM_MON_BIT_ID ,
hrt_isp_css_irq_mod_stream_mon = HIVE_GP_DEV_IRQ_MOD_STREAM_MON_BIT_ID ,
hrt_isp_css_irq_gpio_pin_0 = HIVE_GP_DEV_IRQ_GPIO_PIN_0_BIT_ID,
hrt_isp_css_irq_gpio_pin_1 = HIVE_GP_DEV_IRQ_GPIO_PIN_1_BIT_ID,
hrt_isp_css_irq_gpio_pin_2 = HIVE_GP_DEV_IRQ_GPIO_PIN_2_BIT_ID,
hrt_isp_css_irq_gpio_pin_3 = HIVE_GP_DEV_IRQ_GPIO_PIN_3_BIT_ID,
hrt_isp_css_irq_gpio_pin_4 = HIVE_GP_DEV_IRQ_GPIO_PIN_4_BIT_ID,
hrt_isp_css_irq_gpio_pin_5 = HIVE_GP_DEV_IRQ_GPIO_PIN_5_BIT_ID,
hrt_isp_css_irq_gpio_pin_6 = HIVE_GP_DEV_IRQ_GPIO_PIN_6_BIT_ID,
hrt_isp_css_irq_gpio_pin_7 = HIVE_GP_DEV_IRQ_GPIO_PIN_7_BIT_ID,
hrt_isp_css_irq_gpio_pin_8 = HIVE_GP_DEV_IRQ_GPIO_PIN_8_BIT_ID,
hrt_isp_css_irq_gpio_pin_9 = HIVE_GP_DEV_IRQ_GPIO_PIN_9_BIT_ID,
hrt_isp_css_irq_gpio_pin_10 = HIVE_GP_DEV_IRQ_GPIO_PIN_10_BIT_ID,
hrt_isp_css_irq_gpio_pin_11 = HIVE_GP_DEV_IRQ_GPIO_PIN_11_BIT_ID,
hrt_isp_css_irq_sp = HIVE_GP_DEV_IRQ_SP_BIT_ID,
hrt_isp_css_irq_isp = HIVE_GP_DEV_IRQ_ISP_BIT_ID,
hrt_isp_css_irq_isys = HIVE_GP_DEV_IRQ_ISYS_BIT_ID,
hrt_isp_css_irq_isel = HIVE_GP_DEV_IRQ_ISEL_BIT_ID,
hrt_isp_css_irq_ifmt = HIVE_GP_DEV_IRQ_IFMT_BIT_ID,
hrt_isp_css_irq_sp_stream_mon = HIVE_GP_DEV_IRQ_SP_STREAM_MON_BIT_ID,
hrt_isp_css_irq_isp_stream_mon = HIVE_GP_DEV_IRQ_ISP_STREAM_MON_BIT_ID,
hrt_isp_css_irq_mod_stream_mon = HIVE_GP_DEV_IRQ_MOD_STREAM_MON_BIT_ID,
#ifdef _HIVE_ISP_CSS_2401_SYSTEM
hrt_isp_css_irq_is2401 = HIVE_GP_DEV_IRQ_IS2401_BIT_ID ,
hrt_isp_css_irq_is2401 = HIVE_GP_DEV_IRQ_IS2401_BIT_ID,
#else
hrt_isp_css_irq_isp_pmem_error = HIVE_GP_DEV_IRQ_ISP_PMEM_ERROR_BIT_ID ,
hrt_isp_css_irq_isp_pmem_error = HIVE_GP_DEV_IRQ_ISP_PMEM_ERROR_BIT_ID,
#endif
hrt_isp_css_irq_isp_bamem_error = HIVE_GP_DEV_IRQ_ISP_BAMEM_ERROR_BIT_ID ,
hrt_isp_css_irq_isp_dmem_error = HIVE_GP_DEV_IRQ_ISP_DMEM_ERROR_BIT_ID ,
hrt_isp_css_irq_sp_icache_mem_error = HIVE_GP_DEV_IRQ_SP_ICACHE_MEM_ERROR_BIT_ID ,
hrt_isp_css_irq_sp_dmem_error = HIVE_GP_DEV_IRQ_SP_DMEM_ERROR_BIT_ID ,
hrt_isp_css_irq_mmu_cache_mem_error = HIVE_GP_DEV_IRQ_MMU_CACHE_MEM_ERROR_BIT_ID ,
hrt_isp_css_irq_gp_timer_0 = HIVE_GP_DEV_IRQ_GP_TIMER_0_BIT_ID ,
hrt_isp_css_irq_gp_timer_1 = HIVE_GP_DEV_IRQ_GP_TIMER_1_BIT_ID ,
hrt_isp_css_irq_sw_pin_0 = HIVE_GP_DEV_IRQ_SW_PIN_0_BIT_ID ,
hrt_isp_css_irq_sw_pin_1 = HIVE_GP_DEV_IRQ_SW_PIN_1_BIT_ID ,
hrt_isp_css_irq_dma = HIVE_GP_DEV_IRQ_DMA_BIT_ID ,
hrt_isp_css_irq_sp_stream_mon_b = HIVE_GP_DEV_IRQ_SP_STREAM_MON_B_BIT_ID ,
hrt_isp_css_irq_isp_bamem_error = HIVE_GP_DEV_IRQ_ISP_BAMEM_ERROR_BIT_ID,
hrt_isp_css_irq_isp_dmem_error = HIVE_GP_DEV_IRQ_ISP_DMEM_ERROR_BIT_ID,
hrt_isp_css_irq_sp_icache_mem_error = HIVE_GP_DEV_IRQ_SP_ICACHE_MEM_ERROR_BIT_ID,
hrt_isp_css_irq_sp_dmem_error = HIVE_GP_DEV_IRQ_SP_DMEM_ERROR_BIT_ID,
hrt_isp_css_irq_mmu_cache_mem_error = HIVE_GP_DEV_IRQ_MMU_CACHE_MEM_ERROR_BIT_ID,
hrt_isp_css_irq_gp_timer_0 = HIVE_GP_DEV_IRQ_GP_TIMER_0_BIT_ID,
hrt_isp_css_irq_gp_timer_1 = HIVE_GP_DEV_IRQ_GP_TIMER_1_BIT_ID,
hrt_isp_css_irq_sw_pin_0 = HIVE_GP_DEV_IRQ_SW_PIN_0_BIT_ID,
hrt_isp_css_irq_sw_pin_1 = HIVE_GP_DEV_IRQ_SW_PIN_1_BIT_ID,
hrt_isp_css_irq_dma = HIVE_GP_DEV_IRQ_DMA_BIT_ID,
hrt_isp_css_irq_sp_stream_mon_b = HIVE_GP_DEV_IRQ_SP_STREAM_MON_B_BIT_ID,
/* this must (obviously) be the last on in the enum */
hrt_isp_css_irq_num_irqs
} hrt_isp_css_irq_t;

6
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/hive_isp_css_streaming_to_mipi_types_hrt.h
View File

@ -17,10 +17,10 @@
#include <streaming_to_mipi_defs.h>
#define _HIVE_ISP_CH_ID_MASK ((1U << HIVE_ISP_CH_ID_BITS)-1)
#define _HIVE_ISP_FMT_TYPE_MASK ((1U << HIVE_ISP_FMT_TYPE_BITS)-1)
#define _HIVE_ISP_CH_ID_MASK ((1U << HIVE_ISP_CH_ID_BITS) - 1)
#define _HIVE_ISP_FMT_TYPE_MASK ((1U << HIVE_ISP_FMT_TYPE_BITS) - 1)
#define _HIVE_STR_TO_MIPI_FMT_TYPE_LSB (HIVE_STR_TO_MIPI_CH_ID_LSB + HIVE_ISP_CH_ID_BITS)
#define _HIVE_STR_TO_MIPI_DATA_B_LSB (HIVE_STR_TO_MIPI_DATA_A_LSB + HIVE_IF_PIXEL_WIDTH)
#endif /* _hive_isp_css_streaming_to_mipi_types_hrt_h_ */

30
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/hive_types.h
View File

@ -12,28 +12,28 @@
* more details.
*/
#ifndef _HRT_HIVE_TYPES_H
#define _HRT_HIVE_TYPES_H
#ifndef _HRT_HIVE_TYPES_H
#define _HRT_HIVE_TYPES_H
#include "version.h"
#include "defs.h"
#ifndef HRTCAT3
#define _HRTCAT3(m,n,o) m##n##o
#define HRTCAT3(m,n,o) _HRTCAT3(m,n,o)
#define _HRTCAT3(m, n, o) m##n##o
#define HRTCAT3(m, n, o) _HRTCAT3(m, n, o)
#endif
#ifndef HRTCAT4
#define _HRTCAT4(m,n,o,p) m##n##o##p
#define HRTCAT4(m,n,o,p) _HRTCAT4(m,n,o,p)
#define _HRTCAT4(m, n, o, p) m##n##o##p
#define HRTCAT4(m, n, o, p) _HRTCAT4(m, n, o, p)
#endif
#ifndef HRTMIN
#define HRTMIN(a,b) (((a)<(b))?(a):(b))
#define HRTMIN(a, b) (((a) < (b)) ? (a) : (b))
#endif
#ifndef HRTMAX
#define HRTMAX(a,b) (((a)>(b))?(a):(b))
#define HRTMAX(a, b) (((a) > (b)) ? (a) : (b))
#endif
/* boolean data type */
@ -59,8 +59,8 @@ typedef unsigned long long hive_uint64;
#define HRT_ADDRESS_WIDTH 32
#endif
#define HRT_DATA_BYTES (HRT_DATA_WIDTH/8)
#define HRT_ADDRESS_BYTES (HRT_ADDRESS_WIDTH/8)
#define HRT_DATA_BYTES (HRT_DATA_WIDTH / 8)
#define HRT_ADDRESS_BYTES (HRT_ADDRESS_WIDTH / 8)
#if HRT_DATA_WIDTH == 64
typedef hive_uint64 hrt_data;
@ -71,7 +71,7 @@ typedef hive_uint32 hrt_data;
#endif
#if HRT_ADDRESS_WIDTH == 64
typedef hive_uint64 hrt_address;
typedef hive_uint64 hrt_address;
#elif HRT_ADDRESS_WIDTH == 32
typedef hive_uint32 hrt_address;
#else
@ -95,7 +95,7 @@ typedef hive_address hive_mem_address;
typedef hive_uint hive_mmio_id;
typedef hive_mmio_id hive_slave_id;
typedef hive_mmio_id hive_port_id;
typedef hive_mmio_id hive_master_id;
typedef hive_mmio_id hive_master_id;
typedef hive_mmio_id hive_mem_id;
typedef hive_mmio_id hive_dev_id;
typedef hive_mmio_id hive_fifo_id;
@ -122,7 +122,7 @@ typedef hive_uint hive_inport_id;
typedef hive_uint hive_msink_id;
/* HRT specific */
typedef char* hive_program;
typedef char* hive_function;
typedef char *hive_program;
typedef char *hive_function;
#endif /* _HRT_HIVE_TYPES_H */

2
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/input_formatter_subsystem_defs.h
View File

@ -22,7 +22,7 @@
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_4 4
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_5 5
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_6 6
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_7 7
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_7 7
#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_FSYNC_LUT_REG 8
#define HIVE_IFMT_GP_REGS_SRST_IDX 9
#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IDX 10

43
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/input_selector_defs.h
View File

@ -31,37 +31,36 @@
#define HIVE_ISEL_GP_REGS_SYNCGEN_ENABLE_IDX 0
#define HIVE_ISEL_GP_REGS_SYNCGEN_FREE_RUNNING_IDX 1
#define HIVE_ISEL_GP_REGS_SYNCGEN_PAUSE_IDX 2
#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_FRAMES_IDX 3
#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_PIX_IDX 4
#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_LINES_IDX 5
#define HIVE_ISEL_GP_REGS_SYNCGEN_HBLANK_CYCLES_IDX 6
#define HIVE_ISEL_GP_REGS_SYNCGEN_VBLANK_CYCLES_IDX 7
#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_FRAMES_IDX 3
#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_PIX_IDX 4
#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_LINES_IDX 5
#define HIVE_ISEL_GP_REGS_SYNCGEN_HBLANK_CYCLES_IDX 6
#define HIVE_ISEL_GP_REGS_SYNCGEN_VBLANK_CYCLES_IDX 7
#define HIVE_ISEL_GP_REGS_SOF_IDX 8
#define HIVE_ISEL_GP_REGS_EOF_IDX 9
#define HIVE_ISEL_GP_REGS_SOL_IDX 10
#define HIVE_ISEL_GP_REGS_EOL_IDX 11
#define HIVE_ISEL_GP_REGS_SOF_IDX 8
#define HIVE_ISEL_GP_REGS_EOF_IDX 9
#define HIVE_ISEL_GP_REGS_SOL_IDX 10
#define HIVE_ISEL_GP_REGS_EOL_IDX 11
#define HIVE_ISEL_GP_REGS_PRBS_ENABLE 12
#define HIVE_ISEL_GP_REGS_PRBS_ENABLE_PORT_B 13
#define HIVE_ISEL_GP_REGS_PRBS_LFSR_RESET_VALUE 14
#define HIVE_ISEL_GP_REGS_PRBS_ENABLE 12
#define HIVE_ISEL_GP_REGS_PRBS_ENABLE_PORT_B 13
#define HIVE_ISEL_GP_REGS_PRBS_LFSR_RESET_VALUE 14
#define HIVE_ISEL_GP_REGS_TPG_ENABLE 15
#define HIVE_ISEL_GP_REGS_TPG_ENABLE_PORT_B 16
#define HIVE_ISEL_GP_REGS_TPG_HOR_CNT_MASK_IDX 17
#define HIVE_ISEL_GP_REGS_TPG_VER_CNT_MASK_IDX 18
#define HIVE_ISEL_GP_REGS_TPG_XY_CNT_MASK_IDX 19
#define HIVE_ISEL_GP_REGS_TPG_HOR_CNT_DELTA_IDX 20
#define HIVE_ISEL_GP_REGS_TPG_VER_CNT_DELTA_IDX 21
#define HIVE_ISEL_GP_REGS_TPG_MODE_IDX 22
#define HIVE_ISEL_GP_REGS_TPG_R1_IDX 23
#define HIVE_ISEL_GP_REGS_TPG_ENABLE 15
#define HIVE_ISEL_GP_REGS_TPG_ENABLE_PORT_B 16
#define HIVE_ISEL_GP_REGS_TPG_HOR_CNT_MASK_IDX 17
#define HIVE_ISEL_GP_REGS_TPG_VER_CNT_MASK_IDX 18
#define HIVE_ISEL_GP_REGS_TPG_XY_CNT_MASK_IDX 19
#define HIVE_ISEL_GP_REGS_TPG_HOR_CNT_DELTA_IDX 20
#define HIVE_ISEL_GP_REGS_TPG_VER_CNT_DELTA_IDX 21
#define HIVE_ISEL_GP_REGS_TPG_MODE_IDX 22
#define HIVE_ISEL_GP_REGS_TPG_R1_IDX 23
#define HIVE_ISEL_GP_REGS_TPG_G1_IDX 24
#define HIVE_ISEL_GP_REGS_TPG_B1_IDX 25
#define HIVE_ISEL_GP_REGS_TPG_R2_IDX 26
#define HIVE_ISEL_GP_REGS_TPG_G2_IDX 27
#define HIVE_ISEL_GP_REGS_TPG_B2_IDX 28
#define HIVE_ISEL_GP_REGS_CH_ID_IDX 29
#define HIVE_ISEL_GP_REGS_FMT_TYPE_IDX 30
#define HIVE_ISEL_GP_REGS_DATA_SEL_IDX 31

4
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/input_switch_2400_defs.h
View File

@ -15,8 +15,8 @@
#ifndef _input_switch_2400_defs_h
#define _input_switch_2400_defs_h
#define _HIVE_INPUT_SWITCH_GET_LUT_REG_ID(ch_id, fmt_type) (((ch_id)*2) + ((fmt_type)>=16))
#define _HIVE_INPUT_SWITCH_GET_LUT_REG_LSB(fmt_type) (((fmt_type)%16) * 2)
#define _HIVE_INPUT_SWITCH_GET_LUT_REG_ID(ch_id, fmt_type) (((ch_id) * 2) + ((fmt_type) >= 16))
#define _HIVE_INPUT_SWITCH_GET_LUT_REG_LSB(fmt_type) (((fmt_type) % 16) * 2)
#define HIVE_INPUT_SWITCH_SELECT_NO_OUTPUT 0
#define HIVE_INPUT_SWITCH_SELECT_IF_PRIM 1

159
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/input_system_ctrl_defs.h
View File

@ -50,7 +50,6 @@
#define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_ID 20
#define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_ID 21
#define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_ID 22
/* register reset value */
#define ISYS_CTRL_CAPT_START_ADDR_A_REG_RSTVAL 0
@ -59,38 +58,38 @@
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_RSTVAL 128
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_RSTVAL 128
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_RSTVAL 128
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_RSTVAL 3
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_RSTVAL 3
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_RSTVAL 3
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_RSTVAL 3
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_RSTVAL 3
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_RSTVAL 3
#define ISYS_CTRL_ACQ_START_ADDR_REG_RSTVAL 0
#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_RSTVAL 128
#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_RSTVAL 3
#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_RSTVAL 128
#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_RSTVAL 3
#define ISYS_CTRL_INIT_REG_RSTVAL 0
#define ISYS_CTRL_LAST_COMMAND_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
#define ISYS_CTRL_LAST_COMMAND_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
#define ISYS_CTRL_NEXT_COMMAND_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
#define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
#define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
#define ISYS_CTRL_FSM_STATE_INFO_REG_RSTVAL 0
#define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_RSTVAL 0
#define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_RSTVAL 0
#define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_RSTVAL 0
#define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_RSTVAL 0
#define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_RSTVAL 0
#define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_RSTVAL 0
/* register width value */
#define ISYS_CTRL_CAPT_START_ADDR_A_REG_WIDTH 9
#define ISYS_CTRL_CAPT_START_ADDR_B_REG_WIDTH 9
#define ISYS_CTRL_CAPT_START_ADDR_C_REG_WIDTH 9
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_WIDTH 9
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_WIDTH 9
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_WIDTH 9
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_WIDTH 9
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_WIDTH 9
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_WIDTH 9
#define ISYS_CTRL_ACQ_START_ADDR_REG_WIDTH 9
#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_WIDTH 9
#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_WIDTH 9
#define ISYS_CTRL_INIT_REG_WIDTH 3
#define ISYS_CTRL_CAPT_START_ADDR_A_REG_WIDTH 9
#define ISYS_CTRL_CAPT_START_ADDR_B_REG_WIDTH 9
#define ISYS_CTRL_CAPT_START_ADDR_C_REG_WIDTH 9
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_WIDTH 9
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_WIDTH 9
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_WIDTH 9
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_WIDTH 9
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_WIDTH 9
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_WIDTH 9
#define ISYS_CTRL_ACQ_START_ADDR_REG_WIDTH 9
#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_WIDTH 9
#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_WIDTH 9
#define ISYS_CTRL_INIT_REG_WIDTH 3
#define ISYS_CTRL_LAST_COMMAND_REG_WIDTH 32 /* slave data width */
#define ISYS_CTRL_NEXT_COMMAND_REG_WIDTH 32
#define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_WIDTH 32
@ -111,99 +110,89 @@
/*
InpSysCaptFramesAcq 1/0 [3:0] - 'b0000
[7:4] - CaptPortId,
CaptA-'b0000
CaptB-'b0001
CaptC-'b0010
CaptA-'b0000
CaptB-'b0001
CaptC-'b0010
[31:16] - NOF_frames
InpSysCaptFrameExt 2/0 [3:0] - 'b0001'
[7:4] - CaptPortId,
'b0000 - CaptA
'b0001 - CaptB
'b0010 - CaptC
'b0000 - CaptA
'b0001 - CaptB
'b0010 - CaptC
2/1 [31:0] - external capture address
InpSysAcqFrame 2/0 [3:0] - 'b0010,
InpSysAcqFrame 2/0 [3:0] - 'b0010,
[31:4] - NOF_ext_mem_words
2/1 [31:0] - external memory read start address
InpSysOverruleON 1/0 [3:0] - 'b0011,
InpSysOverruleON 1/0 [3:0] - 'b0011,
[7:4] - overrule port id (opid)
'b0000 - CaptA
'b0001 - CaptB
'b0010 - CaptC
'b0011 - Acq
'b0100 - DMA
'b0000 - CaptA
'b0001 - CaptB
'b0010 - CaptC
'b0011 - Acq
'b0100 - DMA
InpSysOverruleOFF 1/0 [3:0] - 'b0100,
InpSysOverruleOFF 1/0 [3:0] - 'b0100,
[7:4] - overrule port id (opid)
'b0000 - CaptA
'b0001 - CaptB
'b0010 - CaptC
'b0011 - Acq
'b0100 - DMA
'b0000 - CaptA
'b0001 - CaptB
'b0010 - CaptC
'b0011 - Acq
'b0100 - DMA
InpSysOverruleCmd 2/0 [3:0] - 'b0101,
InpSysOverruleCmd 2/0 [3:0] - 'b0101,
[7:4] - overrule port id (opid)
'b0000 - CaptA
'b0001 - CaptB
'b0010 - CaptC
'b0011 - Acq
'b0100 - DMA
'b0000 - CaptA
'b0001 - CaptB
'b0010 - CaptC
'b0011 - Acq
'b0100 - DMA
2/1 [31:0] - command token value for port opid
acknowledge tokens:
InpSysAckCFA 1/0 [3:0] - 'b0000
[7:4] - CaptPortId,
CaptA-'b0000
CaptB- 'b0001
CaptC-'b0010
CaptA-'b0000
CaptB- 'b0001
CaptC-'b0010
[31:16] - NOF_frames
InpSysAckCFE 1/0 [3:0] - 'b0001'
[7:4] - CaptPortId,
'b0000 - CaptA
'b0001 - CaptB
'b0010 - CaptC
'b0000 - CaptA
'b0001 - CaptB
'b0010 - CaptC
InpSysAckAF 1/0 [3:0] - 'b0010
InpSysAckOverruleON 1/0 [3:0] - 'b0011,
InpSysAckOverruleON 1/0 [3:0] - 'b0011,
[7:4] - overrule port id (opid)
'b0000 - CaptA
'b0001 - CaptB
'b0010 - CaptC
'b0011 - Acq
'b0100 - DMA
'b0000 - CaptA
'b0001 - CaptB
'b0010 - CaptC
'b0011 - Acq
'b0100 - DMA
InpSysAckOverruleOFF 1/0 [3:0] - 'b0100,
InpSysAckOverruleOFF 1/0 [3:0] - 'b0100,
[7:4] - overrule port id (opid)
'b0000 - CaptA
'b0001 - CaptB
'b0010 - CaptC
'b0011 - Acq
'b0100 - DMA
'b0000 - CaptA
'b0001 - CaptB
'b0010 - CaptC
'b0011 - Acq
'b0100 - DMA
InpSysAckOverrule 2/0 [3:0] - 'b0101,
InpSysAckOverrule 2/0 [3:0] - 'b0101,
[7:4] - overrule port id (opid)
'b0000 - CaptA
'b0001 - CaptB
'b0010 - CaptC
'b0011 - Acq
'b0100 - DMA
'b0000 - CaptA
'b0001 - CaptB
'b0010 - CaptC
'b0011 - Acq
'b0100 - DMA
2/1 [31:0] - acknowledge token value from port opid
*/
/* Command and acknowledge tokens IDs */
#define ISYS_CTRL_CAPT_FRAMES_ACQ_TOKEN_ID 0 /* 0000b */
#define ISYS_CTRL_CAPT_FRAME_EXT_TOKEN_ID 1 /* 0001b */
@ -232,10 +221,10 @@ InpSysAckOverrule 2/0 [3:0] - 'b0101,
#define ISYS_CTRL_TOKEN_ID_IDX 0
#define ISYS_CTRL_TOKEN_ID_BITS (ISYS_CTRL_TOKEN_ID_MSB - ISYS_CTRL_TOKEN_ID_LSB + 1)
#define ISYS_CTRL_PORT_ID_IDX (ISYS_CTRL_TOKEN_ID_IDX + ISYS_CTRL_TOKEN_ID_BITS)
#define ISYS_CTRL_PORT_ID_BITS (ISYS_CTRL_PORT_ID_TOKEN_MSB - ISYS_CTRL_PORT_ID_TOKEN_LSB +1)
#define ISYS_CTRL_NOF_CAPT_IDX ISYS_CTRL_NOF_CAPT_TOKEN_LSB
#define ISYS_CTRL_PORT_ID_BITS (ISYS_CTRL_PORT_ID_TOKEN_MSB - ISYS_CTRL_PORT_ID_TOKEN_LSB + 1)
#define ISYS_CTRL_NOF_CAPT_IDX ISYS_CTRL_NOF_CAPT_TOKEN_LSB
#define ISYS_CTRL_NOF_CAPT_BITS (ISYS_CTRL_NOF_CAPT_TOKEN_MSB - ISYS_CTRL_NOF_CAPT_TOKEN_LSB + 1)
#define ISYS_CTRL_NOF_EXT_IDX ISYS_CTRL_NOF_EXT_TOKEN_LSB
#define ISYS_CTRL_NOF_EXT_IDX ISYS_CTRL_NOF_EXT_TOKEN_LSB
#define ISYS_CTRL_NOF_EXT_BITS (ISYS_CTRL_NOF_EXT_TOKEN_MSB - ISYS_CTRL_NOF_EXT_TOKEN_LSB + 1)
#define ISYS_CTRL_PORT_ID_CAPT_A 0 /* device ID for capture unit A */
@ -248,7 +237,7 @@ InpSysAckOverrule 2/0 [3:0] - 'b0101,
#define ISYS_CTRL_PORT_ID_DMA_ACQ 7 /* device ID for dma unit */
#define ISYS_CTRL_NO_ACQ_ACK 16 /* no ack from acquisition unit */
#define ISYS_CTRL_NO_DMA_ACK 0
#define ISYS_CTRL_NO_DMA_ACK 0
#define ISYS_CTRL_NO_CAPT_ACK 16
#endif /* _input_system_ctrl_defs_h */
#endif /* _input_system_ctrl_defs_h */

2
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/irq_controller_defs.h
View File

@ -25,4 +25,4 @@
#define _HRT_IRQ_CONTROLLER_REG_ALIGN 4
#endif /* _irq_controller_defs_h */
#endif /* _irq_controller_defs_h */

6
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/isp2400_mamoiada_params.h
View File

@ -111,8 +111,8 @@
#define ISP_SRU_GUARDING 1
#define ISP_VLSU_GUARDING 1
#define ISP_VRF_RAM 1
#define ISP_SRF_RAM 1
#define ISP_VRF_RAM 1
#define ISP_SRF_RAM 1
#define ISP_SPLIT_VMUL_VADD_IS 0
#define ISP_RFSPLIT_FPGA 0
@ -175,7 +175,7 @@
#define ISP_NWAY ISP_VEC_NELEMS
#define NBITS ISP_VEC_ELEMBITS
#define _isp_ceil_div(a,b) (((a)+(b)-1)/(b))
#define _isp_ceil_div(a, b) (((a) + (b) - 1) / (b))
#define ISP_VEC_ALIGN ISP_VMEM_ALIGN

129
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/isp_acquisition_defs.h
View File

@ -16,7 +16,7 @@
#define _isp_acquisition_defs_h
#define _ISP_ACQUISITION_REG_ALIGN 4 /* assuming 32 bit control bus width */
#define _ISP_ACQUISITION_BYTES_PER_ELEM 4
#define _ISP_ACQUISITION_BYTES_PER_ELEM 4
/* --------------------------------------------------*/
@ -32,13 +32,13 @@
/* REGISTER INFO */
/* --------------------------------------------------*/
#define NOF_ACQ_REGS 12
#define NOF_ACQ_REGS 12
// Register id's of MMIO slave accesible registers
#define ACQ_START_ADDR_REG_ID 0
#define ACQ_START_ADDR_REG_ID 0
#define ACQ_MEM_REGION_SIZE_REG_ID 1
#define ACQ_NUM_MEM_REGIONS_REG_ID 2
#define ACQ_INIT_REG_ID 3
#define ACQ_INIT_REG_ID 3
#define ACQ_RECEIVED_SHORT_PACKETS_REG_ID 4
#define ACQ_RECEIVED_LONG_PACKETS_REG_ID 5
#define ACQ_LAST_COMMAND_REG_ID 6
@ -47,34 +47,34 @@
#define ACQ_NEXT_ACKNOWLEDGE_REG_ID 9
#define ACQ_FSM_STATE_INFO_REG_ID 10
#define ACQ_INT_CNTR_INFO_REG_ID 11
// Register width
#define ACQ_START_ADDR_REG_WIDTH 9
#define ACQ_MEM_REGION_SIZE_REG_WIDTH 9
#define ACQ_NUM_MEM_REGIONS_REG_WIDTH 9
#define ACQ_INIT_REG_WIDTH 3
#define ACQ_RECEIVED_SHORT_PACKETS_REG_WIDTH 32
#define ACQ_RECEIVED_LONG_PACKETS_REG_WIDTH 32
#define ACQ_LAST_COMMAND_REG_WIDTH 32
#define ACQ_NEXT_COMMAND_REG_WIDTH 32
#define ACQ_LAST_ACKNOWLEDGE_REG_WIDTH 32
#define ACQ_NEXT_ACKNOWLEDGE_REG_WIDTH 32
#define ACQ_FSM_STATE_INFO_REG_WIDTH ((MEM2STREAM_FSM_STATE_BITS * 3) + (ACQ_SYNCHRONIZER_FSM_STATE_BITS *3))
#define ACQ_START_ADDR_REG_WIDTH 9
#define ACQ_MEM_REGION_SIZE_REG_WIDTH 9
#define ACQ_NUM_MEM_REGIONS_REG_WIDTH 9
#define ACQ_INIT_REG_WIDTH 3
#define ACQ_RECEIVED_SHORT_PACKETS_REG_WIDTH 32
#define ACQ_RECEIVED_LONG_PACKETS_REG_WIDTH 32
#define ACQ_LAST_COMMAND_REG_WIDTH 32
#define ACQ_NEXT_COMMAND_REG_WIDTH 32
#define ACQ_LAST_ACKNOWLEDGE_REG_WIDTH 32
#define ACQ_NEXT_ACKNOWLEDGE_REG_WIDTH 32
#define ACQ_FSM_STATE_INFO_REG_WIDTH ((MEM2STREAM_FSM_STATE_BITS * 3) + (ACQ_SYNCHRONIZER_FSM_STATE_BITS * 3))
#define ACQ_INT_CNTR_INFO_REG_WIDTH 32
/* register reset value */
#define ACQ_START_ADDR_REG_RSTVAL 0
#define ACQ_START_ADDR_REG_RSTVAL 0
#define ACQ_MEM_REGION_SIZE_REG_RSTVAL 128
#define ACQ_NUM_MEM_REGIONS_REG_RSTVAL 3
#define ACQ_INIT_REG_RSTVAL 0
#define ACQ_INIT_REG_RSTVAL 0
#define ACQ_RECEIVED_SHORT_PACKETS_REG_RSTVAL 0
#define ACQ_RECEIVED_LONG_PACKETS_REG_RSTVAL 0
#define ACQ_LAST_COMMAND_REG_RSTVAL 0
#define ACQ_NEXT_COMMAND_REG_RSTVAL 0
#define ACQ_LAST_ACKNOWLEDGE_REG_RSTVAL 0
#define ACQ_NEXT_ACKNOWLEDGE_REG_RSTVAL 0
#define ACQ_NEXT_ACKNOWLEDGE_REG_RSTVAL 0
#define ACQ_FSM_STATE_INFO_REG_RSTVAL 0
#define ACQ_INT_CNTR_INFO_REG_RSTVAL 0
#define ACQ_INT_CNTR_INFO_REG_RSTVAL 0
/* bit definitions */
#define ACQ_INIT_RST_REG_BIT 0
@ -88,7 +88,7 @@
/* TOKEN INFO */
/* --------------------------------------------------*/
#define ACQ_TOKEN_ID_LSB 0
#define ACQ_TOKEN_ID_MSB 3
#define ACQ_TOKEN_ID_MSB 3
#define ACQ_TOKEN_WIDTH (ACQ_TOKEN_ID_MSB - ACQ_TOKEN_ID_LSB + 1) // 4
#define ACQ_TOKEN_ID_IDX 0
#define ACQ_TOKEN_ID_BITS ACQ_TOKEN_WIDTH
@ -97,9 +97,9 @@
#define ACQ_CMD_START_ADDR_IDX 4
#define ACQ_CMD_START_ADDR_BITS 9
#define ACQ_CMD_NOFWORDS_IDX 13
#define ACQ_CMD_NOFWORDS_BITS 9
#define ACQ_CMD_NOFWORDS_BITS 9
#define ACQ_MEM_REGION_ID_IDX 22
#define ACQ_MEM_REGION_ID_BITS 9
#define ACQ_MEM_REGION_ID_BITS 9
#define ACQ_PACKET_LENGTH_TOKEN_MSB 21
#define ACQ_PACKET_LENGTH_TOKEN_LSB 13
#define ACQ_PACKET_DATA_FORMAT_ID_TOKEN_MSB 9
@ -109,11 +109,10 @@
#define ACQ_PACKET_MEM_REGION_ID_TOKEN_MSB 12 /* only for capt_end_of_packet_written */
#define ACQ_PACKET_MEM_REGION_ID_TOKEN_LSB 4 /* only for capt_end_of_packet_written */
/* Command tokens IDs */
#define ACQ_READ_REGION_AUTO_INCR_TOKEN_ID 0 //0000b
#define ACQ_READ_REGION_TOKEN_ID 1 //0001b
#define ACQ_READ_REGION_SOP_TOKEN_ID 2 //0010b
#define ACQ_READ_REGION_SOP_TOKEN_ID 2 //0010b
#define ACQ_INIT_TOKEN_ID 8 //1000b
/* Acknowledge token IDs */
@ -128,18 +127,17 @@
#define ACQ_TOKEN_NOFWORDS_MSB 21
#define ACQ_TOKEN_NOFWORDS_LSB 13
#define ACQ_TOKEN_STARTADDR_MSB 12
#define ACQ_TOKEN_STARTADDR_LSB 4
#define ACQ_TOKEN_STARTADDR_LSB 4
/* --------------------------------------------------*/
/* MIPI */
/* --------------------------------------------------*/
#define WORD_COUNT_WIDTH 16
#define PKT_CODE_WIDTH 6
#define CHN_NO_WIDTH 2
#define PKT_CODE_WIDTH 6
#define CHN_NO_WIDTH 2
#define ERROR_INFO_WIDTH 8
#define LONG_PKTCODE_MAX 63
#define LONG_PKTCODE_MIN 16
#define SHORT_PKTCODE_MAX 15
@ -156,7 +154,6 @@
#define ACQ_LINE_PAYLOAD 4
#define ACQ_GEN_SH_PKT 5
/* bit definition */
#define ACQ_PKT_TYPE_IDX 16
#define ACQ_PKT_TYPE_BITS 6
@ -174,51 +171,49 @@
#define ACQ_ACK_PKT_LEN_IDX 4
#define ACQ_ACK_PKT_LEN_BITS 16
/* --------------------------------------------------*/
/* Packet Data Type */
/* --------------------------------------------------*/
#define ACQ_YUV420_8_DATA 24 /* 01 1000 YUV420 8-bit */
#define ACQ_YUV420_10_DATA 25 /* 01 1001 YUV420 10-bit */
#define ACQ_YUV420_8L_DATA 26 /* 01 1010 YUV420 8-bit legacy */
#define ACQ_YUV422_8_DATA 30 /* 01 1110 YUV422 8-bit */
#define ACQ_YUV422_10_DATA 31 /* 01 1111 YUV422 10-bit */
#define ACQ_RGB444_DATA 32 /* 10 0000 RGB444 */
#define ACQ_RGB555_DATA 33 /* 10 0001 RGB555 */
#define ACQ_RGB565_DATA 34 /* 10 0010 RGB565 */
#define ACQ_RGB666_DATA 35 /* 10 0011 RGB666 */
#define ACQ_RGB888_DATA 36 /* 10 0100 RGB888 */
#define ACQ_RAW6_DATA 40 /* 10 1000 RAW6 */
#define ACQ_RAW7_DATA 41 /* 10 1001 RAW7 */
#define ACQ_RAW8_DATA 42 /* 10 1010 RAW8 */
#define ACQ_RAW10_DATA 43 /* 10 1011 RAW10 */
#define ACQ_RAW12_DATA 44 /* 10 1100 RAW12 */
#define ACQ_RAW14_DATA 45 /* 10 1101 RAW14 */
#define ACQ_USR_DEF_1_DATA 48 /* 11 0000 JPEG [User Defined 8-bit Data Type 1] */
#define ACQ_USR_DEF_2_DATA 49 /* 11 0001 User Defined 8-bit Data Type 2 */
#define ACQ_USR_DEF_3_DATA 50 /* 11 0010 User Defined 8-bit Data Type 3 */
#define ACQ_USR_DEF_4_DATA 51 /* 11 0011 User Defined 8-bit Data Type 4 */
#define ACQ_USR_DEF_5_DATA 52 /* 11 0100 User Defined 8-bit Data Type 5 */
#define ACQ_USR_DEF_6_DATA 53 /* 11 0101 User Defined 8-bit Data Type 6 */
#define ACQ_USR_DEF_7_DATA 54 /* 11 0110 User Defined 8-bit Data Type 7 */
#define ACQ_USR_DEF_8_DATA 55 /* 11 0111 User Defined 8-bit Data Type 8 */
#define ACQ_Emb_DATA 18 /* 01 0010 embedded eight bit non image data */
#define ACQ_SOF_DATA 0 /* 00 0000 frame start */
#define ACQ_EOF_DATA 1 /* 00 0001 frame end */
#define ACQ_SOL_DATA 2 /* 00 0010 line start */
#define ACQ_EOL_DATA 3 /* 00 0011 line end */
#define ACQ_GEN_SH1_DATA 8 /* 00 1000 Generic Short Packet Code 1 */
#define ACQ_GEN_SH2_DATA 9 /* 00 1001 Generic Short Packet Code 2 */
#define ACQ_GEN_SH3_DATA 10 /* 00 1010 Generic Short Packet Code 3 */
#define ACQ_GEN_SH4_DATA 11 /* 00 1011 Generic Short Packet Code 4 */
#define ACQ_GEN_SH5_DATA 12 /* 00 1100 Generic Short Packet Code 5 */
#define ACQ_GEN_SH6_DATA 13 /* 00 1101 Generic Short Packet Code 6 */
#define ACQ_GEN_SH7_DATA 14 /* 00 1110 Generic Short Packet Code 7 */
#define ACQ_GEN_SH8_DATA 15 /* 00 1111 Generic Short Packet Code 8 */
#define ACQ_YUV420_8_CSPS_DATA 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */
#define ACQ_YUV420_10_CSPS_DATA 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */
#define ACQ_RGB555_DATA 33 /* 10 0001 RGB555 */
#define ACQ_RGB565_DATA 34 /* 10 0010 RGB565 */
#define ACQ_RGB666_DATA 35 /* 10 0011 RGB666 */
#define ACQ_RGB888_DATA 36 /* 10 0100 RGB888 */
#define ACQ_RAW6_DATA 40 /* 10 1000 RAW6 */
#define ACQ_RAW7_DATA 41 /* 10 1001 RAW7 */
#define ACQ_RAW8_DATA 42 /* 10 1010 RAW8 */
#define ACQ_RAW10_DATA 43 /* 10 1011 RAW10 */
#define ACQ_RAW12_DATA 44 /* 10 1100 RAW12 */
#define ACQ_RAW14_DATA 45 /* 10 1101 RAW14 */
#define ACQ_USR_DEF_1_DATA 48 /* 11 0000 JPEG [User Defined 8-bit Data Type 1] */
#define ACQ_USR_DEF_2_DATA 49 /* 11 0001 User Defined 8-bit Data Type 2 */
#define ACQ_USR_DEF_3_DATA 50 /* 11 0010 User Defined 8-bit Data Type 3 */
#define ACQ_USR_DEF_4_DATA 51 /* 11 0011 User Defined 8-bit Data Type 4 */
#define ACQ_USR_DEF_5_DATA 52 /* 11 0100 User Defined 8-bit Data Type 5 */
#define ACQ_USR_DEF_6_DATA 53 /* 11 0101 User Defined 8-bit Data Type 6 */
#define ACQ_USR_DEF_7_DATA 54 /* 11 0110 User Defined 8-bit Data Type 7 */
#define ACQ_USR_DEF_8_DATA 55 /* 11 0111 User Defined 8-bit Data Type 8 */
#define ACQ_Emb_DATA 18 /* 01 0010 embedded eight bit non image data */
#define ACQ_SOF_DATA 0 /* 00 0000 frame start */
#define ACQ_EOF_DATA 1 /* 00 0001 frame end */
#define ACQ_SOL_DATA 2 /* 00 0010 line start */
#define ACQ_EOL_DATA 3 /* 00 0011 line end */
#define ACQ_GEN_SH1_DATA 8 /* 00 1000 Generic Short Packet Code 1 */
#define ACQ_GEN_SH2_DATA 9 /* 00 1001 Generic Short Packet Code 2 */
#define ACQ_GEN_SH3_DATA 10 /* 00 1010 Generic Short Packet Code 3 */
#define ACQ_GEN_SH4_DATA 11 /* 00 1011 Generic Short Packet Code 4 */
#define ACQ_GEN_SH5_DATA 12 /* 00 1100 Generic Short Packet Code 5 */
#define ACQ_GEN_SH6_DATA 13 /* 00 1101 Generic Short Packet Code 6 */
#define ACQ_GEN_SH7_DATA 14 /* 00 1110 Generic Short Packet Code 7 */
#define ACQ_GEN_SH8_DATA 15 /* 00 1111 Generic Short Packet Code 8 */
#define ACQ_YUV420_8_CSPS_DATA 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */
#define ACQ_YUV420_10_CSPS_DATA 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */
#define ACQ_RESERVED_DATA_TYPE_MIN 56
#define ACQ_RESERVED_DATA_TYPE_MAX 63
#define ACQ_GEN_LONG_RESERVED_DATA_TYPE_MIN 19
@ -231,4 +226,4 @@
/* --------------------------------------------------*/
#endif /* _isp_acquisition_defs_h */
#endif /* _isp_acquisition_defs_h */

146
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/isp_capture_defs.h
View File

@ -16,14 +16,14 @@
#define _isp_capture_defs_h
#define _ISP_CAPTURE_REG_ALIGN 4 /* assuming 32 bit control bus width */
#define _ISP_CAPTURE_BITS_PER_ELEM 32 /* only for data, not SOP */
#define _ISP_CAPTURE_BYTES_PER_ELEM (_ISP_CAPTURE_BITS_PER_ELEM/8 )
#define _ISP_CAPTURE_BYTES_PER_WORD 32 /* 256/8 */
#define _ISP_CAPTURE_ELEM_PER_WORD _ISP_CAPTURE_BYTES_PER_WORD / _ISP_CAPTURE_BYTES_PER_ELEM
#define _ISP_CAPTURE_BITS_PER_ELEM 32 /* only for data, not SOP */
#define _ISP_CAPTURE_BYTES_PER_ELEM (_ISP_CAPTURE_BITS_PER_ELEM / 8)
#define _ISP_CAPTURE_BYTES_PER_WORD 32 /* 256/8 */
#define _ISP_CAPTURE_ELEM_PER_WORD _ISP_CAPTURE_BYTES_PER_WORD / _ISP_CAPTURE_BYTES_PER_ELEM
//#define CAPT_RCV_ACK 1
//#define CAPT_WRT_ACK 2
//#define CAPT_IRQ_ACK 3
//#define CAPT_WRT_ACK 2
//#define CAPT_IRQ_ACK 3
/* --------------------------------------------------*/
@ -38,25 +38,25 @@
// Register id's of MMIO slave accesible registers
#define CAPT_START_MODE_REG_ID 0
#define CAPT_START_ADDR_REG_ID 1
#define CAPT_MEM_REGION_SIZE_REG_ID 2
#define CAPT_NUM_MEM_REGIONS_REG_ID 3
#define CAPT_INIT_REG_ID 4
#define CAPT_START_ADDR_REG_ID 1
#define CAPT_MEM_REGION_SIZE_REG_ID 2
#define CAPT_NUM_MEM_REGIONS_REG_ID 3
#define CAPT_INIT_REG_ID 4
#define CAPT_START_REG_ID 5
#define CAPT_STOP_REG_ID 6
#define CAPT_STOP_REG_ID 6
#define CAPT_PACKET_LENGTH_REG_ID 7
#define CAPT_RECEIVED_LENGTH_REG_ID 8
#define CAPT_RECEIVED_SHORT_PACKETS_REG_ID 9
#define CAPT_RECEIVED_LONG_PACKETS_REG_ID 10
#define CAPT_LAST_COMMAND_REG_ID 11
#define CAPT_RECEIVED_LENGTH_REG_ID 8
#define CAPT_RECEIVED_SHORT_PACKETS_REG_ID 9
#define CAPT_RECEIVED_LONG_PACKETS_REG_ID 10
#define CAPT_LAST_COMMAND_REG_ID 11
#define CAPT_NEXT_COMMAND_REG_ID 12
#define CAPT_LAST_ACKNOWLEDGE_REG_ID 13
#define CAPT_NEXT_ACKNOWLEDGE_REG_ID 14
#define CAPT_FSM_STATE_INFO_REG_ID 15
// Register width
#define CAPT_START_MODE_REG_WIDTH 1
#define CAPT_START_MODE_REG_WIDTH 1
#define CAPT_START_ADDR_REG_WIDTH 9
#define CAPT_MEM_REGION_SIZE_REG_WIDTH 9
#define CAPT_NUM_MEM_REGIONS_REG_WIDTH 9
@ -71,25 +71,24 @@
#define CAPT_WRITE2MEM_FSM_STATE_BITS 2
#define CAPT_SYNCHRONIZER_FSM_STATE_BITS 3
#define CAPT_PACKET_LENGTH_REG_WIDTH 17
#define CAPT_RECEIVED_LENGTH_REG_WIDTH 17
#define CAPT_RECEIVED_LENGTH_REG_WIDTH 17
#define CAPT_RECEIVED_SHORT_PACKETS_REG_WIDTH 32
#define CAPT_RECEIVED_LONG_PACKETS_REG_WIDTH 32
#define CAPT_LAST_COMMAND_REG_WIDTH 32
/* #define CAPT_NEXT_COMMAND_REG_WIDTH 32 */
/* #define CAPT_NEXT_COMMAND_REG_WIDTH 32 */
#define CAPT_LAST_ACKNOWLEDGE_REG_WIDTH 32
#define CAPT_NEXT_ACKNOWLEDGE_REG_WIDTH 32
#define CAPT_FSM_STATE_INFO_REG_WIDTH ((CAPT_WRITE2MEM_FSM_STATE_BITS * 3) + (CAPT_SYNCHRONIZER_FSM_STATE_BITS * 3))
#define CAPT_INIT_RESTART_MEM_ADDR_WIDTH 9
#define CAPT_INIT_RESTART_MEM_REGION_WIDTH 9
#define CAPT_INIT_RESTART_MEM_ADDR_WIDTH 9
#define CAPT_INIT_RESTART_MEM_REGION_WIDTH 9
/* register reset value */
#define CAPT_START_MODE_REG_RSTVAL 0
#define CAPT_START_MODE_REG_RSTVAL 0
#define CAPT_START_ADDR_REG_RSTVAL 0
#define CAPT_MEM_REGION_SIZE_REG_RSTVAL 128
#define CAPT_NUM_MEM_REGIONS_REG_RSTVAL 3
#define CAPT_NUM_MEM_REGIONS_REG_RSTVAL 3
#define CAPT_INIT_REG_RSTVAL 0
#define CAPT_START_REG_RSTVAL 0
@ -115,7 +114,6 @@
#define CAPT_INIT_RESTART_MEM_REGION_LSB 13
#define CAPT_INIT_RESTART_MEM_REGION_MSB 21
#define CAPT_INIT_RST_REG_IDX CAPT_INIT_RST_REG_BIT
#define CAPT_INIT_RST_REG_BITS 1
#define CAPT_INIT_FLUSH_IDX CAPT_INIT_FLUSH_BIT
@ -123,29 +121,27 @@
#define CAPT_INIT_RESYNC_IDX CAPT_INIT_RESYNC_BIT
#define CAPT_INIT_RESYNC_BITS 1
#define CAPT_INIT_RESTART_IDX CAPT_INIT_RESTART_BIT
#define CAPT_INIT_RESTART_BITS 1
#define CAPT_INIT_RESTART_BITS 1
#define CAPT_INIT_RESTART_MEM_ADDR_IDX CAPT_INIT_RESTART_MEM_ADDR_LSB
#define CAPT_INIT_RESTART_MEM_ADDR_BITS (CAPT_INIT_RESTART_MEM_ADDR_MSB - CAPT_INIT_RESTART_MEM_ADDR_LSB + 1)
#define CAPT_INIT_RESTART_MEM_REGION_IDX CAPT_INIT_RESTART_MEM_REGION_LSB
#define CAPT_INIT_RESTART_MEM_REGION_BITS (CAPT_INIT_RESTART_MEM_REGION_MSB - CAPT_INIT_RESTART_MEM_REGION_LSB + 1)
/* --------------------------------------------------*/
/* TOKEN INFO */
/* --------------------------------------------------*/
#define CAPT_TOKEN_ID_LSB 0
#define CAPT_TOKEN_ID_MSB 3
#define CAPT_TOKEN_ID_MSB 3
#define CAPT_TOKEN_WIDTH (CAPT_TOKEN_ID_MSB - CAPT_TOKEN_ID_LSB + 1) /* 4 */
/* Command tokens IDs */
#define CAPT_START_TOKEN_ID 0 /* 0000b */
#define CAPT_STOP_TOKEN_ID 1 /* 0001b */
#define CAPT_FREEZE_TOKEN_ID 2 /* 0010b */
#define CAPT_FREEZE_TOKEN_ID 2 /* 0010b */
#define CAPT_RESUME_TOKEN_ID 3 /* 0011b */
#define CAPT_INIT_TOKEN_ID 8 /* 1000b */
#define CAPT_START_TOKEN_BIT 0
#define CAPT_START_TOKEN_BIT 0
#define CAPT_STOP_TOKEN_BIT 0
#define CAPT_FREEZE_TOKEN_BIT 0
#define CAPT_RESUME_TOKEN_BIT 0
@ -169,8 +165,8 @@
#define CAPT_PACKET_DATA_FORMAT_ID_TOKEN_LSB 20
#define CAPT_PACKET_CH_ID_TOKEN_MSB 27
#define CAPT_PACKET_CH_ID_TOKEN_LSB 26
#define CAPT_PACKET_MEM_REGION_ID_TOKEN_MSB 29
#define CAPT_PACKET_MEM_REGION_ID_TOKEN_LSB 21
#define CAPT_PACKET_MEM_REGION_ID_TOKEN_MSB 29
#define CAPT_PACKET_MEM_REGION_ID_TOKEN_LSB 21
/* bit definition */
#define CAPT_CMD_IDX CAPT_TOKEN_ID_LSB
@ -208,21 +204,19 @@
#define CAPT_INIT_TOKEN_INIT_IDX 4
#define CAPT_INIT_TOKEN_INIT_BITS 22
/* --------------------------------------------------*/
/* MIPI */
/* --------------------------------------------------*/
#define CAPT_WORD_COUNT_WIDTH 16
#define CAPT_PKT_CODE_WIDTH 6
#define CAPT_CHN_NO_WIDTH 2
#define CAPT_ERROR_INFO_WIDTH 8
#define CAPT_WORD_COUNT_WIDTH 16
#define CAPT_PKT_CODE_WIDTH 6
#define CAPT_CHN_NO_WIDTH 2
#define CAPT_ERROR_INFO_WIDTH 8
#define LONG_PKTCODE_MAX 63
#define LONG_PKTCODE_MIN 16
#define SHORT_PKTCODE_MAX 15
/* --------------------------------------------------*/
/* Packet Info */
/* --------------------------------------------------*/
@ -233,7 +227,6 @@
#define CAPT_LINE_PAYLOAD 4
#define CAPT_GEN_SH_PKT 5
/* --------------------------------------------------*/
/* Packet Data Type */
/* --------------------------------------------------*/
@ -244,39 +237,39 @@
#define CAPT_YUV422_8_DATA 30 /* 01 1110 YUV422 8-bit */
#define CAPT_YUV422_10_DATA 31 /* 01 1111 YUV422 10-bit */
#define CAPT_RGB444_DATA 32 /* 10 0000 RGB444 */
#define CAPT_RGB555_DATA 33 /* 10 0001 RGB555 */
#define CAPT_RGB565_DATA 34 /* 10 0010 RGB565 */
#define CAPT_RGB666_DATA 35 /* 10 0011 RGB666 */
#define CAPT_RGB888_DATA 36 /* 10 0100 RGB888 */
#define CAPT_RAW6_DATA 40 /* 10 1000 RAW6 */
#define CAPT_RAW7_DATA 41 /* 10 1001 RAW7 */
#define CAPT_RAW8_DATA 42 /* 10 1010 RAW8 */
#define CAPT_RAW10_DATA 43 /* 10 1011 RAW10 */
#define CAPT_RAW12_DATA 44 /* 10 1100 RAW12 */
#define CAPT_RAW14_DATA 45 /* 10 1101 RAW14 */
#define CAPT_USR_DEF_1_DATA 48 /* 11 0000 JPEG [User Defined 8-bit Data Type 1] */
#define CAPT_USR_DEF_2_DATA 49 /* 11 0001 User Defined 8-bit Data Type 2 */
#define CAPT_USR_DEF_3_DATA 50 /* 11 0010 User Defined 8-bit Data Type 3 */
#define CAPT_USR_DEF_4_DATA 51 /* 11 0011 User Defined 8-bit Data Type 4 */
#define CAPT_USR_DEF_5_DATA 52 /* 11 0100 User Defined 8-bit Data Type 5 */
#define CAPT_USR_DEF_6_DATA 53 /* 11 0101 User Defined 8-bit Data Type 6 */
#define CAPT_USR_DEF_7_DATA 54 /* 11 0110 User Defined 8-bit Data Type 7 */
#define CAPT_USR_DEF_8_DATA 55 /* 11 0111 User Defined 8-bit Data Type 8 */
#define CAPT_Emb_DATA 18 /* 01 0010 embedded eight bit non image data */
#define CAPT_SOF_DATA 0 /* 00 0000 frame start */
#define CAPT_EOF_DATA 1 /* 00 0001 frame end */
#define CAPT_SOL_DATA 2 /* 00 0010 line start */
#define CAPT_EOL_DATA 3 /* 00 0011 line end */
#define CAPT_GEN_SH1_DATA 8 /* 00 1000 Generic Short Packet Code 1 */
#define CAPT_GEN_SH2_DATA 9 /* 00 1001 Generic Short Packet Code 2 */
#define CAPT_GEN_SH3_DATA 10 /* 00 1010 Generic Short Packet Code 3 */
#define CAPT_GEN_SH4_DATA 11 /* 00 1011 Generic Short Packet Code 4 */
#define CAPT_GEN_SH5_DATA 12 /* 00 1100 Generic Short Packet Code 5 */
#define CAPT_GEN_SH6_DATA 13 /* 00 1101 Generic Short Packet Code 6 */
#define CAPT_GEN_SH7_DATA 14 /* 00 1110 Generic Short Packet Code 7 */
#define CAPT_GEN_SH8_DATA 15 /* 00 1111 Generic Short Packet Code 8 */
#define CAPT_YUV420_8_CSPS_DATA 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */
#define CAPT_YUV420_10_CSPS_DATA 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */
#define CAPT_RGB555_DATA 33 /* 10 0001 RGB555 */
#define CAPT_RGB565_DATA 34 /* 10 0010 RGB565 */
#define CAPT_RGB666_DATA 35 /* 10 0011 RGB666 */
#define CAPT_RGB888_DATA 36 /* 10 0100 RGB888 */
#define CAPT_RAW6_DATA 40 /* 10 1000 RAW6 */
#define CAPT_RAW7_DATA 41 /* 10 1001 RAW7 */
#define CAPT_RAW8_DATA 42 /* 10 1010 RAW8 */
#define CAPT_RAW10_DATA 43 /* 10 1011 RAW10 */
#define CAPT_RAW12_DATA 44 /* 10 1100 RAW12 */
#define CAPT_RAW14_DATA 45 /* 10 1101 RAW14 */
#define CAPT_USR_DEF_1_DATA 48 /* 11 0000 JPEG [User Defined 8-bit Data Type 1] */
#define CAPT_USR_DEF_2_DATA 49 /* 11 0001 User Defined 8-bit Data Type 2 */
#define CAPT_USR_DEF_3_DATA 50 /* 11 0010 User Defined 8-bit Data Type 3 */
#define CAPT_USR_DEF_4_DATA 51 /* 11 0011 User Defined 8-bit Data Type 4 */
#define CAPT_USR_DEF_5_DATA 52 /* 11 0100 User Defined 8-bit Data Type 5 */
#define CAPT_USR_DEF_6_DATA 53 /* 11 0101 User Defined 8-bit Data Type 6 */
#define CAPT_USR_DEF_7_DATA 54 /* 11 0110 User Defined 8-bit Data Type 7 */
#define CAPT_USR_DEF_8_DATA 55 /* 11 0111 User Defined 8-bit Data Type 8 */
#define CAPT_Emb_DATA 18 /* 01 0010 embedded eight bit non image data */
#define CAPT_SOF_DATA 0 /* 00 0000 frame start */
#define CAPT_EOF_DATA 1 /* 00 0001 frame end */
#define CAPT_SOL_DATA 2 /* 00 0010 line start */
#define CAPT_EOL_DATA 3 /* 00 0011 line end */
#define CAPT_GEN_SH1_DATA 8 /* 00 1000 Generic Short Packet Code 1 */
#define CAPT_GEN_SH2_DATA 9 /* 00 1001 Generic Short Packet Code 2 */
#define CAPT_GEN_SH3_DATA 10 /* 00 1010 Generic Short Packet Code 3 */
#define CAPT_GEN_SH4_DATA 11 /* 00 1011 Generic Short Packet Code 4 */
#define CAPT_GEN_SH5_DATA 12 /* 00 1100 Generic Short Packet Code 5 */
#define CAPT_GEN_SH6_DATA 13 /* 00 1101 Generic Short Packet Code 6 */
#define CAPT_GEN_SH7_DATA 14 /* 00 1110 Generic Short Packet Code 7 */
#define CAPT_GEN_SH8_DATA 15 /* 00 1111 Generic Short Packet Code 8 */
#define CAPT_YUV420_8_CSPS_DATA 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */
#define CAPT_YUV420_10_CSPS_DATA 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */
#define CAPT_RESERVED_DATA_TYPE_MIN 56
#define CAPT_RESERVED_DATA_TYPE_MAX 63
#define CAPT_GEN_LONG_RESERVED_DATA_TYPE_MIN 19
@ -287,7 +280,6 @@
#define CAPT_RAW_RESERVED_DATA_TYPE_MIN 46
#define CAPT_RAW_RESERVED_DATA_TYPE_MAX 47
/* --------------------------------------------------*/
/* Capture Unit State */
/* --------------------------------------------------*/
@ -299,12 +291,6 @@
#define CAPT_FREEZE 5
#define CAPT_RUN 6
/* --------------------------------------------------*/
#endif /* _isp_capture_defs_h */
#endif /* _isp_capture_defs_h */

2
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/timed_controller_defs.h
View File

@ -19,4 +19,4 @@
#define _HRT_TIMED_CONTROLLER_REG_ALIGN 4
#endif /* _timed_controller_defs_h */
#endif /* _timed_controller_defs_h */

28
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/var.h
View File

@ -40,35 +40,35 @@
#define hrt_host_type_of_ulong unsigned long
#define hrt_host_type_of_ptr void*
#define HRT_TYPE_BYTES(cell, type) (HRT_TYPE_BITS(cell, type)/8)
#define HRT_TYPE_BYTES(cell, type) (HRT_TYPE_BITS(cell, type) / 8)
#define HRT_HOST_TYPE(cell_type) HRTCAT(hrt_host_type_of_, cell_type)
#define HRT_INT_TYPE(type) HRTCAT(hrt_int_type_of_, type)
#define hrt_scalar_store(cell, type, var, data) \
HRTCAT(hrt_mem_store_,HRT_TYPE_BITS(cell, type))(\
HRTCAT(hrt_mem_store_, HRT_TYPE_BITS(cell, type))(\
cell, \
HRTCAT(HIVE_MEM_,var), \
HRTCAT(HIVE_ADDR_,var), \
HRTCAT(HIVE_MEM_, var), \
HRTCAT(HIVE_ADDR_, var), \
(HRT_INT_TYPE(type))(data))
#define hrt_scalar_load(cell, type, var) \
(HRT_HOST_TYPE(type))(HRTCAT4(_hrt_mem_load_,HRT_PROC_TYPE(cell),_,type) ( \
(HRT_HOST_TYPE(type))(HRTCAT4(_hrt_mem_load_, HRT_PROC_TYPE(cell), _, type) ( \
cell, \
HRTCAT(HIVE_MEM_,var), \
HRTCAT(HIVE_ADDR_,var)))
HRTCAT(HIVE_MEM_, var), \
HRTCAT(HIVE_ADDR_, var)))
#define hrt_indexed_store(cell, type, array, index, data) \
HRTCAT(hrt_mem_store_,HRT_TYPE_BITS(cell, type))(\
HRTCAT(hrt_mem_store_, HRT_TYPE_BITS(cell, type))(\
cell, \
HRTCAT(HIVE_MEM_,array), \
(HRTCAT(HIVE_ADDR_,array))+((index)*HRT_TYPE_BYTES(cell, type)), \
HRTCAT(HIVE_MEM_, array), \
(HRTCAT(HIVE_ADDR_, array)) + ((index) * HRT_TYPE_BYTES(cell, type)), \
(HRT_INT_TYPE(type))(data))
#define hrt_indexed_load(cell, type, array, index) \
(HRT_HOST_TYPE(type))(HRTCAT4(_hrt_mem_load_,HRT_PROC_TYPE(cell),_,type) ( \
cell, \
HRTCAT(HIVE_MEM_,array), \
(HRTCAT(HIVE_ADDR_,array))+((index)*HRT_TYPE_BYTES(cell, type))))
(HRT_HOST_TYPE(type))(HRTCAT4(_hrt_mem_load_, HRT_PROC_TYPE(cell), _, type) ( \
cell, \
HRTCAT(HIVE_MEM_, array), \
(HRTCAT(HIVE_ADDR_, array)) + ((index) * HRT_TYPE_BYTES(cell, type))))
#endif /* _HRT_VAR_H */
#endif

1
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/spmem_dump.c
View File

@ -15,7 +15,6 @@
#ifndef _sp_map_h_
#define _sp_map_h_
#ifndef _hrt_dummy_use_blob_sp
#define _hrt_dummy_use_blob_sp()
#endif

24
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/csi_rx_global.h
View File

@ -27,8 +27,8 @@ typedef enum {
typedef struct csi_rx_backend_lut_entry_s csi_rx_backend_lut_entry_t;
struct csi_rx_backend_lut_entry_s {
uint32_t long_packet_entry;
uint32_t short_packet_entry;
u32 long_packet_entry;
u32 short_packet_entry;
};
typedef struct csi_rx_backend_cfg_s csi_rx_backend_cfg_t;
@ -41,23 +41,23 @@ struct csi_rx_backend_cfg_s {
struct {
bool comp_enable;
uint32_t virtual_channel;
uint32_t data_type;
uint32_t comp_scheme;
uint32_t comp_predictor;
uint32_t comp_bit_idx;
u32 virtual_channel;
u32 data_type;
u32 comp_scheme;
u32 comp_predictor;
u32 comp_bit_idx;
} csi_mipi_cfg;
};
typedef struct csi_rx_frontend_cfg_s csi_rx_frontend_cfg_t;
struct csi_rx_frontend_cfg_s {
uint32_t active_lanes;
u32 active_lanes;
};
extern const uint32_t N_SHORT_PACKET_LUT_ENTRIES[N_CSI_RX_BACKEND_ID];
extern const uint32_t N_LONG_PACKET_LUT_ENTRIES[N_CSI_RX_BACKEND_ID];
extern const uint32_t N_CSI_RX_FE_CTRL_DLANES[N_CSI_RX_FRONTEND_ID];
extern const u32 N_SHORT_PACKET_LUT_ENTRIES[N_CSI_RX_BACKEND_ID];
extern const u32 N_LONG_PACKET_LUT_ENTRIES[N_CSI_RX_BACKEND_ID];
extern const u32 N_CSI_RX_FE_CTRL_DLANES[N_CSI_RX_FRONTEND_ID];
/* sid_width for CSI_RX_BACKEND<N>_ID */
extern const uint32_t N_CSI_RX_BE_SID_WIDTH[N_CSI_RX_BACKEND_ID];
extern const u32 N_CSI_RX_BE_SID_WIDTH[N_CSI_RX_BACKEND_ID];
#endif /* __CSI_RX_GLOBAL_H_INCLUDED__ */

71
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_configs.c
View File

@ -30,8 +30,9 @@ ia_css_configure_iterator(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_iterator() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
unsigned int offset = 0;
unsigned int size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.iterator.size;
offset = binary->info->mem_offsets.offsets.config->dmem.iterator.offset;
@ -54,8 +55,9 @@ ia_css_configure_copy_output(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_copy_output() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
unsigned int offset = 0;
unsigned int size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.copy_output.size;
offset = binary->info->mem_offsets.offsets.config->dmem.copy_output.offset;
@ -78,8 +80,9 @@ ia_css_configure_crop(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_crop() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
unsigned int offset = 0;
unsigned int size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.crop.size;
offset = binary->info->mem_offsets.offsets.config->dmem.crop.offset;
@ -102,8 +105,9 @@ ia_css_configure_fpn(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_fpn() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
unsigned int offset = 0;
unsigned int size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.fpn.size;
offset = binary->info->mem_offsets.offsets.config->dmem.fpn.offset;
@ -126,8 +130,9 @@ ia_css_configure_dvs(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_dvs() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
unsigned int offset = 0;
unsigned int size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.dvs.size;
offset = binary->info->mem_offsets.offsets.config->dmem.dvs.offset;
@ -150,8 +155,9 @@ ia_css_configure_qplane(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_qplane() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
unsigned int offset = 0;
unsigned int size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.qplane.size;
offset = binary->info->mem_offsets.offsets.config->dmem.qplane.offset;
@ -174,8 +180,9 @@ ia_css_configure_output0(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output0() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
unsigned int offset = 0;
unsigned int size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.output0.size;
offset = binary->info->mem_offsets.offsets.config->dmem.output0.offset;
@ -198,8 +205,9 @@ ia_css_configure_output1(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output1() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
unsigned int offset = 0;
unsigned int size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.output1.size;
offset = binary->info->mem_offsets.offsets.config->dmem.output1.offset;
@ -222,8 +230,9 @@ ia_css_configure_output(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
unsigned int offset = 0;
unsigned int size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.output.size;
offset = binary->info->mem_offsets.offsets.config->dmem.output.offset;
@ -247,8 +256,9 @@ ia_css_configure_sc(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_sc() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
unsigned int offset = 0;
unsigned int size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.sc.size;
offset = binary->info->mem_offsets.offsets.config->dmem.sc.offset;
@ -272,8 +282,9 @@ ia_css_configure_raw(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_raw() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
unsigned int offset = 0;
unsigned int size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.raw.size;
offset = binary->info->mem_offsets.offsets.config->dmem.raw.offset;
@ -296,8 +307,9 @@ ia_css_configure_tnr(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_tnr() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
unsigned int offset = 0;
unsigned int size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.tnr.size;
offset = binary->info->mem_offsets.offsets.config->dmem.tnr.offset;
@ -320,8 +332,9 @@ ia_css_configure_ref(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_ref() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
unsigned int offset = 0;
unsigned int size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.ref.size;
offset = binary->info->mem_offsets.offsets.config->dmem.ref.offset;
@ -344,8 +357,9 @@ ia_css_configure_vf(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_vf() enter:\n");
{
unsigned offset = 0;
unsigned size = 0;
unsigned int offset = 0;
unsigned int size = 0;
if (binary->info->mem_offsets.offsets.config) {
size = binary->info->mem_offsets.offsets.config->dmem.vf.size;
offset = binary->info->mem_offsets.offsets.config->dmem.vf.offset;
@ -357,4 +371,3 @@ ia_css_configure_vf(
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_vf() leave:\n");
}

996
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_params.c
View File

File diff suppressed because it is too large Load Diff

4
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_params.h
View File

@ -149,8 +149,8 @@ struct ia_css_memory_offsets {
struct ia_css_pipeline_stage; /* forward declaration */
extern void (* ia_css_kernel_process_param[IA_CSS_NUM_PARAMETER_IDS])(
unsigned pipe_id,
extern void (*ia_css_kernel_process_param[IA_CSS_NUM_PARAMETER_IDS])(
unsigned int pipe_id,
const struct ia_css_pipeline_stage *stage,
struct ia_css_isp_parameters *params);

41
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_states.c
View File

@ -28,12 +28,11 @@ ia_css_initialize_aa_state(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_aa_state() enter:\n");
{
unsigned size = binary->info->mem_offsets.offsets.state->vmem.aa.size;
unsigned offset = binary->info->mem_offsets.offsets.state->vmem.aa.offset;
unsigned int size = binary->info->mem_offsets.offsets.state->vmem.aa.size;
unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.aa.offset;
if (size)
memset(&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset], 0, size);
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_aa_state() leave:\n");
}
@ -47,16 +46,15 @@ ia_css_initialize_cnr_state(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr_state() enter:\n");
{
unsigned size = binary->info->mem_offsets.offsets.state->vmem.cnr.size;
unsigned int size = binary->info->mem_offsets.offsets.state->vmem.cnr.size;
unsigned offset = binary->info->mem_offsets.offsets.state->vmem.cnr.offset;
unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.cnr.offset;
if (size) {
ia_css_init_cnr_state(
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset],
size);
}
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr_state() leave:\n");
}
@ -70,16 +68,15 @@ ia_css_initialize_cnr2_state(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr2_state() enter:\n");
{
unsigned size = binary->info->mem_offsets.offsets.state->vmem.cnr2.size;
unsigned int size = binary->info->mem_offsets.offsets.state->vmem.cnr2.size;
unsigned offset = binary->info->mem_offsets.offsets.state->vmem.cnr2.offset;
unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.cnr2.offset;
if (size) {
ia_css_init_cnr2_state(
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset],
size);
}
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr2_state() leave:\n");
}
@ -93,16 +90,15 @@ ia_css_initialize_dp_state(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_dp_state() enter:\n");
{
unsigned size = binary->info->mem_offsets.offsets.state->vmem.dp.size;
unsigned int size = binary->info->mem_offsets.offsets.state->vmem.dp.size;
unsigned offset = binary->info->mem_offsets.offsets.state->vmem.dp.offset;
unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.dp.offset;
if (size) {
ia_css_init_dp_state(
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset],
size);
}
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_dp_state() leave:\n");
}
@ -116,16 +112,15 @@ ia_css_initialize_de_state(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_de_state() enter:\n");
{
unsigned size = binary->info->mem_offsets.offsets.state->vmem.de.size;
unsigned int size = binary->info->mem_offsets.offsets.state->vmem.de.size;
unsigned offset = binary->info->mem_offsets.offsets.state->vmem.de.offset;
unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.de.offset;
if (size) {
ia_css_init_de_state(
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset],
size);
}
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_de_state() leave:\n");
}
@ -139,16 +134,15 @@ ia_css_initialize_tnr_state(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_tnr_state() enter:\n");
{
unsigned size = binary->info->mem_offsets.offsets.state->dmem.tnr.size;
unsigned int size = binary->info->mem_offsets.offsets.state->dmem.tnr.size;
unsigned offset = binary->info->mem_offsets.offsets.state->dmem.tnr.offset;
unsigned int offset = binary->info->mem_offsets.offsets.state->dmem.tnr.offset;
if (size) {
ia_css_init_tnr_state((struct sh_css_isp_tnr_dmem_state *)
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_DMEM].address[offset],
size);
}
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_tnr_state() leave:\n");
}
@ -162,16 +156,15 @@ ia_css_initialize_ref_state(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ref_state() enter:\n");
{
unsigned size = binary->info->mem_offsets.offsets.state->dmem.ref.size;
unsigned int size = binary->info->mem_offsets.offsets.state->dmem.ref.size;
unsigned offset = binary->info->mem_offsets.offsets.state->dmem.ref.offset;
unsigned int offset = binary->info->mem_offsets.offsets.state->dmem.ref.offset;
if (size) {
ia_css_init_ref_state((struct sh_css_isp_ref_dmem_state *)
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_DMEM].address[offset],
size);
}
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ref_state() leave:\n");
}
@ -185,16 +178,15 @@ ia_css_initialize_ynr_state(
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ynr_state() enter:\n");
{
unsigned size = binary->info->mem_offsets.offsets.state->vmem.ynr.size;
unsigned int size = binary->info->mem_offsets.offsets.state->vmem.ynr.size;
unsigned offset = binary->info->mem_offsets.offsets.state->vmem.ynr.offset;
unsigned int offset = binary->info->mem_offsets.offsets.state->vmem.ynr.offset;
if (size) {
ia_css_init_ynr_state(
&binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset],
size);
}
}
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ynr_state() leave:\n");
}
@ -211,4 +203,3 @@ void (* ia_css_kernel_init_state[IA_CSS_NUM_STATE_IDS])(const struct ia_css_bina
ia_css_initialize_ref_state,
ia_css_initialize_ynr_state,
};

9
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/csi_rx.c
View File

@ -12,29 +12,28 @@
* more details.
*/
#include "system_global.h"
const uint32_t N_SHORT_PACKET_LUT_ENTRIES[N_CSI_RX_BACKEND_ID] = {
const u32 N_SHORT_PACKET_LUT_ENTRIES[N_CSI_RX_BACKEND_ID] = {
4, /* 4 entries at CSI_RX_BACKEND0_ID*/
4, /* 4 entries at CSI_RX_BACKEND1_ID*/
4 /* 4 entries at CSI_RX_BACKEND2_ID*/
};
const uint32_t N_LONG_PACKET_LUT_ENTRIES[N_CSI_RX_BACKEND_ID] = {
const u32 N_LONG_PACKET_LUT_ENTRIES[N_CSI_RX_BACKEND_ID] = {
8, /* 8 entries at CSI_RX_BACKEND0_ID*/
4, /* 4 entries at CSI_RX_BACKEND1_ID*/
4 /* 4 entries at CSI_RX_BACKEND2_ID*/
};
const uint32_t N_CSI_RX_FE_CTRL_DLANES[N_CSI_RX_FRONTEND_ID] = {
const u32 N_CSI_RX_FE_CTRL_DLANES[N_CSI_RX_FRONTEND_ID] = {
N_CSI_RX_DLANE_ID, /* 4 dlanes for CSI_RX_FR0NTEND0_ID */
N_CSI_RX_DLANE_ID, /* 4 dlanes for CSI_RX_FR0NTEND1_ID */
N_CSI_RX_DLANE_ID /* 4 dlanes for CSI_RX_FR0NTEND2_ID */
};
/* sid_width for CSI_RX_BACKEND<N>_ID */
const uint32_t N_CSI_RX_BE_SID_WIDTH[N_CSI_RX_BACKEND_ID] = {
const u32 N_CSI_RX_BE_SID_WIDTH[N_CSI_RX_BACKEND_ID] = {
3,
2,
2

51
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/csi_rx_local.h
View File

@ -16,7 +16,7 @@
#define __CSI_RX_LOCAL_H_INCLUDED__
#include "csi_rx_global.h"
#define N_CSI_RX_BE_MIPI_COMP_FMT_REG 4
#define N_CSI_RX_BE_MIPI_COMP_FMT_REG 4
#define N_CSI_RX_BE_MIPI_CUSTOM_PEC 12
#define N_CSI_RX_BE_SHORT_PKT_LUT 4
#define N_CSI_RX_BE_LONG_PKT_LUT 8
@ -26,36 +26,37 @@ typedef struct csi_rx_be_ctrl_state_s csi_rx_be_ctrl_state_t;
/*mipi_backend_custom_mode_pixel_extraction_config*/
typedef struct csi_rx_be_ctrl_pec_s csi_rx_be_ctrl_pec_t;
struct csi_rx_fe_ctrl_lane_s {
hrt_data termen;
hrt_data settle;
};
struct csi_rx_fe_ctrl_state_s {
hrt_data enable;
hrt_data nof_enable_lanes;
hrt_data error_handling;
hrt_data status;
hrt_data status_dlane_hs;
hrt_data status_dlane_lp;
csi_rx_fe_ctrl_lane_t clane;
csi_rx_fe_ctrl_lane_t dlane[N_CSI_RX_DLANE_ID];
hrt_data enable;
hrt_data nof_enable_lanes;
hrt_data error_handling;
hrt_data status;
hrt_data status_dlane_hs;
hrt_data status_dlane_lp;
csi_rx_fe_ctrl_lane_t clane;
csi_rx_fe_ctrl_lane_t dlane[N_CSI_RX_DLANE_ID];
};
struct csi_rx_be_ctrl_state_s {
hrt_data enable;
hrt_data status;
hrt_data comp_format_reg[N_CSI_RX_BE_MIPI_COMP_FMT_REG];
hrt_data raw16;
hrt_data raw18;
hrt_data force_raw8;
hrt_data irq_status;
hrt_data custom_mode_enable;
hrt_data custom_mode_data_state;
hrt_data pec[N_CSI_RX_BE_MIPI_CUSTOM_PEC];
hrt_data custom_mode_valid_eop_config;
hrt_data global_lut_disregard_reg;
hrt_data packet_status_stall;
hrt_data short_packet_lut_entry[N_CSI_RX_BE_SHORT_PKT_LUT];
hrt_data long_packet_lut_entry[N_CSI_RX_BE_LONG_PKT_LUT];
hrt_data enable;
hrt_data status;
hrt_data comp_format_reg[N_CSI_RX_BE_MIPI_COMP_FMT_REG];
hrt_data raw16;
hrt_data raw18;
hrt_data force_raw8;
hrt_data irq_status;
hrt_data custom_mode_enable;
hrt_data custom_mode_data_state;
hrt_data pec[N_CSI_RX_BE_MIPI_CUSTOM_PEC];
hrt_data custom_mode_valid_eop_config;
hrt_data global_lut_disregard_reg;
hrt_data packet_status_stall;
hrt_data short_packet_lut_entry[N_CSI_RX_BE_SHORT_PKT_LUT];
hrt_data long_packet_lut_entry[N_CSI_RX_BE_LONG_PKT_LUT];
};
#endif /* __CSI_RX_LOCAL_H_INCLUDED__ */

87
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/csi_rx_private.h
View File

@ -24,7 +24,6 @@
#include "assert_support.h" /* assert */
#include "print_support.h" /* print */
/*****************************************************
*
* Native command interface (NCI).
@ -38,7 +37,7 @@ static inline void csi_rx_fe_ctrl_get_state(
const csi_rx_frontend_ID_t ID,
csi_rx_fe_ctrl_state_t *state)
{
uint32_t i;
u32 i;
state->enable =
csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_ENABLE_REG_IDX);
@ -65,7 +64,7 @@ static inline void csi_rx_fe_ctrl_get_state(
csi_rx_fe_ctrl_get_dlane_state(
ID,
i,
&(state->dlane[i]));
&state->dlane[i]);
}
}
@ -75,16 +74,15 @@ static inline void csi_rx_fe_ctrl_get_state(
*/
static inline void csi_rx_fe_ctrl_get_dlane_state(
const csi_rx_frontend_ID_t ID,
const uint32_t lane,
const u32 lane,
csi_rx_fe_ctrl_lane_t *dlane_state)
{
dlane_state->termen =
csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_TERMEN_DLANE_REG_IDX(lane));
dlane_state->settle =
csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_SETTLE_DLANE_REG_IDX(lane));
}
/**
* @brief dump the csi rx fe state.
* Refer to "csi_rx_public.h" for details.
@ -93,24 +91,24 @@ static inline void csi_rx_fe_ctrl_dump_state(
const csi_rx_frontend_ID_t ID,
csi_rx_fe_ctrl_state_t *state)
{
uint32_t i;
u32 i;
ia_css_print("CSI RX FE STATE Controller %d Enable state 0x%x \n", ID, state->enable);
ia_css_print("CSI RX FE STATE Controller %d No Of enable lanes 0x%x \n", ID, state->nof_enable_lanes);
ia_css_print("CSI RX FE STATE Controller %d Error handling 0x%x \n", ID, state->error_handling);
ia_css_print("CSI RX FE STATE Controller %d Status 0x%x \n", ID, state->status);
ia_css_print("CSI RX FE STATE Controller %d Status Dlane HS 0x%x \n", ID, state->status_dlane_hs);
ia_css_print("CSI RX FE STATE Controller %d Status Dlane LP 0x%x \n", ID, state->status_dlane_lp);
ia_css_print("CSI RX FE STATE Controller %d Status term enable LP 0x%x \n", ID, state->clane.termen);
ia_css_print("CSI RX FE STATE Controller %d Status term settle LP 0x%x \n", ID, state->clane.settle);
ia_css_print("CSI RX FE STATE Controller %d Enable state 0x%x\n", ID, state->enable);
ia_css_print("CSI RX FE STATE Controller %d No Of enable lanes 0x%x\n", ID, state->nof_enable_lanes);
ia_css_print("CSI RX FE STATE Controller %d Error handling 0x%x\n", ID, state->error_handling);
ia_css_print("CSI RX FE STATE Controller %d Status 0x%x\n", ID, state->status);
ia_css_print("CSI RX FE STATE Controller %d Status Dlane HS 0x%x\n", ID, state->status_dlane_hs);
ia_css_print("CSI RX FE STATE Controller %d Status Dlane LP 0x%x\n", ID, state->status_dlane_lp);
ia_css_print("CSI RX FE STATE Controller %d Status term enable LP 0x%x\n", ID, state->clane.termen);
ia_css_print("CSI RX FE STATE Controller %d Status term settle LP 0x%x\n", ID, state->clane.settle);
/*
* Get the values of the register-set per
* dlane.
*/
for (i = 0; i < N_CSI_RX_FE_CTRL_DLANES[ID]; i++) {
ia_css_print("CSI RX FE STATE Controller %d DLANE ID %d termen 0x%x \n", ID, i, state->dlane[i].termen);
ia_css_print("CSI RX FE STATE Controller %d DLANE ID %d settle 0x%x \n", ID, i, state->dlane[i].settle);
ia_css_print("CSI RX FE STATE Controller %d DLANE ID %d termen 0x%x\n", ID, i, state->dlane[i].termen);
ia_css_print("CSI RX FE STATE Controller %d DLANE ID %d settle 0x%x\n", ID, i, state->dlane[i].settle);
}
}
@ -122,7 +120,7 @@ static inline void csi_rx_be_ctrl_get_state(
const csi_rx_backend_ID_t ID,
csi_rx_be_ctrl_state_t *state)
{
uint32_t i;
u32 i;
state->enable =
csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_ENABLE_REG_IDX);
@ -130,10 +128,10 @@ static inline void csi_rx_be_ctrl_get_state(
state->status =
csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_STATUS_REG_IDX);
for(i = 0; i <N_CSI_RX_BE_MIPI_COMP_FMT_REG ; i++) {
for (i = 0; i < N_CSI_RX_BE_MIPI_COMP_FMT_REG ; i++) {
state->comp_format_reg[i] =
csi_rx_be_ctrl_reg_load(ID,
_HRT_MIPI_BACKEND_COMP_FORMAT_REG0_IDX+i);
csi_rx_be_ctrl_reg_load(ID,
_HRT_MIPI_BACKEND_COMP_FORMAT_REG0_IDX + i);
}
state->raw16 =
@ -152,8 +150,8 @@ static inline void csi_rx_be_ctrl_get_state(
state->custom_mode_data_state =
csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_DATA_STATE_REG_IDX);
for(i = 0; i <N_CSI_RX_BE_MIPI_CUSTOM_PEC ; i++) {
state->pec[i] =
for (i = 0; i < N_CSI_RX_BE_MIPI_CUSTOM_PEC ; i++) {
state->pec[i] =
csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P0_REG_IDX + i);
}
state->custom_mode_valid_eop_config =
@ -185,36 +183,37 @@ static inline void csi_rx_be_ctrl_dump_state(
const csi_rx_backend_ID_t ID,
csi_rx_be_ctrl_state_t *state)
{
uint32_t i;
u32 i;
ia_css_print("CSI RX BE STATE Controller %d Enable 0x%x \n", ID, state->enable);
ia_css_print("CSI RX BE STATE Controller %d Status 0x%x \n", ID, state->status);
ia_css_print("CSI RX BE STATE Controller %d Enable 0x%x\n", ID, state->enable);
ia_css_print("CSI RX BE STATE Controller %d Status 0x%x\n", ID, state->status);
for(i = 0; i <N_CSI_RX_BE_MIPI_COMP_FMT_REG ; i++) {
ia_css_print("CSI RX BE STATE Controller %d comp format reg vc%d value 0x%x \n", ID, i, state->status);
for (i = 0; i < N_CSI_RX_BE_MIPI_COMP_FMT_REG ; i++) {
ia_css_print("CSI RX BE STATE Controller %d comp format reg vc%d value 0x%x\n", ID, i, state->status);
}
ia_css_print("CSI RX BE STATE Controller %d RAW16 0x%x \n", ID, state->raw16);
ia_css_print("CSI RX BE STATE Controller %d RAW18 0x%x \n", ID, state->raw18);
ia_css_print("CSI RX BE STATE Controller %d Force RAW8 0x%x \n", ID, state->force_raw8);
ia_css_print("CSI RX BE STATE Controller %d IRQ state 0x%x \n", ID, state->irq_status);
ia_css_print("CSI RX BE STATE Controller %d RAW16 0x%x\n", ID, state->raw16);
ia_css_print("CSI RX BE STATE Controller %d RAW18 0x%x\n", ID, state->raw18);
ia_css_print("CSI RX BE STATE Controller %d Force RAW8 0x%x\n", ID, state->force_raw8);
ia_css_print("CSI RX BE STATE Controller %d IRQ state 0x%x\n", ID, state->irq_status);
#if 0 /* ToDo:Getting device access error for this register */
for(i = 0; i <N_CSI_RX_BE_MIPI_CUSTOM_PEC ; i++) {
ia_css_print("CSI RX BE STATE Controller %d PEC ID %d custom pec 0x%x \n", ID, i, state->pec[i]);
for (i = 0; i < N_CSI_RX_BE_MIPI_CUSTOM_PEC ; i++) {
ia_css_print("CSI RX BE STATE Controller %d PEC ID %d custom pec 0x%x\n", ID, i, state->pec[i]);
}
#endif
ia_css_print("CSI RX BE STATE Controller %d Global LUT disregard reg 0x%x \n", ID, state->global_lut_disregard_reg);
ia_css_print("CSI RX BE STATE Controller %d packet stall reg 0x%x \n", ID, state->packet_status_stall);
ia_css_print("CSI RX BE STATE Controller %d Global LUT disregard reg 0x%x\n", ID, state->global_lut_disregard_reg);
ia_css_print("CSI RX BE STATE Controller %d packet stall reg 0x%x\n", ID, state->packet_status_stall);
/*
* Get the values of the register-set per
* lut.
*/
for (i = 0; i < N_SHORT_PACKET_LUT_ENTRIES[ID]; i++) {
ia_css_print("CSI RX BE STATE Controller ID %d Short packat entry %d shart packet lut id 0x%x \n", ID, i, state->short_packet_lut_entry[i]);
ia_css_print("CSI RX BE STATE Controller ID %d Short packat entry %d shart packet lut id 0x%x\n", ID, i, state->short_packet_lut_entry[i]);
}
for (i = 0; i < N_LONG_PACKET_LUT_ENTRIES[ID]; i++) {
ia_css_print("CSI RX BE STATE Controller ID %d Long packat entry %d Long packet lut id 0x%x \n", ID, i, state->long_packet_lut_entry[i]);
ia_css_print("CSI RX BE STATE Controller ID %d Long packat entry %d Long packet lut id 0x%x\n", ID, i, state->long_packet_lut_entry[i]);
}
}
/* end of NCI */
/*****************************************************
*
@ -231,10 +230,9 @@ static inline hrt_data csi_rx_fe_ctrl_reg_load(
{
assert(ID < N_CSI_RX_FRONTEND_ID);
assert(CSI_RX_FE_CTRL_BASE[ID] != (hrt_address)-1);
return ia_css_device_load_uint32(CSI_RX_FE_CTRL_BASE[ID] + reg*sizeof(hrt_data));
return ia_css_device_load_uint32(CSI_RX_FE_CTRL_BASE[ID] + reg * sizeof(hrt_data));
}
/**
* @brief Store a value to the register.
* Refer to "ibuf_ctrl_public.h" for details.
@ -247,8 +245,9 @@ static inline void csi_rx_fe_ctrl_reg_store(
assert(ID < N_CSI_RX_FRONTEND_ID);
assert(CSI_RX_FE_CTRL_BASE[ID] != (hrt_address)-1);
ia_css_device_store_uint32(CSI_RX_FE_CTRL_BASE[ID] + reg*sizeof(hrt_data), value);
ia_css_device_store_uint32(CSI_RX_FE_CTRL_BASE[ID] + reg * sizeof(hrt_data), value);
}
/**
* @brief Load the register value.
* Refer to "csi_rx_public.h" for details.
@ -259,10 +258,9 @@ static inline hrt_data csi_rx_be_ctrl_reg_load(
{
assert(ID < N_CSI_RX_BACKEND_ID);
assert(CSI_RX_BE_CTRL_BASE[ID] != (hrt_address)-1);
return ia_css_device_load_uint32(CSI_RX_BE_CTRL_BASE[ID] + reg*sizeof(hrt_data));
return ia_css_device_load_uint32(CSI_RX_BE_CTRL_BASE[ID] + reg * sizeof(hrt_data));
}
/**
* @brief Store a value to the register.
* Refer to "ibuf_ctrl_public.h" for details.
@ -275,8 +273,9 @@ static inline void csi_rx_be_ctrl_reg_store(
assert(ID < N_CSI_RX_BACKEND_ID);
assert(CSI_RX_BE_CTRL_BASE[ID] != (hrt_address)-1);
ia_css_device_store_uint32(CSI_RX_BE_CTRL_BASE[ID] + reg*sizeof(hrt_data), value);
ia_css_device_store_uint32(CSI_RX_BE_CTRL_BASE[ID] + reg * sizeof(hrt_data), value);
}
/* end of DLI */
#endif /* __CSI_RX_PRIVATE_H_INCLUDED__ */

2
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/ibuf_ctrl.c
View File

@ -15,7 +15,7 @@
#include <type_support.h>
#include "system_global.h"
const uint32_t N_IBUF_CTRL_PROCS[N_IBUF_CTRL_ID] = {
const u32 N_IBUF_CTRL_PROCS[N_IBUF_CTRL_ID] = {
8, /* IBUF_CTRL0_ID supports at most 8 processes */
4, /* IBUF_CTRL1_ID supports at most 4 processes */
4 /* IBUF_CTRL2_ID supports at most 4 processes */

19
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/ibuf_ctrl_private.h
View File

@ -22,7 +22,6 @@
#include "assert_support.h" /* assert */
#include "print_support.h" /* print */
/*****************************************************
*
* Native command interface (NCI).
@ -36,7 +35,7 @@ STORAGE_CLASS_IBUF_CTRL_C void ibuf_ctrl_get_state(
const ibuf_ctrl_ID_t ID,
ibuf_ctrl_state_t *state)
{
uint32_t i;
u32 i;
state->recalc_words =
ibuf_ctrl_reg_load(ID, _IBUF_CNTRL_RECALC_WORDS_STATUS);
@ -51,7 +50,7 @@ STORAGE_CLASS_IBUF_CTRL_C void ibuf_ctrl_get_state(
ibuf_ctrl_get_proc_state(
ID,
i,
&(state->proc_state[i]));
&state->proc_state[i]);
}
}
@ -61,7 +60,7 @@ STORAGE_CLASS_IBUF_CTRL_C void ibuf_ctrl_get_state(
*/
STORAGE_CLASS_IBUF_CTRL_C void ibuf_ctrl_get_proc_state(
const ibuf_ctrl_ID_t ID,
const uint32_t proc_id,
const u32 proc_id,
ibuf_ctrl_proc_state_t *state)
{
hrt_address reg_bank_offset;
@ -147,6 +146,7 @@ STORAGE_CLASS_IBUF_CTRL_C void ibuf_ctrl_get_proc_state(
state->isp_sync_state =
ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_ISP_SYNC_STATE);
}
/**
* @brief Dump the ibuf-controller state.
* Refer to "ibuf_ctrl_public.h" for details.
@ -155,7 +155,8 @@ STORAGE_CLASS_IBUF_CTRL_C void ibuf_ctrl_dump_state(
const ibuf_ctrl_ID_t ID,
ibuf_ctrl_state_t *state)
{
uint32_t i;
u32 i;
ia_css_print("IBUF controller ID %d recalculate words 0x%x\n", ID, state->recalc_words);
ia_css_print("IBUF controller ID %d arbiters 0x%x\n", ID, state->arbiters);
@ -192,6 +193,7 @@ STORAGE_CLASS_IBUF_CTRL_C void ibuf_ctrl_dump_state(
ia_css_print("IBUF controller ID %d Process ID %d isp_sync_state 0x%x\n", ID, i, state->proc_state[i].isp_sync_state);
}
}
/* end of NCI */
/*****************************************************
@ -209,10 +211,9 @@ STORAGE_CLASS_IBUF_CTRL_C hrt_data ibuf_ctrl_reg_load(
{
assert(ID < N_IBUF_CTRL_ID);
assert(IBUF_CTRL_BASE[ID] != (hrt_address)-1);
return ia_css_device_load_uint32(IBUF_CTRL_BASE[ID] + reg*sizeof(hrt_data));
return ia_css_device_load_uint32(IBUF_CTRL_BASE[ID] + reg * sizeof(hrt_data));
}
/**
* @brief Store a value to the register.
* Refer to "ibuf_ctrl_public.h" for details.
@ -225,9 +226,9 @@ STORAGE_CLASS_IBUF_CTRL_C void ibuf_ctrl_reg_store(
assert(ID < N_IBUF_CTRL_ID);
assert(IBUF_CTRL_BASE[ID] != (hrt_address)-1);
ia_css_device_store_uint32(IBUF_CTRL_BASE[ID] + reg*sizeof(hrt_data), value);
ia_css_device_store_uint32(IBUF_CTRL_BASE[ID] + reg * sizeof(hrt_data), value);
}
/* end of DLI */
#endif /* __IBUF_CTRL_PRIVATE_H_INCLUDED__ */

29
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/input_system_private.h
View File

@ -21,7 +21,7 @@ STORAGE_CLASS_INPUT_SYSTEM_C input_system_err_t input_system_get_state(
const input_system_ID_t ID,
input_system_state_t *state)
{
uint32_t i;
u32 i;
(void)(ID);
@ -29,40 +29,40 @@ STORAGE_CLASS_INPUT_SYSTEM_C input_system_err_t input_system_get_state(
for (i = 0; i < N_CSI_RX_FRONTEND_ID; i++) {
csi_rx_fe_ctrl_get_state(
(csi_rx_frontend_ID_t)i,
&(state->csi_rx_fe_ctrl_state[i]));
&state->csi_rx_fe_ctrl_state[i]);
}
/* get the states of all CIS RX backend devices */
for (i = 0; i < N_CSI_RX_BACKEND_ID; i++) {
csi_rx_be_ctrl_get_state(
(csi_rx_backend_ID_t)i,
&(state->csi_rx_be_ctrl_state[i]));
&state->csi_rx_be_ctrl_state[i]);
}
/* get the states of all pixelgen devices */
for (i = 0; i < N_PIXELGEN_ID; i++) {
pixelgen_ctrl_get_state(
(pixelgen_ID_t)i,
&(state->pixelgen_ctrl_state[i]));
&state->pixelgen_ctrl_state[i]);
}
/* get the states of all stream2mmio devices */
for (i = 0; i < N_STREAM2MMIO_ID; i++) {
stream2mmio_get_state(
(stream2mmio_ID_t)i,
&(state->stream2mmio_state[i]));
&state->stream2mmio_state[i]);
}
/* get the states of all ibuf-controller devices */
for (i = 0; i < N_IBUF_CTRL_ID; i++) {
ibuf_ctrl_get_state(
(ibuf_ctrl_ID_t)i,
&(state->ibuf_ctrl_state[i]));
&state->ibuf_ctrl_state[i]);
}
/* get the states of all isys irq controllers */
for (i = 0; i < N_ISYS_IRQ_ID; i++) {
isys_irqc_state_get((isys_irq_ID_t)i, &(state->isys_irqc_state[i]));
isys_irqc_state_get((isys_irq_ID_t)i, &state->isys_irqc_state[i]);
}
/* TODO: get the states of all ISYS2401 DMA devices */
@ -71,11 +71,12 @@ STORAGE_CLASS_INPUT_SYSTEM_C input_system_err_t input_system_get_state(
return INPUT_SYSTEM_ERR_NO_ERROR;
}
STORAGE_CLASS_INPUT_SYSTEM_C void input_system_dump_state(
const input_system_ID_t ID,
input_system_state_t *state)
{
uint32_t i;
u32 i;
(void)(ID);
@ -83,40 +84,40 @@ STORAGE_CLASS_INPUT_SYSTEM_C void input_system_dump_state(
for (i = 0; i < N_CSI_RX_FRONTEND_ID; i++) {
csi_rx_fe_ctrl_dump_state(
(csi_rx_frontend_ID_t)i,
&(state->csi_rx_fe_ctrl_state[i]));
&state->csi_rx_fe_ctrl_state[i]);
}
/* dump the states of all CIS RX backend devices */
for (i = 0; i < N_CSI_RX_BACKEND_ID; i++) {
csi_rx_be_ctrl_dump_state(
(csi_rx_backend_ID_t)i,
&(state->csi_rx_be_ctrl_state[i]));
&state->csi_rx_be_ctrl_state[i]);
}
/* dump the states of all pixelgen devices */
for (i = 0; i < N_PIXELGEN_ID; i++) {
pixelgen_ctrl_dump_state(
(pixelgen_ID_t)i,
&(state->pixelgen_ctrl_state[i]));
&state->pixelgen_ctrl_state[i]);
}
/* dump the states of all st2mmio devices */
for (i = 0; i < N_STREAM2MMIO_ID; i++) {
stream2mmio_dump_state(
(stream2mmio_ID_t)i,
&(state->stream2mmio_state[i]));
&state->stream2mmio_state[i]);
}
/* dump the states of all ibuf-controller devices */
for (i = 0; i < N_IBUF_CTRL_ID; i++) {
ibuf_ctrl_dump_state(
(ibuf_ctrl_ID_t)i,
&(state->ibuf_ctrl_state[i]));
&state->ibuf_ctrl_state[i]);
}
/* dump the states of all isys irq controllers */
for (i = 0; i < N_ISYS_IRQ_ID; i++) {
isys_irqc_state_dump((isys_irq_ID_t)i, &(state->isys_irqc_state[i]));
isys_irqc_state_dump((isys_irq_ID_t)i, &state->isys_irqc_state[i]);
}
/* TODO: dump the states of all ISYS2401 DMA devices */

5
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_dma_private.h
View File

@ -22,7 +22,6 @@
#include "dma_v2_defs.h"
#include "print_support.h"
STORAGE_CLASS_ISYS2401_DMA_C void isys2401_dma_reg_store(
const isys2401_dma_ID_t dma_id,
const unsigned int reg,
@ -31,7 +30,7 @@ STORAGE_CLASS_ISYS2401_DMA_C void isys2401_dma_reg_store(
unsigned int reg_loc;
assert(dma_id < N_ISYS2401_DMA_ID);
assert(ISYS2401_DMA_BASE[dma_id] != (hrt_address)-1);
assert(ISYS2401_DMA_BASE[dma_id] != (hrt_address) - 1);
reg_loc = ISYS2401_DMA_BASE[dma_id] + (reg * sizeof(hrt_data));
@ -47,7 +46,7 @@ STORAGE_CLASS_ISYS2401_DMA_C hrt_data isys2401_dma_reg_load(
hrt_data value;
assert(dma_id < N_ISYS2401_DMA_ID);
assert(ISYS2401_DMA_BASE[dma_id] != (hrt_address)-1);
assert(ISYS2401_DMA_BASE[dma_id] != (hrt_address) - 1);
reg_loc = ISYS2401_DMA_BASE[dma_id] + (reg * sizeof(hrt_data));

4
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_irq_private.h
View File

@ -52,9 +52,7 @@ STORAGE_CLASS_ISYS2401_IRQ_C void isys_irqc_state_dump(
const isys_irqc_state_t *state)
{
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
"isys irq controller id %d"
"\n\tstatus:0x%x\n\tedge:0x%x\n\tmask:0x%x"
"\n\tenable:0x%x\n\tlevel_not_pulse:0x%x\n",
"isys irq controller id %d\n\tstatus:0x%x\n\tedge:0x%x\n\tmask:0x%x\n\tenable:0x%x\n\tlevel_not_pulse:0x%x\n",
isys_irqc_id,
state->status, state->edge, state->mask, state->enable, state->level_no);
}

2
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_stream2mmio_local.h
View File

@ -31,6 +31,6 @@ struct stream2mmio_sid_state_s {
};
struct stream2mmio_state_s {
stream2mmio_sid_state_t sid_state[N_STREAM2MMIO_SID_ID];
stream2mmio_sid_state_t sid_state[N_STREAM2MMIO_SID_ID];
};
#endif /* __ISYS_STREAM2MMIO_LOCAL_H_INCLUDED__ */

13
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_stream2mmio_private.h
View File

@ -50,7 +50,7 @@ STORAGE_CLASS_STREAM2MMIO_C void stream2mmio_get_state(
* stream2mmio-controller sids.
*/
for (i = STREAM2MMIO_SID0_ID; i < N_STREAM2MMIO_SID_PROCS[ID]; i++) {
stream2mmio_get_sid_state(ID, i, &(state->sid_state[i]));
stream2mmio_get_sid_state(ID, i, &state->sid_state[i]);
}
}
@ -63,7 +63,6 @@ STORAGE_CLASS_STREAM2MMIO_C void stream2mmio_get_sid_state(
const stream2mmio_sid_ID_t sid_id,
stream2mmio_sid_state_t *state)
{
state->rcv_ack =
stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_ACKNOWLEDGE_REG_ID);
@ -84,7 +83,6 @@ STORAGE_CLASS_STREAM2MMIO_C void stream2mmio_get_sid_state(
state->block_when_no_cmd =
stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_BLOCK_WHEN_NO_CMD_REG_ID);
}
/**
@ -101,8 +99,8 @@ STORAGE_CLASS_STREAM2MMIO_C void stream2mmio_print_sid_state(
ia_css_print("\t \t Strides 0x%x\n", state->strides);
ia_css_print("\t \t Num Items 0x%x\n", state->num_items);
ia_css_print("\t \t block when no cmd 0x%x\n", state->block_when_no_cmd);
}
/**
* @brief Dump the ibuf-controller state.
* Refer to "stream2mmio_public.h" for details.
@ -119,9 +117,10 @@ STORAGE_CLASS_STREAM2MMIO_C void stream2mmio_dump_state(
*/
for (i = STREAM2MMIO_SID0_ID; i < N_STREAM2MMIO_SID_PROCS[ID]; i++) {
ia_css_print("StREAM2MMIO ID %d SID %d\n", ID, i);
stream2mmio_print_sid_state(&(state->sid_state[i]));
stream2mmio_print_sid_state(&state->sid_state[i]);
}
}
/* end of NCI */
/*****************************************************
@ -138,7 +137,7 @@ STORAGE_CLASS_STREAM2MMIO_C hrt_data stream2mmio_reg_load(
const stream2mmio_sid_ID_t sid_id,
const uint32_t reg_idx)
{
uint32_t reg_bank_offset;
u32 reg_bank_offset;
assert(ID < N_STREAM2MMIO_ID);
@ -147,7 +146,6 @@ STORAGE_CLASS_STREAM2MMIO_C hrt_data stream2mmio_reg_load(
(reg_bank_offset + reg_idx) * sizeof(hrt_data));
}
/**
* @brief Store a value to the register.
* Refer to "stream2mmio_public.h" for details.
@ -163,6 +161,7 @@ STORAGE_CLASS_STREAM2MMIO_C void stream2mmio_reg_store(
ia_css_device_store_uint32(STREAM2MMIO_CTRL_BASE[ID] +
reg * sizeof(hrt_data), value);
}
/* end of DLI */
#endif /* __ISYS_STREAM2MMIO_PRIVATE_H_INCLUDED__ */

66
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/pixelgen_private.h
View File

@ -20,7 +20,6 @@
#include "device_access.h" /* ia_css_device_load_uint32 */
#include "assert_support.h" /* assert */
/*****************************************************
*
* Native command interface (NCI).
@ -34,7 +33,6 @@ STORAGE_CLASS_PIXELGEN_C void pixelgen_ctrl_get_state(
const pixelgen_ID_t ID,
pixelgen_ctrl_state_t *state)
{
state->com_enable =
pixelgen_ctrl_reg_load(ID, _PXG_COM_ENABLE_REG_IDX);
state->prbs_rstval0 =
@ -90,6 +88,7 @@ STORAGE_CLASS_PIXELGEN_C void pixelgen_ctrl_get_state(
state->tpg_b2 =
pixelgen_ctrl_reg_load(ID, _PXG_TPG_B2_REG_IDX);
}
/**
* @brief Dump the pixelgen state.
* Refer to "pixelgen_public.h" for details.
@ -98,34 +97,35 @@ STORAGE_CLASS_PIXELGEN_C void pixelgen_ctrl_dump_state(
const pixelgen_ID_t ID,
pixelgen_ctrl_state_t *state)
{
ia_css_print("Pixel Generator ID %d Enable 0x%x \n", ID, state->com_enable);
ia_css_print("Pixel Generator ID %d PRBS reset vlue 0 0x%x \n", ID, state->prbs_rstval0);
ia_css_print("Pixel Generator ID %d PRBS reset vlue 1 0x%x \n", ID, state->prbs_rstval1);
ia_css_print("Pixel Generator ID %d SYNC SID 0x%x \n", ID, state->syng_sid);
ia_css_print("Pixel Generator ID %d syng free run 0x%x \n", ID, state->syng_free_run);
ia_css_print("Pixel Generator ID %d syng pause 0x%x \n", ID, state->syng_pause);
ia_css_print("Pixel Generator ID %d syng no of frames 0x%x \n", ID, state->syng_nof_frames);
ia_css_print("Pixel Generator ID %d syng no of pixels 0x%x \n", ID, state->syng_nof_pixels);
ia_css_print("Pixel Generator ID %d syng no of line 0x%x \n", ID, state->syng_nof_line);
ia_css_print("Pixel Generator ID %d syng hblank cyc 0x%x \n", ID, state->syng_hblank_cyc);
ia_css_print("Pixel Generator ID %d syng vblank cyc 0x%x \n", ID, state->syng_vblank_cyc);
ia_css_print("Pixel Generator ID %d syng stat hcnt 0x%x \n", ID, state->syng_stat_hcnt);
ia_css_print("Pixel Generator ID %d syng stat vcnt 0x%x \n", ID, state->syng_stat_vcnt);
ia_css_print("Pixel Generator ID %d syng stat fcnt 0x%x \n", ID, state->syng_stat_fcnt);
ia_css_print("Pixel Generator ID %d syng stat done 0x%x \n", ID, state->syng_stat_done);
ia_css_print("Pixel Generator ID %d tpg modee 0x%x \n", ID, state->tpg_mode);
ia_css_print("Pixel Generator ID %d tpg hcnt mask 0x%x \n", ID, state->tpg_hcnt_mask);
ia_css_print("Pixel Generator ID %d tpg hcnt mask 0x%x \n", ID, state->tpg_hcnt_mask);
ia_css_print("Pixel Generator ID %d tpg xycnt mask 0x%x \n", ID, state->tpg_xycnt_mask);
ia_css_print("Pixel Generator ID %d tpg hcnt delta 0x%x \n", ID, state->tpg_hcnt_delta);
ia_css_print("Pixel Generator ID %d tpg vcnt delta 0x%x \n", ID, state->tpg_vcnt_delta);
ia_css_print("Pixel Generator ID %d tpg r1 0x%x \n", ID, state->tpg_r1);
ia_css_print("Pixel Generator ID %d tpg g1 0x%x \n", ID, state->tpg_g1);
ia_css_print("Pixel Generator ID %d tpg b1 0x%x \n", ID, state->tpg_b1);
ia_css_print("Pixel Generator ID %d tpg r2 0x%x \n", ID, state->tpg_r2);
ia_css_print("Pixel Generator ID %d tpg g2 0x%x \n", ID, state->tpg_g2);
ia_css_print("Pixel Generator ID %d tpg b2 0x%x \n", ID, state->tpg_b2);
ia_css_print("Pixel Generator ID %d Enable 0x%x\n", ID, state->com_enable);
ia_css_print("Pixel Generator ID %d PRBS reset vlue 0 0x%x\n", ID, state->prbs_rstval0);
ia_css_print("Pixel Generator ID %d PRBS reset vlue 1 0x%x\n", ID, state->prbs_rstval1);
ia_css_print("Pixel Generator ID %d SYNC SID 0x%x\n", ID, state->syng_sid);
ia_css_print("Pixel Generator ID %d syng free run 0x%x\n", ID, state->syng_free_run);
ia_css_print("Pixel Generator ID %d syng pause 0x%x\n", ID, state->syng_pause);
ia_css_print("Pixel Generator ID %d syng no of frames 0x%x\n", ID, state->syng_nof_frames);
ia_css_print("Pixel Generator ID %d syng no of pixels 0x%x\n", ID, state->syng_nof_pixels);
ia_css_print("Pixel Generator ID %d syng no of line 0x%x\n", ID, state->syng_nof_line);
ia_css_print("Pixel Generator ID %d syng hblank cyc 0x%x\n", ID, state->syng_hblank_cyc);
ia_css_print("Pixel Generator ID %d syng vblank cyc 0x%x\n", ID, state->syng_vblank_cyc);
ia_css_print("Pixel Generator ID %d syng stat hcnt 0x%x\n", ID, state->syng_stat_hcnt);
ia_css_print("Pixel Generator ID %d syng stat vcnt 0x%x\n", ID, state->syng_stat_vcnt);
ia_css_print("Pixel Generator ID %d syng stat fcnt 0x%x\n", ID, state->syng_stat_fcnt);
ia_css_print("Pixel Generator ID %d syng stat done 0x%x\n", ID, state->syng_stat_done);
ia_css_print("Pixel Generator ID %d tpg modee 0x%x\n", ID, state->tpg_mode);
ia_css_print("Pixel Generator ID %d tpg hcnt mask 0x%x\n", ID, state->tpg_hcnt_mask);
ia_css_print("Pixel Generator ID %d tpg hcnt mask 0x%x\n", ID, state->tpg_hcnt_mask);
ia_css_print("Pixel Generator ID %d tpg xycnt mask 0x%x\n", ID, state->tpg_xycnt_mask);
ia_css_print("Pixel Generator ID %d tpg hcnt delta 0x%x\n", ID, state->tpg_hcnt_delta);
ia_css_print("Pixel Generator ID %d tpg vcnt delta 0x%x\n", ID, state->tpg_vcnt_delta);
ia_css_print("Pixel Generator ID %d tpg r1 0x%x\n", ID, state->tpg_r1);
ia_css_print("Pixel Generator ID %d tpg g1 0x%x\n", ID, state->tpg_g1);
ia_css_print("Pixel Generator ID %d tpg b1 0x%x\n", ID, state->tpg_b1);
ia_css_print("Pixel Generator ID %d tpg r2 0x%x\n", ID, state->tpg_r2);
ia_css_print("Pixel Generator ID %d tpg g2 0x%x\n", ID, state->tpg_g2);
ia_css_print("Pixel Generator ID %d tpg b2 0x%x\n", ID, state->tpg_b2);
}
/* end of NCI */
/*****************************************************
*
@ -141,11 +141,10 @@ STORAGE_CLASS_PIXELGEN_C hrt_data pixelgen_ctrl_reg_load(
const hrt_address reg)
{
assert(ID < N_PIXELGEN_ID);
assert(PIXELGEN_CTRL_BASE[ID] != (hrt_address)-1);
return ia_css_device_load_uint32(PIXELGEN_CTRL_BASE[ID] + reg*sizeof(hrt_data));
assert(PIXELGEN_CTRL_BASE[ID] != (hrt_address) - 1);
return ia_css_device_load_uint32(PIXELGEN_CTRL_BASE[ID] + reg * sizeof(hrt_data));
}
/**
* @brief Store a value to the register.
* Refer to "pixelgen_ctrl_public.h" for details.
@ -158,7 +157,8 @@ STORAGE_CLASS_PIXELGEN_C void pixelgen_ctrl_reg_store(
assert(ID < N_PIXELGEN_ID);
assert(PIXELGEN_CTRL_BASE[ID] != (hrt_address)-1);
ia_css_device_store_uint32(PIXELGEN_CTRL_BASE[ID] + reg*sizeof(hrt_data), value);
ia_css_device_store_uint32(PIXELGEN_CTRL_BASE[ID] + reg * sizeof(hrt_data), value);
}
/* end of DLI */
#endif /* __PIXELGEN_PRIVATE_H_INCLUDED__ */

8
drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/system_local.h
View File

@ -135,7 +135,6 @@ static const hrt_address GPIO_BASE[N_GPIO_ID] = {
static const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID] = {
0x0000000000000100ULL};
/* INPUT_FORMATTER */
static const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID] = {
0x0000000000030000ULL,
@ -180,18 +179,21 @@ static const hrt_address CSI_RX_FE_CTRL_BASE[N_CSI_RX_FRONTEND_ID] = {
0x00000000000C2400ULL, /* csi fe controller B */
0x00000000000C4400ULL /* csi fe controller C */
};
/* CSI BE, part of the Input System 2401 */
static const hrt_address CSI_RX_BE_CTRL_BASE[N_CSI_RX_BACKEND_ID] = {
0x00000000000C0800ULL, /* csi be controller A */
0x00000000000C2800ULL, /* csi be controller B */
0x00000000000C4800ULL /* csi be controller C */
};
/* PIXEL Generator, part of the Input System 2401 */
static const hrt_address PIXELGEN_CTRL_BASE[N_PIXELGEN_ID] = {
0x00000000000C1000ULL, /* pixel gen controller A */
0x00000000000C3000ULL, /* pixel gen controller B */
0x00000000000C5000ULL /* pixel gen controller C */
};
/* Stream2MMIO, part of the Input System 2401 */
static const hrt_address STREAM2MMIO_CTRL_BASE[N_STREAM2MMIO_ID] = {
0x00000000000C0C00ULL, /* stream2mmio controller A */
@ -295,7 +297,6 @@ static const hrt_address GPIO_BASE[N_GPIO_ID] = {
static const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID] = {
0x00000100UL};
/* INPUT_FORMATTER */
static const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID] = {
0x00030000UL,
@ -340,18 +341,21 @@ static const hrt_address CSI_RX_FE_CTRL_BASE[N_CSI_RX_FRONTEND_ID] = {
0x000C2400UL, /* csi fe controller B */
0x000C4400UL /* csi fe controller C */
};
/* CSI BE, part of the Input System 2401 */
static const hrt_address CSI_RX_FE_CTRL_BASE[N_CSI_RX_BACKEND_ID] = {
0x000C0800UL, /* csi be controller A */
0x000C2800UL, /* csi be controller B */
0x000C4800UL /* csi be controller C */
};
/* PIXEL Generator, part of the Input System 2401 */
static const hrt_address PIXELGEN_CTRL_BASE[N_PIXELGEN_ID] = {
0x000C1000UL, /* pixel gen controller A */
0x000C3000UL, /* pixel gen controller B */
0x000C5000UL /* pixel gen controller C */
};
/* Stream2MMIO, part of the Input System 2401 */
static const hrt_address STREAM2MMIO_CTRL_BASE[N_STREAM2MMIO_ID] = {
0x000C0C00UL, /* stream2mmio controller A */

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