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devicetree/bindings: correct possessive "its" typos
Correct all uses of "it's" that are meant to be possessive "its". Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Jonathan Corbet <corbet@lwn.net> Cc: Rob Herring <robh+dt@kernel.org> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220801025221.30563-1-rdunlap@infradead.org
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11 changed files with 11 additions and 11 deletions
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@ -78,7 +78,7 @@ Required properties:
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- #clock-cells : from common clock binding; shall be set to 1 (multiple clock
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outputs).
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- clocks : must be set to the parent's phandle. it's could be output clocks of
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- clocks : must be set to the parent's phandle. it could be output clocks of
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a quadsfs or/and a pll or/and clk_sysin (up to 7 clocks)
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- clock-output-names : List of strings used to name the clock outputs.
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@ -6,7 +6,7 @@ functional clock but can be configured to provide different clocks.
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ATL can maintain a clock averages to some desired frequency based on the bws/aws
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signals - can compensate the drift between the two ws signal.
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In order to provide the support for ATL and it's output clocks (which can be used
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In order to provide the support for ATL and its output clocks (which can be used
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internally within the SoC or external components) two sets of bindings is needed:
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Clock tree binding:
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@ -57,7 +57,7 @@ patternProperties:
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Configures bypassing the individual voltage input attenuator. If
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set to 1 the attenuator is bypassed if set to 0 the attenuator is
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not bypassed. If the property is absent then the attenuator
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retains it's configuration from the bios/bootloader.
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retains its configuration from the bios/bootloader.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1]
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@ -6,7 +6,7 @@ Required properties:
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- interrupts : interrupt specification for the ektf2127 interrupt
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- power-gpios : GPIO specification for the pin connected to the
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ektf2127's wake input. This needs to be driven high
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to take ektf2127 out of it's low power state
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to take ektf2127 out of its low power state
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For additional optional properties see: touchscreen.txt
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@ -74,7 +74,7 @@ properties:
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rohm,enable-hidden-gpo:
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description: |
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The BD71815 has undocumented GPO at pin E5. Pin is marked as GND at the
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data-sheet as it's location in the middle of GND pins makes it hard to
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data-sheet as its location in the middle of GND pins makes it hard to
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use on PCB. If your board has managed to use this pin you can enable the
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second GPO by defining this property. Dont enable this if you are unsure
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about how the E5 pin is connected on your board.
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@ -2,7 +2,7 @@ Lantiq XWAY SoC RCU binding
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===========================
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This binding describes the RCU (reset controller unit) multifunction device,
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where each sub-device has it's own set of registers.
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where each sub-device has its own set of registers.
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The RCU register range is used for multiple purposes. Mostly one device
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uses one or multiple register exclusively, but for some registers some
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@ -15,7 +15,7 @@ Required properties:
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"rx_desc": MSGDMA Rx dispatcher descriptor space region
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"rx_resp": MSGDMA Rx dispatcher response space region
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"s1": SGDMA descriptor memory
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- interrupts: Should contain the TSE interrupts and it's mode.
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- interrupts: Should contain the TSE interrupts and its mode.
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- interrupt-names: Should contain the interrupt names
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"rx_irq": xDMA Rx dispatcher interrupt
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"tx_irq": xDMA Tx dispatcher interrupt
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@ -20,7 +20,7 @@ Required properties:
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- active_slave : Specifies the slave to use for time stamping,
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ethtool and SIOCGMIIPHY
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- cpsw-phy-sel : Specifies the phandle to the CPSW phy mode selection
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device. See also cpsw-phy-sel.txt for it's binding.
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device. See also cpsw-phy-sel.txt for its binding.
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Note that in legacy cases cpsw-phy-sel may be
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a child device instead of a phandle
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(DEPRECATED, use phys property instead).
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@ -172,7 +172,7 @@ Interrupt controller (fsl,mpc5200-pic) node
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The mpc5200 pic binding splits hardware IRQ numbers into two levels. The
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split reflects the layout of the PIC hardware itself, which groups
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interrupts into one of three groups; CRIT, MAIN or PERP. Also, the
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Bestcomm dma engine has it's own set of interrupt sources which are
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Bestcomm dma engine has its own set of interrupt sources which are
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cascaded off of peripheral interrupt 0, which the driver interprets as a
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fourth group, SDMA.
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@ -13,7 +13,7 @@ description:
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This binding describes the hardware component responsible for side channel
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requests to the always-on subsystem (AOSS), used for certain power management
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requests that is not handled by the standard RPMh interface. Each client in the
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SoC has it's own block of message RAM and IRQ for communication with the AOSS.
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SoC has its own block of message RAM and IRQ for communication with the AOSS.
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The protocol used to communicate in the message RAM is known as Qualcomm
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Messaging Protocol (QMP)
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@ -2,7 +2,7 @@
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DA9055 provides Audio CODEC support (I2C only).
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The Audio CODEC device in DA9055 has it's own I2C address which is configurable,
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The Audio CODEC device in DA9055 has its own I2C address which is configurable,
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so the device is instantiated separately from the PMIC (MFD) device.
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For details on accompanying PMIC I2C device, see the following:
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