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synced 2024-08-24 01:41:39 +00:00
ata_piix: drop merged SCR access and use slave_link instead
Now that libata has slave_link, there's no need to keep ugly merged SCR access. Drop it and use slave_link instead. This results in simpler code and much better separate link handling for master and slave. Signed-off-by: Tejun Heo <tj@kernel.org> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
This commit is contained in:
parent
b1c72916ab
commit
be77e43abb
1 changed files with 40 additions and 127 deletions
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@ -887,23 +887,9 @@ static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
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* Serial ATA Index/Data Pair Superset Registers access
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*
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* Beginning from ICH8, there's a sane way to access SCRs using index
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* and data register pair located at BAR5. This creates an
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* interesting problem of mapping two SCRs to one port.
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*
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* Although they have separate SCRs, the master and slave aren't
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* independent enough to be treated as separate links - e.g. softreset
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* resets both. Also, there's no protocol defined for hard resetting
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* singled device sharing the virtual port (no defined way to acquire
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* device signature). This is worked around by merging the SCR values
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* into one sensible value and requesting follow-up SRST after
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* hardreset.
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*
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* SCR merging is perfomed in nibbles which is the unit contents in
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* SCRs are organized. If two values are equal, the value is used.
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* When they differ, merge table which lists precedence of possible
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* values is consulted and the first match or the last entry when
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* nothing matches is used. When there's no merge table for the
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* specific nibble, value from the first port is used.
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* and data register pair located at BAR5 which means that we have
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* separate SCRs for master and slave. This is handled using libata
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* slave_link facility.
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*/
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static const int piix_sidx_map[] = {
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[SCR_STATUS] = 0,
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@ -911,125 +897,38 @@ static const int piix_sidx_map[] = {
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[SCR_CONTROL] = 1,
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};
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static void piix_sidpr_sel(struct ata_device *dev, unsigned int reg)
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static void piix_sidpr_sel(struct ata_link *link, unsigned int reg)
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{
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struct ata_port *ap = dev->link->ap;
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struct ata_port *ap = link->ap;
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struct piix_host_priv *hpriv = ap->host->private_data;
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iowrite32(((ap->port_no * 2 + dev->devno) << 8) | piix_sidx_map[reg],
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iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg],
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hpriv->sidpr + PIIX_SIDPR_IDX);
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}
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static int piix_sidpr_read(struct ata_device *dev, unsigned int reg)
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{
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struct piix_host_priv *hpriv = dev->link->ap->host->private_data;
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piix_sidpr_sel(dev, reg);
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return ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
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}
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static void piix_sidpr_write(struct ata_device *dev, unsigned int reg, u32 val)
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{
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struct piix_host_priv *hpriv = dev->link->ap->host->private_data;
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piix_sidpr_sel(dev, reg);
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iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
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}
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static u32 piix_merge_scr(u32 val0, u32 val1, const int * const *merge_tbl)
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{
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u32 val = 0;
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int i, mi;
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for (i = 0, mi = 0; i < 32 / 4; i++) {
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u8 c0 = (val0 >> (i * 4)) & 0xf;
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u8 c1 = (val1 >> (i * 4)) & 0xf;
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u8 merged = c0;
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const int *cur;
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/* if no merge preference, assume the first value */
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cur = merge_tbl[mi];
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if (!cur)
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goto done;
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mi++;
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/* if two values equal, use it */
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if (c0 == c1)
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goto done;
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/* choose the first match or the last from the merge table */
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while (*cur != -1) {
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if (c0 == *cur || c1 == *cur)
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break;
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cur++;
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}
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if (*cur == -1)
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cur--;
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merged = *cur;
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done:
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val |= merged << (i * 4);
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}
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return val;
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}
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static int piix_sidpr_scr_read(struct ata_link *link,
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unsigned int reg, u32 *val)
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{
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struct ata_port *ap = link->ap;
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const int * const sstatus_merge_tbl[] = {
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/* DET */ (const int []){ 1, 3, 0, 4, 3, -1 },
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/* SPD */ (const int []){ 2, 1, 0, -1 },
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/* IPM */ (const int []){ 6, 2, 1, 0, -1 },
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NULL,
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};
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const int * const scontrol_merge_tbl[] = {
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/* DET */ (const int []){ 1, 0, 4, 0, -1 },
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/* SPD */ (const int []){ 0, 2, 1, 0, -1 },
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/* IPM */ (const int []){ 0, 1, 2, 3, 0, -1 },
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NULL,
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};
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u32 v0, v1;
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struct piix_host_priv *hpriv = link->ap->host->private_data;
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if (reg >= ARRAY_SIZE(piix_sidx_map))
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return -EINVAL;
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if (!(ap->flags & ATA_FLAG_SLAVE_POSS)) {
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*val = piix_sidpr_read(&ap->link.device[0], reg);
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return 0;
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}
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v0 = piix_sidpr_read(&ap->link.device[0], reg);
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v1 = piix_sidpr_read(&ap->link.device[1], reg);
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switch (reg) {
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case SCR_STATUS:
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*val = piix_merge_scr(v0, v1, sstatus_merge_tbl);
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break;
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case SCR_ERROR:
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*val = v0 | v1;
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break;
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case SCR_CONTROL:
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*val = piix_merge_scr(v0, v1, scontrol_merge_tbl);
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break;
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}
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piix_sidpr_sel(link, reg);
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*val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
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return 0;
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}
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static int piix_sidpr_scr_write(struct ata_link *link,
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unsigned int reg, u32 val)
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{
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struct ata_port *ap = link->ap;
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struct piix_host_priv *hpriv = link->ap->host->private_data;
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if (reg >= ARRAY_SIZE(piix_sidx_map))
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return -EINVAL;
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piix_sidpr_write(&ap->link.device[0], reg, val);
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if (ap->flags & ATA_FLAG_SLAVE_POSS)
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piix_sidpr_write(&ap->link.device[1], reg, val);
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piix_sidpr_sel(link, reg);
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iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
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return 0;
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}
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@ -1370,28 +1269,28 @@ static const int *__devinit piix_init_sata_map(struct pci_dev *pdev,
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return map;
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}
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static void __devinit piix_init_sidpr(struct ata_host *host)
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static int __devinit piix_init_sidpr(struct ata_host *host)
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{
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struct pci_dev *pdev = to_pci_dev(host->dev);
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struct piix_host_priv *hpriv = host->private_data;
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struct ata_device *dev0 = &host->ports[0]->link.device[0];
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struct ata_link *link0 = &host->ports[0]->link;
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u32 scontrol;
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int i;
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int i, rc;
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/* check for availability */
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for (i = 0; i < 4; i++)
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if (hpriv->map[i] == IDE)
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return;
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return 0;
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if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
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return;
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return 0;
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if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
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pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
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return;
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return 0;
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if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
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return;
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return 0;
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hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
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@ -1399,7 +1298,7 @@ static void __devinit piix_init_sidpr(struct ata_host *host)
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* Give it a test drive by inhibiting power save modes which
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* we'll do anyway.
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*/
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scontrol = piix_sidpr_read(dev0, SCR_CONTROL);
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piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
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/* if IPM is already 3, SCR access is probably working. Don't
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* un-inhibit power save modes as BIOS might have inhibited
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@ -1407,18 +1306,30 @@ static void __devinit piix_init_sidpr(struct ata_host *host)
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*/
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if ((scontrol & 0xf00) != 0x300) {
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scontrol |= 0x300;
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piix_sidpr_write(dev0, SCR_CONTROL, scontrol);
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scontrol = piix_sidpr_read(dev0, SCR_CONTROL);
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piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol);
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piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
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if ((scontrol & 0xf00) != 0x300) {
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dev_printk(KERN_INFO, host->dev, "SCR access via "
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"SIDPR is available but doesn't work\n");
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return;
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return 0;
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}
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}
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host->ports[0]->ops = &piix_sidpr_sata_ops;
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host->ports[1]->ops = &piix_sidpr_sata_ops;
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/* okay, SCRs available, set ops and ask libata for slave_link */
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for (i = 0; i < 2; i++) {
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struct ata_port *ap = host->ports[i];
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ap->ops = &piix_sidpr_sata_ops;
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if (ap->flags & ATA_FLAG_SLAVE_POSS) {
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rc = ata_slave_link_init(ap);
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if (rc)
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return rc;
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}
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}
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return 0;
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}
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static void piix_iocfg_bit18_quirk(struct pci_dev *pdev)
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@ -1528,7 +1439,9 @@ static int __devinit piix_init_one(struct pci_dev *pdev,
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/* initialize controller */
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if (port_flags & ATA_FLAG_SATA) {
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piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
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piix_init_sidpr(host);
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rc = piix_init_sidpr(host);
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if (rc)
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return rc;
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}
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/* apply IOCFG bit18 quirk */
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