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dt-bindings: clock: Add resets for LPASS audio clock controller for SC7280

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Add support for LPASS audio clock gating for RX/TX/SWA core bus clocks
for SC7280. Update reg property min/max items in YAML schema.

Fixes: 4185b27b3b ("dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280")
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1662005846-4838-4-git-send-email-quic_c_skakit@quicinc.com
This commit is contained in:
Taniya Das 2022-09-01 09:47:24 +05:30 committed by Bjorn Andersson
parent 7afdf3afff
commit be9439df23
2 changed files with 21 additions and 3 deletions
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19
Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
View file

@ -22,6 +22,8 @@ properties:
clock-names: true clock-names: true
reg: true
compatible: compatible:
enum: enum:
- qcom,sc7280-lpassaoncc - qcom,sc7280-lpassaoncc
@ -38,8 +40,8 @@ properties:
'#power-domain-cells': '#power-domain-cells':
const: 1 const: 1
reg: '#reset-cells':
maxItems: 1 const: 1
qcom,adsp-pil-mode: qcom,adsp-pil-mode:
description: description:
@ -75,6 +77,11 @@ allOf:
items: items:
- const: bi_tcxo - const: bi_tcxo
- const: lpass_aon_cc_main_rcg_clk_src - const: lpass_aon_cc_main_rcg_clk_src
reg:
items:
- description: lpass core cc register
- description: lpass audio csr register
- if: - if:
properties: properties:
compatible: compatible:
@ -96,6 +103,8 @@ allOf:
- const: bi_tcxo_ao - const: bi_tcxo_ao
- const: iface - const: iface
reg:
maxItems: 1
- if: - if:
properties: properties:
compatible: compatible:
@ -114,6 +123,8 @@ allOf:
items: items:
- const: bi_tcxo - const: bi_tcxo
reg:
maxItems: 1
examples: examples:
- | - |
#include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,rpmh.h>
@ -122,13 +133,15 @@ examples:
#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
lpass_audiocc: clock-controller@3300000 { lpass_audiocc: clock-controller@3300000 {
compatible = "qcom,sc7280-lpassaudiocc"; compatible = "qcom,sc7280-lpassaudiocc";
reg = <0x3300000 0x30000>; reg = <0x3300000 0x30000>,
<0x32a9000 0x1000>;
clocks = <&rpmhcc RPMH_CXO_CLK>, clocks = <&rpmhcc RPMH_CXO_CLK>,
<&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>;
clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
#clock-cells = <1>; #clock-cells = <1>;
#power-domain-cells = <1>; #power-domain-cells = <1>;
#reset-cells = <1>;
}; };
- | - |

5
include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h
View file

@ -24,6 +24,11 @@
#define LPASS_AUDIO_CC_RX_MCLK_CLK 14 #define LPASS_AUDIO_CC_RX_MCLK_CLK 14
#define LPASS_AUDIO_CC_RX_MCLK_CLK_SRC 15 #define LPASS_AUDIO_CC_RX_MCLK_CLK_SRC 15
/* LPASS AUDIO CC CSR */
#define LPASS_AUDIO_SWR_RX_CGCR 0
#define LPASS_AUDIO_SWR_TX_CGCR 1
#define LPASS_AUDIO_SWR_WSA_CGCR 2
/* LPASS_AON_CC clocks */ /* LPASS_AON_CC clocks */
#define LPASS_AON_CC_PLL 0 #define LPASS_AON_CC_PLL 0
#define LPASS_AON_CC_PLL_OUT_EVEN 1 #define LPASS_AON_CC_PLL_OUT_EVEN 1