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staging: dwc2: add check on dwc2_core_reset return
If the GRSTCTL_CSFTRST self-clearing bit never comes back to 0 for any reason, the controller is under reset state and cannot be used. It's preferable to abort initialization in such case. Signed-off-by: Julien Delacou <julien.delacou@st.com> Acked-by: Paul Zimmerman <paulz@synopsys.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
parent
b34085fdc2
commit
beb7e592bc
1 changed files with 45 additions and 13 deletions
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@ -114,7 +114,7 @@ static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
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* Do core a soft reset of the core. Be careful with this because it
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* resets all the internal state machines of the core.
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*/
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static void dwc2_core_reset(struct dwc2_hsotg *hsotg)
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static int dwc2_core_reset(struct dwc2_hsotg *hsotg)
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{
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u32 greset;
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int count = 0;
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@ -129,7 +129,7 @@ static void dwc2_core_reset(struct dwc2_hsotg *hsotg)
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dev_warn(hsotg->dev,
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"%s() HANG! AHB Idle GRSTCTL=%0x\n",
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__func__, greset);
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return;
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return -EBUSY;
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}
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} while (!(greset & GRSTCTL_AHBIDLE));
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@ -144,7 +144,7 @@ static void dwc2_core_reset(struct dwc2_hsotg *hsotg)
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dev_warn(hsotg->dev,
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"%s() HANG! Soft Reset GRSTCTL=%0x\n",
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__func__, greset);
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break;
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return -EBUSY;
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}
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} while (greset & GRSTCTL_CSFTRST);
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@ -153,11 +153,14 @@ static void dwc2_core_reset(struct dwc2_hsotg *hsotg)
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* not stay in host mode after a connector ID change!
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*/
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usleep_range(150000, 200000);
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return 0;
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}
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static void dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
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static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
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{
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u32 usbcfg, i2cctl;
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int retval = 0;
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/*
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* core_init() is now called on every switch so only call the
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@ -170,7 +173,12 @@ static void dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
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writel(usbcfg, hsotg->regs + GUSBCFG);
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/* Reset after a PHY select */
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dwc2_core_reset(hsotg);
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retval = dwc2_core_reset(hsotg);
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if (retval) {
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dev_err(hsotg->dev, "%s() Reset failed, aborting",
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__func__);
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return retval;
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}
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}
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/*
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@ -198,14 +206,17 @@ static void dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
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i2cctl |= GI2CCTL_I2CEN;
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writel(i2cctl, hsotg->regs + GI2CCTL);
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}
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return retval;
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}
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static void dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
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static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
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{
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u32 usbcfg;
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int retval = 0;
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if (!select_phy)
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return;
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return -ENODEV;
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usbcfg = readl(hsotg->regs + GUSBCFG);
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@ -238,20 +249,32 @@ static void dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
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writel(usbcfg, hsotg->regs + GUSBCFG);
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/* Reset after setting the PHY parameters */
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dwc2_core_reset(hsotg);
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retval = dwc2_core_reset(hsotg);
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if (retval) {
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dev_err(hsotg->dev, "%s() Reset failed, aborting",
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__func__);
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return retval;
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}
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return retval;
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}
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static void dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
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static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
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{
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u32 usbcfg;
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int retval = 0;
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if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL &&
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hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) {
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/* If FS mode with FS PHY */
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dwc2_fs_phy_init(hsotg, select_phy);
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retval = dwc2_fs_phy_init(hsotg, select_phy);
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if (retval)
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return retval;
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} else {
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/* High speed PHY */
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dwc2_hs_phy_init(hsotg, select_phy);
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retval = dwc2_hs_phy_init(hsotg, select_phy);
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if (retval)
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return retval;
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}
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if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
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@ -268,6 +291,8 @@ static void dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
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usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
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writel(usbcfg, hsotg->regs + GUSBCFG);
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}
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return retval;
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}
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static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
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@ -382,12 +407,19 @@ int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy, int irq)
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writel(usbcfg, hsotg->regs + GUSBCFG);
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/* Reset the Controller */
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dwc2_core_reset(hsotg);
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retval = dwc2_core_reset(hsotg);
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if (retval) {
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dev_err(hsotg->dev, "%s(): Reset failed, aborting\n",
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__func__);
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return retval;
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}
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/*
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* This needs to happen in FS mode before any other programming occurs
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*/
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dwc2_phy_init(hsotg, select_phy);
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retval = dwc2_phy_init(hsotg, select_phy);
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if (retval)
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return retval;
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/* Program the GAHBCFG Register */
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retval = dwc2_gahbcfg_init(hsotg);
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