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powerpc/xive: introduce H_INT_ESB hcall
The H_INT_ESB hcall() is used to issue a load or store to the ESB page instead of using the MMIO pages. This can be used as a workaround on some HW issues. The OS knows that this hcall should be used on an interrupt source when the ESB hcall flag is set to 1 in the hcall H_INT_GET_SOURCE_INFO. To maintain the frontier between the xive frontend and backend, we introduce a new xive operation 'esb_rw' to be used in the routines doing memory accesses on the ESBs. Signed-off-by: Cédric Le Goater <clg@kaod.org> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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parent
c58a14a9cc
commit
bed81ee181
4 changed files with 53 additions and 3 deletions
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@ -56,6 +56,7 @@ struct xive_irq_data {
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#define XIVE_IRQ_FLAG_SHIFT_BUG 0x04
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#define XIVE_IRQ_FLAG_MASK_FW 0x08
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#define XIVE_IRQ_FLAG_EOI_FW 0x10
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#define XIVE_IRQ_FLAG_H_INT_ESB 0x20
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#define XIVE_INVALID_CHIP_ID -1
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@ -198,7 +198,10 @@ static notrace u8 xive_esb_read(struct xive_irq_data *xd, u32 offset)
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if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)
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offset |= offset << 4;
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val = in_be64(xd->eoi_mmio + offset);
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if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw)
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val = xive_ops->esb_rw(xd->hw_irq, offset, 0, 0);
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else
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val = in_be64(xd->eoi_mmio + offset);
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return (u8)val;
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}
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@ -209,7 +212,10 @@ static void xive_esb_write(struct xive_irq_data *xd, u32 offset, u64 data)
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if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)
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offset |= offset << 4;
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out_be64(xd->eoi_mmio + offset, data);
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if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw)
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xive_ops->esb_rw(xd->hw_irq, offset, data, 1);
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else
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out_be64(xd->eoi_mmio + offset, data);
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}
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#ifdef CONFIG_XMON
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@ -224,7 +224,46 @@ static long plpar_int_sync(unsigned long flags, unsigned long lisn)
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return 0;
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}
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#define XIVE_SRC_H_INT_ESB (1ull << (63 - 60)) /* TODO */
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#define XIVE_ESB_FLAG_STORE (1ull << (63 - 63))
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static long plpar_int_esb(unsigned long flags,
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unsigned long lisn,
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unsigned long offset,
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unsigned long in_data,
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unsigned long *out_data)
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{
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unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
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long rc;
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pr_devel("H_INT_ESB flags=%lx lisn=%lx offset=%lx in=%lx\n",
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flags, lisn, offset, in_data);
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rc = plpar_hcall(H_INT_ESB, retbuf, flags, lisn, offset, in_data);
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if (rc) {
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pr_err("H_INT_ESB lisn=%ld offset=%ld returned %ld\n",
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lisn, offset, rc);
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return rc;
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}
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*out_data = retbuf[0];
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return 0;
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}
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static u64 xive_spapr_esb_rw(u32 lisn, u32 offset, u64 data, bool write)
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{
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unsigned long read_data;
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long rc;
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rc = plpar_int_esb(write ? XIVE_ESB_FLAG_STORE : 0,
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lisn, offset, data, &read_data);
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if (rc)
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return -1;
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return write ? 0 : read_data;
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}
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#define XIVE_SRC_H_INT_ESB (1ull << (63 - 60))
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#define XIVE_SRC_LSI (1ull << (63 - 61))
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#define XIVE_SRC_TRIGGER (1ull << (63 - 62))
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#define XIVE_SRC_STORE_EOI (1ull << (63 - 63))
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@ -244,6 +283,8 @@ static int xive_spapr_populate_irq_data(u32 hw_irq, struct xive_irq_data *data)
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if (rc)
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return -EINVAL;
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if (flags & XIVE_SRC_H_INT_ESB)
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data->flags |= XIVE_IRQ_FLAG_H_INT_ESB;
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if (flags & XIVE_SRC_STORE_EOI)
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data->flags |= XIVE_IRQ_FLAG_STORE_EOI;
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if (flags & XIVE_SRC_LSI)
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@ -487,6 +528,7 @@ static const struct xive_ops xive_spapr_ops = {
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.setup_cpu = xive_spapr_setup_cpu,
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.teardown_cpu = xive_spapr_teardown_cpu,
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.sync_source = xive_spapr_sync_source,
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.esb_rw = xive_spapr_esb_rw,
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#ifdef CONFIG_SMP
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.get_ipi = xive_spapr_get_ipi,
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.put_ipi = xive_spapr_put_ipi,
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@ -47,6 +47,7 @@ struct xive_ops {
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void (*update_pending)(struct xive_cpu *xc);
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void (*eoi)(u32 hw_irq);
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void (*sync_source)(u32 hw_irq);
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u64 (*esb_rw)(u32 hw_irq, u32 offset, u64 data, bool write);
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#ifdef CONFIG_SMP
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int (*get_ipi)(unsigned int cpu, struct xive_cpu *xc);
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void (*put_ipi)(unsigned int cpu, struct xive_cpu *xc);
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