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drm/amdgpu: get hash bit for CH4 in umc channel index

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On ALDEBARAN, the umc channel bits are not original values, they
are hashed.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Tao Zhou 2022-01-24 16:41:40 +08:00 committed by Alex Deucher
parent e63fa4dcea
commit bee7f8d092
2 changed files with 23 additions and 0 deletions
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8
drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
View file

@ -148,6 +148,10 @@ static void umc_v6_7_ecc_info_query_error_address(struct amdgpu_device *adev,
soc_pa = ADDR_OF_8KB_BLOCK(err_addr) |
ADDR_OF_256B_BLOCK(channel_index) |
OFFSET_IN_256B_BLOCK(err_addr);
/* The umc channel bits are not original values, they are hashed */
SET_CHANNEL_HASH(channel_index, soc_pa);
/* clear [C4 C3 C2] in soc physical address */
soc_pa &= ~(0x7ULL << UMC_V6_7_PA_C2_BIT);
@ -379,6 +383,10 @@ static void umc_v6_7_query_error_address(struct amdgpu_device *adev,
soc_pa = ADDR_OF_8KB_BLOCK(err_addr) |
ADDR_OF_256B_BLOCK(channel_index) |
OFFSET_IN_256B_BLOCK(err_addr);
/* The umc channel bits are not original values, they are hashed */
SET_CHANNEL_HASH(channel_index, soc_pa);
/* clear [C4 C3 C2] in soc physical address */
soc_pa &= ~(0x7ULL << UMC_V6_7_PA_C2_BIT);

15
drivers/gpu/drm/amd/amdgpu/umc_v6_7.h
View file

@ -45,12 +45,27 @@
#define UMC_V6_7_NA_MAP_PA_NUM 8
/* R14 bit shift should be considered, double the number */
#define UMC_V6_7_BAD_PAGE_NUM_PER_CHANNEL (UMC_V6_7_NA_MAP_PA_NUM * 2)
/* The CH4 bit in SOC physical address */
#define UMC_V6_7_PA_CH4_BIT 12
/* The C2 bit in SOC physical address */
#define UMC_V6_7_PA_C2_BIT 17
/* The R14 bit in SOC physical address */
#define UMC_V6_7_PA_R14_BIT 34
/* UMC regiser per channel offset */
#define UMC_V6_7_PER_CHANNEL_OFFSET 0x400
/* XOR bit 20, 25, 34 of PA into CH4 bit (bit 12 of PA),
* hash bit is only effective when related setting is enabled
*/
#define CHANNEL_HASH(channel_idx, pa) (((channel_idx) >> 4) ^ \
(((pa) >> 20) & 0x1ULL & adev->df.hash_status.hash_64k) ^ \
(((pa) >> 25) & 0x1ULL & adev->df.hash_status.hash_2m) ^ \
(((pa) >> 34) & 0x1ULL & adev->df.hash_status.hash_1g))
#define SET_CHANNEL_HASH(channel_idx, pa) do { \
(pa) &= ~(0x1ULL << UMC_V6_7_PA_CH4_BIT); \
(pa) |= (CHANNEL_HASH(channel_idx, pa) << UMC_V6_7_PA_CH4_BIT); \
} while (0)
extern struct amdgpu_umc_ras umc_v6_7_ras;
extern const uint32_t
umc_v6_7_channel_idx_tbl_second[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM];