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@ -35,20 +35,21 @@
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#define MUX_FUNC(pinconf) (((pinconf) & MUX_FUNC_MASK) >> MUX_FUNC_OFFS)
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/* PIN capabilities */
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#define PIN_CFG_IOLH BIT(0)
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#define PIN_CFG_SR BIT(1)
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#define PIN_CFG_IEN BIT(2)
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#define PIN_CFG_PUPD BIT(3)
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#define PIN_CFG_IOLH_SD0 BIT(4)
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#define PIN_CFG_IOLH_SD1 BIT(5)
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#define PIN_CFG_IOLH_QSPI BIT(6)
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#define PIN_CFG_IOLH_ETH0 BIT(7)
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#define PIN_CFG_IOLH_ETH1 BIT(8)
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#define PIN_CFG_FILONOFF BIT(9)
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#define PIN_CFG_FILNUM BIT(10)
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#define PIN_CFG_FILCLKSEL BIT(11)
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#define PIN_CFG_IOLH_A BIT(0)
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#define PIN_CFG_IOLH_B BIT(1)
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#define PIN_CFG_SR BIT(2)
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#define PIN_CFG_IEN BIT(3)
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#define PIN_CFG_PUPD BIT(4)
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#define PIN_CFG_IO_VMC_SD0 BIT(5)
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#define PIN_CFG_IO_VMC_SD1 BIT(6)
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#define PIN_CFG_IO_VMC_QSPI BIT(7)
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#define PIN_CFG_IO_VMC_ETH0 BIT(8)
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#define PIN_CFG_IO_VMC_ETH1 BIT(9)
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#define PIN_CFG_FILONOFF BIT(10)
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#define PIN_CFG_FILNUM BIT(11)
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#define PIN_CFG_FILCLKSEL BIT(12)
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#define RZG2L_MPXED_PIN_FUNCS (PIN_CFG_IOLH | \
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#define RZG2L_MPXED_PIN_FUNCS (PIN_CFG_IOLH_A | \
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PIN_CFG_SR | \
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PIN_CFG_PUPD | \
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PIN_CFG_FILONOFF | \
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@ -77,7 +78,7 @@
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#define RZG2L_SINGLE_PIN BIT(31)
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#define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \
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((p) << 24) | ((b) << 20) | (f))
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#define RZG2L_SINGLE_PIN_GET_PORT(x) (((x) & GENMASK(30, 24)) >> 24)
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#define RZG2L_SINGLE_PIN_GET_PORT_OFFSET(x) (((x) & GENMASK(30, 24)) >> 24)
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#define RZG2L_SINGLE_PIN_GET_BIT(x) (((x) & GENMASK(22, 20)) >> 20)
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#define RZG2L_SINGLE_PIN_GET_CFGS(x) ((x) & GENMASK(19, 0))
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@ -86,6 +87,7 @@
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#define PMC(n) (0x0200 + 0x10 + (n))
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#define PFC(n) (0x0400 + 0x40 + (n) * 4)
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#define PIN(n) (0x0800 + 0x10 + (n))
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#define IOLH(n) (0x1000 + (n) * 8)
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#define IEN(n) (0x1800 + (n) * 8)
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#define PWPR (0x3014)
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#define SD_CH(n) (0x3000 + (n) * 4)
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@ -101,11 +103,13 @@
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#define PVDD_MASK 0x01
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#define PFC_MASK 0x07
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#define IEN_MASK 0x01
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#define IOLH_MASK 0x03
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#define PM_INPUT 0x1
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#define PM_OUTPUT 0x2
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#define RZG2L_PIN_ID_TO_PORT(id) ((id) / RZG2L_PINS_PER_PORT)
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#define RZG2L_PIN_ID_TO_PORT_OFFSET(id) (RZG2L_PIN_ID_TO_PORT(id) + 0x10)
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#define RZG2L_PIN_ID_TO_PIN(id) ((id) % RZG2L_PINS_PER_PORT)
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struct rzg2l_dedicated_configs {
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@ -137,6 +141,9 @@ struct rzg2l_pinctrl {
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spinlock_t lock;
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};
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static const unsigned int iolh_groupa_mA[] = { 2, 4, 8, 12 };
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static const unsigned int iolh_groupb_oi[] = { 100, 66, 50, 33 };
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static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
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u8 port, u8 pin, u8 func)
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{
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@ -424,6 +431,56 @@ static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev,
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return ret;
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}
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static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl,
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u32 cfg, u32 port, u8 bit)
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{
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u8 pincount = RZG2L_GPIO_PORT_GET_PINCNT(cfg);
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u32 port_index = RZG2L_GPIO_PORT_GET_INDEX(cfg);
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u32 data;
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if (bit >= pincount || port >= pctrl->data->n_port_pins)
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return -EINVAL;
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data = pctrl->data->port_pin_configs[port];
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if (port_index != RZG2L_GPIO_PORT_GET_INDEX(data))
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return -EINVAL;
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return 0;
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}
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static u32 rzg2l_read_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset,
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u8 bit, u32 mask)
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{
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void __iomem *addr = pctrl->base + offset;
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/* handle _L/_H for 32-bit register read/write */
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if (bit >= 4) {
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bit -= 4;
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addr += 4;
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}
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return (readl(addr) >> (bit * 8)) & mask;
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}
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static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset,
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u8 bit, u32 mask, u32 val)
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{
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void __iomem *addr = pctrl->base + offset;
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unsigned long flags;
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u32 reg;
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/* handle _L/_H for 32-bit register read/write */
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if (bit >= 4) {
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bit -= 4;
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addr += 4;
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}
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spin_lock_irqsave(&pctrl->lock, flags);
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reg = readl(addr) & ~(mask << (bit * 8));
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writel(reg | (val << (bit * 8)), addr);
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spin_unlock_irqrestore(&pctrl->lock, flags);
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}
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static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
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unsigned int _pin,
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unsigned long *config)
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@ -435,7 +492,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
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unsigned int arg = 0;
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unsigned long flags;
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void __iomem *addr;
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u32 port = 0, reg;
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u32 port_offset;
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u32 cfg = 0;
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u8 bit = 0;
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@ -443,36 +500,33 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
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return -EINVAL;
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if (*pin_data & RZG2L_SINGLE_PIN) {
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port = RZG2L_SINGLE_PIN_GET_PORT(*pin_data);
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port_offset = RZG2L_SINGLE_PIN_GET_PORT_OFFSET(*pin_data);
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cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data);
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bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data);
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} else {
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cfg = RZG2L_GPIO_PORT_GET_CFGS(*pin_data);
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port_offset = RZG2L_PIN_ID_TO_PORT_OFFSET(_pin);
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bit = RZG2L_PIN_ID_TO_PIN(_pin);
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if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))
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return -EINVAL;
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}
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switch (param) {
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case PIN_CONFIG_INPUT_ENABLE:
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if (!(cfg & PIN_CFG_IEN))
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return -EINVAL;
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spin_lock_irqsave(&pctrl->lock, flags);
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/* handle _L/_H for 32-bit register read/write */
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addr = pctrl->base + IEN(port);
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if (bit >= 4) {
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bit -= 4;
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addr += 4;
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}
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reg = readl(addr) & (IEN_MASK << (bit * 8));
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arg = (reg >> (bit * 8)) & 0x1;
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spin_unlock_irqrestore(&pctrl->lock, flags);
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arg = rzg2l_read_pin_config(pctrl, IEN(port_offset), bit, IEN_MASK);
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break;
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case PIN_CONFIG_POWER_SOURCE: {
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u32 pwr_reg = 0x0;
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if (cfg & PIN_CFG_IOLH_SD0)
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if (cfg & PIN_CFG_IO_VMC_SD0)
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pwr_reg = SD_CH(0);
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else if (cfg & PIN_CFG_IOLH_SD1)
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else if (cfg & PIN_CFG_IO_VMC_SD1)
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pwr_reg = SD_CH(1);
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else if (cfg & PIN_CFG_IOLH_QSPI)
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else if (cfg & PIN_CFG_IO_VMC_QSPI)
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pwr_reg = QSPI;
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else
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return -EINVAL;
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@ -484,6 +538,28 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
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break;
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}
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case PIN_CONFIG_DRIVE_STRENGTH: {
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unsigned int index;
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if (!(cfg & PIN_CFG_IOLH_A))
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return -EINVAL;
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index = rzg2l_read_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK);
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arg = iolh_groupa_mA[index];
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break;
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}
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case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: {
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unsigned int index;
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if (!(cfg & PIN_CFG_IOLH_B))
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return -EINVAL;
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index = rzg2l_read_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK);
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arg = iolh_groupb_oi[index];
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break;
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}
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default:
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return -ENOTSUPP;
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}
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@ -504,7 +580,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
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enum pin_config_param param;
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unsigned long flags;
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void __iomem *addr;
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u32 port = 0, reg;
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u32 port_offset;
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unsigned int i;
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u32 cfg = 0;
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u8 bit = 0;
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@ -513,9 +589,16 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
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return -EINVAL;
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if (*pin_data & RZG2L_SINGLE_PIN) {
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port = RZG2L_SINGLE_PIN_GET_PORT(*pin_data);
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port_offset = RZG2L_SINGLE_PIN_GET_PORT_OFFSET(*pin_data);
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cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data);
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bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data);
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} else {
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cfg = RZG2L_GPIO_PORT_GET_CFGS(*pin_data);
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port_offset = RZG2L_PIN_ID_TO_PORT_OFFSET(_pin);
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bit = RZG2L_PIN_ID_TO_PIN(_pin);
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if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))
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return -EINVAL;
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}
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for (i = 0; i < num_configs; i++) {
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@ -528,17 +611,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
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if (!(cfg & PIN_CFG_IEN))
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return -EINVAL;
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/* handle _L/_H for 32-bit register read/write */
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addr = pctrl->base + IEN(port);
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if (bit >= 4) {
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bit -= 4;
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addr += 4;
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}
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spin_lock_irqsave(&pctrl->lock, flags);
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reg = readl(addr) & ~(IEN_MASK << (bit * 8));
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writel(reg | (arg << (bit * 8)), addr);
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spin_unlock_irqrestore(&pctrl->lock, flags);
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rzg2l_rmw_pin_config(pctrl, IEN(port_offset), bit, IEN_MASK, !!arg);
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break;
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}
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@ -549,11 +622,11 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
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if (mV != 1800 && mV != 3300)
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return -EINVAL;
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if (cfg & PIN_CFG_IOLH_SD0)
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if (cfg & PIN_CFG_IO_VMC_SD0)
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pwr_reg = SD_CH(0);
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else if (cfg & PIN_CFG_IOLH_SD1)
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else if (cfg & PIN_CFG_IO_VMC_SD1)
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pwr_reg = SD_CH(1);
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else if (cfg & PIN_CFG_IOLH_QSPI)
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else if (cfg & PIN_CFG_IO_VMC_QSPI)
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pwr_reg = QSPI;
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else
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return -EINVAL;
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@ -564,6 +637,43 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
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spin_unlock_irqrestore(&pctrl->lock, flags);
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break;
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}
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case PIN_CONFIG_DRIVE_STRENGTH: {
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unsigned int arg = pinconf_to_config_argument(_configs[i]);
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unsigned int index;
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if (!(cfg & PIN_CFG_IOLH_A))
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return -EINVAL;
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|
|
|
|
|
|
|
|
|
for (index = 0; index < ARRAY_SIZE(iolh_groupa_mA); index++) {
|
|
|
|
|
if (arg == iolh_groupa_mA[index])
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
if (index >= ARRAY_SIZE(iolh_groupa_mA))
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
rzg2l_rmw_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK, index);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: {
|
|
|
|
|
unsigned int arg = pinconf_to_config_argument(_configs[i]);
|
|
|
|
|
unsigned int index;
|
|
|
|
|
|
|
|
|
|
if (!(cfg & PIN_CFG_IOLH_B))
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
for (index = 0; index < ARRAY_SIZE(iolh_groupb_oi); index++) {
|
|
|
|
|
if (arg == iolh_groupb_oi[index])
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
if (index >= ARRAY_SIZE(iolh_groupb_oi))
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
rzg2l_rmw_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK, index);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
}
|
|
|
|
@ -855,24 +965,24 @@ static const u32 rzg2l_gpio_configs[] = {
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(2, 0x28, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(2, 0x29, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(2, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(2, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(2, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(2, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(3, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(2, 0x28, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(2, 0x29, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(2, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(2, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(2, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(2, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(3, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(2, 0x36, RZG2L_MPXED_PIN_FUNCS),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(3, 0x37, RZG2L_MPXED_PIN_FUNCS),
|
|
|
|
|
RZG2L_GPIO_PORT_PACK(3, 0x38, RZG2L_MPXED_PIN_FUNCS),
|
|
|
|
@ -890,75 +1000,75 @@ static struct rzg2l_dedicated_configs rzg2l_dedicated_pins[] = {
|
|
|
|
|
{ "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0,
|
|
|
|
|
(PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) },
|
|
|
|
|
{ "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0,
|
|
|
|
|
(PIN_CFG_SR | PIN_CFG_IOLH | PIN_CFG_IEN)) },
|
|
|
|
|
(PIN_CFG_SR | PIN_CFG_IOLH_A | PIN_CFG_IEN)) },
|
|
|
|
|
{ "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0,
|
|
|
|
|
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN)) },
|
|
|
|
|
(PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) },
|
|
|
|
|
{ "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) },
|
|
|
|
|
{ "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) },
|
|
|
|
|
{ "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0,
|
|
|
|
|
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_SD0)) },
|
|
|
|
|
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) },
|
|
|
|
|
{ "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1,
|
|
|
|
|
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) },
|
|
|
|
|
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
|
|
|
|
|
{ "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2,
|
|
|
|
|
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_SD0)) },
|
|
|
|
|
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) },
|
|
|
|
|
{ "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0,
|
|
|
|
|
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) },
|
|
|
|
|
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
|
|
|
|
|
{ "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1,
|
|
|
|
|
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) },
|
|
|
|
|
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
|
|
|
|
|
{ "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2,
|
|
|
|
|
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) },
|
|
|
|
|
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
|
|
|
|
|
{ "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3,
|
|
|
|
|
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) },
|
|
|
|
|
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
|
|
|
|
|
{ "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4,
|
|
|
|
|
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) },
|
|
|
|
|
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
|
|
|
|
|
{ "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5,
|
|
|
|
|
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) },
|
|
|
|
|
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
|
|
|
|
|
{ "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6,
|
|
|
|
|
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) },
|
|
|
|
|
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
|
|
|
|
|
{ "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x7, 7,
|
|
|
|
|
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) },
|
|
|
|
|
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
|
|
|
|
|
{ "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0,
|
|
|
|
|
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_SD1))},
|
|
|
|
|
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1)) },
|
|
|
|
|
{ "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x8, 1,
|
|
|
|
|
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD1)) },
|
|
|
|
|
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
|
|
|
|
|
{ "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x9, 0,
|
|
|
|
|
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD1)) },
|
|
|
|
|
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
|
|
|
|
|
{ "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x9, 1,
|
|
|
|
|
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD1)) },
|
|
|
|
|
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
|
|
|
|
|
{ "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x9, 2,
|
|
|
|
|
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD1)) },
|
|
|
|
|
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
|
|
|
|
|
{ "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x9, 3,
|
|
|
|
|
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD1)) },
|
|
|
|
|
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
|
|
|
|
|
{ "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0,
|
|
|
|
|
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
|
|
|
|
|
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
|
|
|
|
|
{ "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1,
|
|
|
|
|
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
|
|
|
|
|
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
|
|
|
|
|
{ "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2,
|
|
|
|
|
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
|
|
|
|
|
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
|
|
|
|
|
{ "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3,
|
|
|
|
|
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
|
|
|
|
|
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
|
|
|
|
|
{ "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4,
|
|
|
|
|
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
|
|
|
|
|
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
|
|
|
|
|
{ "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5,
|
|
|
|
|
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
|
|
|
|
|
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
|
|
|
|
|
{ "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0,
|
|
|
|
|
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
|
|
|
|
|
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
|
|
|
|
|
{ "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1,
|
|
|
|
|
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
|
|
|
|
|
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
|
|
|
|
|
{ "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2,
|
|
|
|
|
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
|
|
|
|
|
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
|
|
|
|
|
{ "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3,
|
|
|
|
|
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
|
|
|
|
|
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
|
|
|
|
|
{ "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4,
|
|
|
|
|
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
|
|
|
|
|
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
|
|
|
|
|
{ "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5,
|
|
|
|
|
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
|
|
|
|
|
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
|
|
|
|
|
{ "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0,
|
|
|
|
|
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
|
|
|
|
|
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
|
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{ "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1,
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(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
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{ "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
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{ "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH | PIN_CFG_SR)) },
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(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
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{ "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
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{ "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) },
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{ "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) },
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{ "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) },
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{ "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) },
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