mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-23 02:51:47 +00:00
Documentation: PCI: convert endpoint/pci-test-function.txt to reST
Convert plain text documentation to reStructuredText format and add it to Sphinx TOC tree. No essential content change. Signed-off-by: Changbin Du <changbin.du@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
This commit is contained in:
parent
d4518e4ac6
commit
bf2c2658d4
2 changed files with 50 additions and 33 deletions
|
@ -9,3 +9,4 @@ PCI Endpoint Framework
|
||||||
|
|
||||||
pci-endpoint
|
pci-endpoint
|
||||||
pci-endpoint-cfs
|
pci-endpoint-cfs
|
||||||
|
pci-test-function
|
||||||
|
|
|
@ -1,5 +1,10 @@
|
||||||
PCI TEST
|
.. SPDX-License-Identifier: GPL-2.0
|
||||||
Kishon Vijay Abraham I <kishon@ti.com>
|
|
||||||
|
=================
|
||||||
|
PCI Test Function
|
||||||
|
=================
|
||||||
|
|
||||||
|
:Author: Kishon Vijay Abraham I <kishon@ti.com>
|
||||||
|
|
||||||
Traditionally PCI RC has always been validated by using standard
|
Traditionally PCI RC has always been validated by using standard
|
||||||
PCI cards like ethernet PCI cards or USB PCI cards or SATA PCI cards.
|
PCI cards like ethernet PCI cards or USB PCI cards or SATA PCI cards.
|
||||||
|
@ -23,65 +28,76 @@ The PCI endpoint test device has the following registers:
|
||||||
8) PCI_ENDPOINT_TEST_IRQ_TYPE
|
8) PCI_ENDPOINT_TEST_IRQ_TYPE
|
||||||
9) PCI_ENDPOINT_TEST_IRQ_NUMBER
|
9) PCI_ENDPOINT_TEST_IRQ_NUMBER
|
||||||
|
|
||||||
*) PCI_ENDPOINT_TEST_MAGIC
|
* PCI_ENDPOINT_TEST_MAGIC
|
||||||
|
|
||||||
This register will be used to test BAR0. A known pattern will be written
|
This register will be used to test BAR0. A known pattern will be written
|
||||||
and read back from MAGIC register to verify BAR0.
|
and read back from MAGIC register to verify BAR0.
|
||||||
|
|
||||||
*) PCI_ENDPOINT_TEST_COMMAND:
|
* PCI_ENDPOINT_TEST_COMMAND
|
||||||
|
|
||||||
This register will be used by the host driver to indicate the function
|
This register will be used by the host driver to indicate the function
|
||||||
that the endpoint device must perform.
|
that the endpoint device must perform.
|
||||||
|
|
||||||
Bitfield Description:
|
======== ================================================================
|
||||||
Bit 0 : raise legacy IRQ
|
Bitfield Description
|
||||||
Bit 1 : raise MSI IRQ
|
======== ================================================================
|
||||||
Bit 2 : raise MSI-X IRQ
|
Bit 0 raise legacy IRQ
|
||||||
Bit 3 : read command (read data from RC buffer)
|
Bit 1 raise MSI IRQ
|
||||||
Bit 4 : write command (write data to RC buffer)
|
Bit 2 raise MSI-X IRQ
|
||||||
Bit 5 : copy command (copy data from one RC buffer to another
|
Bit 3 read command (read data from RC buffer)
|
||||||
RC buffer)
|
Bit 4 write command (write data to RC buffer)
|
||||||
|
Bit 5 copy command (copy data from one RC buffer to another RC buffer)
|
||||||
|
======== ================================================================
|
||||||
|
|
||||||
*) PCI_ENDPOINT_TEST_STATUS
|
* PCI_ENDPOINT_TEST_STATUS
|
||||||
|
|
||||||
This register reflects the status of the PCI endpoint device.
|
This register reflects the status of the PCI endpoint device.
|
||||||
|
|
||||||
Bitfield Description:
|
======== ==============================
|
||||||
Bit 0 : read success
|
Bitfield Description
|
||||||
Bit 1 : read fail
|
======== ==============================
|
||||||
Bit 2 : write success
|
Bit 0 read success
|
||||||
Bit 3 : write fail
|
Bit 1 read fail
|
||||||
Bit 4 : copy success
|
Bit 2 write success
|
||||||
Bit 5 : copy fail
|
Bit 3 write fail
|
||||||
Bit 6 : IRQ raised
|
Bit 4 copy success
|
||||||
Bit 7 : source address is invalid
|
Bit 5 copy fail
|
||||||
Bit 8 : destination address is invalid
|
Bit 6 IRQ raised
|
||||||
|
Bit 7 source address is invalid
|
||||||
|
Bit 8 destination address is invalid
|
||||||
|
======== ==============================
|
||||||
|
|
||||||
*) PCI_ENDPOINT_TEST_SRC_ADDR
|
* PCI_ENDPOINT_TEST_SRC_ADDR
|
||||||
|
|
||||||
This register contains the source address (RC buffer address) for the
|
This register contains the source address (RC buffer address) for the
|
||||||
COPY/READ command.
|
COPY/READ command.
|
||||||
|
|
||||||
*) PCI_ENDPOINT_TEST_DST_ADDR
|
* PCI_ENDPOINT_TEST_DST_ADDR
|
||||||
|
|
||||||
This register contains the destination address (RC buffer address) for
|
This register contains the destination address (RC buffer address) for
|
||||||
the COPY/WRITE command.
|
the COPY/WRITE command.
|
||||||
|
|
||||||
*) PCI_ENDPOINT_TEST_IRQ_TYPE
|
* PCI_ENDPOINT_TEST_IRQ_TYPE
|
||||||
|
|
||||||
This register contains the interrupt type (Legacy/MSI) triggered
|
This register contains the interrupt type (Legacy/MSI) triggered
|
||||||
for the READ/WRITE/COPY and raise IRQ (Legacy/MSI) commands.
|
for the READ/WRITE/COPY and raise IRQ (Legacy/MSI) commands.
|
||||||
|
|
||||||
Possible types:
|
Possible types:
|
||||||
- Legacy : 0
|
|
||||||
- MSI : 1
|
|
||||||
- MSI-X : 2
|
|
||||||
|
|
||||||
*) PCI_ENDPOINT_TEST_IRQ_NUMBER
|
====== ==
|
||||||
|
Legacy 0
|
||||||
|
MSI 1
|
||||||
|
MSI-X 2
|
||||||
|
====== ==
|
||||||
|
|
||||||
|
* PCI_ENDPOINT_TEST_IRQ_NUMBER
|
||||||
|
|
||||||
This register contains the triggered ID interrupt.
|
This register contains the triggered ID interrupt.
|
||||||
|
|
||||||
Admissible values:
|
Admissible values:
|
||||||
- Legacy : 0
|
|
||||||
- MSI : [1 .. 32]
|
====== ===========
|
||||||
- MSI-X : [1 .. 2048]
|
Legacy 0
|
||||||
|
MSI [1 .. 32]
|
||||||
|
MSI-X [1 .. 2048]
|
||||||
|
====== ===========
|
Loading…
Reference in a new issue