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drm/amdgpu: Avoid accessing HW when suspending SW state
At this point the ASIC is already post reset by the HW/PSP so the HW not in proper state to be configured for suspension, some blocks might be even gated and so best is to avoid touching it. v2: Rename in_dpc to more meaningful name Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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parent
c9a6b82f45
commit
bf36b52e78
6 changed files with 65 additions and 7 deletions
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@ -989,6 +989,7 @@ struct amdgpu_device {
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atomic_t throttling_logging_enabled;
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struct ratelimit_state throttling_logging_rs;
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uint32_t ras_features;
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bool in_pci_err_recovery;
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};
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static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
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@ -319,6 +319,9 @@ uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
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{
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uint32_t ret;
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if (adev->in_pci_err_recovery)
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return 0;
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if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev) &&
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down_read_trylock(&adev->reset_sem)) {
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ret = amdgpu_kiq_rreg(adev, reg);
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@ -356,6 +359,9 @@ uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
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* Returns the 8 bit value from the offset specified.
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*/
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uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) {
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if (adev->in_pci_err_recovery)
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return 0;
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if (offset < adev->rmmio_size)
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return (readb(adev->rmmio + offset));
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BUG();
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@ -377,6 +383,9 @@ uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) {
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* Writes the value specified to the offset specified.
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*/
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void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) {
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if (adev->in_pci_err_recovery)
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return;
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if (offset < adev->rmmio_size)
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writeb(value, adev->rmmio + offset);
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else
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@ -387,6 +396,9 @@ static inline void amdgpu_mm_wreg_mmio(struct amdgpu_device *adev,
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uint32_t reg, uint32_t v,
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uint32_t acc_flags)
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{
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if (adev->in_pci_err_recovery)
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return;
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trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
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if ((reg * 4) < adev->rmmio_size)
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@ -414,6 +426,9 @@ static inline void amdgpu_mm_wreg_mmio(struct amdgpu_device *adev,
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void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
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uint32_t acc_flags)
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{
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if (adev->in_pci_err_recovery)
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return;
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if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev) &&
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down_read_trylock(&adev->reset_sem)) {
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amdgpu_kiq_wreg(adev, reg, v);
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@ -432,6 +447,9 @@ void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
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void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
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uint32_t acc_flags)
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{
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if (adev->in_pci_err_recovery)
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return;
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if (amdgpu_sriov_fullaccess(adev) &&
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adev->gfx.rlc.funcs &&
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adev->gfx.rlc.funcs->is_rlcg_access_range) {
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@ -453,6 +471,9 @@ void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, uint32_t reg, uint32_t
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*/
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u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
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{
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if (adev->in_pci_err_recovery)
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return 0;
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if ((reg * 4) < adev->rio_mem_size)
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return ioread32(adev->rio_mem + (reg * 4));
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else {
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@ -472,6 +493,9 @@ u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
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*/
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void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
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{
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if (adev->in_pci_err_recovery)
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return;
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if ((reg * 4) < adev->rio_mem_size)
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iowrite32(v, adev->rio_mem + (reg * 4));
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else {
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@ -491,6 +515,9 @@ void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
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*/
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u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
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{
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if (adev->in_pci_err_recovery)
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return 0;
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if (index < adev->doorbell.num_doorbells) {
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return readl(adev->doorbell.ptr + index);
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} else {
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@ -511,6 +538,9 @@ u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
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*/
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void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
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{
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if (adev->in_pci_err_recovery)
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return;
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if (index < adev->doorbell.num_doorbells) {
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writel(v, adev->doorbell.ptr + index);
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} else {
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@ -529,6 +559,9 @@ void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
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*/
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u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
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{
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if (adev->in_pci_err_recovery)
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return 0;
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if (index < adev->doorbell.num_doorbells) {
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return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
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} else {
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@ -549,6 +582,9 @@ u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
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*/
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void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
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{
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if (adev->in_pci_err_recovery)
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return;
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if (index < adev->doorbell.num_doorbells) {
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atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
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} else {
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@ -4778,7 +4814,9 @@ pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev)
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pci_restore_state(pdev);
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adev->in_pci_err_recovery = true;
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r = amdgpu_device_ip_suspend(adev);
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adev->in_pci_err_recovery = false;
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if (r)
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goto out;
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@ -693,6 +693,9 @@ uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
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struct amdgpu_kiq *kiq = &adev->gfx.kiq;
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struct amdgpu_ring *ring = &kiq->ring;
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if (adev->in_pci_err_recovery)
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return 0;
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BUG_ON(!ring->funcs->emit_rreg);
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spin_lock_irqsave(&kiq->ring_lock, flags);
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@ -757,6 +760,9 @@ void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
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BUG_ON(!ring->funcs->emit_wreg);
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if (adev->in_pci_err_recovery)
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return;
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spin_lock_irqsave(&kiq->ring_lock, flags);
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amdgpu_ring_alloc(ring, 32);
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amdgpu_ring_emit_wreg(ring, reg, v);
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@ -219,6 +219,9 @@ int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
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int i;
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struct amdgpu_device *adev = psp->adev;
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if (psp->adev->in_pci_err_recovery)
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return 0;
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for (i = 0; i < adev->usec_timeout; i++) {
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val = RREG32(reg_index);
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if (check_changed) {
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@ -245,6 +248,9 @@ psp_cmd_submit_buf(struct psp_context *psp,
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bool ras_intr = false;
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bool skip_unsupport = false;
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if (psp->adev->in_pci_err_recovery)
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return 0;
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mutex_lock(&psp->mutex);
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memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
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@ -6980,15 +6980,19 @@ static int gfx_v10_0_hw_fini(void *handle)
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amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
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amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
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if (!adev->in_pci_err_recovery) {
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#ifndef BRING_UP_DEBUG
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if (amdgpu_async_gfx_ring) {
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r = gfx_v10_0_kiq_disable_kgq(adev);
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if (r)
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DRM_ERROR("KGQ disable failed\n");
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}
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if (amdgpu_async_gfx_ring) {
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r = gfx_v10_0_kiq_disable_kgq(adev);
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if (r)
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DRM_ERROR("KGQ disable failed\n");
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}
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#endif
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if (amdgpu_gfx_disable_kcq(adev))
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DRM_ERROR("KCQ disable failed\n");
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if (amdgpu_gfx_disable_kcq(adev))
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DRM_ERROR("KCQ disable failed\n");
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}
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if (amdgpu_sriov_vf(adev)) {
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gfx_v10_0_cp_gfx_enable(adev, false);
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/* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
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@ -112,6 +112,9 @@ int smu_cmn_send_smc_msg_with_param(struct smu_context *smu,
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struct amdgpu_device *adev = smu->adev;
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int ret = 0, index = 0;
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if (smu->adev->in_pci_err_recovery)
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return 0;
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index = smu_cmn_to_asic_specific_index(smu,
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CMN2ASIC_MAPPING_MSG,
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msg);
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