mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-05 18:39:59 +00:00
Merge branch 'staging/for_v3.7' into v4l_for_linus
Applied on the top of changeset 782cd9e
, as some of those patches
depend on some fixes that went via -arm tree.
* staging/for_v3.7: (109 commits)
[media] m5mols: Add missing #include <linux/sizes.h>
[media] stk1160: Add support for S-Video input
Revert "[media] omap3isp: Replace cpu_is_omap3630() with ISP revision check"
[media] dvb: LNA implementation changes
[media] v4l2-ioctl: fix W=1 warnings
[media] v4l2-ioctl: add blocks check for VIDIOC_SUBDEV_G/S_EDID
[media] omap3isp: Fix compilation error in ispreg.h
[media] rc-msi-digivox-ii: Add full scan keycodes
[media] cx25821: testing the wrong variable
[media] tda18271-common: hold the I2C adapter during write transfers
[media] ds3000: add module parameter to force firmware upload
[media] drivers/media: Remove unnecessary semicolon
[media] winbond: remove space from driver name
[media] iguanair: cannot send data from the stack
[media] omap3isp: Replace cpu_is_omap3630() with ISP revision check
[media] dvb-usb: print small buffers via %*ph
[media] uvc: Add return code check at vb2_queue_init()
[media] em28xx: Replace memcpy with struct assignment
[media] bt8xx: Add video4linux control V4L2_CID_COLOR_KILLER
[media] mem2mem_testdev: Use devm_kzalloc() in probe
...
This commit is contained in:
commit
bf3b202b41
171 changed files with 8078 additions and 3214 deletions
|
@ -2582,6 +2582,10 @@ ioctls.</para>
|
||||||
<listitem>
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<listitem>
|
||||||
<para>Support for frequency band enumeration: &VIDIOC-ENUM-FREQ-BANDS; ioctl.</para>
|
<para>Support for frequency band enumeration: &VIDIOC-ENUM-FREQ-BANDS; ioctl.</para>
|
||||||
</listitem>
|
</listitem>
|
||||||
|
<listitem>
|
||||||
|
<para>Vendor and device specific media bus pixel formats.
|
||||||
|
<xref linkend="v4l2-mbus-vendor-spec-fmts" />.</para>
|
||||||
|
</listitem>
|
||||||
</itemizedlist>
|
</itemizedlist>
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||||||
</section>
|
</section>
|
||||||
|
|
||||||
|
|
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@ -1586,7 +1586,6 @@ frame counter of the frame that is currently displayed (decoded). This value is
|
||||||
the decoder is started.</entry>
|
the decoder is started.</entry>
|
||||||
</row>
|
</row>
|
||||||
|
|
||||||
|
|
||||||
<row><entry></entry></row>
|
<row><entry></entry></row>
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||||||
<row>
|
<row>
|
||||||
<entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_DECODER_SLICE_INTERFACE</constant> </entry>
|
<entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_DECODER_SLICE_INTERFACE</constant> </entry>
|
||||||
|
@ -2269,6 +2268,14 @@ encoder or editing process may produce.".
|
||||||
Applicable to the MPEG1, MPEG2, MPEG4 encoders.</entry>
|
Applicable to the MPEG1, MPEG2, MPEG4 encoders.</entry>
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||||||
</row>
|
</row>
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||||||
|
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||||||
|
<row><entry></entry></row>
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||||||
|
<row id="v4l2-mpeg-video-vbv-delay">
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||||||
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<entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_VBV_DELAY</constant> </entry>
|
||||||
|
<entry>integer</entry>
|
||||||
|
</row><row><entry spanname="descr">Sets the initial delay in milliseconds for
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||||||
|
VBV buffer control.</entry>
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||||||
|
</row>
|
||||||
|
|
||||||
<row><entry></entry></row>
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<row><entry></entry></row>
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||||||
<row>
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<row>
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||||||
<entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE</constant> </entry>
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<entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE</constant> </entry>
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||||||
|
@ -2334,6 +2341,265 @@ Applicable to the MPEG4 decoder.</entry>
|
||||||
</row><row><entry spanname="descr">vop_time_increment value for MPEG4. Applicable to the MPEG4 encoder.</entry>
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</row><row><entry spanname="descr">vop_time_increment value for MPEG4. Applicable to the MPEG4 encoder.</entry>
|
||||||
</row>
|
</row>
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||||||
|
|
||||||
|
<row><entry></entry></row>
|
||||||
|
<row>
|
||||||
|
<entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_H264_SEI_FRAME_PACKING</constant> </entry>
|
||||||
|
<entry>boolean</entry>
|
||||||
|
</row>
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||||||
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<row><entry spanname="descr">Enable generation of frame packing supplemental enhancement information in the encoded bitstream.
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||||||
|
The frame packing SEI message contains the arrangement of L and R planes for 3D viewing. Applicable to the H264 encoder.</entry>
|
||||||
|
</row>
|
||||||
|
|
||||||
|
<row><entry></entry></row>
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||||||
|
<row>
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||||||
|
<entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_H264_SEI_FP_CURRENT_FRAME_0</constant> </entry>
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||||||
|
<entry>boolean</entry>
|
||||||
|
</row>
|
||||||
|
<row><entry spanname="descr">Sets current frame as frame0 in frame packing SEI.
|
||||||
|
Applicable to the H264 encoder.</entry>
|
||||||
|
</row>
|
||||||
|
|
||||||
|
<row><entry></entry></row>
|
||||||
|
<row id="v4l2-mpeg-video-h264-sei-fp-arrangement-type">
|
||||||
|
<entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE</constant> </entry>
|
||||||
|
<entry>enum v4l2_mpeg_video_h264_sei_fp_arrangement_type</entry>
|
||||||
|
</row>
|
||||||
|
<row><entry spanname="descr">Frame packing arrangement type for H264 SEI.
|
||||||
|
Applicable to the H264 encoder.
|
||||||
|
Possible values are:</entry>
|
||||||
|
</row>
|
||||||
|
<row>
|
||||||
|
<entrytbl spanname="descr" cols="2">
|
||||||
|
<tbody valign="top">
|
||||||
|
<row>
|
||||||
|
<entry><constant>V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_CHEKERBOARD</constant> </entry>
|
||||||
|
<entry>Pixels are alternatively from L and R.</entry>
|
||||||
|
</row>
|
||||||
|
<row>
|
||||||
|
<entry><constant>V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_COLUMN</constant> </entry>
|
||||||
|
<entry>L and R are interlaced by column.</entry>
|
||||||
|
</row>
|
||||||
|
<row>
|
||||||
|
<entry><constant>V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_ROW</constant> </entry>
|
||||||
|
<entry>L and R are interlaced by row.</entry>
|
||||||
|
</row>
|
||||||
|
<row>
|
||||||
|
<entry><constant>V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_SIDE_BY_SIDE</constant> </entry>
|
||||||
|
<entry>L is on the left, R on the right.</entry>
|
||||||
|
</row>
|
||||||
|
<row>
|
||||||
|
<entry><constant>V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_TOP_BOTTOM</constant> </entry>
|
||||||
|
<entry>L is on top, R on bottom.</entry>
|
||||||
|
</row>
|
||||||
|
<row>
|
||||||
|
<entry><constant>V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_TEMPORAL</constant> </entry>
|
||||||
|
<entry>One view per frame.</entry>
|
||||||
|
</row>
|
||||||
|
</tbody>
|
||||||
|
</entrytbl>
|
||||||
|
</row>
|
||||||
|
|
||||||
|
<row><entry></entry></row>
|
||||||
|
<row>
|
||||||
|
<entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_H264_FMO</constant> </entry>
|
||||||
|
<entry>boolean</entry>
|
||||||
|
</row>
|
||||||
|
<row><entry spanname="descr">Enables flexible macroblock ordering in the encoded bitstream. It is a technique
|
||||||
|
used for restructuring the ordering of macroblocks in pictures. Applicable to the H264 encoder.</entry>
|
||||||
|
</row>
|
||||||
|
|
||||||
|
<row><entry></entry></row>
|
||||||
|
<row id="v4l2-mpeg-video-h264-fmo-map-type">
|
||||||
|
<entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_H264_FMO_MAP_TYPE</constant> </entry>
|
||||||
|
<entry>enum v4l2_mpeg_video_h264_fmo_map_type</entry>
|
||||||
|
</row>
|
||||||
|
<row><entry spanname="descr">When using FMO, the map type divides the image in different scan patterns of macroblocks.
|
||||||
|
Applicable to the H264 encoder.
|
||||||
|
Possible values are:</entry>
|
||||||
|
</row>
|
||||||
|
<row>
|
||||||
|
<entrytbl spanname="descr" cols="2">
|
||||||
|
<tbody valign="top">
|
||||||
|
<row>
|
||||||
|
<entry><constant>V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_INTERLEAVED_SLICES</constant> </entry>
|
||||||
|
<entry>Slices are interleaved one after other with macroblocks in run length order.</entry>
|
||||||
|
</row>
|
||||||
|
<row>
|
||||||
|
<entry><constant>V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_SCATTERED_SLICES</constant> </entry>
|
||||||
|
<entry>Scatters the macroblocks based on a mathematical function known to both encoder and decoder.</entry>
|
||||||
|
</row>
|
||||||
|
<row>
|
||||||
|
<entry><constant>V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_FOREGROUND_WITH_LEFT_OVER</constant> </entry>
|
||||||
|
<entry>Macroblocks arranged in rectangular areas or regions of interest.</entry>
|
||||||
|
</row>
|
||||||
|
<row>
|
||||||
|
<entry><constant>V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_BOX_OUT</constant> </entry>
|
||||||
|
<entry>Slice groups grow in a cyclic way from centre to outwards.</entry>
|
||||||
|
</row>
|
||||||
|
<row>
|
||||||
|
<entry><constant>V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_RASTER_SCAN</constant> </entry>
|
||||||
|
<entry>Slice groups grow in raster scan pattern from left to right.</entry>
|
||||||
|
</row>
|
||||||
|
<row>
|
||||||
|
<entry><constant>V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_WIPE_SCAN</constant> </entry>
|
||||||
|
<entry>Slice groups grow in wipe scan pattern from top to bottom.</entry>
|
||||||
|
</row>
|
||||||
|
<row>
|
||||||
|
<entry><constant>V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_EXPLICIT</constant> </entry>
|
||||||
|
<entry>User defined map type.</entry>
|
||||||
|
</row>
|
||||||
|
</tbody>
|
||||||
|
</entrytbl>
|
||||||
|
</row>
|
||||||
|
|
||||||
|
<row><entry></entry></row>
|
||||||
|
<row>
|
||||||
|
<entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_H264_FMO_SLICE_GROUP</constant> </entry>
|
||||||
|
<entry>integer</entry>
|
||||||
|
</row>
|
||||||
|
<row><entry spanname="descr">Number of slice groups in FMO.
|
||||||
|
Applicable to the H264 encoder.</entry>
|
||||||
|
</row>
|
||||||
|
|
||||||
|
<row><entry></entry></row>
|
||||||
|
<row id="v4l2-mpeg-video-h264-fmo-change-direction">
|
||||||
|
<entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_H264_FMO_CHANGE_DIRECTION</constant> </entry>
|
||||||
|
<entry>enum v4l2_mpeg_video_h264_fmo_change_dir</entry>
|
||||||
|
</row>
|
||||||
|
<row><entry spanname="descr">Specifies a direction of the slice group change for raster and wipe maps.
|
||||||
|
Applicable to the H264 encoder.
|
||||||
|
Possible values are:</entry>
|
||||||
|
</row>
|
||||||
|
<row>
|
||||||
|
<entrytbl spanname="descr" cols="2">
|
||||||
|
<tbody valign="top">
|
||||||
|
<row>
|
||||||
|
<entry><constant>V4L2_MPEG_VIDEO_H264_FMO_CHANGE_DIR_RIGHT</constant> </entry>
|
||||||
|
<entry>Raster scan or wipe right.</entry>
|
||||||
|
</row>
|
||||||
|
<row>
|
||||||
|
<entry><constant>V4L2_MPEG_VIDEO_H264_FMO_CHANGE_DIR_LEFT</constant> </entry>
|
||||||
|
<entry>Reverse raster scan or wipe left.</entry>
|
||||||
|
</row>
|
||||||
|
</tbody>
|
||||||
|
</entrytbl>
|
||||||
|
</row>
|
||||||
|
|
||||||
|
<row><entry></entry></row>
|
||||||
|
<row>
|
||||||
|
<entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_H264_FMO_CHANGE_RATE</constant> </entry>
|
||||||
|
<entry>integer</entry>
|
||||||
|
</row>
|
||||||
|
<row><entry spanname="descr">Specifies the size of the first slice group for raster and wipe map.
|
||||||
|
Applicable to the H264 encoder.</entry>
|
||||||
|
</row>
|
||||||
|
|
||||||
|
<row><entry></entry></row>
|
||||||
|
<row>
|
||||||
|
<entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_H264_FMO_RUN_LENGTH</constant> </entry>
|
||||||
|
<entry>integer</entry>
|
||||||
|
</row>
|
||||||
|
<row><entry spanname="descr">Specifies the number of consecutive macroblocks for the interleaved map.
|
||||||
|
Applicable to the H264 encoder.</entry>
|
||||||
|
</row>
|
||||||
|
|
||||||
|
<row><entry></entry></row>
|
||||||
|
<row>
|
||||||
|
<entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_H264_ASO</constant> </entry>
|
||||||
|
<entry>boolean</entry>
|
||||||
|
</row>
|
||||||
|
<row><entry spanname="descr">Enables arbitrary slice ordering in encoded bitstream.
|
||||||
|
Applicable to the H264 encoder.</entry>
|
||||||
|
</row>
|
||||||
|
|
||||||
|
<row><entry></entry></row>
|
||||||
|
<row>
|
||||||
|
<entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_H264_ASO_SLICE_ORDER</constant> </entry>
|
||||||
|
<entry>integer</entry>
|
||||||
|
</row><row><entry spanname="descr">Specifies the slice order in ASO. Applicable to the H264 encoder.
|
||||||
|
The supplied 32-bit integer is interpreted as follows (bit
|
||||||
|
0 = least significant bit):</entry>
|
||||||
|
</row>
|
||||||
|
<row>
|
||||||
|
<entrytbl spanname="descr" cols="2">
|
||||||
|
<tbody valign="top">
|
||||||
|
<row>
|
||||||
|
<entry>Bit 0:15</entry>
|
||||||
|
<entry>Slice ID</entry>
|
||||||
|
</row>
|
||||||
|
<row>
|
||||||
|
<entry>Bit 16:32</entry>
|
||||||
|
<entry>Slice position or order</entry>
|
||||||
|
</row>
|
||||||
|
</tbody>
|
||||||
|
</entrytbl>
|
||||||
|
</row>
|
||||||
|
|
||||||
|
<row><entry></entry></row>
|
||||||
|
<row>
|
||||||
|
<entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING</constant> </entry>
|
||||||
|
<entry>boolean</entry>
|
||||||
|
</row>
|
||||||
|
<row><entry spanname="descr">Enables H264 hierarchical coding.
|
||||||
|
Applicable to the H264 encoder.</entry>
|
||||||
|
</row>
|
||||||
|
|
||||||
|
<row><entry></entry></row>
|
||||||
|
<row id="v4l2-mpeg-video-h264-hierarchical-coding-type">
|
||||||
|
<entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_TYPE</constant> </entry>
|
||||||
|
<entry>enum v4l2_mpeg_video_h264_hierarchical_coding_type</entry>
|
||||||
|
</row>
|
||||||
|
<row><entry spanname="descr">Specifies the hierarchical coding type.
|
||||||
|
Applicable to the H264 encoder.
|
||||||
|
Possible values are:</entry>
|
||||||
|
</row>
|
||||||
|
<row>
|
||||||
|
<entrytbl spanname="descr" cols="2">
|
||||||
|
<tbody valign="top">
|
||||||
|
<row>
|
||||||
|
<entry><constant>V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_B</constant> </entry>
|
||||||
|
<entry>Hierarchical B coding.</entry>
|
||||||
|
</row>
|
||||||
|
<row>
|
||||||
|
<entry><constant>V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_P</constant> </entry>
|
||||||
|
<entry>Hierarchical P coding.</entry>
|
||||||
|
</row>
|
||||||
|
</tbody>
|
||||||
|
</entrytbl>
|
||||||
|
</row>
|
||||||
|
|
||||||
|
<row><entry></entry></row>
|
||||||
|
<row>
|
||||||
|
<entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER</constant> </entry>
|
||||||
|
<entry>integer</entry>
|
||||||
|
</row>
|
||||||
|
<row><entry spanname="descr">Specifies the number of hierarchical coding layers.
|
||||||
|
Applicable to the H264 encoder.</entry>
|
||||||
|
</row>
|
||||||
|
|
||||||
|
<row><entry></entry></row>
|
||||||
|
<row>
|
||||||
|
<entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_QP</constant> </entry>
|
||||||
|
<entry>integer</entry>
|
||||||
|
</row><row><entry spanname="descr">Specifies a user defined QP for each layer. Applicable to the H264 encoder.
|
||||||
|
The supplied 32-bit integer is interpreted as follows (bit
|
||||||
|
0 = least significant bit):</entry>
|
||||||
|
</row>
|
||||||
|
<row>
|
||||||
|
<entrytbl spanname="descr" cols="2">
|
||||||
|
<tbody valign="top">
|
||||||
|
<row>
|
||||||
|
<entry>Bit 0:15</entry>
|
||||||
|
<entry>QP value</entry>
|
||||||
|
</row>
|
||||||
|
<row>
|
||||||
|
<entry>Bit 16:32</entry>
|
||||||
|
<entry>Layer number</entry>
|
||||||
|
</row>
|
||||||
|
</tbody>
|
||||||
|
</entrytbl>
|
||||||
|
</row>
|
||||||
|
|
||||||
</tbody>
|
</tbody>
|
||||||
</tgroup>
|
</tgroup>
|
||||||
</table>
|
</table>
|
||||||
|
@ -4267,6 +4533,16 @@ interface and may change in the future.</para>
|
||||||
pixels / second.
|
pixels / second.
|
||||||
</entry>
|
</entry>
|
||||||
</row>
|
</row>
|
||||||
|
<row>
|
||||||
|
<entry spanname="id"><constant>V4L2_CID_TEST_PATTERN</constant></entry>
|
||||||
|
<entry>menu</entry>
|
||||||
|
</row>
|
||||||
|
<row id="v4l2-test-pattern">
|
||||||
|
<entry spanname="descr"> Some capture/display/sensor devices have
|
||||||
|
the capability to generate test pattern images. These hardware
|
||||||
|
specific test patterns can be used to test if a device is working
|
||||||
|
properly.</entry>
|
||||||
|
</row>
|
||||||
<row><entry></entry></row>
|
<row><entry></entry></row>
|
||||||
</tbody>
|
</tbody>
|
||||||
</tgroup>
|
</tgroup>
|
||||||
|
|
|
@ -677,8 +677,10 @@ memory, set by the application. See <xref linkend="userp" /> for details.
|
||||||
<entry><structfield>length</structfield></entry>
|
<entry><structfield>length</structfield></entry>
|
||||||
<entry></entry>
|
<entry></entry>
|
||||||
<entry>Size of the buffer (not the payload) in bytes for the
|
<entry>Size of the buffer (not the payload) in bytes for the
|
||||||
single-planar API. For the multi-planar API should contain the
|
single-planar API. For the multi-planar API the application sets
|
||||||
number of elements in the <structfield>planes</structfield> array.
|
this to the number of elements in the <structfield>planes</structfield>
|
||||||
|
array. The driver will fill in the actual number of valid elements in
|
||||||
|
that array.
|
||||||
</entry>
|
</entry>
|
||||||
</row>
|
</row>
|
||||||
<row>
|
<row>
|
||||||
|
|
|
@ -1,11 +1,13 @@
|
||||||
<refentry id="V4L2-PIX-FMT-NV12M">
|
<refentry>
|
||||||
<refmeta>
|
<refmeta>
|
||||||
<refentrytitle>V4L2_PIX_FMT_NV12M ('NM12')</refentrytitle>
|
<refentrytitle>V4L2_PIX_FMT_NV12M ('NM12'), V4L2_PIX_FMT_NV21M ('NM21'), V4L2_PIX_FMT_NV12MT_16X16</refentrytitle>
|
||||||
&manvol;
|
&manvol;
|
||||||
</refmeta>
|
</refmeta>
|
||||||
<refnamediv>
|
<refnamediv>
|
||||||
<refname> <constant>V4L2_PIX_FMT_NV12M</constant></refname>
|
<refname id="V4L2-PIX-FMT-NV12M"><constant>V4L2_PIX_FMT_NV12M</constant></refname>
|
||||||
<refpurpose>Variation of <constant>V4L2_PIX_FMT_NV12</constant> with planes
|
<refname id="V4L2-PIX-FMT-NV21M"><constant>V4L2_PIX_FMT_NV21M</constant></refname>
|
||||||
|
<refname id="V4L2-PIX-FMT-NV12MT_16X16"><constant>V4L2_PIX_FMT_NV12MT_16X16</constant></refname>
|
||||||
|
<refpurpose>Variation of <constant>V4L2_PIX_FMT_NV12</constant> and <constant>V4L2_PIX_FMT_NV21</constant> with planes
|
||||||
non contiguous in memory. </refpurpose>
|
non contiguous in memory. </refpurpose>
|
||||||
</refnamediv>
|
</refnamediv>
|
||||||
<refsect1>
|
<refsect1>
|
||||||
|
@ -22,7 +24,12 @@ The CbCr plane is the same width, in bytes, as the Y plane (and of the image),
|
||||||
but is half as tall in pixels. Each CbCr pair belongs to four pixels. For example,
|
but is half as tall in pixels. Each CbCr pair belongs to four pixels. For example,
|
||||||
Cb<subscript>0</subscript>/Cr<subscript>0</subscript> belongs to
|
Cb<subscript>0</subscript>/Cr<subscript>0</subscript> belongs to
|
||||||
Y'<subscript>00</subscript>, Y'<subscript>01</subscript>,
|
Y'<subscript>00</subscript>, Y'<subscript>01</subscript>,
|
||||||
Y'<subscript>10</subscript>, Y'<subscript>11</subscript>. </para>
|
Y'<subscript>10</subscript>, Y'<subscript>11</subscript>.
|
||||||
|
<constant>V4L2_PIX_FMT_NV12MT_16X16</constant> is the tiled version of
|
||||||
|
<constant>V4L2_PIX_FMT_NV12M</constant> with 16x16 macroblock tiles. Here pixels
|
||||||
|
are arranged in 16x16 2D tiles and tiles are arranged in linear order in memory.
|
||||||
|
<constant>V4L2_PIX_FMT_NV21M</constant> is the same as <constant>V4L2_PIX_FMT_NV12M</constant>
|
||||||
|
except the Cb and Cr bytes are swapped, the CrCb plane starts with a Cr byte.</para>
|
||||||
|
|
||||||
<para><constant>V4L2_PIX_FMT_NV12M</constant> is intended to be
|
<para><constant>V4L2_PIX_FMT_NV12M</constant> is intended to be
|
||||||
used only in drivers and applications that support the multi-planar API,
|
used only in drivers and applications that support the multi-planar API,
|
||||||
|
|
|
@ -758,6 +758,11 @@ extended control <constant>V4L2_CID_MPEG_STREAM_TYPE</constant>, see
|
||||||
<entry>'AVC1'</entry>
|
<entry>'AVC1'</entry>
|
||||||
<entry>H264 video elementary stream without start codes.</entry>
|
<entry>H264 video elementary stream without start codes.</entry>
|
||||||
</row>
|
</row>
|
||||||
|
<row id="V4L2-PIX-FMT-H264-MVC">
|
||||||
|
<entry><constant>V4L2_PIX_FMT_H264_MVC</constant></entry>
|
||||||
|
<entry>'MVC'</entry>
|
||||||
|
<entry>H264 MVC video elementary stream.</entry>
|
||||||
|
</row>
|
||||||
<row id="V4L2-PIX-FMT-H263">
|
<row id="V4L2-PIX-FMT-H263">
|
||||||
<entry><constant>V4L2_PIX_FMT_H263</constant></entry>
|
<entry><constant>V4L2_PIX_FMT_H263</constant></entry>
|
||||||
<entry>'H263'</entry>
|
<entry>'H263'</entry>
|
||||||
|
@ -793,6 +798,11 @@ extended control <constant>V4L2_CID_MPEG_STREAM_TYPE</constant>, see
|
||||||
<entry>'VC1L'</entry>
|
<entry>'VC1L'</entry>
|
||||||
<entry>VC1, SMPTE 421M Annex L compliant stream.</entry>
|
<entry>VC1, SMPTE 421M Annex L compliant stream.</entry>
|
||||||
</row>
|
</row>
|
||||||
|
<row id="V4L2-PIX-FMT-VP8">
|
||||||
|
<entry><constant>V4L2_PIX_FMT_VP8</constant></entry>
|
||||||
|
<entry>'VP8'</entry>
|
||||||
|
<entry>VP8 video elementary stream.</entry>
|
||||||
|
</row>
|
||||||
</tbody>
|
</tbody>
|
||||||
</tgroup>
|
</tgroup>
|
||||||
</table>
|
</table>
|
||||||
|
@ -996,6 +1006,34 @@ the other bits are set to 0.</entry>
|
||||||
<entry>Old 6-bit greyscale format. Only the most significant 6 bits of each byte are used,
|
<entry>Old 6-bit greyscale format. Only the most significant 6 bits of each byte are used,
|
||||||
the other bits are set to 0.</entry>
|
the other bits are set to 0.</entry>
|
||||||
</row>
|
</row>
|
||||||
|
<row id="V4L2-PIX-FMT-S5C-UYVY-JPG">
|
||||||
|
<entry><constant>V4L2_PIX_FMT_S5C_UYVY_JPG</constant></entry>
|
||||||
|
<entry>'S5CI'</entry>
|
||||||
|
<entry>Two-planar format used by Samsung S5C73MX cameras. The
|
||||||
|
first plane contains interleaved JPEG and UYVY image data, followed by meta data
|
||||||
|
in form of an array of offsets to the UYVY data blocks. The actual pointer array
|
||||||
|
follows immediately the interleaved JPEG/UYVY data, the number of entries in
|
||||||
|
this array equals the height of the UYVY image. Each entry is a 4-byte unsigned
|
||||||
|
integer in big endian order and it's an offset to a single pixel line of the
|
||||||
|
UYVY image. The first plane can start either with JPEG or UYVY data chunk. The
|
||||||
|
size of a single UYVY block equals the UYVY image's width multiplied by 2. The
|
||||||
|
size of a JPEG chunk depends on the image and can vary with each line.
|
||||||
|
<para>The second plane, at an offset of 4084 bytes, contains a 4-byte offset to
|
||||||
|
the pointer array in the first plane. This offset is followed by a 4-byte value
|
||||||
|
indicating size of the pointer array. All numbers in the second plane are also
|
||||||
|
in big endian order. Remaining data in the second plane is undefined. The
|
||||||
|
information in the second plane allows to easily find location of the pointer
|
||||||
|
array, which can be different for each frame. The size of the pointer array is
|
||||||
|
constant for given UYVY image height.</para>
|
||||||
|
<para>In order to extract UYVY and JPEG frames an application can initially set
|
||||||
|
a data pointer to the start of first plane and then add an offset from the first
|
||||||
|
entry of the pointers table. Such a pointer indicates start of an UYVY image
|
||||||
|
pixel line. Whole UYVY line can be copied to a separate buffer. These steps
|
||||||
|
should be repeated for each line, i.e. the number of entries in the pointer
|
||||||
|
array. Anything what's in between the UYVY lines is JPEG data and should be
|
||||||
|
concatenated to form the JPEG stream. </para>
|
||||||
|
</entry>
|
||||||
|
</row>
|
||||||
</tbody>
|
</tbody>
|
||||||
</tgroup>
|
</tgroup>
|
||||||
</table>
|
</table>
|
||||||
|
|
|
@ -2565,5 +2565,49 @@
|
||||||
</tgroup>
|
</tgroup>
|
||||||
</table>
|
</table>
|
||||||
</section>
|
</section>
|
||||||
|
|
||||||
|
<section id="v4l2-mbus-vendor-spec-fmts">
|
||||||
|
<title>Vendor and Device Specific Formats</title>
|
||||||
|
|
||||||
|
<note>
|
||||||
|
<title>Experimental</title>
|
||||||
|
<para>This is an <link linkend="experimental">experimental</link>
|
||||||
|
interface and may change in the future.</para>
|
||||||
|
</note>
|
||||||
|
|
||||||
|
<para>This section lists complex data formats that are either vendor or
|
||||||
|
device specific.
|
||||||
|
</para>
|
||||||
|
|
||||||
|
<para>The following table lists the existing vendor and device specific
|
||||||
|
formats.</para>
|
||||||
|
|
||||||
|
<table pgwide="0" frame="none" id="v4l2-mbus-pixelcode-vendor-specific">
|
||||||
|
<title>Vendor and device specific formats</title>
|
||||||
|
<tgroup cols="3">
|
||||||
|
<colspec colname="id" align="left" />
|
||||||
|
<colspec colname="code" align="left"/>
|
||||||
|
<colspec colname="remarks" align="left"/>
|
||||||
|
<thead>
|
||||||
|
<row>
|
||||||
|
<entry>Identifier</entry>
|
||||||
|
<entry>Code</entry>
|
||||||
|
<entry>Comments</entry>
|
||||||
|
</row>
|
||||||
|
</thead>
|
||||||
|
<tbody valign="top">
|
||||||
|
<row id="V4L2-MBUS-FMT-S5C-UYVY-JPEG-1X8">
|
||||||
|
<entry>V4L2_MBUS_FMT_S5C_UYVY_JPEG_1X8</entry>
|
||||||
|
<entry>0x5001</entry>
|
||||||
|
<entry>
|
||||||
|
Interleaved raw UYVY and JPEG image format with embedded
|
||||||
|
meta-data used by Samsung S3C73MX camera sensors.
|
||||||
|
</entry>
|
||||||
|
</row>
|
||||||
|
</tbody>
|
||||||
|
</tgroup>
|
||||||
|
</table>
|
||||||
|
</section>
|
||||||
|
|
||||||
</section>
|
</section>
|
||||||
</section>
|
</section>
|
||||||
|
|
|
@ -121,8 +121,7 @@ remaining fields or returns an error code. The driver may also set
|
||||||
field. It indicates a non-critical (recoverable) streaming error. In such case
|
field. It indicates a non-critical (recoverable) streaming error. In such case
|
||||||
the application may continue as normal, but should be aware that data in the
|
the application may continue as normal, but should be aware that data in the
|
||||||
dequeued buffer might be corrupted. When using the multi-planar API, the
|
dequeued buffer might be corrupted. When using the multi-planar API, the
|
||||||
planes array does not have to be passed; the <structfield>m.planes</structfield>
|
planes array must be passed in as well.</para>
|
||||||
member must be set to NULL in that case.</para>
|
|
||||||
|
|
||||||
<para>By default <constant>VIDIOC_DQBUF</constant> blocks when no
|
<para>By default <constant>VIDIOC_DQBUF</constant> blocks when no
|
||||||
buffer is in the outgoing queue. When the
|
buffer is in the outgoing queue. When the
|
||||||
|
|
|
@ -48,8 +48,8 @@
|
||||||
<refsect1>
|
<refsect1>
|
||||||
<title>Description</title>
|
<title>Description</title>
|
||||||
|
|
||||||
<para>This ioctl is part of the <link linkend="mmap">memory
|
<para>This ioctl is part of the <link linkend="mmap">streaming
|
||||||
mapping</link> I/O method. It can be used to query the status of a
|
</link> I/O method. It can be used to query the status of a
|
||||||
buffer at any time after buffers have been allocated with the
|
buffer at any time after buffers have been allocated with the
|
||||||
&VIDIOC-REQBUFS; ioctl.</para>
|
&VIDIOC-REQBUFS; ioctl.</para>
|
||||||
|
|
||||||
|
@ -71,6 +71,7 @@ the structure.</para>
|
||||||
|
|
||||||
<para>In the <structfield>flags</structfield> field the
|
<para>In the <structfield>flags</structfield> field the
|
||||||
<constant>V4L2_BUF_FLAG_MAPPED</constant>,
|
<constant>V4L2_BUF_FLAG_MAPPED</constant>,
|
||||||
|
<constant>V4L2_BUF_FLAG_PREPARED</constant>,
|
||||||
<constant>V4L2_BUF_FLAG_QUEUED</constant> and
|
<constant>V4L2_BUF_FLAG_QUEUED</constant> and
|
||||||
<constant>V4L2_BUF_FLAG_DONE</constant> flags will be valid. The
|
<constant>V4L2_BUF_FLAG_DONE</constant> flags will be valid. The
|
||||||
<structfield>memory</structfield> field will be set to the current
|
<structfield>memory</structfield> field will be set to the current
|
||||||
|
@ -79,8 +80,10 @@ contains the offset of the buffer from the start of the device memory,
|
||||||
the <structfield>length</structfield> field its size. For the multi-planar API,
|
the <structfield>length</structfield> field its size. For the multi-planar API,
|
||||||
fields <structfield>m.mem_offset</structfield> and
|
fields <structfield>m.mem_offset</structfield> and
|
||||||
<structfield>length</structfield> in the <structfield>m.planes</structfield>
|
<structfield>length</structfield> in the <structfield>m.planes</structfield>
|
||||||
array elements will be used instead. The driver may or may not set the remaining
|
array elements will be used instead and the <structfield>length</structfield>
|
||||||
fields and flags, they are meaningless in this context.</para>
|
field of &v4l2-buffer; is set to the number of filled-in array elements.
|
||||||
|
The driver may or may not set the remaining fields and flags, they are
|
||||||
|
meaningless in this context.</para>
|
||||||
|
|
||||||
<para>The <structname>v4l2_buffer</structname> structure is
|
<para>The <structname>v4l2_buffer</structname> structure is
|
||||||
specified in <xref linkend="buffer" />.</para>
|
specified in <xref linkend="buffer" />.</para>
|
||||||
|
|
|
@ -136,11 +136,25 @@ Or alternatively for integer menu controls, by calling v4l2_ctrl_new_int_menu:
|
||||||
const struct v4l2_ctrl_ops *ops,
|
const struct v4l2_ctrl_ops *ops,
|
||||||
u32 id, s32 max, s32 def, const s64 *qmenu_int);
|
u32 id, s32 max, s32 def, const s64 *qmenu_int);
|
||||||
|
|
||||||
|
Standard menu controls with a driver specific menu are added by calling
|
||||||
|
v4l2_ctrl_new_std_menu_items:
|
||||||
|
|
||||||
|
struct v4l2_ctrl *v4l2_ctrl_new_std_menu_items(
|
||||||
|
struct v4l2_ctrl_handler *hdl,
|
||||||
|
const struct v4l2_ctrl_ops *ops, u32 id, s32 max,
|
||||||
|
s32 skip_mask, s32 def, const char * const *qmenu);
|
||||||
|
|
||||||
These functions are typically called right after the v4l2_ctrl_handler_init:
|
These functions are typically called right after the v4l2_ctrl_handler_init:
|
||||||
|
|
||||||
static const s64 exp_bias_qmenu[] = {
|
static const s64 exp_bias_qmenu[] = {
|
||||||
-2, -1, 0, 1, 2
|
-2, -1, 0, 1, 2
|
||||||
};
|
};
|
||||||
|
static const char * const test_pattern[] = {
|
||||||
|
"Disabled",
|
||||||
|
"Vertical Bars",
|
||||||
|
"Solid Black",
|
||||||
|
"Solid White",
|
||||||
|
};
|
||||||
|
|
||||||
v4l2_ctrl_handler_init(&foo->ctrl_handler, nr_of_controls);
|
v4l2_ctrl_handler_init(&foo->ctrl_handler, nr_of_controls);
|
||||||
v4l2_ctrl_new_std(&foo->ctrl_handler, &foo_ctrl_ops,
|
v4l2_ctrl_new_std(&foo->ctrl_handler, &foo_ctrl_ops,
|
||||||
|
@ -156,6 +170,9 @@ These functions are typically called right after the v4l2_ctrl_handler_init:
|
||||||
ARRAY_SIZE(exp_bias_qmenu) - 1,
|
ARRAY_SIZE(exp_bias_qmenu) - 1,
|
||||||
ARRAY_SIZE(exp_bias_qmenu) / 2 - 1,
|
ARRAY_SIZE(exp_bias_qmenu) / 2 - 1,
|
||||||
exp_bias_qmenu);
|
exp_bias_qmenu);
|
||||||
|
v4l2_ctrl_new_std_menu_items(&foo->ctrl_handler, &foo_ctrl_ops,
|
||||||
|
V4L2_CID_TEST_PATTERN, ARRAY_SIZE(test_pattern) - 1, 0,
|
||||||
|
0, test_pattern);
|
||||||
...
|
...
|
||||||
if (foo->ctrl_handler.error) {
|
if (foo->ctrl_handler.error) {
|
||||||
int err = foo->ctrl_handler.error;
|
int err = foo->ctrl_handler.error;
|
||||||
|
@ -185,6 +202,13 @@ v4l2_ctrl_new_std_menu in that it doesn't have the mask argument and takes
|
||||||
as the last argument an array of signed 64-bit integers that form an exact
|
as the last argument an array of signed 64-bit integers that form an exact
|
||||||
menu item list.
|
menu item list.
|
||||||
|
|
||||||
|
The v4l2_ctrl_new_std_menu_items function is very similar to
|
||||||
|
v4l2_ctrl_new_std_menu but takes an extra parameter qmenu, which is the driver
|
||||||
|
specific menu for an otherwise standard menu control. A good example for this
|
||||||
|
control is the test pattern control for capture/display/sensors devices that
|
||||||
|
have the capability to generate test patterns. These test patterns are hardware
|
||||||
|
specific, so the contents of the menu will vary from device to device.
|
||||||
|
|
||||||
Note that if something fails, the function will return NULL or an error and
|
Note that if something fails, the function will return NULL or an error and
|
||||||
set ctrl_handler->error to the error code. If ctrl_handler->error was already
|
set ctrl_handler->error to the error code. If ctrl_handler->error was already
|
||||||
set, then it will just return and do nothing. This is also true for
|
set, then it will just return and do nothing. This is also true for
|
||||||
|
|
|
@ -186,6 +186,13 @@ config DA850_UI_RMII
|
||||||
NOTE: Please take care while choosing this option, MII PHY will
|
NOTE: Please take care while choosing this option, MII PHY will
|
||||||
not be functional if RMII mode is selected.
|
not be functional if RMII mode is selected.
|
||||||
|
|
||||||
|
config DA850_UI_SD_VIDEO_PORT
|
||||||
|
bool "Video Port Interface"
|
||||||
|
help
|
||||||
|
Say Y if you want to use Video Port Interface (VPIF) on the
|
||||||
|
DA850/OMAP-L138 EVM. The Video decoders/encoders are found on the
|
||||||
|
UI daughter card that is supplied with the EVM.
|
||||||
|
|
||||||
endchoice
|
endchoice
|
||||||
|
|
||||||
config DA850_WL12XX
|
config DA850_WL12XX
|
||||||
|
|
|
@ -45,6 +45,9 @@
|
||||||
#include <linux/platform_data/mtd-davinci-aemif.h>
|
#include <linux/platform_data/mtd-davinci-aemif.h>
|
||||||
#include <linux/platform_data/spi-davinci.h>
|
#include <linux/platform_data/spi-davinci.h>
|
||||||
|
|
||||||
|
#include <media/tvp514x.h>
|
||||||
|
#include <media/adv7343.h>
|
||||||
|
|
||||||
#define DA850_EVM_PHY_ID "davinci_mdio-0:00"
|
#define DA850_EVM_PHY_ID "davinci_mdio-0:00"
|
||||||
#define DA850_LCD_PWR_PIN GPIO_TO_PIN(2, 8)
|
#define DA850_LCD_PWR_PIN GPIO_TO_PIN(2, 8)
|
||||||
#define DA850_LCD_BL_PIN GPIO_TO_PIN(2, 15)
|
#define DA850_LCD_BL_PIN GPIO_TO_PIN(2, 15)
|
||||||
|
@ -452,6 +455,15 @@ static void da850_evm_ui_keys_init(unsigned gpio)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#ifdef CONFIG_DA850_UI_SD_VIDEO_PORT
|
||||||
|
static inline void da850_evm_setup_video_port(int video_sel)
|
||||||
|
{
|
||||||
|
gpio_set_value_cansleep(video_sel, 0);
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
static inline void da850_evm_setup_video_port(int video_sel) { }
|
||||||
|
#endif
|
||||||
|
|
||||||
static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio,
|
static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio,
|
||||||
unsigned ngpio, void *c)
|
unsigned ngpio, void *c)
|
||||||
{
|
{
|
||||||
|
@ -497,6 +509,8 @@ static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio,
|
||||||
|
|
||||||
da850_evm_setup_emac_rmii(sel_a);
|
da850_evm_setup_emac_rmii(sel_a);
|
||||||
|
|
||||||
|
da850_evm_setup_video_port(sel_c);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
exp_setup_keys_fail:
|
exp_setup_keys_fail:
|
||||||
|
@ -1149,6 +1163,169 @@ static __init int da850_evm_init_cpufreq(void)
|
||||||
static __init int da850_evm_init_cpufreq(void) { return 0; }
|
static __init int da850_evm_init_cpufreq(void) { return 0; }
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_DA850_UI_SD_VIDEO_PORT)
|
||||||
|
|
||||||
|
#define TVP5147_CH0 "tvp514x-0"
|
||||||
|
#define TVP5147_CH1 "tvp514x-1"
|
||||||
|
|
||||||
|
/* VPIF capture configuration */
|
||||||
|
static struct tvp514x_platform_data tvp5146_pdata = {
|
||||||
|
.clk_polarity = 0,
|
||||||
|
.hs_polarity = 1,
|
||||||
|
.vs_polarity = 1,
|
||||||
|
};
|
||||||
|
|
||||||
|
#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
|
||||||
|
|
||||||
|
static const struct vpif_input da850_ch0_inputs[] = {
|
||||||
|
{
|
||||||
|
.input = {
|
||||||
|
.index = 0,
|
||||||
|
.name = "Composite",
|
||||||
|
.type = V4L2_INPUT_TYPE_CAMERA,
|
||||||
|
.capabilities = V4L2_IN_CAP_STD,
|
||||||
|
.std = TVP514X_STD_ALL,
|
||||||
|
},
|
||||||
|
.input_route = INPUT_CVBS_VI2B,
|
||||||
|
.output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC,
|
||||||
|
.subdev_name = TVP5147_CH0,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct vpif_input da850_ch1_inputs[] = {
|
||||||
|
{
|
||||||
|
.input = {
|
||||||
|
.index = 0,
|
||||||
|
.name = "S-Video",
|
||||||
|
.type = V4L2_INPUT_TYPE_CAMERA,
|
||||||
|
.capabilities = V4L2_IN_CAP_STD,
|
||||||
|
.std = TVP514X_STD_ALL,
|
||||||
|
},
|
||||||
|
.input_route = INPUT_SVIDEO_VI2C_VI1C,
|
||||||
|
.output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC,
|
||||||
|
.subdev_name = TVP5147_CH1,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct vpif_subdev_info da850_vpif_capture_sdev_info[] = {
|
||||||
|
{
|
||||||
|
.name = TVP5147_CH0,
|
||||||
|
.board_info = {
|
||||||
|
I2C_BOARD_INFO("tvp5146", 0x5d),
|
||||||
|
.platform_data = &tvp5146_pdata,
|
||||||
|
},
|
||||||
|
},
|
||||||
|
{
|
||||||
|
.name = TVP5147_CH1,
|
||||||
|
.board_info = {
|
||||||
|
I2C_BOARD_INFO("tvp5146", 0x5c),
|
||||||
|
.platform_data = &tvp5146_pdata,
|
||||||
|
},
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct vpif_capture_config da850_vpif_capture_config = {
|
||||||
|
.subdev_info = da850_vpif_capture_sdev_info,
|
||||||
|
.subdev_count = ARRAY_SIZE(da850_vpif_capture_sdev_info),
|
||||||
|
.chan_config[0] = {
|
||||||
|
.inputs = da850_ch0_inputs,
|
||||||
|
.input_count = ARRAY_SIZE(da850_ch0_inputs),
|
||||||
|
.vpif_if = {
|
||||||
|
.if_type = VPIF_IF_BT656,
|
||||||
|
.hd_pol = 1,
|
||||||
|
.vd_pol = 1,
|
||||||
|
.fid_pol = 0,
|
||||||
|
},
|
||||||
|
},
|
||||||
|
.chan_config[1] = {
|
||||||
|
.inputs = da850_ch1_inputs,
|
||||||
|
.input_count = ARRAY_SIZE(da850_ch1_inputs),
|
||||||
|
.vpif_if = {
|
||||||
|
.if_type = VPIF_IF_BT656,
|
||||||
|
.hd_pol = 1,
|
||||||
|
.vd_pol = 1,
|
||||||
|
.fid_pol = 0,
|
||||||
|
},
|
||||||
|
},
|
||||||
|
.card_name = "DA850/OMAP-L138 Video Capture",
|
||||||
|
};
|
||||||
|
|
||||||
|
/* VPIF display configuration */
|
||||||
|
static struct vpif_subdev_info da850_vpif_subdev[] = {
|
||||||
|
{
|
||||||
|
.name = "adv7343",
|
||||||
|
.board_info = {
|
||||||
|
I2C_BOARD_INFO("adv7343", 0x2a),
|
||||||
|
},
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct vpif_output da850_ch0_outputs[] = {
|
||||||
|
{
|
||||||
|
.output = {
|
||||||
|
.index = 0,
|
||||||
|
.name = "Composite",
|
||||||
|
.type = V4L2_OUTPUT_TYPE_ANALOG,
|
||||||
|
.capabilities = V4L2_OUT_CAP_STD,
|
||||||
|
.std = V4L2_STD_ALL,
|
||||||
|
},
|
||||||
|
.subdev_name = "adv7343",
|
||||||
|
.output_route = ADV7343_COMPOSITE_ID,
|
||||||
|
},
|
||||||
|
{
|
||||||
|
.output = {
|
||||||
|
.index = 1,
|
||||||
|
.name = "S-Video",
|
||||||
|
.type = V4L2_OUTPUT_TYPE_ANALOG,
|
||||||
|
.capabilities = V4L2_OUT_CAP_STD,
|
||||||
|
.std = V4L2_STD_ALL,
|
||||||
|
},
|
||||||
|
.subdev_name = "adv7343",
|
||||||
|
.output_route = ADV7343_SVIDEO_ID,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct vpif_display_config da850_vpif_display_config = {
|
||||||
|
.subdevinfo = da850_vpif_subdev,
|
||||||
|
.subdev_count = ARRAY_SIZE(da850_vpif_subdev),
|
||||||
|
.chan_config[0] = {
|
||||||
|
.outputs = da850_ch0_outputs,
|
||||||
|
.output_count = ARRAY_SIZE(da850_ch0_outputs),
|
||||||
|
},
|
||||||
|
.card_name = "DA850/OMAP-L138 Video Display",
|
||||||
|
};
|
||||||
|
|
||||||
|
static __init void da850_vpif_init(void)
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
ret = da850_register_vpif();
|
||||||
|
if (ret)
|
||||||
|
pr_warn("da850_evm_init: VPIF setup failed: %d\n", ret);
|
||||||
|
|
||||||
|
ret = davinci_cfg_reg_list(da850_vpif_capture_pins);
|
||||||
|
if (ret)
|
||||||
|
pr_warn("da850_evm_init: VPIF capture mux setup failed: %d\n",
|
||||||
|
ret);
|
||||||
|
|
||||||
|
ret = da850_register_vpif_capture(&da850_vpif_capture_config);
|
||||||
|
if (ret)
|
||||||
|
pr_warn("da850_evm_init: VPIF capture setup failed: %d\n", ret);
|
||||||
|
|
||||||
|
ret = davinci_cfg_reg_list(da850_vpif_display_pins);
|
||||||
|
if (ret)
|
||||||
|
pr_warn("da850_evm_init: VPIF display mux setup failed: %d\n",
|
||||||
|
ret);
|
||||||
|
|
||||||
|
ret = da850_register_vpif_display(&da850_vpif_display_config);
|
||||||
|
if (ret)
|
||||||
|
pr_warn("da850_evm_init: VPIF display setup failed: %d\n", ret);
|
||||||
|
}
|
||||||
|
|
||||||
|
#else
|
||||||
|
static __init void da850_vpif_init(void) {}
|
||||||
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_DA850_WL12XX
|
#ifdef CONFIG_DA850_WL12XX
|
||||||
|
|
||||||
static void wl12xx_set_power(int index, bool power_on)
|
static void wl12xx_set_power(int index, bool power_on)
|
||||||
|
@ -1375,6 +1552,8 @@ static __init void da850_evm_init(void)
|
||||||
pr_warning("da850_evm_init: suspend registration failed: %d\n",
|
pr_warning("da850_evm_init: suspend registration failed: %d\n",
|
||||||
ret);
|
ret);
|
||||||
|
|
||||||
|
da850_vpif_init();
|
||||||
|
|
||||||
ret = da8xx_register_spi(1, da850evm_spi_info,
|
ret = da8xx_register_spi(1, da850evm_spi_info,
|
||||||
ARRAY_SIZE(da850evm_spi_info));
|
ARRAY_SIZE(da850evm_spi_info));
|
||||||
if (ret)
|
if (ret)
|
||||||
|
|
|
@ -23,6 +23,7 @@
|
||||||
#include <linux/phy.h>
|
#include <linux/phy.h>
|
||||||
#include <linux/clk.h>
|
#include <linux/clk.h>
|
||||||
#include <linux/videodev2.h>
|
#include <linux/videodev2.h>
|
||||||
|
#include <linux/v4l2-dv-timings.h>
|
||||||
#include <linux/export.h>
|
#include <linux/export.h>
|
||||||
|
|
||||||
#include <media/tvp514x.h>
|
#include <media/tvp514x.h>
|
||||||
|
@ -620,7 +621,7 @@ static struct vpbe_enc_mode_info dm644xevm_enc_std_timing[] = {
|
||||||
{
|
{
|
||||||
.name = "ntsc",
|
.name = "ntsc",
|
||||||
.timings_type = VPBE_ENC_STD,
|
.timings_type = VPBE_ENC_STD,
|
||||||
.timings = {V4L2_STD_525_60},
|
.std_id = V4L2_STD_525_60,
|
||||||
.interlaced = 1,
|
.interlaced = 1,
|
||||||
.xres = 720,
|
.xres = 720,
|
||||||
.yres = 480,
|
.yres = 480,
|
||||||
|
@ -632,7 +633,7 @@ static struct vpbe_enc_mode_info dm644xevm_enc_std_timing[] = {
|
||||||
{
|
{
|
||||||
.name = "pal",
|
.name = "pal",
|
||||||
.timings_type = VPBE_ENC_STD,
|
.timings_type = VPBE_ENC_STD,
|
||||||
.timings = {V4L2_STD_625_50},
|
.std_id = V4L2_STD_625_50,
|
||||||
.interlaced = 1,
|
.interlaced = 1,
|
||||||
.xres = 720,
|
.xres = 720,
|
||||||
.yres = 576,
|
.yres = 576,
|
||||||
|
@ -647,8 +648,8 @@ static struct vpbe_enc_mode_info dm644xevm_enc_std_timing[] = {
|
||||||
static struct vpbe_enc_mode_info dm644xevm_enc_preset_timing[] = {
|
static struct vpbe_enc_mode_info dm644xevm_enc_preset_timing[] = {
|
||||||
{
|
{
|
||||||
.name = "480p59_94",
|
.name = "480p59_94",
|
||||||
.timings_type = VPBE_ENC_DV_PRESET,
|
.timings_type = VPBE_ENC_CUSTOM_TIMINGS,
|
||||||
.timings = {V4L2_DV_480P59_94},
|
.dv_timings = V4L2_DV_BT_CEA_720X480P59_94,
|
||||||
.interlaced = 0,
|
.interlaced = 0,
|
||||||
.xres = 720,
|
.xres = 720,
|
||||||
.yres = 480,
|
.yres = 480,
|
||||||
|
@ -659,8 +660,8 @@ static struct vpbe_enc_mode_info dm644xevm_enc_preset_timing[] = {
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
.name = "576p50",
|
.name = "576p50",
|
||||||
.timings_type = VPBE_ENC_DV_PRESET,
|
.timings_type = VPBE_ENC_CUSTOM_TIMINGS,
|
||||||
.timings = {V4L2_DV_576P50},
|
.dv_timings = V4L2_DV_BT_CEA_720X576P50,
|
||||||
.interlaced = 0,
|
.interlaced = 0,
|
||||||
.xres = 720,
|
.xres = 720,
|
||||||
.yres = 576,
|
.yres = 576,
|
||||||
|
@ -698,7 +699,7 @@ static struct vpbe_output dm644xevm_vpbe_outputs[] = {
|
||||||
.index = 1,
|
.index = 1,
|
||||||
.name = "Component",
|
.name = "Component",
|
||||||
.type = V4L2_OUTPUT_TYPE_ANALOG,
|
.type = V4L2_OUTPUT_TYPE_ANALOG,
|
||||||
.capabilities = V4L2_OUT_CAP_PRESETS,
|
.capabilities = V4L2_OUT_CAP_DV_TIMINGS,
|
||||||
},
|
},
|
||||||
.subdev_name = VPBE_VENC_SUBDEV_NAME,
|
.subdev_name = VPBE_VENC_SUBDEV_NAME,
|
||||||
.default_mode = "480p59_94",
|
.default_mode = "480p59_94",
|
||||||
|
|
|
@ -26,6 +26,7 @@
|
||||||
#include <linux/i2c/pcf857x.h>
|
#include <linux/i2c/pcf857x.h>
|
||||||
|
|
||||||
#include <media/tvp514x.h>
|
#include <media/tvp514x.h>
|
||||||
|
#include <media/adv7343.h>
|
||||||
|
|
||||||
#include <linux/mtd/mtd.h>
|
#include <linux/mtd/mtd.h>
|
||||||
#include <linux/mtd/nand.h>
|
#include <linux/mtd/nand.h>
|
||||||
|
@ -496,18 +497,49 @@ static struct vpif_subdev_info dm646x_vpif_subdev[] = {
|
||||||
},
|
},
|
||||||
};
|
};
|
||||||
|
|
||||||
static const char *output[] = {
|
static const struct vpif_output dm6467_ch0_outputs[] = {
|
||||||
"Composite",
|
{
|
||||||
"Component",
|
.output = {
|
||||||
"S-Video",
|
.index = 0,
|
||||||
|
.name = "Composite",
|
||||||
|
.type = V4L2_OUTPUT_TYPE_ANALOG,
|
||||||
|
.capabilities = V4L2_OUT_CAP_STD,
|
||||||
|
.std = V4L2_STD_ALL,
|
||||||
|
},
|
||||||
|
.subdev_name = "adv7343",
|
||||||
|
.output_route = ADV7343_COMPOSITE_ID,
|
||||||
|
},
|
||||||
|
{
|
||||||
|
.output = {
|
||||||
|
.index = 1,
|
||||||
|
.name = "Component",
|
||||||
|
.type = V4L2_OUTPUT_TYPE_ANALOG,
|
||||||
|
.capabilities = V4L2_OUT_CAP_CUSTOM_TIMINGS,
|
||||||
|
},
|
||||||
|
.subdev_name = "adv7343",
|
||||||
|
.output_route = ADV7343_COMPONENT_ID,
|
||||||
|
},
|
||||||
|
{
|
||||||
|
.output = {
|
||||||
|
.index = 2,
|
||||||
|
.name = "S-Video",
|
||||||
|
.type = V4L2_OUTPUT_TYPE_ANALOG,
|
||||||
|
.capabilities = V4L2_OUT_CAP_STD,
|
||||||
|
.std = V4L2_STD_ALL,
|
||||||
|
},
|
||||||
|
.subdev_name = "adv7343",
|
||||||
|
.output_route = ADV7343_SVIDEO_ID,
|
||||||
|
},
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct vpif_display_config dm646x_vpif_display_config = {
|
static struct vpif_display_config dm646x_vpif_display_config = {
|
||||||
.set_clock = set_vpif_clock,
|
.set_clock = set_vpif_clock,
|
||||||
.subdevinfo = dm646x_vpif_subdev,
|
.subdevinfo = dm646x_vpif_subdev,
|
||||||
.subdev_count = ARRAY_SIZE(dm646x_vpif_subdev),
|
.subdev_count = ARRAY_SIZE(dm646x_vpif_subdev),
|
||||||
.output = output,
|
.chan_config[0] = {
|
||||||
.output_count = ARRAY_SIZE(output),
|
.outputs = dm6467_ch0_outputs,
|
||||||
|
.output_count = ARRAY_SIZE(dm6467_ch0_outputs),
|
||||||
|
},
|
||||||
.card_name = "DM646x EVM",
|
.card_name = "DM646x EVM",
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -601,15 +633,6 @@ static struct vpif_subdev_info vpif_capture_sdev_info[] = {
|
||||||
I2C_BOARD_INFO("tvp5146", 0x5d),
|
I2C_BOARD_INFO("tvp5146", 0x5d),
|
||||||
.platform_data = &tvp5146_pdata,
|
.platform_data = &tvp5146_pdata,
|
||||||
},
|
},
|
||||||
.input = INPUT_CVBS_VI2B,
|
|
||||||
.output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
|
|
||||||
.can_route = 1,
|
|
||||||
.vpif_if = {
|
|
||||||
.if_type = VPIF_IF_BT656,
|
|
||||||
.hd_pol = 1,
|
|
||||||
.vd_pol = 1,
|
|
||||||
.fid_pol = 0,
|
|
||||||
},
|
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
.name = TVP5147_CH1,
|
.name = TVP5147_CH1,
|
||||||
|
@ -617,15 +640,6 @@ static struct vpif_subdev_info vpif_capture_sdev_info[] = {
|
||||||
I2C_BOARD_INFO("tvp5146", 0x5c),
|
I2C_BOARD_INFO("tvp5146", 0x5c),
|
||||||
.platform_data = &tvp5146_pdata,
|
.platform_data = &tvp5146_pdata,
|
||||||
},
|
},
|
||||||
.input = INPUT_SVIDEO_VI2C_VI1C,
|
|
||||||
.output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
|
|
||||||
.can_route = 1,
|
|
||||||
.vpif_if = {
|
|
||||||
.if_type = VPIF_IF_BT656,
|
|
||||||
.hd_pol = 1,
|
|
||||||
.vd_pol = 1,
|
|
||||||
.fid_pol = 0,
|
|
||||||
},
|
|
||||||
},
|
},
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -635,9 +649,12 @@ static const struct vpif_input dm6467_ch0_inputs[] = {
|
||||||
.index = 0,
|
.index = 0,
|
||||||
.name = "Composite",
|
.name = "Composite",
|
||||||
.type = V4L2_INPUT_TYPE_CAMERA,
|
.type = V4L2_INPUT_TYPE_CAMERA,
|
||||||
|
.capabilities = V4L2_IN_CAP_STD,
|
||||||
.std = TVP514X_STD_ALL,
|
.std = TVP514X_STD_ALL,
|
||||||
},
|
},
|
||||||
.subdev_name = TVP5147_CH0,
|
.subdev_name = TVP5147_CH0,
|
||||||
|
.input_route = INPUT_CVBS_VI2B,
|
||||||
|
.output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC,
|
||||||
},
|
},
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -647,9 +664,12 @@ static const struct vpif_input dm6467_ch1_inputs[] = {
|
||||||
.index = 0,
|
.index = 0,
|
||||||
.name = "S-Video",
|
.name = "S-Video",
|
||||||
.type = V4L2_INPUT_TYPE_CAMERA,
|
.type = V4L2_INPUT_TYPE_CAMERA,
|
||||||
|
.capabilities = V4L2_IN_CAP_STD,
|
||||||
.std = TVP514X_STD_ALL,
|
.std = TVP514X_STD_ALL,
|
||||||
},
|
},
|
||||||
.subdev_name = TVP5147_CH1,
|
.subdev_name = TVP5147_CH1,
|
||||||
|
.input_route = INPUT_SVIDEO_VI2C_VI1C,
|
||||||
|
.output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC,
|
||||||
},
|
},
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -661,10 +681,22 @@ static struct vpif_capture_config dm646x_vpif_capture_cfg = {
|
||||||
.chan_config[0] = {
|
.chan_config[0] = {
|
||||||
.inputs = dm6467_ch0_inputs,
|
.inputs = dm6467_ch0_inputs,
|
||||||
.input_count = ARRAY_SIZE(dm6467_ch0_inputs),
|
.input_count = ARRAY_SIZE(dm6467_ch0_inputs),
|
||||||
|
.vpif_if = {
|
||||||
|
.if_type = VPIF_IF_BT656,
|
||||||
|
.hd_pol = 1,
|
||||||
|
.vd_pol = 1,
|
||||||
|
.fid_pol = 0,
|
||||||
|
},
|
||||||
},
|
},
|
||||||
.chan_config[1] = {
|
.chan_config[1] = {
|
||||||
.inputs = dm6467_ch1_inputs,
|
.inputs = dm6467_ch1_inputs,
|
||||||
.input_count = ARRAY_SIZE(dm6467_ch1_inputs),
|
.input_count = ARRAY_SIZE(dm6467_ch1_inputs),
|
||||||
|
.vpif_if = {
|
||||||
|
.if_type = VPIF_IF_BT656,
|
||||||
|
.hd_pol = 1,
|
||||||
|
.vd_pol = 1,
|
||||||
|
.fid_pol = 0,
|
||||||
|
},
|
||||||
},
|
},
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
@ -347,6 +347,13 @@ static struct clk spi1_clk = {
|
||||||
.flags = DA850_CLK_ASYNC3,
|
.flags = DA850_CLK_ASYNC3,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static struct clk vpif_clk = {
|
||||||
|
.name = "vpif",
|
||||||
|
.parent = &pll0_sysclk2,
|
||||||
|
.lpsc = DA850_LPSC1_VPIF,
|
||||||
|
.gpsc = 1,
|
||||||
|
};
|
||||||
|
|
||||||
static struct clk sata_clk = {
|
static struct clk sata_clk = {
|
||||||
.name = "sata",
|
.name = "sata",
|
||||||
.parent = &pll0_sysclk2,
|
.parent = &pll0_sysclk2,
|
||||||
|
@ -397,6 +404,7 @@ static struct clk_lookup da850_clks[] = {
|
||||||
CLK(NULL, "usb20", &usb20_clk),
|
CLK(NULL, "usb20", &usb20_clk),
|
||||||
CLK("spi_davinci.0", NULL, &spi0_clk),
|
CLK("spi_davinci.0", NULL, &spi0_clk),
|
||||||
CLK("spi_davinci.1", NULL, &spi1_clk),
|
CLK("spi_davinci.1", NULL, &spi1_clk),
|
||||||
|
CLK("vpif", NULL, &vpif_clk),
|
||||||
CLK("ahci", NULL, &sata_clk),
|
CLK("ahci", NULL, &sata_clk),
|
||||||
CLK(NULL, NULL, NULL),
|
CLK(NULL, NULL, NULL),
|
||||||
};
|
};
|
||||||
|
@ -573,6 +581,46 @@ static const struct mux_config da850_pins[] = {
|
||||||
MUX_CFG(DA850, GPIO6_10, 13, 20, 15, 8, false)
|
MUX_CFG(DA850, GPIO6_10, 13, 20, 15, 8, false)
|
||||||
MUX_CFG(DA850, GPIO6_13, 13, 8, 15, 8, false)
|
MUX_CFG(DA850, GPIO6_13, 13, 8, 15, 8, false)
|
||||||
MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false)
|
MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false)
|
||||||
|
/* VPIF Capture */
|
||||||
|
MUX_CFG(DA850, VPIF_DIN0, 15, 4, 15, 1, false)
|
||||||
|
MUX_CFG(DA850, VPIF_DIN1, 15, 0, 15, 1, false)
|
||||||
|
MUX_CFG(DA850, VPIF_DIN2, 14, 28, 15, 1, false)
|
||||||
|
MUX_CFG(DA850, VPIF_DIN3, 14, 24, 15, 1, false)
|
||||||
|
MUX_CFG(DA850, VPIF_DIN4, 14, 20, 15, 1, false)
|
||||||
|
MUX_CFG(DA850, VPIF_DIN5, 14, 16, 15, 1, false)
|
||||||
|
MUX_CFG(DA850, VPIF_DIN6, 14, 12, 15, 1, false)
|
||||||
|
MUX_CFG(DA850, VPIF_DIN7, 14, 8, 15, 1, false)
|
||||||
|
MUX_CFG(DA850, VPIF_DIN8, 16, 4, 15, 1, false)
|
||||||
|
MUX_CFG(DA850, VPIF_DIN9, 16, 0, 15, 1, false)
|
||||||
|
MUX_CFG(DA850, VPIF_DIN10, 15, 28, 15, 1, false)
|
||||||
|
MUX_CFG(DA850, VPIF_DIN11, 15, 24, 15, 1, false)
|
||||||
|
MUX_CFG(DA850, VPIF_DIN12, 15, 20, 15, 1, false)
|
||||||
|
MUX_CFG(DA850, VPIF_DIN13, 15, 16, 15, 1, false)
|
||||||
|
MUX_CFG(DA850, VPIF_DIN14, 15, 12, 15, 1, false)
|
||||||
|
MUX_CFG(DA850, VPIF_DIN15, 15, 8, 15, 1, false)
|
||||||
|
MUX_CFG(DA850, VPIF_CLKIN0, 14, 0, 15, 1, false)
|
||||||
|
MUX_CFG(DA850, VPIF_CLKIN1, 14, 4, 15, 1, false)
|
||||||
|
MUX_CFG(DA850, VPIF_CLKIN2, 19, 8, 15, 1, false)
|
||||||
|
MUX_CFG(DA850, VPIF_CLKIN3, 19, 16, 15, 1, false)
|
||||||
|
/* VPIF Display */
|
||||||
|
MUX_CFG(DA850, VPIF_DOUT0, 17, 4, 15, 1, false)
|
||||||
|
MUX_CFG(DA850, VPIF_DOUT1, 17, 0, 15, 1, false)
|
||||||
|
MUX_CFG(DA850, VPIF_DOUT2, 16, 28, 15, 1, false)
|
||||||
|
MUX_CFG(DA850, VPIF_DOUT3, 16, 24, 15, 1, false)
|
||||||
|
MUX_CFG(DA850, VPIF_DOUT4, 16, 20, 15, 1, false)
|
||||||
|
MUX_CFG(DA850, VPIF_DOUT5, 16, 16, 15, 1, false)
|
||||||
|
MUX_CFG(DA850, VPIF_DOUT6, 16, 12, 15, 1, false)
|
||||||
|
MUX_CFG(DA850, VPIF_DOUT7, 16, 8, 15, 1, false)
|
||||||
|
MUX_CFG(DA850, VPIF_DOUT8, 18, 4, 15, 1, false)
|
||||||
|
MUX_CFG(DA850, VPIF_DOUT9, 18, 0, 15, 1, false)
|
||||||
|
MUX_CFG(DA850, VPIF_DOUT10, 17, 28, 15, 1, false)
|
||||||
|
MUX_CFG(DA850, VPIF_DOUT11, 17, 24, 15, 1, false)
|
||||||
|
MUX_CFG(DA850, VPIF_DOUT12, 17, 20, 15, 1, false)
|
||||||
|
MUX_CFG(DA850, VPIF_DOUT13, 17, 16, 15, 1, false)
|
||||||
|
MUX_CFG(DA850, VPIF_DOUT14, 17, 12, 15, 1, false)
|
||||||
|
MUX_CFG(DA850, VPIF_DOUT15, 17, 8, 15, 1, false)
|
||||||
|
MUX_CFG(DA850, VPIF_CLKO2, 19, 12, 15, 1, false)
|
||||||
|
MUX_CFG(DA850, VPIF_CLKO3, 19, 20, 15, 1, false)
|
||||||
#endif
|
#endif
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -595,6 +643,26 @@ const short da850_lcdcntl_pins[] __initconst = {
|
||||||
-1
|
-1
|
||||||
};
|
};
|
||||||
|
|
||||||
|
const short da850_vpif_capture_pins[] __initdata = {
|
||||||
|
DA850_VPIF_DIN0, DA850_VPIF_DIN1, DA850_VPIF_DIN2, DA850_VPIF_DIN3,
|
||||||
|
DA850_VPIF_DIN4, DA850_VPIF_DIN5, DA850_VPIF_DIN6, DA850_VPIF_DIN7,
|
||||||
|
DA850_VPIF_DIN8, DA850_VPIF_DIN9, DA850_VPIF_DIN10, DA850_VPIF_DIN11,
|
||||||
|
DA850_VPIF_DIN12, DA850_VPIF_DIN13, DA850_VPIF_DIN14, DA850_VPIF_DIN15,
|
||||||
|
DA850_VPIF_CLKIN0, DA850_VPIF_CLKIN1, DA850_VPIF_CLKIN2,
|
||||||
|
DA850_VPIF_CLKIN3,
|
||||||
|
-1
|
||||||
|
};
|
||||||
|
|
||||||
|
const short da850_vpif_display_pins[] __initdata = {
|
||||||
|
DA850_VPIF_DOUT0, DA850_VPIF_DOUT1, DA850_VPIF_DOUT2, DA850_VPIF_DOUT3,
|
||||||
|
DA850_VPIF_DOUT4, DA850_VPIF_DOUT5, DA850_VPIF_DOUT6, DA850_VPIF_DOUT7,
|
||||||
|
DA850_VPIF_DOUT8, DA850_VPIF_DOUT9, DA850_VPIF_DOUT10,
|
||||||
|
DA850_VPIF_DOUT11, DA850_VPIF_DOUT12, DA850_VPIF_DOUT13,
|
||||||
|
DA850_VPIF_DOUT14, DA850_VPIF_DOUT15, DA850_VPIF_CLKO2,
|
||||||
|
DA850_VPIF_CLKO3,
|
||||||
|
-1
|
||||||
|
};
|
||||||
|
|
||||||
/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
|
/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
|
||||||
static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
|
static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
|
||||||
[IRQ_DA8XX_COMMTX] = 7,
|
[IRQ_DA8XX_COMMTX] = 7,
|
||||||
|
@ -1064,6 +1132,90 @@ int __init da850_register_pm(struct platform_device *pdev)
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/* VPIF resource, platform data */
|
||||||
|
static u64 da850_vpif_dma_mask = DMA_BIT_MASK(32);
|
||||||
|
|
||||||
|
static struct resource da850_vpif_resource[] = {
|
||||||
|
{
|
||||||
|
.start = DA8XX_VPIF_BASE,
|
||||||
|
.end = DA8XX_VPIF_BASE + 0xfff,
|
||||||
|
.flags = IORESOURCE_MEM,
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct platform_device da850_vpif_dev = {
|
||||||
|
.name = "vpif",
|
||||||
|
.id = -1,
|
||||||
|
.dev = {
|
||||||
|
.dma_mask = &da850_vpif_dma_mask,
|
||||||
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||||
|
},
|
||||||
|
.resource = da850_vpif_resource,
|
||||||
|
.num_resources = ARRAY_SIZE(da850_vpif_resource),
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct resource da850_vpif_display_resource[] = {
|
||||||
|
{
|
||||||
|
.start = IRQ_DA850_VPIFINT,
|
||||||
|
.end = IRQ_DA850_VPIFINT,
|
||||||
|
.flags = IORESOURCE_IRQ,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct platform_device da850_vpif_display_dev = {
|
||||||
|
.name = "vpif_display",
|
||||||
|
.id = -1,
|
||||||
|
.dev = {
|
||||||
|
.dma_mask = &da850_vpif_dma_mask,
|
||||||
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||||
|
},
|
||||||
|
.resource = da850_vpif_display_resource,
|
||||||
|
.num_resources = ARRAY_SIZE(da850_vpif_display_resource),
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct resource da850_vpif_capture_resource[] = {
|
||||||
|
{
|
||||||
|
.start = IRQ_DA850_VPIFINT,
|
||||||
|
.end = IRQ_DA850_VPIFINT,
|
||||||
|
.flags = IORESOURCE_IRQ,
|
||||||
|
},
|
||||||
|
{
|
||||||
|
.start = IRQ_DA850_VPIFINT,
|
||||||
|
.end = IRQ_DA850_VPIFINT,
|
||||||
|
.flags = IORESOURCE_IRQ,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct platform_device da850_vpif_capture_dev = {
|
||||||
|
.name = "vpif_capture",
|
||||||
|
.id = -1,
|
||||||
|
.dev = {
|
||||||
|
.dma_mask = &da850_vpif_dma_mask,
|
||||||
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||||
|
},
|
||||||
|
.resource = da850_vpif_capture_resource,
|
||||||
|
.num_resources = ARRAY_SIZE(da850_vpif_capture_resource),
|
||||||
|
};
|
||||||
|
|
||||||
|
int __init da850_register_vpif(void)
|
||||||
|
{
|
||||||
|
return platform_device_register(&da850_vpif_dev);
|
||||||
|
}
|
||||||
|
|
||||||
|
int __init da850_register_vpif_display(struct vpif_display_config
|
||||||
|
*display_config)
|
||||||
|
{
|
||||||
|
da850_vpif_display_dev.dev.platform_data = display_config;
|
||||||
|
return platform_device_register(&da850_vpif_display_dev);
|
||||||
|
}
|
||||||
|
|
||||||
|
int __init da850_register_vpif_capture(struct vpif_capture_config
|
||||||
|
*capture_config)
|
||||||
|
{
|
||||||
|
da850_vpif_capture_dev.dev.platform_data = capture_config;
|
||||||
|
return platform_device_register(&da850_vpif_capture_dev);
|
||||||
|
}
|
||||||
|
|
||||||
static struct davinci_soc_info davinci_soc_info_da850 = {
|
static struct davinci_soc_info davinci_soc_info_da850 = {
|
||||||
.io_desc = da850_io_desc,
|
.io_desc = da850_io_desc,
|
||||||
.io_desc_num = ARRAY_SIZE(da850_io_desc),
|
.io_desc_num = ARRAY_SIZE(da850_io_desc),
|
||||||
|
|
|
@ -701,7 +701,7 @@ static struct resource dm644x_venc_resources[] = {
|
||||||
#define DM644X_VPSS_DACCLKEN BIT(4)
|
#define DM644X_VPSS_DACCLKEN BIT(4)
|
||||||
|
|
||||||
static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type,
|
static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type,
|
||||||
unsigned int mode)
|
unsigned int pclock)
|
||||||
{
|
{
|
||||||
int ret = 0;
|
int ret = 0;
|
||||||
u32 v = DM644X_VPSS_VENCLKEN;
|
u32 v = DM644X_VPSS_VENCLKEN;
|
||||||
|
@ -711,27 +711,18 @@ static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type,
|
||||||
v |= DM644X_VPSS_DACCLKEN;
|
v |= DM644X_VPSS_DACCLKEN;
|
||||||
writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
|
writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
|
||||||
break;
|
break;
|
||||||
case VPBE_ENC_DV_PRESET:
|
case VPBE_ENC_CUSTOM_TIMINGS:
|
||||||
switch (mode) {
|
if (pclock <= 27000000) {
|
||||||
case V4L2_DV_480P59_94:
|
|
||||||
case V4L2_DV_576P50:
|
|
||||||
v |= DM644X_VPSS_MUXSEL_PLL2_MODE |
|
v |= DM644X_VPSS_MUXSEL_PLL2_MODE |
|
||||||
DM644X_VPSS_DACCLKEN;
|
DM644X_VPSS_DACCLKEN;
|
||||||
writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
|
writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
|
||||||
break;
|
} else {
|
||||||
case V4L2_DV_720P60:
|
|
||||||
case V4L2_DV_1080I60:
|
|
||||||
case V4L2_DV_1080P30:
|
|
||||||
/*
|
/*
|
||||||
* For HD, use external clock source since
|
* For HD, use external clock source since
|
||||||
* HD requires higher clock rate
|
* HD requires higher clock rate
|
||||||
*/
|
*/
|
||||||
v |= DM644X_VPSS_MUXSEL_VPBECLK_MODE;
|
v |= DM644X_VPSS_MUXSEL_VPBECLK_MODE;
|
||||||
writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
|
writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
|
||||||
break;
|
|
||||||
default:
|
|
||||||
ret = -EINVAL;
|
|
||||||
break;
|
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
|
|
|
@ -16,6 +16,7 @@
|
||||||
#include <linux/platform_device.h>
|
#include <linux/platform_device.h>
|
||||||
#include <linux/davinci_emac.h>
|
#include <linux/davinci_emac.h>
|
||||||
#include <linux/spi/spi.h>
|
#include <linux/spi/spi.h>
|
||||||
|
#include <linux/videodev2.h>
|
||||||
|
|
||||||
#include <mach/serial.h>
|
#include <mach/serial.h>
|
||||||
#include <mach/edma.h>
|
#include <mach/edma.h>
|
||||||
|
@ -26,6 +27,8 @@
|
||||||
#include <linux/platform_data/usb-davinci.h>
|
#include <linux/platform_data/usb-davinci.h>
|
||||||
#include <linux/platform_data/spi-davinci.h>
|
#include <linux/platform_data/spi-davinci.h>
|
||||||
|
|
||||||
|
#include <media/davinci/vpif_types.h>
|
||||||
|
|
||||||
extern void __iomem *da8xx_syscfg0_base;
|
extern void __iomem *da8xx_syscfg0_base;
|
||||||
extern void __iomem *da8xx_syscfg1_base;
|
extern void __iomem *da8xx_syscfg1_base;
|
||||||
|
|
||||||
|
@ -63,6 +66,7 @@ extern unsigned int da850_max_speed;
|
||||||
#define DA8XX_PLL0_BASE 0x01c11000
|
#define DA8XX_PLL0_BASE 0x01c11000
|
||||||
#define DA8XX_TIMER64P0_BASE 0x01c20000
|
#define DA8XX_TIMER64P0_BASE 0x01c20000
|
||||||
#define DA8XX_TIMER64P1_BASE 0x01c21000
|
#define DA8XX_TIMER64P1_BASE 0x01c21000
|
||||||
|
#define DA8XX_VPIF_BASE 0x01e17000
|
||||||
#define DA8XX_GPIO_BASE 0x01e26000
|
#define DA8XX_GPIO_BASE 0x01e26000
|
||||||
#define DA8XX_PSC1_BASE 0x01e27000
|
#define DA8XX_PSC1_BASE 0x01e27000
|
||||||
#define DA8XX_AEMIF_CS2_BASE 0x60000000
|
#define DA8XX_AEMIF_CS2_BASE 0x60000000
|
||||||
|
@ -92,6 +96,11 @@ int da8xx_register_cpuidle(void);
|
||||||
void __iomem * __init da8xx_get_mem_ctlr(void);
|
void __iomem * __init da8xx_get_mem_ctlr(void);
|
||||||
int da850_register_pm(struct platform_device *pdev);
|
int da850_register_pm(struct platform_device *pdev);
|
||||||
int __init da850_register_sata(unsigned long refclkpn);
|
int __init da850_register_sata(unsigned long refclkpn);
|
||||||
|
int __init da850_register_vpif(void);
|
||||||
|
int __init da850_register_vpif_display
|
||||||
|
(struct vpif_display_config *display_config);
|
||||||
|
int __init da850_register_vpif_capture
|
||||||
|
(struct vpif_capture_config *capture_config);
|
||||||
void da8xx_restart(char mode, const char *cmd);
|
void da8xx_restart(char mode, const char *cmd);
|
||||||
|
|
||||||
extern struct platform_device da8xx_serial_device;
|
extern struct platform_device da8xx_serial_device;
|
||||||
|
@ -126,6 +135,8 @@ extern const short da830_ecap1_pins[];
|
||||||
extern const short da830_ecap2_pins[];
|
extern const short da830_ecap2_pins[];
|
||||||
extern const short da830_eqep0_pins[];
|
extern const short da830_eqep0_pins[];
|
||||||
extern const short da830_eqep1_pins[];
|
extern const short da830_eqep1_pins[];
|
||||||
|
extern const short da850_vpif_capture_pins[];
|
||||||
|
extern const short da850_vpif_display_pins[];
|
||||||
|
|
||||||
extern const short da850_i2c0_pins[];
|
extern const short da850_i2c0_pins[];
|
||||||
extern const short da850_i2c1_pins[];
|
extern const short da850_i2c1_pins[];
|
||||||
|
|
|
@ -928,6 +928,48 @@ enum davinci_da850_index {
|
||||||
DA850_GPIO6_10,
|
DA850_GPIO6_10,
|
||||||
DA850_GPIO6_13,
|
DA850_GPIO6_13,
|
||||||
DA850_RTC_ALARM,
|
DA850_RTC_ALARM,
|
||||||
|
|
||||||
|
/* VPIF Capture */
|
||||||
|
DA850_VPIF_DIN0,
|
||||||
|
DA850_VPIF_DIN1,
|
||||||
|
DA850_VPIF_DIN2,
|
||||||
|
DA850_VPIF_DIN3,
|
||||||
|
DA850_VPIF_DIN4,
|
||||||
|
DA850_VPIF_DIN5,
|
||||||
|
DA850_VPIF_DIN6,
|
||||||
|
DA850_VPIF_DIN7,
|
||||||
|
DA850_VPIF_DIN8,
|
||||||
|
DA850_VPIF_DIN9,
|
||||||
|
DA850_VPIF_DIN10,
|
||||||
|
DA850_VPIF_DIN11,
|
||||||
|
DA850_VPIF_DIN12,
|
||||||
|
DA850_VPIF_DIN13,
|
||||||
|
DA850_VPIF_DIN14,
|
||||||
|
DA850_VPIF_DIN15,
|
||||||
|
DA850_VPIF_CLKIN0,
|
||||||
|
DA850_VPIF_CLKIN1,
|
||||||
|
DA850_VPIF_CLKIN2,
|
||||||
|
DA850_VPIF_CLKIN3,
|
||||||
|
|
||||||
|
/* VPIF Display */
|
||||||
|
DA850_VPIF_DOUT0,
|
||||||
|
DA850_VPIF_DOUT1,
|
||||||
|
DA850_VPIF_DOUT2,
|
||||||
|
DA850_VPIF_DOUT3,
|
||||||
|
DA850_VPIF_DOUT4,
|
||||||
|
DA850_VPIF_DOUT5,
|
||||||
|
DA850_VPIF_DOUT6,
|
||||||
|
DA850_VPIF_DOUT7,
|
||||||
|
DA850_VPIF_DOUT8,
|
||||||
|
DA850_VPIF_DOUT9,
|
||||||
|
DA850_VPIF_DOUT10,
|
||||||
|
DA850_VPIF_DOUT11,
|
||||||
|
DA850_VPIF_DOUT12,
|
||||||
|
DA850_VPIF_DOUT13,
|
||||||
|
DA850_VPIF_DOUT14,
|
||||||
|
DA850_VPIF_DOUT15,
|
||||||
|
DA850_VPIF_CLKO2,
|
||||||
|
DA850_VPIF_CLKO3,
|
||||||
};
|
};
|
||||||
|
|
||||||
enum davinci_tnetv107x_index {
|
enum davinci_tnetv107x_index {
|
||||||
|
|
|
@ -166,6 +166,7 @@
|
||||||
#define DA830_LPSC1_McASP1 8
|
#define DA830_LPSC1_McASP1 8
|
||||||
#define DA850_LPSC1_SATA 8
|
#define DA850_LPSC1_SATA 8
|
||||||
#define DA830_LPSC1_McASP2 9
|
#define DA830_LPSC1_McASP2 9
|
||||||
|
#define DA850_LPSC1_VPIF 9
|
||||||
#define DA8XX_LPSC1_SPI1 10
|
#define DA8XX_LPSC1_SPI1 10
|
||||||
#define DA8XX_LPSC1_I2C 11
|
#define DA8XX_LPSC1_I2C 11
|
||||||
#define DA8XX_LPSC1_UART1 12
|
#define DA8XX_LPSC1_UART1 12
|
||||||
|
|
|
@ -378,10 +378,10 @@ static struct regulator_consumer_supply __initdata max8997_ldo1_[] = {
|
||||||
};
|
};
|
||||||
static struct regulator_consumer_supply __initdata max8997_ldo3_[] = {
|
static struct regulator_consumer_supply __initdata max8997_ldo3_[] = {
|
||||||
REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"), /* USB */
|
REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"), /* USB */
|
||||||
REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"), /* MIPI */
|
REGULATOR_SUPPLY("vddcore", "s5p-mipi-csis.0"), /* MIPI */
|
||||||
};
|
};
|
||||||
static struct regulator_consumer_supply __initdata max8997_ldo4_[] = {
|
static struct regulator_consumer_supply __initdata max8997_ldo4_[] = {
|
||||||
REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"), /* MIPI */
|
REGULATOR_SUPPLY("vddio", "s5p-mipi-csis.0"), /* MIPI */
|
||||||
};
|
};
|
||||||
static struct regulator_consumer_supply __initdata max8997_ldo5_[] = {
|
static struct regulator_consumer_supply __initdata max8997_ldo5_[] = {
|
||||||
REGULATOR_SUPPLY("vhsic", "modemctl"), /* MODEM */
|
REGULATOR_SUPPLY("vhsic", "modemctl"), /* MODEM */
|
||||||
|
@ -1180,9 +1180,7 @@ static struct platform_device cam_8m_12v_fixed_rdev = {
|
||||||
static struct s5p_platform_mipi_csis mipi_csis_platdata = {
|
static struct s5p_platform_mipi_csis mipi_csis_platdata = {
|
||||||
.clk_rate = 166000000UL,
|
.clk_rate = 166000000UL,
|
||||||
.lanes = 2,
|
.lanes = 2,
|
||||||
.alignment = 32,
|
|
||||||
.hs_settle = 12,
|
.hs_settle = 12,
|
||||||
.phy_enable = s5p_csis_phy_enable,
|
|
||||||
};
|
};
|
||||||
|
|
||||||
#define GPIO_CAM_MEGA_RST EXYNOS4_GPY3(7) /* ISP_RESET */
|
#define GPIO_CAM_MEGA_RST EXYNOS4_GPY3(7) /* ISP_RESET */
|
||||||
|
@ -1226,7 +1224,6 @@ static struct s5p_fimc_isp_info nuri_camera_sensors[] = {
|
||||||
.bus_type = FIMC_MIPI_CSI2,
|
.bus_type = FIMC_MIPI_CSI2,
|
||||||
.board_info = &m5mols_board_info,
|
.board_info = &m5mols_board_info,
|
||||||
.clk_frequency = 24000000UL,
|
.clk_frequency = 24000000UL,
|
||||||
.csi_data_align = 32,
|
|
||||||
},
|
},
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
@ -97,12 +97,12 @@ static struct s3c2410_uartcfg origen_uartcfgs[] __initdata = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct regulator_consumer_supply __initdata ldo3_consumer[] = {
|
static struct regulator_consumer_supply __initdata ldo3_consumer[] = {
|
||||||
REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"), /* MIPI */
|
REGULATOR_SUPPLY("vddcore", "s5p-mipi-csis.0"), /* MIPI */
|
||||||
REGULATOR_SUPPLY("vdd", "exynos4-hdmi"), /* HDMI */
|
REGULATOR_SUPPLY("vdd", "exynos4-hdmi"), /* HDMI */
|
||||||
REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"), /* HDMI */
|
REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"), /* HDMI */
|
||||||
};
|
};
|
||||||
static struct regulator_consumer_supply __initdata ldo6_consumer[] = {
|
static struct regulator_consumer_supply __initdata ldo6_consumer[] = {
|
||||||
REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"), /* MIPI */
|
REGULATOR_SUPPLY("vddio", "s5p-mipi-csis.0"), /* MIPI */
|
||||||
};
|
};
|
||||||
static struct regulator_consumer_supply __initdata ldo7_consumer[] = {
|
static struct regulator_consumer_supply __initdata ldo7_consumer[] = {
|
||||||
REGULATOR_SUPPLY("avdd", "alc5625"), /* Realtek ALC5625 */
|
REGULATOR_SUPPLY("avdd", "alc5625"), /* Realtek ALC5625 */
|
||||||
|
|
|
@ -209,7 +209,7 @@ static struct regulator_consumer_supply lp3974_ldo3_consumer[] = {
|
||||||
REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"),
|
REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"),
|
||||||
REGULATOR_SUPPLY("vdd", "exynos4-hdmi"),
|
REGULATOR_SUPPLY("vdd", "exynos4-hdmi"),
|
||||||
REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"),
|
REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"),
|
||||||
REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"),
|
REGULATOR_SUPPLY("vddcore", "s5p-mipi-csis.0"),
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct regulator_init_data lp3974_ldo3_data = {
|
static struct regulator_init_data lp3974_ldo3_data = {
|
||||||
|
@ -273,7 +273,7 @@ static struct regulator_init_data lp3974_ldo6_data = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct regulator_consumer_supply lp3974_ldo7_consumer[] = {
|
static struct regulator_consumer_supply lp3974_ldo7_consumer[] = {
|
||||||
REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"),
|
REGULATOR_SUPPLY("vddio", "s5p-mipi-csis.0"),
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct regulator_init_data lp3974_ldo7_data = {
|
static struct regulator_init_data lp3974_ldo7_data = {
|
||||||
|
@ -942,9 +942,7 @@ static struct platform_device cam_s_if_fixed_reg_dev = {
|
||||||
static struct s5p_platform_mipi_csis mipi_csis_platdata = {
|
static struct s5p_platform_mipi_csis mipi_csis_platdata = {
|
||||||
.clk_rate = 166000000UL,
|
.clk_rate = 166000000UL,
|
||||||
.lanes = 2,
|
.lanes = 2,
|
||||||
.alignment = 32,
|
|
||||||
.hs_settle = 12,
|
.hs_settle = 12,
|
||||||
.phy_enable = s5p_csis_phy_enable,
|
|
||||||
};
|
};
|
||||||
|
|
||||||
#define GPIO_CAM_LEVEL_EN(n) EXYNOS4_GPE4(n + 3)
|
#define GPIO_CAM_LEVEL_EN(n) EXYNOS4_GPE4(n + 3)
|
||||||
|
@ -1008,7 +1006,6 @@ static struct s5p_fimc_isp_info universal_camera_sensors[] = {
|
||||||
.board_info = &m5mols_board_info,
|
.board_info = &m5mols_board_info,
|
||||||
.i2c_bus_num = 0,
|
.i2c_bus_num = 0,
|
||||||
.clk_frequency = 24000000UL,
|
.clk_frequency = 24000000UL,
|
||||||
.csi_data_align = 32,
|
|
||||||
},
|
},
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
@ -14,24 +14,18 @@
|
||||||
#include <linux/spinlock.h>
|
#include <linux/spinlock.h>
|
||||||
#include <mach/regs-clock.h>
|
#include <mach/regs-clock.h>
|
||||||
|
|
||||||
static int __s5p_mipi_phy_control(struct platform_device *pdev,
|
static int __s5p_mipi_phy_control(int id, bool on, u32 reset)
|
||||||
bool on, u32 reset)
|
|
||||||
{
|
{
|
||||||
static DEFINE_SPINLOCK(lock);
|
static DEFINE_SPINLOCK(lock);
|
||||||
void __iomem *addr;
|
void __iomem *addr;
|
||||||
unsigned long flags;
|
unsigned long flags;
|
||||||
int pid;
|
|
||||||
u32 cfg;
|
u32 cfg;
|
||||||
|
|
||||||
if (!pdev)
|
id = max(0, id);
|
||||||
|
if (id > 1)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
||||||
pid = (pdev->id == -1) ? 0 : pdev->id;
|
addr = S5P_MIPI_DPHY_CONTROL(id);
|
||||||
|
|
||||||
if (pid != 0 && pid != 1)
|
|
||||||
return -EINVAL;
|
|
||||||
|
|
||||||
addr = S5P_MIPI_DPHY_CONTROL(pid);
|
|
||||||
|
|
||||||
spin_lock_irqsave(&lock, flags);
|
spin_lock_irqsave(&lock, flags);
|
||||||
|
|
||||||
|
@ -52,12 +46,12 @@ static int __s5p_mipi_phy_control(struct platform_device *pdev,
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
int s5p_csis_phy_enable(struct platform_device *pdev, bool on)
|
int s5p_csis_phy_enable(int id, bool on)
|
||||||
{
|
{
|
||||||
return __s5p_mipi_phy_control(pdev, on, S5P_MIPI_DPHY_SRESETN);
|
return __s5p_mipi_phy_control(id, on, S5P_MIPI_DPHY_SRESETN);
|
||||||
}
|
}
|
||||||
|
|
||||||
int s5p_dsim_phy_enable(struct platform_device *pdev, bool on)
|
int s5p_dsim_phy_enable(struct platform_device *pdev, bool on)
|
||||||
{
|
{
|
||||||
return __s5p_mipi_phy_control(pdev, on, S5P_MIPI_DPHY_MRESETN);
|
return __s5p_mipi_phy_control(pdev->id, on, S5P_MIPI_DPHY_MRESETN);
|
||||||
}
|
}
|
||||||
|
|
|
@ -966,6 +966,8 @@ static int dvb_frontend_clear_cache(struct dvb_frontend *fe)
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
c->lna = LNA_AUTO;
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1054,6 +1056,8 @@ static struct dtv_cmds_h dtv_cmds[DTV_MAX_COMMAND + 1] = {
|
||||||
_DTV_CMD(DTV_ATSCMH_SCCC_CODE_MODE_B, 0, 0),
|
_DTV_CMD(DTV_ATSCMH_SCCC_CODE_MODE_B, 0, 0),
|
||||||
_DTV_CMD(DTV_ATSCMH_SCCC_CODE_MODE_C, 0, 0),
|
_DTV_CMD(DTV_ATSCMH_SCCC_CODE_MODE_C, 0, 0),
|
||||||
_DTV_CMD(DTV_ATSCMH_SCCC_CODE_MODE_D, 0, 0),
|
_DTV_CMD(DTV_ATSCMH_SCCC_CODE_MODE_D, 0, 0),
|
||||||
|
|
||||||
|
_DTV_CMD(DTV_LNA, 0, 0),
|
||||||
};
|
};
|
||||||
|
|
||||||
static void dtv_property_dump(struct dvb_frontend *fe, struct dtv_property *tvp)
|
static void dtv_property_dump(struct dvb_frontend *fe, struct dtv_property *tvp)
|
||||||
|
@ -1440,6 +1444,10 @@ static int dtv_property_process_get(struct dvb_frontend *fe,
|
||||||
tvp->u.data = fe->dtv_property_cache.atscmh_sccc_code_mode_d;
|
tvp->u.data = fe->dtv_property_cache.atscmh_sccc_code_mode_d;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
|
case DTV_LNA:
|
||||||
|
tvp->u.data = c->lna;
|
||||||
|
break;
|
||||||
|
|
||||||
default:
|
default:
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
}
|
}
|
||||||
|
@ -1731,10 +1739,6 @@ static int dtv_property_process_set(struct dvb_frontend *fe,
|
||||||
case DTV_INTERLEAVING:
|
case DTV_INTERLEAVING:
|
||||||
c->interleaving = tvp->u.data;
|
c->interleaving = tvp->u.data;
|
||||||
break;
|
break;
|
||||||
case DTV_LNA:
|
|
||||||
if (fe->ops.set_lna)
|
|
||||||
r = fe->ops.set_lna(fe, tvp->u.data);
|
|
||||||
break;
|
|
||||||
|
|
||||||
/* ISDB-T Support here */
|
/* ISDB-T Support here */
|
||||||
case DTV_ISDBT_PARTIAL_RECEPTION:
|
case DTV_ISDBT_PARTIAL_RECEPTION:
|
||||||
|
@ -1806,6 +1810,12 @@ static int dtv_property_process_set(struct dvb_frontend *fe,
|
||||||
fe->dtv_property_cache.atscmh_rs_frame_ensemble = tvp->u.data;
|
fe->dtv_property_cache.atscmh_rs_frame_ensemble = tvp->u.data;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
|
case DTV_LNA:
|
||||||
|
c->lna = tvp->u.data;
|
||||||
|
if (fe->ops.set_lna)
|
||||||
|
r = fe->ops.set_lna(fe);
|
||||||
|
break;
|
||||||
|
|
||||||
default:
|
default:
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
}
|
}
|
||||||
|
@ -2309,7 +2319,7 @@ static int dvb_frontend_ioctl_legacy(struct file *file,
|
||||||
fepriv->tune_mode_flags = (unsigned long) parg;
|
fepriv->tune_mode_flags = (unsigned long) parg;
|
||||||
err = 0;
|
err = 0;
|
||||||
break;
|
break;
|
||||||
};
|
}
|
||||||
|
|
||||||
return err;
|
return err;
|
||||||
}
|
}
|
||||||
|
|
|
@ -303,7 +303,7 @@ struct dvb_frontend_ops {
|
||||||
int (*dishnetwork_send_legacy_command)(struct dvb_frontend* fe, unsigned long cmd);
|
int (*dishnetwork_send_legacy_command)(struct dvb_frontend* fe, unsigned long cmd);
|
||||||
int (*i2c_gate_ctrl)(struct dvb_frontend* fe, int enable);
|
int (*i2c_gate_ctrl)(struct dvb_frontend* fe, int enable);
|
||||||
int (*ts_bus_ctrl)(struct dvb_frontend* fe, int acquire);
|
int (*ts_bus_ctrl)(struct dvb_frontend* fe, int acquire);
|
||||||
int (*set_lna)(struct dvb_frontend *, int);
|
int (*set_lna)(struct dvb_frontend *);
|
||||||
|
|
||||||
/* These callbacks are for devices that implement their own
|
/* These callbacks are for devices that implement their own
|
||||||
* tuning algorithms, rather than a simple swzigzag
|
* tuning algorithms, rather than a simple swzigzag
|
||||||
|
@ -391,6 +391,8 @@ struct dtv_frontend_properties {
|
||||||
u8 atscmh_sccc_code_mode_b;
|
u8 atscmh_sccc_code_mode_b;
|
||||||
u8 atscmh_sccc_code_mode_c;
|
u8 atscmh_sccc_code_mode_c;
|
||||||
u8 atscmh_sccc_code_mode_d;
|
u8 atscmh_sccc_code_mode_d;
|
||||||
|
|
||||||
|
u32 lna;
|
||||||
};
|
};
|
||||||
|
|
||||||
struct dvb_frontend {
|
struct dvb_frontend {
|
||||||
|
|
|
@ -90,7 +90,7 @@ static int a8293_set_voltage(struct dvb_frontend *fe,
|
||||||
default:
|
default:
|
||||||
ret = -EINVAL;
|
ret = -EINVAL;
|
||||||
goto err;
|
goto err;
|
||||||
};
|
}
|
||||||
|
|
||||||
ret = a8293_wr(priv, &priv->reg[0], 1);
|
ret = a8293_wr(priv, &priv->reg[0], 1);
|
||||||
if (ret)
|
if (ret)
|
||||||
|
|
|
@ -241,7 +241,7 @@ static int af9013_set_gpio(struct af9013_state *state, u8 gpio, u8 gpioval)
|
||||||
KBUILD_MODNAME, gpio);
|
KBUILD_MODNAME, gpio);
|
||||||
ret = -EINVAL;
|
ret = -EINVAL;
|
||||||
goto err;
|
goto err;
|
||||||
};
|
}
|
||||||
|
|
||||||
switch (gpio) {
|
switch (gpio) {
|
||||||
case 0:
|
case 0:
|
||||||
|
@ -253,7 +253,7 @@ static int af9013_set_gpio(struct af9013_state *state, u8 gpio, u8 gpioval)
|
||||||
default:
|
default:
|
||||||
pos = 4;
|
pos = 4;
|
||||||
break;
|
break;
|
||||||
};
|
}
|
||||||
|
|
||||||
ret = af9013_wr_reg_bits(state, addr, pos, 4, gpioval);
|
ret = af9013_wr_reg_bits(state, addr, pos, 4, gpioval);
|
||||||
if (ret)
|
if (ret)
|
||||||
|
@ -726,7 +726,7 @@ static int af9013_set_frontend(struct dvb_frontend *fe)
|
||||||
default:
|
default:
|
||||||
dev_dbg(&state->i2c->dev, "%s: invalid hierarchy\n", __func__);
|
dev_dbg(&state->i2c->dev, "%s: invalid hierarchy\n", __func__);
|
||||||
auto_mode = 1;
|
auto_mode = 1;
|
||||||
};
|
}
|
||||||
|
|
||||||
switch (c->modulation) {
|
switch (c->modulation) {
|
||||||
case QAM_AUTO:
|
case QAM_AUTO:
|
||||||
|
|
|
@ -408,7 +408,7 @@ static int af9033_set_frontend(struct dvb_frontend *fe)
|
||||||
{
|
{
|
||||||
struct af9033_state *state = fe->demodulator_priv;
|
struct af9033_state *state = fe->demodulator_priv;
|
||||||
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
|
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
|
||||||
int ret, i, spec_inv;
|
int ret, i, spec_inv, sampling_freq;
|
||||||
u8 tmp, buf[3], bandwidth_reg_val;
|
u8 tmp, buf[3], bandwidth_reg_val;
|
||||||
u32 if_frequency, freq_cw, adc_freq;
|
u32 if_frequency, freq_cw, adc_freq;
|
||||||
|
|
||||||
|
@ -465,18 +465,20 @@ static int af9033_set_frontend(struct dvb_frontend *fe)
|
||||||
else
|
else
|
||||||
if_frequency = 0;
|
if_frequency = 0;
|
||||||
|
|
||||||
while (if_frequency > (adc_freq / 2))
|
sampling_freq = if_frequency;
|
||||||
if_frequency -= adc_freq;
|
|
||||||
|
|
||||||
if (if_frequency >= 0)
|
while (sampling_freq > (adc_freq / 2))
|
||||||
|
sampling_freq -= adc_freq;
|
||||||
|
|
||||||
|
if (sampling_freq >= 0)
|
||||||
spec_inv *= -1;
|
spec_inv *= -1;
|
||||||
else
|
else
|
||||||
if_frequency *= -1;
|
sampling_freq *= -1;
|
||||||
|
|
||||||
freq_cw = af9033_div(state, if_frequency, adc_freq, 23ul);
|
freq_cw = af9033_div(state, sampling_freq, adc_freq, 23ul);
|
||||||
|
|
||||||
if (spec_inv == -1)
|
if (spec_inv == -1)
|
||||||
freq_cw *= -1;
|
freq_cw = 0x800000 - freq_cw;
|
||||||
|
|
||||||
/* get adc multiplies */
|
/* get adc multiplies */
|
||||||
ret = af9033_rd_reg(state, 0x800045, &tmp);
|
ret = af9033_rd_reg(state, 0x800045, &tmp);
|
||||||
|
|
|
@ -527,7 +527,7 @@ static int bcm3510_set_frontend(struct dvb_frontend *fe)
|
||||||
cmd.ACQUIRE1.IF_FREQ = 0x0;
|
cmd.ACQUIRE1.IF_FREQ = 0x0;
|
||||||
default:
|
default:
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
};
|
}
|
||||||
cmd.ACQUIRE0.OFFSET = 0;
|
cmd.ACQUIRE0.OFFSET = 0;
|
||||||
cmd.ACQUIRE0.NTSCSWEEP = 1;
|
cmd.ACQUIRE0.NTSCSWEEP = 1;
|
||||||
cmd.ACQUIRE0.FA = 1;
|
cmd.ACQUIRE0.FA = 1;
|
||||||
|
|
|
@ -218,7 +218,7 @@ static int cx24110_set_fec (struct cx24110_state* state, fe_code_rate_t fec)
|
||||||
} else
|
} else
|
||||||
return -EOPNOTSUPP;
|
return -EOPNOTSUPP;
|
||||||
/* fixme (low): which is the correct return code? */
|
/* fixme (low): which is the correct return code? */
|
||||||
};
|
}
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -275,7 +275,7 @@ static int cx24110_set_symbolrate (struct cx24110_state* state, u32 srate)
|
||||||
cx24110_writereg(state,0x07,tmp|0x3);
|
cx24110_writereg(state,0x07,tmp|0x3);
|
||||||
cx24110_writereg(state,0x06,0x78);
|
cx24110_writereg(state,0x06,0x78);
|
||||||
fclk=90999000UL;
|
fclk=90999000UL;
|
||||||
};
|
}
|
||||||
dprintk("cx24110 debug: fclk %d Hz\n",fclk);
|
dprintk("cx24110 debug: fclk %d Hz\n",fclk);
|
||||||
/* we need to divide two integers with approx. 27 bits in 32 bit
|
/* we need to divide two integers with approx. 27 bits in 32 bit
|
||||||
arithmetic giving a 25 bit result */
|
arithmetic giving a 25 bit result */
|
||||||
|
@ -362,7 +362,7 @@ static int cx24110_initfe(struct dvb_frontend* fe)
|
||||||
|
|
||||||
for(i = 0; i < ARRAY_SIZE(cx24110_regdata); i++) {
|
for(i = 0; i < ARRAY_SIZE(cx24110_regdata); i++) {
|
||||||
cx24110_writereg(state, cx24110_regdata[i].reg, cx24110_regdata[i].data);
|
cx24110_writereg(state, cx24110_regdata[i].reg, cx24110_regdata[i].data);
|
||||||
};
|
}
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
|
@ -688,7 +688,7 @@ struct dvb_frontend *cxd2820r_attach(const struct cxd2820r_config *cfg,
|
||||||
{
|
{
|
||||||
struct cxd2820r_priv *priv;
|
struct cxd2820r_priv *priv;
|
||||||
int ret;
|
int ret;
|
||||||
u8 tmp, gpio[GPIO_COUNT];
|
u8 tmp;
|
||||||
|
|
||||||
priv = kzalloc(sizeof(struct cxd2820r_priv), GFP_KERNEL);
|
priv = kzalloc(sizeof(struct cxd2820r_priv), GFP_KERNEL);
|
||||||
if (!priv) {
|
if (!priv) {
|
||||||
|
@ -735,6 +735,7 @@ struct dvb_frontend *cxd2820r_attach(const struct cxd2820r_config *cfg,
|
||||||
* Use static GPIO configuration if GPIOLIB is undefined.
|
* Use static GPIO configuration if GPIOLIB is undefined.
|
||||||
* This is fallback condition.
|
* This is fallback condition.
|
||||||
*/
|
*/
|
||||||
|
u8 gpio[GPIO_COUNT];
|
||||||
gpio[0] = (*gpio_chip_base >> 0) & 0x07;
|
gpio[0] = (*gpio_chip_base >> 0) & 0x07;
|
||||||
gpio[1] = (*gpio_chip_base >> 3) & 0x07;
|
gpio[1] = (*gpio_chip_base >> 3) & 0x07;
|
||||||
gpio[2] = 0;
|
gpio[2] = 0;
|
||||||
|
|
|
@ -991,7 +991,7 @@ static int HI_Command(struct drxd_state *state, u16 cmd, u16 * pResult)
|
||||||
if (nrRetries > DRXD_MAX_RETRIES) {
|
if (nrRetries > DRXD_MAX_RETRIES) {
|
||||||
status = -1;
|
status = -1;
|
||||||
break;
|
break;
|
||||||
};
|
}
|
||||||
status = Read16(state, HI_RA_RAM_SRV_CMD__A, &waitCmd, 0);
|
status = Read16(state, HI_RA_RAM_SRV_CMD__A, &waitCmd, 0);
|
||||||
} while (waitCmd != 0);
|
} while (waitCmd != 0);
|
||||||
|
|
||||||
|
|
|
@ -30,6 +30,7 @@
|
||||||
#include "ds3000.h"
|
#include "ds3000.h"
|
||||||
|
|
||||||
static int debug;
|
static int debug;
|
||||||
|
static int force_fw_upload;
|
||||||
|
|
||||||
#define dprintk(args...) \
|
#define dprintk(args...) \
|
||||||
do { \
|
do { \
|
||||||
|
@ -392,11 +393,13 @@ static int ds3000_firmware_ondemand(struct dvb_frontend *fe)
|
||||||
|
|
||||||
dprintk("%s()\n", __func__);
|
dprintk("%s()\n", __func__);
|
||||||
|
|
||||||
if (ds3000_readreg(state, 0xb2) <= 0)
|
ret = ds3000_readreg(state, 0xb2);
|
||||||
|
if (ret < 0)
|
||||||
return ret;
|
return ret;
|
||||||
|
|
||||||
if (state->skip_fw_load)
|
if (state->skip_fw_load || !force_fw_upload)
|
||||||
return 0;
|
return 0; /* Firmware already uploaded, skipping */
|
||||||
|
|
||||||
/* Load firmware */
|
/* Load firmware */
|
||||||
/* request the firmware, this will block until someone uploads it */
|
/* request the firmware, this will block until someone uploads it */
|
||||||
printk(KERN_INFO "%s: Waiting for firmware upload (%s)...\n", __func__,
|
printk(KERN_INFO "%s: Waiting for firmware upload (%s)...\n", __func__,
|
||||||
|
@ -1306,6 +1309,9 @@ static struct dvb_frontend_ops ds3000_ops = {
|
||||||
module_param(debug, int, 0644);
|
module_param(debug, int, 0644);
|
||||||
MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
|
MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
|
||||||
|
|
||||||
|
module_param(force_fw_upload, int, 0644);
|
||||||
|
MODULE_PARM_DESC(force_fw_upload, "Force firmware upload (default:0)");
|
||||||
|
|
||||||
MODULE_DESCRIPTION("DVB Frontend module for Montage Technology "
|
MODULE_DESCRIPTION("DVB Frontend module for Montage Technology "
|
||||||
"DS3000/TS2020 hardware");
|
"DS3000/TS2020 hardware");
|
||||||
MODULE_AUTHOR("Konstantin Dimitrov");
|
MODULE_AUTHOR("Konstantin Dimitrov");
|
||||||
|
|
|
@ -121,16 +121,13 @@ struct dvb_frontend* dvb_dummy_fe_ofdm_attach(void)
|
||||||
|
|
||||||
/* allocate memory for the internal state */
|
/* allocate memory for the internal state */
|
||||||
state = kzalloc(sizeof(struct dvb_dummy_fe_state), GFP_KERNEL);
|
state = kzalloc(sizeof(struct dvb_dummy_fe_state), GFP_KERNEL);
|
||||||
if (state == NULL) goto error;
|
if (!state)
|
||||||
|
return NULL;
|
||||||
|
|
||||||
/* create dvb_frontend */
|
/* create dvb_frontend */
|
||||||
memcpy(&state->frontend.ops, &dvb_dummy_fe_ofdm_ops, sizeof(struct dvb_frontend_ops));
|
memcpy(&state->frontend.ops, &dvb_dummy_fe_ofdm_ops, sizeof(struct dvb_frontend_ops));
|
||||||
state->frontend.demodulator_priv = state;
|
state->frontend.demodulator_priv = state;
|
||||||
return &state->frontend;
|
return &state->frontend;
|
||||||
|
|
||||||
error:
|
|
||||||
kfree(state);
|
|
||||||
return NULL;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct dvb_frontend_ops dvb_dummy_fe_qpsk_ops;
|
static struct dvb_frontend_ops dvb_dummy_fe_qpsk_ops;
|
||||||
|
@ -141,16 +138,13 @@ struct dvb_frontend *dvb_dummy_fe_qpsk_attach(void)
|
||||||
|
|
||||||
/* allocate memory for the internal state */
|
/* allocate memory for the internal state */
|
||||||
state = kzalloc(sizeof(struct dvb_dummy_fe_state), GFP_KERNEL);
|
state = kzalloc(sizeof(struct dvb_dummy_fe_state), GFP_KERNEL);
|
||||||
if (state == NULL) goto error;
|
if (!state)
|
||||||
|
return NULL;
|
||||||
|
|
||||||
/* create dvb_frontend */
|
/* create dvb_frontend */
|
||||||
memcpy(&state->frontend.ops, &dvb_dummy_fe_qpsk_ops, sizeof(struct dvb_frontend_ops));
|
memcpy(&state->frontend.ops, &dvb_dummy_fe_qpsk_ops, sizeof(struct dvb_frontend_ops));
|
||||||
state->frontend.demodulator_priv = state;
|
state->frontend.demodulator_priv = state;
|
||||||
return &state->frontend;
|
return &state->frontend;
|
||||||
|
|
||||||
error:
|
|
||||||
kfree(state);
|
|
||||||
return NULL;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct dvb_frontend_ops dvb_dummy_fe_qam_ops;
|
static struct dvb_frontend_ops dvb_dummy_fe_qam_ops;
|
||||||
|
@ -161,16 +155,13 @@ struct dvb_frontend *dvb_dummy_fe_qam_attach(void)
|
||||||
|
|
||||||
/* allocate memory for the internal state */
|
/* allocate memory for the internal state */
|
||||||
state = kzalloc(sizeof(struct dvb_dummy_fe_state), GFP_KERNEL);
|
state = kzalloc(sizeof(struct dvb_dummy_fe_state), GFP_KERNEL);
|
||||||
if (state == NULL) goto error;
|
if (!state)
|
||||||
|
return NULL;
|
||||||
|
|
||||||
/* create dvb_frontend */
|
/* create dvb_frontend */
|
||||||
memcpy(&state->frontend.ops, &dvb_dummy_fe_qam_ops, sizeof(struct dvb_frontend_ops));
|
memcpy(&state->frontend.ops, &dvb_dummy_fe_qam_ops, sizeof(struct dvb_frontend_ops));
|
||||||
state->frontend.demodulator_priv = state;
|
state->frontend.demodulator_priv = state;
|
||||||
return &state->frontend;
|
return &state->frontend;
|
||||||
|
|
||||||
error:
|
|
||||||
kfree(state);
|
|
||||||
return NULL;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct dvb_frontend_ops dvb_dummy_fe_ofdm_ops = {
|
static struct dvb_frontend_ops dvb_dummy_fe_ofdm_ops = {
|
||||||
|
|
|
@ -77,7 +77,7 @@ static int isl6405_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
};
|
}
|
||||||
}
|
}
|
||||||
isl6405->config |= isl6405->override_or;
|
isl6405->config |= isl6405->override_or;
|
||||||
isl6405->config &= isl6405->override_and;
|
isl6405->config &= isl6405->override_and;
|
||||||
|
|
|
@ -63,7 +63,7 @@ static int isl6421_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
};
|
}
|
||||||
|
|
||||||
isl6421->config |= isl6421->override_or;
|
isl6421->config |= isl6421->override_or;
|
||||||
isl6421->config &= isl6421->override_and;
|
isl6421->config &= isl6421->override_and;
|
||||||
|
|
|
@ -231,7 +231,7 @@ static void itd1000_set_lo(struct itd1000_state *state, u32 freq_khz)
|
||||||
state->frequency = ((plln * 1000) + (pllf * 1000)/1048576) * 2*FREF;
|
state->frequency = ((plln * 1000) + (pllf * 1000)/1048576) * 2*FREF;
|
||||||
itd_dbg("frequency: %dkHz (wanted) %dkHz (set), PLLF = %d, PLLN = %d\n", freq_khz, state->frequency, pllf, plln);
|
itd_dbg("frequency: %dkHz (wanted) %dkHz (set), PLLF = %d, PLLN = %d\n", freq_khz, state->frequency, pllf, plln);
|
||||||
|
|
||||||
itd1000_write_reg(state, PLLNH, 0x80); /* PLLNH */;
|
itd1000_write_reg(state, PLLNH, 0x80); /* PLLNH */
|
||||||
itd1000_write_reg(state, PLLNL, plln & 0xff);
|
itd1000_write_reg(state, PLLNL, plln & 0xff);
|
||||||
itd1000_write_reg(state, PLLFH, (itd1000_read_reg(state, PLLFH) & 0xf0) | ((pllf >> 16) & 0x0f));
|
itd1000_write_reg(state, PLLFH, (itd1000_read_reg(state, PLLFH) & 0xf0) | ((pllf >> 16) & 0x0f));
|
||||||
itd1000_write_reg(state, PLLFM, (pllf >> 8) & 0xff);
|
itd1000_write_reg(state, PLLFM, (pllf >> 8) & 0xff);
|
||||||
|
|
|
@ -1421,8 +1421,8 @@ struct dvb_frontend *lg2160_attach(const struct lg2160_config *config,
|
||||||
config ? config->i2c_addr : 0);
|
config ? config->i2c_addr : 0);
|
||||||
|
|
||||||
state = kzalloc(sizeof(struct lg216x_state), GFP_KERNEL);
|
state = kzalloc(sizeof(struct lg216x_state), GFP_KERNEL);
|
||||||
if (state == NULL)
|
if (!state)
|
||||||
goto fail;
|
return NULL;
|
||||||
|
|
||||||
state->cfg = config;
|
state->cfg = config;
|
||||||
state->i2c_adap = i2c_adap;
|
state->i2c_adap = i2c_adap;
|
||||||
|
@ -1449,10 +1449,6 @@ struct dvb_frontend *lg2160_attach(const struct lg2160_config *config,
|
||||||
state->frontend.dtv_property_cache.atscmh_parade_id = 1;
|
state->frontend.dtv_property_cache.atscmh_parade_id = 1;
|
||||||
|
|
||||||
return &state->frontend;
|
return &state->frontend;
|
||||||
fail:
|
|
||||||
lg_warn("unable to detect LG216x hardware\n");
|
|
||||||
kfree(state);
|
|
||||||
return NULL;
|
|
||||||
}
|
}
|
||||||
EXPORT_SYMBOL(lg2160_attach);
|
EXPORT_SYMBOL(lg2160_attach);
|
||||||
|
|
||||||
|
|
|
@ -65,7 +65,7 @@ static int lnbp21_set_voltage(struct dvb_frontend *fe,
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
};
|
}
|
||||||
|
|
||||||
lnbp21->config |= lnbp21->override_or;
|
lnbp21->config |= lnbp21->override_or;
|
||||||
lnbp21->config &= lnbp21->override_and;
|
lnbp21->config &= lnbp21->override_and;
|
||||||
|
@ -108,7 +108,7 @@ static int lnbp21_set_tone(struct dvb_frontend *fe,
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
};
|
}
|
||||||
|
|
||||||
lnbp21->config |= lnbp21->override_or;
|
lnbp21->config |= lnbp21->override_or;
|
||||||
lnbp21->config &= lnbp21->override_and;
|
lnbp21->config &= lnbp21->override_and;
|
||||||
|
|
|
@ -73,7 +73,7 @@ static int lnbp22_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
};
|
}
|
||||||
|
|
||||||
dprintk(1, "%s: 0x%02x)\n", __func__, lnbp22->config[3]);
|
dprintk(1, "%s: 0x%02x)\n", __func__, lnbp22->config[3]);
|
||||||
return (i2c_transfer(lnbp22->i2c, &msg, 1) == 1) ? 0 : -EIO;
|
return (i2c_transfer(lnbp22->i2c, &msg, 1) == 1) ? 0 : -EIO;
|
||||||
|
|
|
@ -351,8 +351,8 @@ struct dvb_frontend *s5h1432_attach(const struct s5h1432_config *config,
|
||||||
printk(KERN_INFO " Enter s5h1432_attach(). attach success!\n");
|
printk(KERN_INFO " Enter s5h1432_attach(). attach success!\n");
|
||||||
/* allocate memory for the internal state */
|
/* allocate memory for the internal state */
|
||||||
state = kmalloc(sizeof(struct s5h1432_state), GFP_KERNEL);
|
state = kmalloc(sizeof(struct s5h1432_state), GFP_KERNEL);
|
||||||
if (state == NULL)
|
if (!state)
|
||||||
goto error;
|
return NULL;
|
||||||
|
|
||||||
/* setup the state */
|
/* setup the state */
|
||||||
state->config = config;
|
state->config = config;
|
||||||
|
@ -367,10 +367,6 @@ struct dvb_frontend *s5h1432_attach(const struct s5h1432_config *config,
|
||||||
state->frontend.demodulator_priv = state;
|
state->frontend.demodulator_priv = state;
|
||||||
|
|
||||||
return &state->frontend;
|
return &state->frontend;
|
||||||
|
|
||||||
error:
|
|
||||||
kfree(state);
|
|
||||||
return NULL;
|
|
||||||
}
|
}
|
||||||
EXPORT_SYMBOL(s5h1432_attach);
|
EXPORT_SYMBOL(s5h1432_attach);
|
||||||
|
|
||||||
|
|
|
@ -487,9 +487,9 @@ struct dvb_frontend *s921_attach(const struct s921_config *config,
|
||||||
kzalloc(sizeof(struct s921_state), GFP_KERNEL);
|
kzalloc(sizeof(struct s921_state), GFP_KERNEL);
|
||||||
|
|
||||||
dprintk("\n");
|
dprintk("\n");
|
||||||
if (state == NULL) {
|
if (!state) {
|
||||||
rc("Unable to kzalloc\n");
|
rc("Unable to kzalloc\n");
|
||||||
goto rcor;
|
return NULL;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* setup the state */
|
/* setup the state */
|
||||||
|
@ -502,11 +502,6 @@ struct dvb_frontend *s921_attach(const struct s921_config *config,
|
||||||
state->frontend.demodulator_priv = state;
|
state->frontend.demodulator_priv = state;
|
||||||
|
|
||||||
return &state->frontend;
|
return &state->frontend;
|
||||||
|
|
||||||
rcor:
|
|
||||||
kfree(state);
|
|
||||||
|
|
||||||
return NULL;
|
|
||||||
}
|
}
|
||||||
EXPORT_SYMBOL(s921_attach);
|
EXPORT_SYMBOL(s921_attach);
|
||||||
|
|
||||||
|
|
|
@ -343,7 +343,7 @@ static int si21xx_wait_diseqc_idle(struct si21xx_state *state, int timeout)
|
||||||
return -ETIMEDOUT;
|
return -ETIMEDOUT;
|
||||||
}
|
}
|
||||||
msleep(10);
|
msleep(10);
|
||||||
};
|
}
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
@ -472,7 +472,7 @@ static int si21xx_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t volt)
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
};
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static int si21xx_init(struct dvb_frontend *fe)
|
static int si21xx_init(struct dvb_frontend *fe)
|
||||||
|
|
|
@ -188,7 +188,7 @@ static int configure_reg0xc05 (struct dtv_frontend_properties *p, u16 *reg0xc05)
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
};
|
}
|
||||||
|
|
||||||
switch (p->hierarchy) {
|
switch (p->hierarchy) {
|
||||||
case HIERARCHY_NONE:
|
case HIERARCHY_NONE:
|
||||||
|
@ -207,7 +207,7 @@ static int configure_reg0xc05 (struct dtv_frontend_properties *p, u16 *reg0xc05)
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
};
|
}
|
||||||
|
|
||||||
switch (p->code_rate_HP) {
|
switch (p->code_rate_HP) {
|
||||||
case FEC_1_2:
|
case FEC_1_2:
|
||||||
|
@ -229,7 +229,7 @@ static int configure_reg0xc05 (struct dtv_frontend_properties *p, u16 *reg0xc05)
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
};
|
}
|
||||||
|
|
||||||
if (known_parameters)
|
if (known_parameters)
|
||||||
*reg0xc05 |= (2 << 1); /* use specified parameters */
|
*reg0xc05 |= (2 << 1); /* use specified parameters */
|
||||||
|
|
|
@ -229,7 +229,7 @@ static int configure_reg0xc05(struct dtv_frontend_properties *p, u16 *reg0xc05)
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
};
|
}
|
||||||
|
|
||||||
switch (p->hierarchy) {
|
switch (p->hierarchy) {
|
||||||
case HIERARCHY_NONE:
|
case HIERARCHY_NONE:
|
||||||
|
@ -248,7 +248,7 @@ static int configure_reg0xc05(struct dtv_frontend_properties *p, u16 *reg0xc05)
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
};
|
}
|
||||||
|
|
||||||
switch (p->code_rate_HP) {
|
switch (p->code_rate_HP) {
|
||||||
case FEC_1_2:
|
case FEC_1_2:
|
||||||
|
@ -270,7 +270,7 @@ static int configure_reg0xc05(struct dtv_frontend_properties *p, u16 *reg0xc05)
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
};
|
}
|
||||||
|
|
||||||
if (known_parameters)
|
if (known_parameters)
|
||||||
*reg0xc05 |= (2 << 1); /* use specified parameters */
|
*reg0xc05 |= (2 << 1); /* use specified parameters */
|
||||||
|
|
|
@ -575,8 +575,8 @@ struct dvb_frontend *stb6100_attach(struct dvb_frontend *fe,
|
||||||
struct stb6100_state *state = NULL;
|
struct stb6100_state *state = NULL;
|
||||||
|
|
||||||
state = kzalloc(sizeof (struct stb6100_state), GFP_KERNEL);
|
state = kzalloc(sizeof (struct stb6100_state), GFP_KERNEL);
|
||||||
if (state == NULL)
|
if (!state)
|
||||||
goto error;
|
return NULL;
|
||||||
|
|
||||||
state->config = config;
|
state->config = config;
|
||||||
state->i2c = i2c;
|
state->i2c = i2c;
|
||||||
|
@ -587,10 +587,6 @@ struct dvb_frontend *stb6100_attach(struct dvb_frontend *fe,
|
||||||
|
|
||||||
printk("%s: Attaching STB6100 \n", __func__);
|
printk("%s: Attaching STB6100 \n", __func__);
|
||||||
return fe;
|
return fe;
|
||||||
|
|
||||||
error:
|
|
||||||
kfree(state);
|
|
||||||
return NULL;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static int stb6100_release(struct dvb_frontend *fe)
|
static int stb6100_release(struct dvb_frontend *fe)
|
||||||
|
|
|
@ -199,7 +199,7 @@ static int stv0299_wait_diseqc_fifo (struct stv0299_state* state, int timeout)
|
||||||
return -ETIMEDOUT;
|
return -ETIMEDOUT;
|
||||||
}
|
}
|
||||||
msleep(10);
|
msleep(10);
|
||||||
};
|
}
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
@ -216,7 +216,7 @@ static int stv0299_wait_diseqc_idle (struct stv0299_state* state, int timeout)
|
||||||
return -ETIMEDOUT;
|
return -ETIMEDOUT;
|
||||||
}
|
}
|
||||||
msleep(10);
|
msleep(10);
|
||||||
};
|
}
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
@ -387,7 +387,7 @@ static int stv0299_set_voltage (struct dvb_frontend* fe, fe_sec_voltage_t voltag
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
};
|
}
|
||||||
|
|
||||||
if (state->config->op0_off)
|
if (state->config->op0_off)
|
||||||
reg0x0c &= ~0x10;
|
reg0x0c &= ~0x10;
|
||||||
|
|
|
@ -1552,8 +1552,8 @@ static int stv0900_status(struct stv0900_internal *intp,
|
||||||
bitrate = (stv0900_get_mclk_freq(intp, intp->quartz)/1000000)
|
bitrate = (stv0900_get_mclk_freq(intp, intp->quartz)/1000000)
|
||||||
* (tsbitrate1_val << 8 | tsbitrate0_val);
|
* (tsbitrate1_val << 8 | tsbitrate0_val);
|
||||||
bitrate /= 16384;
|
bitrate /= 16384;
|
||||||
dprintk("TS bitrate = %d Mbit/sec \n", bitrate);
|
dprintk("TS bitrate = %d Mbit/sec\n", bitrate);
|
||||||
};
|
}
|
||||||
|
|
||||||
return locked;
|
return locked;
|
||||||
}
|
}
|
||||||
|
|
|
@ -228,8 +228,8 @@ struct dvb_frontend *tda665x_attach(struct dvb_frontend *fe,
|
||||||
struct dvb_tuner_info *info;
|
struct dvb_tuner_info *info;
|
||||||
|
|
||||||
state = kzalloc(sizeof(struct tda665x_state), GFP_KERNEL);
|
state = kzalloc(sizeof(struct tda665x_state), GFP_KERNEL);
|
||||||
if (state == NULL)
|
if (!state)
|
||||||
goto exit;
|
return NULL;
|
||||||
|
|
||||||
state->config = config;
|
state->config = config;
|
||||||
state->i2c = i2c;
|
state->i2c = i2c;
|
||||||
|
@ -246,10 +246,6 @@ struct dvb_frontend *tda665x_attach(struct dvb_frontend *fe,
|
||||||
printk(KERN_DEBUG "%s: Attaching TDA665x (%s) tuner\n", __func__, info->name);
|
printk(KERN_DEBUG "%s: Attaching TDA665x (%s) tuner\n", __func__, info->name);
|
||||||
|
|
||||||
return fe;
|
return fe;
|
||||||
|
|
||||||
exit:
|
|
||||||
kfree(state);
|
|
||||||
return NULL;
|
|
||||||
}
|
}
|
||||||
EXPORT_SYMBOL(tda665x_attach);
|
EXPORT_SYMBOL(tda665x_attach);
|
||||||
|
|
||||||
|
|
|
@ -175,7 +175,7 @@ static void tda8083_wait_diseqc_fifo (struct tda8083_state* state, int timeout)
|
||||||
!(tda8083_readreg(state, 0x02) & 0x80))
|
!(tda8083_readreg(state, 0x02) & 0x80))
|
||||||
{
|
{
|
||||||
msleep(50);
|
msleep(50);
|
||||||
};
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static int tda8083_set_tone (struct tda8083_state* state, fe_sec_tone_mode_t tone)
|
static int tda8083_set_tone (struct tda8083_state* state, fe_sec_tone_mode_t tone)
|
||||||
|
@ -215,7 +215,7 @@ static int tda8083_send_diseqc_burst (struct tda8083_state* state, fe_sec_mini_c
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
};
|
}
|
||||||
|
|
||||||
tda8083_wait_diseqc_fifo (state, 100);
|
tda8083_wait_diseqc_fifo (state, 100);
|
||||||
|
|
||||||
|
|
|
@ -599,7 +599,7 @@ static void cx23885_initialize(struct i2c_client *client)
|
||||||
cx25840_write4(client, 0x114, 0x01bf0c9e);
|
cx25840_write4(client, 0x114, 0x01bf0c9e);
|
||||||
cx25840_write4(client, 0x110, 0x000a030c);
|
cx25840_write4(client, 0x110, 0x000a030c);
|
||||||
break;
|
break;
|
||||||
};
|
}
|
||||||
|
|
||||||
/* ADC2 input select */
|
/* ADC2 input select */
|
||||||
cx25840_write(client, 0x102, 0x10);
|
cx25840_write(client, 0x102, 0x10);
|
||||||
|
|
|
@ -16,9 +16,17 @@
|
||||||
#ifndef M5MOLS_H
|
#ifndef M5MOLS_H
|
||||||
#define M5MOLS_H
|
#define M5MOLS_H
|
||||||
|
|
||||||
|
#include <linux/sizes.h>
|
||||||
#include <media/v4l2-subdev.h>
|
#include <media/v4l2-subdev.h>
|
||||||
#include "m5mols_reg.h"
|
#include "m5mols_reg.h"
|
||||||
|
|
||||||
|
|
||||||
|
/* An amount of data transmitted in addition to the value
|
||||||
|
* determined by CAPP_JPEG_SIZE_MAX register.
|
||||||
|
*/
|
||||||
|
#define M5MOLS_JPEG_TAGS_SIZE 0x20000
|
||||||
|
#define M5MOLS_MAIN_JPEG_SIZE_MAX (5 * SZ_1M)
|
||||||
|
|
||||||
extern int m5mols_debug;
|
extern int m5mols_debug;
|
||||||
|
|
||||||
enum m5mols_restype {
|
enum m5mols_restype {
|
||||||
|
@ -67,12 +75,14 @@ struct m5mols_exif {
|
||||||
/**
|
/**
|
||||||
* struct m5mols_capture - Structure for the capture capability
|
* struct m5mols_capture - Structure for the capture capability
|
||||||
* @exif: EXIF information
|
* @exif: EXIF information
|
||||||
|
* @buf_size: internal JPEG frame buffer size, in bytes
|
||||||
* @main: size in bytes of the main image
|
* @main: size in bytes of the main image
|
||||||
* @thumb: size in bytes of the thumb image, if it was accompanied
|
* @thumb: size in bytes of the thumb image, if it was accompanied
|
||||||
* @total: total size in bytes of the produced image
|
* @total: total size in bytes of the produced image
|
||||||
*/
|
*/
|
||||||
struct m5mols_capture {
|
struct m5mols_capture {
|
||||||
struct m5mols_exif exif;
|
struct m5mols_exif exif;
|
||||||
|
unsigned int buf_size;
|
||||||
u32 main;
|
u32 main;
|
||||||
u32 thumb;
|
u32 thumb;
|
||||||
u32 total;
|
u32 total;
|
||||||
|
|
|
@ -105,6 +105,7 @@ static int m5mols_capture_info(struct m5mols_info *info)
|
||||||
|
|
||||||
int m5mols_start_capture(struct m5mols_info *info)
|
int m5mols_start_capture(struct m5mols_info *info)
|
||||||
{
|
{
|
||||||
|
unsigned int framesize = info->cap.buf_size - M5MOLS_JPEG_TAGS_SIZE;
|
||||||
struct v4l2_subdev *sd = &info->sd;
|
struct v4l2_subdev *sd = &info->sd;
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
|
@ -120,6 +121,8 @@ int m5mols_start_capture(struct m5mols_info *info)
|
||||||
ret = m5mols_write(sd, CAPP_YUVOUT_MAIN, REG_JPEG);
|
ret = m5mols_write(sd, CAPP_YUVOUT_MAIN, REG_JPEG);
|
||||||
if (!ret)
|
if (!ret)
|
||||||
ret = m5mols_write(sd, CAPP_MAIN_IMAGE_SIZE, info->resolution);
|
ret = m5mols_write(sd, CAPP_MAIN_IMAGE_SIZE, info->resolution);
|
||||||
|
if (!ret)
|
||||||
|
ret = m5mols_write(sd, CAPP_JPEG_SIZE_MAX, framesize);
|
||||||
if (!ret)
|
if (!ret)
|
||||||
ret = m5mols_set_mode(info, REG_CAPTURE);
|
ret = m5mols_set_mode(info, REG_CAPTURE);
|
||||||
if (!ret)
|
if (!ret)
|
||||||
|
|
|
@ -599,6 +599,51 @@ static int m5mols_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static int m5mols_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad,
|
||||||
|
struct v4l2_mbus_frame_desc *fd)
|
||||||
|
{
|
||||||
|
struct m5mols_info *info = to_m5mols(sd);
|
||||||
|
|
||||||
|
if (pad != 0 || fd == NULL)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
mutex_lock(&info->lock);
|
||||||
|
/*
|
||||||
|
* .get_frame_desc is only used for compressed formats,
|
||||||
|
* thus we always return the capture frame parameters here.
|
||||||
|
*/
|
||||||
|
fd->entry[0].length = info->cap.buf_size;
|
||||||
|
fd->entry[0].pixelcode = info->ffmt[M5MOLS_RESTYPE_CAPTURE].code;
|
||||||
|
mutex_unlock(&info->lock);
|
||||||
|
|
||||||
|
fd->entry[0].flags = V4L2_MBUS_FRAME_DESC_FL_LEN_MAX;
|
||||||
|
fd->num_entries = 1;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int m5mols_set_frame_desc(struct v4l2_subdev *sd, unsigned int pad,
|
||||||
|
struct v4l2_mbus_frame_desc *fd)
|
||||||
|
{
|
||||||
|
struct m5mols_info *info = to_m5mols(sd);
|
||||||
|
struct v4l2_mbus_framefmt *mf = &info->ffmt[M5MOLS_RESTYPE_CAPTURE];
|
||||||
|
|
||||||
|
if (pad != 0 || fd == NULL)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
fd->entry[0].flags = V4L2_MBUS_FRAME_DESC_FL_LEN_MAX;
|
||||||
|
fd->num_entries = 1;
|
||||||
|
fd->entry[0].length = clamp_t(u32, fd->entry[0].length,
|
||||||
|
mf->width * mf->height,
|
||||||
|
M5MOLS_MAIN_JPEG_SIZE_MAX);
|
||||||
|
mutex_lock(&info->lock);
|
||||||
|
info->cap.buf_size = fd->entry[0].length;
|
||||||
|
mutex_unlock(&info->lock);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
static int m5mols_enum_mbus_code(struct v4l2_subdev *sd,
|
static int m5mols_enum_mbus_code(struct v4l2_subdev *sd,
|
||||||
struct v4l2_subdev_fh *fh,
|
struct v4l2_subdev_fh *fh,
|
||||||
struct v4l2_subdev_mbus_code_enum *code)
|
struct v4l2_subdev_mbus_code_enum *code)
|
||||||
|
@ -615,6 +660,8 @@ static struct v4l2_subdev_pad_ops m5mols_pad_ops = {
|
||||||
.enum_mbus_code = m5mols_enum_mbus_code,
|
.enum_mbus_code = m5mols_enum_mbus_code,
|
||||||
.get_fmt = m5mols_get_fmt,
|
.get_fmt = m5mols_get_fmt,
|
||||||
.set_fmt = m5mols_set_fmt,
|
.set_fmt = m5mols_set_fmt,
|
||||||
|
.get_frame_desc = m5mols_get_frame_desc,
|
||||||
|
.set_frame_desc = m5mols_set_frame_desc,
|
||||||
};
|
};
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
|
@ -310,6 +310,7 @@
|
||||||
#define REG_JPEG 0x10
|
#define REG_JPEG 0x10
|
||||||
|
|
||||||
#define CAPP_MAIN_IMAGE_SIZE I2C_REG(CAT_CAPT_PARM, 0x01, 1)
|
#define CAPP_MAIN_IMAGE_SIZE I2C_REG(CAT_CAPT_PARM, 0x01, 1)
|
||||||
|
#define CAPP_JPEG_SIZE_MAX I2C_REG(CAT_CAPT_PARM, 0x0f, 4)
|
||||||
#define CAPP_JPEG_RATIO I2C_REG(CAT_CAPT_PARM, 0x17, 1)
|
#define CAPP_JPEG_RATIO I2C_REG(CAT_CAPT_PARM, 0x17, 1)
|
||||||
|
|
||||||
#define CAPP_MCC_MODE I2C_REG(CAT_CAPT_PARM, 0x1d, 1)
|
#define CAPP_MCC_MODE I2C_REG(CAT_CAPT_PARM, 0x1d, 1)
|
||||||
|
|
|
@ -574,7 +574,6 @@ static int mt9p031_set_crop(struct v4l2_subdev *subdev,
|
||||||
* V4L2 subdev control operations
|
* V4L2 subdev control operations
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#define V4L2_CID_TEST_PATTERN (V4L2_CID_USER_BASE | 0x1001)
|
|
||||||
#define V4L2_CID_BLC_AUTO (V4L2_CID_USER_BASE | 0x1002)
|
#define V4L2_CID_BLC_AUTO (V4L2_CID_USER_BASE | 0x1002)
|
||||||
#define V4L2_CID_BLC_TARGET_LEVEL (V4L2_CID_USER_BASE | 0x1003)
|
#define V4L2_CID_BLC_TARGET_LEVEL (V4L2_CID_USER_BASE | 0x1003)
|
||||||
#define V4L2_CID_BLC_ANALOG_OFFSET (V4L2_CID_USER_BASE | 0x1004)
|
#define V4L2_CID_BLC_ANALOG_OFFSET (V4L2_CID_USER_BASE | 0x1004)
|
||||||
|
@ -739,18 +738,6 @@ static const char * const mt9p031_test_pattern_menu[] = {
|
||||||
|
|
||||||
static const struct v4l2_ctrl_config mt9p031_ctrls[] = {
|
static const struct v4l2_ctrl_config mt9p031_ctrls[] = {
|
||||||
{
|
{
|
||||||
.ops = &mt9p031_ctrl_ops,
|
|
||||||
.id = V4L2_CID_TEST_PATTERN,
|
|
||||||
.type = V4L2_CTRL_TYPE_MENU,
|
|
||||||
.name = "Test Pattern",
|
|
||||||
.min = 0,
|
|
||||||
.max = ARRAY_SIZE(mt9p031_test_pattern_menu) - 1,
|
|
||||||
.step = 0,
|
|
||||||
.def = 0,
|
|
||||||
.flags = 0,
|
|
||||||
.menu_skip_mask = 0,
|
|
||||||
.qmenu = mt9p031_test_pattern_menu,
|
|
||||||
}, {
|
|
||||||
.ops = &mt9p031_ctrl_ops,
|
.ops = &mt9p031_ctrl_ops,
|
||||||
.id = V4L2_CID_BLC_AUTO,
|
.id = V4L2_CID_BLC_AUTO,
|
||||||
.type = V4L2_CTRL_TYPE_BOOLEAN,
|
.type = V4L2_CTRL_TYPE_BOOLEAN,
|
||||||
|
@ -950,7 +937,7 @@ static int mt9p031_probe(struct i2c_client *client,
|
||||||
mt9p031->model = did->driver_data;
|
mt9p031->model = did->driver_data;
|
||||||
mt9p031->reset = -1;
|
mt9p031->reset = -1;
|
||||||
|
|
||||||
v4l2_ctrl_handler_init(&mt9p031->ctrls, ARRAY_SIZE(mt9p031_ctrls) + 5);
|
v4l2_ctrl_handler_init(&mt9p031->ctrls, ARRAY_SIZE(mt9p031_ctrls) + 6);
|
||||||
|
|
||||||
v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops,
|
v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops,
|
||||||
V4L2_CID_EXPOSURE, MT9P031_SHUTTER_WIDTH_MIN,
|
V4L2_CID_EXPOSURE, MT9P031_SHUTTER_WIDTH_MIN,
|
||||||
|
@ -966,6 +953,10 @@ static int mt9p031_probe(struct i2c_client *client,
|
||||||
v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops,
|
v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops,
|
||||||
V4L2_CID_PIXEL_RATE, pdata->target_freq,
|
V4L2_CID_PIXEL_RATE, pdata->target_freq,
|
||||||
pdata->target_freq, 1, pdata->target_freq);
|
pdata->target_freq, 1, pdata->target_freq);
|
||||||
|
v4l2_ctrl_new_std_menu_items(&mt9p031->ctrls, &mt9p031_ctrl_ops,
|
||||||
|
V4L2_CID_TEST_PATTERN,
|
||||||
|
ARRAY_SIZE(mt9p031_test_pattern_menu) - 1, 0,
|
||||||
|
0, mt9p031_test_pattern_menu);
|
||||||
|
|
||||||
for (i = 0; i < ARRAY_SIZE(mt9p031_ctrls); ++i)
|
for (i = 0; i < ARRAY_SIZE(mt9p031_ctrls); ++i)
|
||||||
v4l2_ctrl_new_custom(&mt9p031->ctrls, &mt9p031_ctrls[i], NULL);
|
v4l2_ctrl_new_custom(&mt9p031->ctrls, &mt9p031_ctrls[i], NULL);
|
||||||
|
|
|
@ -371,7 +371,7 @@ static int mt9t001_set_crop(struct v4l2_subdev *subdev,
|
||||||
* V4L2 subdev control operations
|
* V4L2 subdev control operations
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#define V4L2_CID_TEST_PATTERN (V4L2_CID_USER_BASE | 0x1001)
|
#define V4L2_CID_TEST_PATTERN_COLOR (V4L2_CID_USER_BASE | 0x1001)
|
||||||
#define V4L2_CID_BLACK_LEVEL_AUTO (V4L2_CID_USER_BASE | 0x1002)
|
#define V4L2_CID_BLACK_LEVEL_AUTO (V4L2_CID_USER_BASE | 0x1002)
|
||||||
#define V4L2_CID_BLACK_LEVEL_OFFSET (V4L2_CID_USER_BASE | 0x1003)
|
#define V4L2_CID_BLACK_LEVEL_OFFSET (V4L2_CID_USER_BASE | 0x1003)
|
||||||
#define V4L2_CID_BLACK_LEVEL_CALIBRATE (V4L2_CID_USER_BASE | 0x1004)
|
#define V4L2_CID_BLACK_LEVEL_CALIBRATE (V4L2_CID_USER_BASE | 0x1004)
|
||||||
|
@ -487,12 +487,11 @@ static int mt9t001_s_ctrl(struct v4l2_ctrl *ctrl)
|
||||||
ctrl->val >> 16);
|
ctrl->val >> 16);
|
||||||
|
|
||||||
case V4L2_CID_TEST_PATTERN:
|
case V4L2_CID_TEST_PATTERN:
|
||||||
ret = mt9t001_set_output_control(mt9t001,
|
return mt9t001_set_output_control(mt9t001,
|
||||||
ctrl->val ? 0 : MT9T001_OUTPUT_CONTROL_TEST_DATA,
|
ctrl->val ? 0 : MT9T001_OUTPUT_CONTROL_TEST_DATA,
|
||||||
ctrl->val ? MT9T001_OUTPUT_CONTROL_TEST_DATA : 0);
|
ctrl->val ? MT9T001_OUTPUT_CONTROL_TEST_DATA : 0);
|
||||||
if (ret < 0)
|
|
||||||
return ret;
|
|
||||||
|
|
||||||
|
case V4L2_CID_TEST_PATTERN_COLOR:
|
||||||
return mt9t001_write(client, MT9T001_TEST_DATA, ctrl->val << 2);
|
return mt9t001_write(client, MT9T001_TEST_DATA, ctrl->val << 2);
|
||||||
|
|
||||||
case V4L2_CID_BLACK_LEVEL_AUTO:
|
case V4L2_CID_BLACK_LEVEL_AUTO:
|
||||||
|
@ -533,12 +532,17 @@ static struct v4l2_ctrl_ops mt9t001_ctrl_ops = {
|
||||||
.s_ctrl = mt9t001_s_ctrl,
|
.s_ctrl = mt9t001_s_ctrl,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static const char * const mt9t001_test_pattern_menu[] = {
|
||||||
|
"Disabled",
|
||||||
|
"Enabled",
|
||||||
|
};
|
||||||
|
|
||||||
static const struct v4l2_ctrl_config mt9t001_ctrls[] = {
|
static const struct v4l2_ctrl_config mt9t001_ctrls[] = {
|
||||||
{
|
{
|
||||||
.ops = &mt9t001_ctrl_ops,
|
.ops = &mt9t001_ctrl_ops,
|
||||||
.id = V4L2_CID_TEST_PATTERN,
|
.id = V4L2_CID_TEST_PATTERN_COLOR,
|
||||||
.type = V4L2_CTRL_TYPE_INTEGER,
|
.type = V4L2_CTRL_TYPE_INTEGER,
|
||||||
.name = "Test pattern",
|
.name = "Test Pattern Color",
|
||||||
.min = 0,
|
.min = 0,
|
||||||
.max = 1023,
|
.max = 1023,
|
||||||
.step = 1,
|
.step = 1,
|
||||||
|
@ -741,7 +745,7 @@ static int mt9t001_probe(struct i2c_client *client,
|
||||||
return -ENOMEM;
|
return -ENOMEM;
|
||||||
|
|
||||||
v4l2_ctrl_handler_init(&mt9t001->ctrls, ARRAY_SIZE(mt9t001_ctrls) +
|
v4l2_ctrl_handler_init(&mt9t001->ctrls, ARRAY_SIZE(mt9t001_ctrls) +
|
||||||
ARRAY_SIZE(mt9t001_gains) + 3);
|
ARRAY_SIZE(mt9t001_gains) + 4);
|
||||||
|
|
||||||
v4l2_ctrl_new_std(&mt9t001->ctrls, &mt9t001_ctrl_ops,
|
v4l2_ctrl_new_std(&mt9t001->ctrls, &mt9t001_ctrl_ops,
|
||||||
V4L2_CID_EXPOSURE, MT9T001_SHUTTER_WIDTH_MIN,
|
V4L2_CID_EXPOSURE, MT9T001_SHUTTER_WIDTH_MIN,
|
||||||
|
@ -752,6 +756,10 @@ static int mt9t001_probe(struct i2c_client *client,
|
||||||
v4l2_ctrl_new_std(&mt9t001->ctrls, &mt9t001_ctrl_ops,
|
v4l2_ctrl_new_std(&mt9t001->ctrls, &mt9t001_ctrl_ops,
|
||||||
V4L2_CID_PIXEL_RATE, pdata->ext_clk, pdata->ext_clk,
|
V4L2_CID_PIXEL_RATE, pdata->ext_clk, pdata->ext_clk,
|
||||||
1, pdata->ext_clk);
|
1, pdata->ext_clk);
|
||||||
|
v4l2_ctrl_new_std_menu_items(&mt9t001->ctrls, &mt9t001_ctrl_ops,
|
||||||
|
V4L2_CID_TEST_PATTERN,
|
||||||
|
ARRAY_SIZE(mt9t001_test_pattern_menu) - 1, 0,
|
||||||
|
0, mt9t001_test_pattern_menu);
|
||||||
|
|
||||||
for (i = 0; i < ARRAY_SIZE(mt9t001_ctrls); ++i)
|
for (i = 0; i < ARRAY_SIZE(mt9t001_ctrls); ++i)
|
||||||
v4l2_ctrl_new_custom(&mt9t001->ctrls, &mt9t001_ctrls[i], NULL);
|
v4l2_ctrl_new_custom(&mt9t001->ctrls, &mt9t001_ctrls[i], NULL);
|
||||||
|
|
|
@ -141,6 +141,10 @@ struct mt9v032 {
|
||||||
u16 chip_control;
|
u16 chip_control;
|
||||||
u16 aec_agc;
|
u16 aec_agc;
|
||||||
u16 hblank;
|
u16 hblank;
|
||||||
|
struct {
|
||||||
|
struct v4l2_ctrl *test_pattern;
|
||||||
|
struct v4l2_ctrl *test_pattern_color;
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct mt9v032 *to_mt9v032(struct v4l2_subdev *sd)
|
static struct mt9v032 *to_mt9v032(struct v4l2_subdev *sd)
|
||||||
|
@ -500,7 +504,7 @@ static int mt9v032_set_crop(struct v4l2_subdev *subdev,
|
||||||
* V4L2 subdev control operations
|
* V4L2 subdev control operations
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#define V4L2_CID_TEST_PATTERN (V4L2_CID_USER_BASE | 0x1001)
|
#define V4L2_CID_TEST_PATTERN_COLOR (V4L2_CID_USER_BASE | 0x1001)
|
||||||
|
|
||||||
static int mt9v032_s_ctrl(struct v4l2_ctrl *ctrl)
|
static int mt9v032_s_ctrl(struct v4l2_ctrl *ctrl)
|
||||||
{
|
{
|
||||||
|
@ -545,7 +549,7 @@ static int mt9v032_s_ctrl(struct v4l2_ctrl *ctrl)
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case V4L2_CID_TEST_PATTERN:
|
case V4L2_CID_TEST_PATTERN:
|
||||||
switch (ctrl->val) {
|
switch (mt9v032->test_pattern->val) {
|
||||||
case 0:
|
case 0:
|
||||||
data = 0;
|
data = 0;
|
||||||
break;
|
break;
|
||||||
|
@ -562,13 +566,13 @@ static int mt9v032_s_ctrl(struct v4l2_ctrl *ctrl)
|
||||||
| MT9V032_TEST_PATTERN_ENABLE;
|
| MT9V032_TEST_PATTERN_ENABLE;
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
data = (ctrl->val << MT9V032_TEST_PATTERN_DATA_SHIFT)
|
data = (mt9v032->test_pattern_color->val <<
|
||||||
|
MT9V032_TEST_PATTERN_DATA_SHIFT)
|
||||||
| MT9V032_TEST_PATTERN_USE_DATA
|
| MT9V032_TEST_PATTERN_USE_DATA
|
||||||
| MT9V032_TEST_PATTERN_ENABLE
|
| MT9V032_TEST_PATTERN_ENABLE
|
||||||
| MT9V032_TEST_PATTERN_FLIP;
|
| MT9V032_TEST_PATTERN_FLIP;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
return mt9v032_write(client, MT9V032_TEST_PATTERN, data);
|
return mt9v032_write(client, MT9V032_TEST_PATTERN, data);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -579,18 +583,24 @@ static struct v4l2_ctrl_ops mt9v032_ctrl_ops = {
|
||||||
.s_ctrl = mt9v032_s_ctrl,
|
.s_ctrl = mt9v032_s_ctrl,
|
||||||
};
|
};
|
||||||
|
|
||||||
static const struct v4l2_ctrl_config mt9v032_ctrls[] = {
|
static const char * const mt9v032_test_pattern_menu[] = {
|
||||||
{
|
"Disabled",
|
||||||
.ops = &mt9v032_ctrl_ops,
|
"Gray Vertical Shade",
|
||||||
.id = V4L2_CID_TEST_PATTERN,
|
"Gray Horizontal Shade",
|
||||||
.type = V4L2_CTRL_TYPE_INTEGER,
|
"Gray Diagonal Shade",
|
||||||
.name = "Test pattern",
|
"Plain",
|
||||||
.min = 0,
|
};
|
||||||
.max = 1023,
|
|
||||||
.step = 1,
|
static const struct v4l2_ctrl_config mt9v032_test_pattern_color = {
|
||||||
.def = 0,
|
.ops = &mt9v032_ctrl_ops,
|
||||||
.flags = 0,
|
.id = V4L2_CID_TEST_PATTERN_COLOR,
|
||||||
}
|
.type = V4L2_CTRL_TYPE_INTEGER,
|
||||||
|
.name = "Test Pattern Color",
|
||||||
|
.min = 0,
|
||||||
|
.max = 1023,
|
||||||
|
.step = 1,
|
||||||
|
.def = 0,
|
||||||
|
.flags = 0,
|
||||||
};
|
};
|
||||||
|
|
||||||
/* -----------------------------------------------------------------------------
|
/* -----------------------------------------------------------------------------
|
||||||
|
@ -741,7 +751,7 @@ static int mt9v032_probe(struct i2c_client *client,
|
||||||
mutex_init(&mt9v032->power_lock);
|
mutex_init(&mt9v032->power_lock);
|
||||||
mt9v032->pdata = pdata;
|
mt9v032->pdata = pdata;
|
||||||
|
|
||||||
v4l2_ctrl_handler_init(&mt9v032->ctrls, ARRAY_SIZE(mt9v032_ctrls) + 8);
|
v4l2_ctrl_handler_init(&mt9v032->ctrls, 10);
|
||||||
|
|
||||||
v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
|
v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
|
||||||
V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
|
V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
|
||||||
|
@ -763,6 +773,14 @@ static int mt9v032_probe(struct i2c_client *client,
|
||||||
V4L2_CID_VBLANK, MT9V032_VERTICAL_BLANKING_MIN,
|
V4L2_CID_VBLANK, MT9V032_VERTICAL_BLANKING_MIN,
|
||||||
MT9V032_VERTICAL_BLANKING_MAX, 1,
|
MT9V032_VERTICAL_BLANKING_MAX, 1,
|
||||||
MT9V032_VERTICAL_BLANKING_DEF);
|
MT9V032_VERTICAL_BLANKING_DEF);
|
||||||
|
mt9v032->test_pattern = v4l2_ctrl_new_std_menu_items(&mt9v032->ctrls,
|
||||||
|
&mt9v032_ctrl_ops, V4L2_CID_TEST_PATTERN,
|
||||||
|
ARRAY_SIZE(mt9v032_test_pattern_menu) - 1, 0, 0,
|
||||||
|
mt9v032_test_pattern_menu);
|
||||||
|
mt9v032->test_pattern_color = v4l2_ctrl_new_custom(&mt9v032->ctrls,
|
||||||
|
&mt9v032_test_pattern_color, NULL);
|
||||||
|
|
||||||
|
v4l2_ctrl_cluster(2, &mt9v032->test_pattern);
|
||||||
|
|
||||||
mt9v032->pixel_rate =
|
mt9v032->pixel_rate =
|
||||||
v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
|
v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
|
||||||
|
@ -784,8 +802,6 @@ static int mt9v032_probe(struct i2c_client *client,
|
||||||
v4l2_ctrl_cluster(2, &mt9v032->link_freq);
|
v4l2_ctrl_cluster(2, &mt9v032->link_freq);
|
||||||
}
|
}
|
||||||
|
|
||||||
for (i = 0; i < ARRAY_SIZE(mt9v032_ctrls); ++i)
|
|
||||||
v4l2_ctrl_new_custom(&mt9v032->ctrls, &mt9v032_ctrls[i], NULL);
|
|
||||||
|
|
||||||
mt9v032->subdev.ctrl_handler = &mt9v032->ctrls;
|
mt9v032->subdev.ctrl_handler = &mt9v032->ctrls;
|
||||||
|
|
||||||
|
|
|
@ -684,6 +684,11 @@ static int ov2640_s_ctrl(struct v4l2_ctrl *ctrl)
|
||||||
&container_of(ctrl->handler, struct ov2640_priv, hdl)->subdev;
|
&container_of(ctrl->handler, struct ov2640_priv, hdl)->subdev;
|
||||||
struct i2c_client *client = v4l2_get_subdevdata(sd);
|
struct i2c_client *client = v4l2_get_subdevdata(sd);
|
||||||
u8 val;
|
u8 val;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
ret = i2c_smbus_write_byte_data(client, BANK_SEL, BANK_SEL_SENS);
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
|
||||||
switch (ctrl->id) {
|
switch (ctrl->id) {
|
||||||
case V4L2_CID_VFLIP:
|
case V4L2_CID_VFLIP:
|
||||||
|
|
|
@ -28,6 +28,18 @@
|
||||||
#include <media/v4l2-subdev.h>
|
#include <media/v4l2-subdev.h>
|
||||||
#include <media/v4l2-chip-ident.h>
|
#include <media/v4l2-chip-ident.h>
|
||||||
|
|
||||||
|
#define THS7303_CHANNEL_1 1
|
||||||
|
#define THS7303_CHANNEL_2 2
|
||||||
|
#define THS7303_CHANNEL_3 3
|
||||||
|
|
||||||
|
enum ths7303_filter_mode {
|
||||||
|
THS7303_FILTER_MODE_480I_576I,
|
||||||
|
THS7303_FILTER_MODE_480P_576P,
|
||||||
|
THS7303_FILTER_MODE_720P_1080I,
|
||||||
|
THS7303_FILTER_MODE_1080P,
|
||||||
|
THS7303_FILTER_MODE_DISABLE
|
||||||
|
};
|
||||||
|
|
||||||
MODULE_DESCRIPTION("TI THS7303 video amplifier driver");
|
MODULE_DESCRIPTION("TI THS7303 video amplifier driver");
|
||||||
MODULE_AUTHOR("Chaithrika U S");
|
MODULE_AUTHOR("Chaithrika U S");
|
||||||
MODULE_LICENSE("GPL");
|
MODULE_LICENSE("GPL");
|
||||||
|
@ -37,35 +49,96 @@ module_param(debug, int, 0644);
|
||||||
MODULE_PARM_DESC(debug, "Debug level 0-1");
|
MODULE_PARM_DESC(debug, "Debug level 0-1");
|
||||||
|
|
||||||
/* following function is used to set ths7303 */
|
/* following function is used to set ths7303 */
|
||||||
static int ths7303_setvalue(struct v4l2_subdev *sd, v4l2_std_id std)
|
int ths7303_setval(struct v4l2_subdev *sd, enum ths7303_filter_mode mode)
|
||||||
{
|
{
|
||||||
|
u8 input_bias_chroma = 3;
|
||||||
|
u8 input_bias_luma = 3;
|
||||||
|
int disable = 0;
|
||||||
int err = 0;
|
int err = 0;
|
||||||
u8 val;
|
u8 val = 0;
|
||||||
struct i2c_client *client;
|
u8 temp;
|
||||||
|
|
||||||
client = v4l2_get_subdevdata(sd);
|
struct i2c_client *client = v4l2_get_subdevdata(sd);
|
||||||
|
|
||||||
if (std & (V4L2_STD_ALL & ~V4L2_STD_SECAM)) {
|
if (!client)
|
||||||
val = 0x02;
|
return -EINVAL;
|
||||||
v4l2_dbg(1, debug, sd, "setting value for SDTV format\n");
|
|
||||||
} else {
|
switch (mode) {
|
||||||
val = 0x00;
|
case THS7303_FILTER_MODE_1080P:
|
||||||
v4l2_dbg(1, debug, sd, "disabling all channels\n");
|
val = (3 << 6);
|
||||||
|
val |= (3 << 3);
|
||||||
|
break;
|
||||||
|
case THS7303_FILTER_MODE_720P_1080I:
|
||||||
|
val = (2 << 6);
|
||||||
|
val |= (2 << 3);
|
||||||
|
break;
|
||||||
|
case THS7303_FILTER_MODE_480P_576P:
|
||||||
|
val = (1 << 6);
|
||||||
|
val |= (1 << 3);
|
||||||
|
break;
|
||||||
|
case THS7303_FILTER_MODE_480I_576I:
|
||||||
|
break;
|
||||||
|
case THS7303_FILTER_MODE_DISABLE:
|
||||||
|
pr_info("mode disabled\n");
|
||||||
|
/* disable all channels */
|
||||||
|
disable = 1;
|
||||||
|
default:
|
||||||
|
/* disable all channels */
|
||||||
|
disable = 1;
|
||||||
}
|
}
|
||||||
|
/* Setup channel 2 - Luma - Green */
|
||||||
err |= i2c_smbus_write_byte_data(client, 0x01, val);
|
temp = val;
|
||||||
err |= i2c_smbus_write_byte_data(client, 0x02, val);
|
if (!disable)
|
||||||
err |= i2c_smbus_write_byte_data(client, 0x03, val);
|
val |= input_bias_luma;
|
||||||
|
err = i2c_smbus_write_byte_data(client, THS7303_CHANNEL_2, val);
|
||||||
if (err)
|
if (err)
|
||||||
v4l2_err(sd, "write failed\n");
|
goto out;
|
||||||
|
|
||||||
|
/* setup two chroma channels */
|
||||||
|
if (!disable)
|
||||||
|
temp |= input_bias_chroma;
|
||||||
|
|
||||||
|
err = i2c_smbus_write_byte_data(client, THS7303_CHANNEL_1, temp);
|
||||||
|
if (err)
|
||||||
|
goto out;
|
||||||
|
|
||||||
|
err = i2c_smbus_write_byte_data(client, THS7303_CHANNEL_3, temp);
|
||||||
|
if (err)
|
||||||
|
goto out;
|
||||||
|
return err;
|
||||||
|
out:
|
||||||
|
pr_info("write byte data failed\n");
|
||||||
return err;
|
return err;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int ths7303_s_std_output(struct v4l2_subdev *sd, v4l2_std_id norm)
|
static int ths7303_s_std_output(struct v4l2_subdev *sd, v4l2_std_id norm)
|
||||||
{
|
{
|
||||||
return ths7303_setvalue(sd, norm);
|
if (norm & (V4L2_STD_ALL & ~V4L2_STD_SECAM))
|
||||||
|
return ths7303_setval(sd, THS7303_FILTER_MODE_480I_576I);
|
||||||
|
else
|
||||||
|
return ths7303_setval(sd, THS7303_FILTER_MODE_DISABLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* for setting filter for HD output */
|
||||||
|
static int ths7303_s_dv_timings(struct v4l2_subdev *sd,
|
||||||
|
struct v4l2_dv_timings *dv_timings)
|
||||||
|
{
|
||||||
|
u32 height = dv_timings->bt.height;
|
||||||
|
int interlaced = dv_timings->bt.interlaced;
|
||||||
|
int res = 0;
|
||||||
|
|
||||||
|
if (height == 1080 && !interlaced)
|
||||||
|
res = ths7303_setval(sd, THS7303_FILTER_MODE_1080P);
|
||||||
|
else if ((height == 720 && !interlaced) ||
|
||||||
|
(height == 1080 && interlaced))
|
||||||
|
res = ths7303_setval(sd, THS7303_FILTER_MODE_720P_1080I);
|
||||||
|
else if ((height == 480 || height == 576) && !interlaced)
|
||||||
|
res = ths7303_setval(sd, THS7303_FILTER_MODE_480P_576P);
|
||||||
|
else
|
||||||
|
/* disable all channels */
|
||||||
|
res = ths7303_setval(sd, THS7303_FILTER_MODE_DISABLE);
|
||||||
|
|
||||||
|
return res;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int ths7303_g_chip_ident(struct v4l2_subdev *sd,
|
static int ths7303_g_chip_ident(struct v4l2_subdev *sd,
|
||||||
|
@ -78,6 +151,7 @@ static int ths7303_g_chip_ident(struct v4l2_subdev *sd,
|
||||||
|
|
||||||
static const struct v4l2_subdev_video_ops ths7303_video_ops = {
|
static const struct v4l2_subdev_video_ops ths7303_video_ops = {
|
||||||
.s_std_output = ths7303_s_std_output,
|
.s_std_output = ths7303_s_std_output,
|
||||||
|
.s_dv_timings = ths7303_s_dv_timings,
|
||||||
};
|
};
|
||||||
|
|
||||||
static const struct v4l2_subdev_core_ops ths7303_core_ops = {
|
static const struct v4l2_subdev_core_ops ths7303_core_ops = {
|
||||||
|
@ -107,7 +181,7 @@ static int ths7303_probe(struct i2c_client *client,
|
||||||
|
|
||||||
v4l2_i2c_subdev_init(sd, client, &ths7303_ops);
|
v4l2_i2c_subdev_init(sd, client, &ths7303_ops);
|
||||||
|
|
||||||
return ths7303_setvalue(sd, std_id);
|
return ths7303_s_std_output(sd, std_id);
|
||||||
}
|
}
|
||||||
|
|
||||||
static int ths7303_remove(struct i2c_client *client)
|
static int ths7303_remove(struct i2c_client *client)
|
||||||
|
|
|
@ -519,6 +519,12 @@ static int tvp514x_querystd(struct v4l2_subdev *sd, v4l2_std_id *std_id)
|
||||||
|
|
||||||
*std_id = V4L2_STD_UNKNOWN;
|
*std_id = V4L2_STD_UNKNOWN;
|
||||||
|
|
||||||
|
/* To query the standard the TVP514x must power on the ADCs. */
|
||||||
|
if (!decoder->streaming) {
|
||||||
|
tvp514x_s_stream(sd, 1);
|
||||||
|
msleep(LOCK_RETRY_DELAY);
|
||||||
|
}
|
||||||
|
|
||||||
/* query the current standard */
|
/* query the current standard */
|
||||||
current_std = tvp514x_query_current_std(sd);
|
current_std = tvp514x_query_current_std(sd);
|
||||||
if (current_std == STD_INVALID)
|
if (current_std == STD_INVALID)
|
||||||
|
@ -625,25 +631,12 @@ static int tvp514x_s_routing(struct v4l2_subdev *sd,
|
||||||
int err;
|
int err;
|
||||||
enum tvp514x_input input_sel;
|
enum tvp514x_input input_sel;
|
||||||
enum tvp514x_output output_sel;
|
enum tvp514x_output output_sel;
|
||||||
u8 sync_lock_status, lock_mask;
|
|
||||||
int try_count = LOCK_RETRY_COUNT;
|
|
||||||
|
|
||||||
if ((input >= INPUT_INVALID) ||
|
if ((input >= INPUT_INVALID) ||
|
||||||
(output >= OUTPUT_INVALID))
|
(output >= OUTPUT_INVALID))
|
||||||
/* Index out of bound */
|
/* Index out of bound */
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
||||||
/*
|
|
||||||
* For the sequence streamon -> streamoff and again s_input
|
|
||||||
* it fails to lock the signal, since streamoff puts TVP514x
|
|
||||||
* into power off state which leads to failure in sub-sequent s_input.
|
|
||||||
*
|
|
||||||
* So power up the TVP514x device here, since it is important to lock
|
|
||||||
* the signal at this stage.
|
|
||||||
*/
|
|
||||||
if (!decoder->streaming)
|
|
||||||
tvp514x_s_stream(sd, 1);
|
|
||||||
|
|
||||||
input_sel = input;
|
input_sel = input;
|
||||||
output_sel = output;
|
output_sel = output;
|
||||||
|
|
||||||
|
@ -660,64 +653,6 @@ static int tvp514x_s_routing(struct v4l2_subdev *sd,
|
||||||
|
|
||||||
decoder->tvp514x_regs[REG_INPUT_SEL].val = input_sel;
|
decoder->tvp514x_regs[REG_INPUT_SEL].val = input_sel;
|
||||||
decoder->tvp514x_regs[REG_OUTPUT_FORMATTER1].val = output_sel;
|
decoder->tvp514x_regs[REG_OUTPUT_FORMATTER1].val = output_sel;
|
||||||
|
|
||||||
/* Clear status */
|
|
||||||
msleep(LOCK_RETRY_DELAY);
|
|
||||||
err =
|
|
||||||
tvp514x_write_reg(sd, REG_CLEAR_LOST_LOCK, 0x01);
|
|
||||||
if (err)
|
|
||||||
return err;
|
|
||||||
|
|
||||||
switch (input_sel) {
|
|
||||||
case INPUT_CVBS_VI1A:
|
|
||||||
case INPUT_CVBS_VI1B:
|
|
||||||
case INPUT_CVBS_VI1C:
|
|
||||||
case INPUT_CVBS_VI2A:
|
|
||||||
case INPUT_CVBS_VI2B:
|
|
||||||
case INPUT_CVBS_VI2C:
|
|
||||||
case INPUT_CVBS_VI3A:
|
|
||||||
case INPUT_CVBS_VI3B:
|
|
||||||
case INPUT_CVBS_VI3C:
|
|
||||||
case INPUT_CVBS_VI4A:
|
|
||||||
lock_mask = STATUS_CLR_SUBCAR_LOCK_BIT |
|
|
||||||
STATUS_HORZ_SYNC_LOCK_BIT |
|
|
||||||
STATUS_VIRT_SYNC_LOCK_BIT;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case INPUT_SVIDEO_VI2A_VI1A:
|
|
||||||
case INPUT_SVIDEO_VI2B_VI1B:
|
|
||||||
case INPUT_SVIDEO_VI2C_VI1C:
|
|
||||||
case INPUT_SVIDEO_VI2A_VI3A:
|
|
||||||
case INPUT_SVIDEO_VI2B_VI3B:
|
|
||||||
case INPUT_SVIDEO_VI2C_VI3C:
|
|
||||||
case INPUT_SVIDEO_VI4A_VI1A:
|
|
||||||
case INPUT_SVIDEO_VI4A_VI1B:
|
|
||||||
case INPUT_SVIDEO_VI4A_VI1C:
|
|
||||||
case INPUT_SVIDEO_VI4A_VI3A:
|
|
||||||
case INPUT_SVIDEO_VI4A_VI3B:
|
|
||||||
case INPUT_SVIDEO_VI4A_VI3C:
|
|
||||||
lock_mask = STATUS_HORZ_SYNC_LOCK_BIT |
|
|
||||||
STATUS_VIRT_SYNC_LOCK_BIT;
|
|
||||||
break;
|
|
||||||
/* Need to add other interfaces*/
|
|
||||||
default:
|
|
||||||
return -EINVAL;
|
|
||||||
}
|
|
||||||
|
|
||||||
while (try_count-- > 0) {
|
|
||||||
/* Allow decoder to sync up with new input */
|
|
||||||
msleep(LOCK_RETRY_DELAY);
|
|
||||||
|
|
||||||
sync_lock_status = tvp514x_read_reg(sd,
|
|
||||||
REG_STATUS1);
|
|
||||||
if (lock_mask == (sync_lock_status & lock_mask))
|
|
||||||
/* Input detected */
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (try_count < 0)
|
|
||||||
return -EINVAL;
|
|
||||||
|
|
||||||
decoder->input = input;
|
decoder->input = input;
|
||||||
decoder->output = output;
|
decoder->output = output;
|
||||||
|
|
||||||
|
|
|
@ -668,6 +668,12 @@ static const struct v4l2_queryctrl bttv_ctls[] = {
|
||||||
.default_value = 32768,
|
.default_value = 32768,
|
||||||
.type = V4L2_CTRL_TYPE_INTEGER,
|
.type = V4L2_CTRL_TYPE_INTEGER,
|
||||||
},{
|
},{
|
||||||
|
.id = V4L2_CID_COLOR_KILLER,
|
||||||
|
.name = "Color killer",
|
||||||
|
.minimum = 0,
|
||||||
|
.maximum = 1,
|
||||||
|
.type = V4L2_CTRL_TYPE_BOOLEAN,
|
||||||
|
}, {
|
||||||
.id = V4L2_CID_HUE,
|
.id = V4L2_CID_HUE,
|
||||||
.name = "Hue",
|
.name = "Hue",
|
||||||
.minimum = 0,
|
.minimum = 0,
|
||||||
|
@ -1474,6 +1480,9 @@ static int bttv_g_ctrl(struct file *file, void *priv,
|
||||||
case V4L2_CID_SATURATION:
|
case V4L2_CID_SATURATION:
|
||||||
c->value = btv->saturation;
|
c->value = btv->saturation;
|
||||||
break;
|
break;
|
||||||
|
case V4L2_CID_COLOR_KILLER:
|
||||||
|
c->value = btv->opt_color_killer;
|
||||||
|
break;
|
||||||
|
|
||||||
case V4L2_CID_AUDIO_MUTE:
|
case V4L2_CID_AUDIO_MUTE:
|
||||||
case V4L2_CID_AUDIO_VOLUME:
|
case V4L2_CID_AUDIO_VOLUME:
|
||||||
|
@ -1526,7 +1535,6 @@ static int bttv_s_ctrl(struct file *file, void *f,
|
||||||
struct v4l2_control *c)
|
struct v4l2_control *c)
|
||||||
{
|
{
|
||||||
int err;
|
int err;
|
||||||
int val;
|
|
||||||
struct bttv_fh *fh = f;
|
struct bttv_fh *fh = f;
|
||||||
struct bttv *btv = fh->btv;
|
struct bttv *btv = fh->btv;
|
||||||
|
|
||||||
|
@ -1547,6 +1555,16 @@ static int bttv_s_ctrl(struct file *file, void *f,
|
||||||
case V4L2_CID_SATURATION:
|
case V4L2_CID_SATURATION:
|
||||||
bt848_sat(btv, c->value);
|
bt848_sat(btv, c->value);
|
||||||
break;
|
break;
|
||||||
|
case V4L2_CID_COLOR_KILLER:
|
||||||
|
btv->opt_color_killer = c->value;
|
||||||
|
if (btv->opt_color_killer) {
|
||||||
|
btor(BT848_SCLOOP_CKILL, BT848_E_SCLOOP);
|
||||||
|
btor(BT848_SCLOOP_CKILL, BT848_O_SCLOOP);
|
||||||
|
} else {
|
||||||
|
btand(~BT848_SCLOOP_CKILL, BT848_E_SCLOOP);
|
||||||
|
btand(~BT848_SCLOOP_CKILL, BT848_O_SCLOOP);
|
||||||
|
}
|
||||||
|
break;
|
||||||
case V4L2_CID_AUDIO_MUTE:
|
case V4L2_CID_AUDIO_MUTE:
|
||||||
audio_mute(btv, c->value);
|
audio_mute(btv, c->value);
|
||||||
/* fall through */
|
/* fall through */
|
||||||
|
@ -1564,9 +1582,13 @@ static int bttv_s_ctrl(struct file *file, void *f,
|
||||||
|
|
||||||
case V4L2_CID_PRIVATE_CHROMA_AGC:
|
case V4L2_CID_PRIVATE_CHROMA_AGC:
|
||||||
btv->opt_chroma_agc = c->value;
|
btv->opt_chroma_agc = c->value;
|
||||||
val = btv->opt_chroma_agc ? BT848_SCLOOP_CAGC : 0;
|
if (btv->opt_chroma_agc) {
|
||||||
btwrite(val, BT848_E_SCLOOP);
|
btor(BT848_SCLOOP_CAGC, BT848_E_SCLOOP);
|
||||||
btwrite(val, BT848_O_SCLOOP);
|
btor(BT848_SCLOOP_CAGC, BT848_O_SCLOOP);
|
||||||
|
} else {
|
||||||
|
btand(~BT848_SCLOOP_CAGC, BT848_E_SCLOOP);
|
||||||
|
btand(~BT848_SCLOOP_CAGC, BT848_O_SCLOOP);
|
||||||
|
}
|
||||||
break;
|
break;
|
||||||
case V4L2_CID_PRIVATE_COMBFILTER:
|
case V4L2_CID_PRIVATE_COMBFILTER:
|
||||||
btv->opt_combfilter = c->value;
|
btv->opt_combfilter = c->value;
|
||||||
|
|
|
@ -429,6 +429,7 @@ struct bttv {
|
||||||
int opt_lumafilter;
|
int opt_lumafilter;
|
||||||
int opt_automute;
|
int opt_automute;
|
||||||
int opt_chroma_agc;
|
int opt_chroma_agc;
|
||||||
|
int opt_color_killer;
|
||||||
int opt_adc_crush;
|
int opt_adc_crush;
|
||||||
int opt_vcr_hack;
|
int opt_vcr_hack;
|
||||||
int opt_whitecrush_upper;
|
int opt_whitecrush_upper;
|
||||||
|
|
|
@ -646,7 +646,7 @@ static long dst_ca_ioctl(struct file *file, unsigned int cmd, unsigned long ioct
|
||||||
dprintk(verbose, DST_CA_INFO, 1, " -->CA_SET_PID Success !");
|
dprintk(verbose, DST_CA_INFO, 1, " -->CA_SET_PID Success !");
|
||||||
default:
|
default:
|
||||||
result = -EOPNOTSUPP;
|
result = -EOPNOTSUPP;
|
||||||
};
|
}
|
||||||
free_mem_and_exit:
|
free_mem_and_exit:
|
||||||
kfree (p_ca_message);
|
kfree (p_ca_message);
|
||||||
kfree (p_ca_slot_info);
|
kfree (p_ca_slot_info);
|
||||||
|
|
|
@ -416,7 +416,7 @@ static void netup_read_ci_status(struct work_struct *work)
|
||||||
DVB_CA_EN50221_POLL_CAM_READY : 0);
|
DVB_CA_EN50221_POLL_CAM_READY : 0);
|
||||||
ci_dbg_print("%s: setting CI[1] status = 0x%x\n",
|
ci_dbg_print("%s: setting CI[1] status = 0x%x\n",
|
||||||
__func__, inter->state[1]->status);
|
__func__, inter->state[1]->status);
|
||||||
};
|
}
|
||||||
|
|
||||||
if (inter->state[0] != NULL) {
|
if (inter->state[0] != NULL) {
|
||||||
inter->state[0]->status =
|
inter->state[0]->status =
|
||||||
|
@ -425,7 +425,7 @@ static void netup_read_ci_status(struct work_struct *work)
|
||||||
DVB_CA_EN50221_POLL_CAM_READY : 0);
|
DVB_CA_EN50221_POLL_CAM_READY : 0);
|
||||||
ci_dbg_print("%s: setting CI[0] status = 0x%x\n",
|
ci_dbg_print("%s: setting CI[0] status = 0x%x\n",
|
||||||
__func__, inter->state[0]->status);
|
__func__, inter->state[0]->status);
|
||||||
};
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/* CI irq handler */
|
/* CI irq handler */
|
||||||
|
|
|
@ -193,7 +193,7 @@ int netup_ci_op_cam(struct dvb_ca_en50221 *en50221, int slot,
|
||||||
0, &store, 1);
|
0, &store, 1);
|
||||||
if (ret != 0)
|
if (ret != 0)
|
||||||
return ret;
|
return ret;
|
||||||
};
|
}
|
||||||
state->current_ci_flag = flag;
|
state->current_ci_flag = flag;
|
||||||
|
|
||||||
mutex_lock(&dev->gpio_lock);
|
mutex_lock(&dev->gpio_lock);
|
||||||
|
|
|
@ -542,11 +542,13 @@ struct cx23885_board cx23885_boards[] = {
|
||||||
{
|
{
|
||||||
.type = CX23885_VMUX_COMPOSITE1,
|
.type = CX23885_VMUX_COMPOSITE1,
|
||||||
.vmux = CX25840_COMPOSITE8,
|
.vmux = CX25840_COMPOSITE8,
|
||||||
|
.amux = CX25840_AUDIO7,
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
.type = CX23885_VMUX_SVIDEO,
|
.type = CX23885_VMUX_SVIDEO,
|
||||||
.vmux = CX25840_SVIDEO_LUMA3 |
|
.vmux = CX25840_SVIDEO_LUMA3 |
|
||||||
CX25840_SVIDEO_CHROMA4,
|
CX25840_SVIDEO_CHROMA4,
|
||||||
|
.amux = CX25840_AUDIO7,
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
.type = CX23885_VMUX_COMPONENT,
|
.type = CX23885_VMUX_COMPONENT,
|
||||||
|
@ -554,6 +556,7 @@ struct cx23885_board cx23885_boards[] = {
|
||||||
CX25840_VIN1_CH1 |
|
CX25840_VIN1_CH1 |
|
||||||
CX25840_VIN6_CH2 |
|
CX25840_VIN6_CH2 |
|
||||||
CX25840_VIN7_CH3,
|
CX25840_VIN7_CH3,
|
||||||
|
.amux = CX25840_AUDIO7,
|
||||||
},
|
},
|
||||||
},
|
},
|
||||||
},
|
},
|
||||||
|
|
|
@ -508,7 +508,8 @@ static int cx23885_video_mux(struct cx23885_dev *dev, unsigned int input)
|
||||||
(dev->board == CX23885_BOARD_HAUPPAUGE_HVR1250) ||
|
(dev->board == CX23885_BOARD_HAUPPAUGE_HVR1250) ||
|
||||||
(dev->board == CX23885_BOARD_HAUPPAUGE_HVR1255) ||
|
(dev->board == CX23885_BOARD_HAUPPAUGE_HVR1255) ||
|
||||||
(dev->board == CX23885_BOARD_HAUPPAUGE_HVR1255_22111) ||
|
(dev->board == CX23885_BOARD_HAUPPAUGE_HVR1255_22111) ||
|
||||||
(dev->board == CX23885_BOARD_HAUPPAUGE_HVR1850)) {
|
(dev->board == CX23885_BOARD_HAUPPAUGE_HVR1850) ||
|
||||||
|
(dev->board == CX23885_BOARD_MYGICA_X8507)) {
|
||||||
/* Configure audio routing */
|
/* Configure audio routing */
|
||||||
v4l2_subdev_call(dev->sd_cx25840, audio, s_routing,
|
v4l2_subdev_call(dev->sd_cx25840, audio, s_routing,
|
||||||
INPUT(input)->amux, 0, 0);
|
INPUT(input)->amux, 0, 0);
|
||||||
|
|
|
@ -761,7 +761,7 @@ int cx25821_vidupstream_init_ch2(struct cx25821_dev *dev, int channel_select,
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Default if filename is empty string */
|
/* Default if filename is empty string */
|
||||||
if (strcmp(dev->input_filename_ch2, "") == 0) {
|
if (strcmp(dev->_filename_ch2, "") == 0) {
|
||||||
if (dev->_isNTSC_ch2) {
|
if (dev->_isNTSC_ch2) {
|
||||||
dev->_filename_ch2 = (dev->_pixel_format_ch2 ==
|
dev->_filename_ch2 = (dev->_pixel_format_ch2 ==
|
||||||
PIXEL_FRMT_411) ? "/root/vid411.yuv" :
|
PIXEL_FRMT_411) ? "/root/vid411.yuv" :
|
||||||
|
|
|
@ -808,7 +808,7 @@ int cx25821_vidupstream_init_ch1(struct cx25821_dev *dev, int channel_select,
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Default if filename is empty string */
|
/* Default if filename is empty string */
|
||||||
if (strcmp(dev->input_filename, "") == 0) {
|
if (strcmp(dev->_filename, "") == 0) {
|
||||||
if (dev->_isNTSC) {
|
if (dev->_isNTSC) {
|
||||||
dev->_filename =
|
dev->_filename =
|
||||||
(dev->_pixel_format == PIXEL_FRMT_411) ?
|
(dev->_pixel_format == PIXEL_FRMT_411) ?
|
||||||
|
|
|
@ -721,7 +721,7 @@ static int vidioc_g_fmt_vid_cap (struct file *file, void *priv,
|
||||||
|
|
||||||
f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
|
f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
|
||||||
f->fmt.pix.bytesperline = 0;
|
f->fmt.pix.bytesperline = 0;
|
||||||
f->fmt.pix.sizeimage = 188 * 4 * mpegbufs; /* 188 * 4 * 1024; */;
|
f->fmt.pix.sizeimage = 188 * 4 * mpegbufs; /* 188 * 4 * 1024; */
|
||||||
f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
|
f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
|
||||||
f->fmt.pix.width = dev->width;
|
f->fmt.pix.width = dev->width;
|
||||||
f->fmt.pix.height = dev->height;
|
f->fmt.pix.height = dev->height;
|
||||||
|
@ -739,7 +739,7 @@ static int vidioc_try_fmt_vid_cap (struct file *file, void *priv,
|
||||||
|
|
||||||
f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
|
f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
|
||||||
f->fmt.pix.bytesperline = 0;
|
f->fmt.pix.bytesperline = 0;
|
||||||
f->fmt.pix.sizeimage = 188 * 4 * mpegbufs; /* 188 * 4 * 1024; */;
|
f->fmt.pix.sizeimage = 188 * 4 * mpegbufs; /* 188 * 4 * 1024; */
|
||||||
f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
|
f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
|
||||||
dprintk(1, "VIDIOC_TRY_FMT: w: %d, h: %d, f: %d\n",
|
dprintk(1, "VIDIOC_TRY_FMT: w: %d, h: %d, f: %d\n",
|
||||||
dev->width, dev->height, fh->mpegq.field );
|
dev->width, dev->height, fh->mpegq.field );
|
||||||
|
@ -755,7 +755,7 @@ static int vidioc_s_fmt_vid_cap (struct file *file, void *priv,
|
||||||
|
|
||||||
f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
|
f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
|
||||||
f->fmt.pix.bytesperline = 0;
|
f->fmt.pix.bytesperline = 0;
|
||||||
f->fmt.pix.sizeimage = 188 * 4 * mpegbufs; /* 188 * 4 * 1024; */;
|
f->fmt.pix.sizeimage = 188 * 4 * mpegbufs; /* 188 * 4 * 1024; */
|
||||||
f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
|
f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
|
||||||
dev->width = f->fmt.pix.width;
|
dev->width = f->fmt.pix.width;
|
||||||
dev->height = f->fmt.pix.height;
|
dev->height = f->fmt.pix.height;
|
||||||
|
|
|
@ -896,7 +896,7 @@ static int samsung_smt_7020_set_voltage(struct dvb_frontend *fe,
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
};
|
}
|
||||||
|
|
||||||
return (i2c_transfer(&dev->core->i2c_adap, &msg, 1) == 1) ? 0 : -EIO;
|
return (i2c_transfer(&dev->core->i2c_adap, &msg, 1) == 1) ? 0 : -EIO;
|
||||||
}
|
}
|
||||||
|
|
|
@ -450,7 +450,7 @@ static irqreturn_t cx8802_irq(int irq, void *dev_id)
|
||||||
cx88_core_irq(core,status);
|
cx88_core_irq(core,status);
|
||||||
if (status & PCI_INT_TSINT)
|
if (status & PCI_INT_TSINT)
|
||||||
cx8802_mpeg_irq(dev);
|
cx8802_mpeg_irq(dev);
|
||||||
};
|
}
|
||||||
if (MAX_IRQ_LOOP == loop) {
|
if (MAX_IRQ_LOOP == loop) {
|
||||||
dprintk( 0, "clearing mask\n" );
|
dprintk( 0, "clearing mask\n" );
|
||||||
printk(KERN_WARNING "%s/0: irq loop -- clearing mask\n",
|
printk(KERN_WARNING "%s/0: irq loop -- clearing mask\n",
|
||||||
|
|
|
@ -373,7 +373,7 @@ static void set_audio_standard_NICAM(struct cx88_core *core, u32 mode)
|
||||||
set_audio_registers(core, nicam_bgdki_common);
|
set_audio_registers(core, nicam_bgdki_common);
|
||||||
set_audio_registers(core, nicam_default);
|
set_audio_registers(core, nicam_default);
|
||||||
break;
|
break;
|
||||||
};
|
}
|
||||||
|
|
||||||
mode |= EN_DMTRX_LR | EN_DMTRX_BYPASS;
|
mode |= EN_DMTRX_LR | EN_DMTRX_BYPASS;
|
||||||
set_audio_finish(core, mode);
|
set_audio_finish(core, mode);
|
||||||
|
@ -639,7 +639,7 @@ static void set_audio_standard_A2(struct cx88_core *core, u32 mode)
|
||||||
dprintk("%s Warning: wrong value\n", __func__);
|
dprintk("%s Warning: wrong value\n", __func__);
|
||||||
return;
|
return;
|
||||||
break;
|
break;
|
||||||
};
|
}
|
||||||
|
|
||||||
mode |= EN_FMRADIO_EN_RDS | EN_DMTRX_SUMDIFF;
|
mode |= EN_FMRADIO_EN_RDS | EN_DMTRX_SUMDIFF;
|
||||||
set_audio_finish(core, mode);
|
set_audio_finish(core, mode);
|
||||||
|
|
|
@ -1535,7 +1535,7 @@ static irqreturn_t cx8800_irq(int irq, void *dev_id)
|
||||||
cx88_core_irq(core,status);
|
cx88_core_irq(core,status);
|
||||||
if (status & PCI_INT_VIDINT)
|
if (status & PCI_INT_VIDINT)
|
||||||
cx8800_vid_irq(dev);
|
cx8800_vid_irq(dev);
|
||||||
};
|
}
|
||||||
if (10 == loop) {
|
if (10 == loop) {
|
||||||
printk(KERN_WARNING "%s/0: irq loop -- clearing mask\n",
|
printk(KERN_WARNING "%s/0: irq loop -- clearing mask\n",
|
||||||
core->name);
|
core->name);
|
||||||
|
|
|
@ -1204,7 +1204,7 @@ int saa7134_s_ctrl_internal(struct saa7134_dev *dev, struct saa7134_fh *fh, str
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
/* nothing */;
|
/* nothing */;
|
||||||
};
|
}
|
||||||
switch (c->id) {
|
switch (c->id) {
|
||||||
case V4L2_CID_BRIGHTNESS:
|
case V4L2_CID_BRIGHTNESS:
|
||||||
dev->ctl_bright = c->value;
|
dev->ctl_bright = c->value;
|
||||||
|
|
|
@ -165,12 +165,12 @@ config VIDEO_SAMSUNG_S5P_JPEG
|
||||||
This is a v4l2 driver for Samsung S5P and EXYNOS4 JPEG codec
|
This is a v4l2 driver for Samsung S5P and EXYNOS4 JPEG codec
|
||||||
|
|
||||||
config VIDEO_SAMSUNG_S5P_MFC
|
config VIDEO_SAMSUNG_S5P_MFC
|
||||||
tristate "Samsung S5P MFC 5.1 Video Codec"
|
tristate "Samsung S5P MFC Video Codec"
|
||||||
depends on VIDEO_DEV && VIDEO_V4L2 && PLAT_S5P
|
depends on VIDEO_DEV && VIDEO_V4L2 && PLAT_S5P
|
||||||
select VIDEOBUF2_DMA_CONTIG
|
select VIDEOBUF2_DMA_CONTIG
|
||||||
default n
|
default n
|
||||||
help
|
help
|
||||||
MFC 5.1 driver for V4L2.
|
MFC 5.1 and 6.x driver for V4L2
|
||||||
|
|
||||||
config VIDEO_MX2_EMMAPRP
|
config VIDEO_MX2_EMMAPRP
|
||||||
tristate "MX2 eMMa-PrP support"
|
tristate "MX2 eMMa-PrP support"
|
||||||
|
|
|
@ -174,26 +174,6 @@ static int vpbe_get_current_mode_info(struct vpbe_device *vpbe_dev,
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int vpbe_get_dv_preset_info(struct vpbe_device *vpbe_dev,
|
|
||||||
unsigned int dv_preset)
|
|
||||||
{
|
|
||||||
struct vpbe_config *cfg = vpbe_dev->cfg;
|
|
||||||
struct vpbe_enc_mode_info var;
|
|
||||||
int curr_output = vpbe_dev->current_out_index;
|
|
||||||
int i;
|
|
||||||
|
|
||||||
for (i = 0; i < vpbe_dev->cfg->outputs[curr_output].num_modes; i++) {
|
|
||||||
var = cfg->outputs[curr_output].modes[i];
|
|
||||||
if ((var.timings_type & VPBE_ENC_DV_PRESET) &&
|
|
||||||
(var.timings.dv_preset == dv_preset)) {
|
|
||||||
vpbe_dev->current_timings = var;
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
return -EINVAL;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Get std by std id */
|
/* Get std by std id */
|
||||||
static int vpbe_get_std_info(struct vpbe_device *vpbe_dev,
|
static int vpbe_get_std_info(struct vpbe_device *vpbe_dev,
|
||||||
v4l2_std_id std_id)
|
v4l2_std_id std_id)
|
||||||
|
@ -206,7 +186,7 @@ static int vpbe_get_std_info(struct vpbe_device *vpbe_dev,
|
||||||
for (i = 0; i < vpbe_dev->cfg->outputs[curr_output].num_modes; i++) {
|
for (i = 0; i < vpbe_dev->cfg->outputs[curr_output].num_modes; i++) {
|
||||||
var = cfg->outputs[curr_output].modes[i];
|
var = cfg->outputs[curr_output].modes[i];
|
||||||
if ((var.timings_type & VPBE_ENC_STD) &&
|
if ((var.timings_type & VPBE_ENC_STD) &&
|
||||||
(var.timings.std_id & std_id)) {
|
(var.std_id & std_id)) {
|
||||||
vpbe_dev->current_timings = var;
|
vpbe_dev->current_timings = var;
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
@ -344,38 +324,42 @@ static unsigned int vpbe_get_output(struct vpbe_device *vpbe_dev)
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* vpbe_s_dv_preset - Set the given preset timings in the encoder
|
* vpbe_s_dv_timings - Set the given preset timings in the encoder
|
||||||
*
|
*
|
||||||
* Sets the preset if supported by the current encoder. Return the status.
|
* Sets the timings if supported by the current encoder. Return the status.
|
||||||
* 0 - success & -EINVAL on error
|
* 0 - success & -EINVAL on error
|
||||||
*/
|
*/
|
||||||
static int vpbe_s_dv_preset(struct vpbe_device *vpbe_dev,
|
static int vpbe_s_dv_timings(struct vpbe_device *vpbe_dev,
|
||||||
struct v4l2_dv_preset *dv_preset)
|
struct v4l2_dv_timings *dv_timings)
|
||||||
{
|
{
|
||||||
struct vpbe_config *cfg = vpbe_dev->cfg;
|
struct vpbe_config *cfg = vpbe_dev->cfg;
|
||||||
int out_index = vpbe_dev->current_out_index;
|
int out_index = vpbe_dev->current_out_index;
|
||||||
|
struct vpbe_output *output = &cfg->outputs[out_index];
|
||||||
int sd_index = vpbe_dev->current_sd_index;
|
int sd_index = vpbe_dev->current_sd_index;
|
||||||
int ret;
|
int ret, i;
|
||||||
|
|
||||||
|
|
||||||
if (!(cfg->outputs[out_index].output.capabilities &
|
if (!(cfg->outputs[out_index].output.capabilities &
|
||||||
V4L2_OUT_CAP_PRESETS))
|
V4L2_OUT_CAP_DV_TIMINGS))
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
||||||
ret = vpbe_get_dv_preset_info(vpbe_dev, dv_preset->preset);
|
for (i = 0; i < output->num_modes; i++) {
|
||||||
|
if (output->modes[i].timings_type == VPBE_ENC_CUSTOM_TIMINGS &&
|
||||||
if (ret)
|
!memcmp(&output->modes[i].dv_timings,
|
||||||
return ret;
|
dv_timings, sizeof(*dv_timings)))
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
if (i >= output->num_modes)
|
||||||
|
return -EINVAL;
|
||||||
|
vpbe_dev->current_timings = output->modes[i];
|
||||||
mutex_lock(&vpbe_dev->lock);
|
mutex_lock(&vpbe_dev->lock);
|
||||||
|
|
||||||
|
|
||||||
ret = v4l2_subdev_call(vpbe_dev->encoders[sd_index], video,
|
ret = v4l2_subdev_call(vpbe_dev->encoders[sd_index], video,
|
||||||
s_dv_preset, dv_preset);
|
s_dv_timings, dv_timings);
|
||||||
if (!ret && (vpbe_dev->amp != NULL)) {
|
if (!ret && (vpbe_dev->amp != NULL)) {
|
||||||
/* Call amplifier subdevice */
|
/* Call amplifier subdevice */
|
||||||
ret = v4l2_subdev_call(vpbe_dev->amp, video,
|
ret = v4l2_subdev_call(vpbe_dev->amp, video,
|
||||||
s_dv_preset, dv_preset);
|
s_dv_timings, dv_timings);
|
||||||
}
|
}
|
||||||
/* set the lcd controller output for the given mode */
|
/* set the lcd controller output for the given mode */
|
||||||
if (!ret) {
|
if (!ret) {
|
||||||
|
@ -392,17 +376,17 @@ static int vpbe_s_dv_preset(struct vpbe_device *vpbe_dev,
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* vpbe_g_dv_preset - Get the preset in the current encoder
|
* vpbe_g_dv_timings - Get the timings in the current encoder
|
||||||
*
|
*
|
||||||
* Get the preset in the current encoder. Return the status. 0 - success
|
* Get the timings in the current encoder. Return the status. 0 - success
|
||||||
* -EINVAL on error
|
* -EINVAL on error
|
||||||
*/
|
*/
|
||||||
static int vpbe_g_dv_preset(struct vpbe_device *vpbe_dev,
|
static int vpbe_g_dv_timings(struct vpbe_device *vpbe_dev,
|
||||||
struct v4l2_dv_preset *dv_preset)
|
struct v4l2_dv_timings *dv_timings)
|
||||||
{
|
{
|
||||||
if (vpbe_dev->current_timings.timings_type &
|
if (vpbe_dev->current_timings.timings_type &
|
||||||
VPBE_ENC_DV_PRESET) {
|
VPBE_ENC_CUSTOM_TIMINGS) {
|
||||||
dv_preset->preset = vpbe_dev->current_timings.timings.dv_preset;
|
*dv_timings = vpbe_dev->current_timings.dv_timings;
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -410,13 +394,13 @@ static int vpbe_g_dv_preset(struct vpbe_device *vpbe_dev,
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* vpbe_enum_dv_presets - Enumerate the dv presets in the current encoder
|
* vpbe_enum_dv_timings - Enumerate the dv timings in the current encoder
|
||||||
*
|
*
|
||||||
* Get the preset in the current encoder. Return the status. 0 - success
|
* Get the timings in the current encoder. Return the status. 0 - success
|
||||||
* -EINVAL on error
|
* -EINVAL on error
|
||||||
*/
|
*/
|
||||||
static int vpbe_enum_dv_presets(struct vpbe_device *vpbe_dev,
|
static int vpbe_enum_dv_timings(struct vpbe_device *vpbe_dev,
|
||||||
struct v4l2_dv_enum_preset *preset_info)
|
struct v4l2_enum_dv_timings *timings)
|
||||||
{
|
{
|
||||||
struct vpbe_config *cfg = vpbe_dev->cfg;
|
struct vpbe_config *cfg = vpbe_dev->cfg;
|
||||||
int out_index = vpbe_dev->current_out_index;
|
int out_index = vpbe_dev->current_out_index;
|
||||||
|
@ -424,12 +408,12 @@ static int vpbe_enum_dv_presets(struct vpbe_device *vpbe_dev,
|
||||||
int j = 0;
|
int j = 0;
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
if (!(output->output.capabilities & V4L2_OUT_CAP_PRESETS))
|
if (!(output->output.capabilities & V4L2_OUT_CAP_DV_TIMINGS))
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
||||||
for (i = 0; i < output->num_modes; i++) {
|
for (i = 0; i < output->num_modes; i++) {
|
||||||
if (output->modes[i].timings_type == VPBE_ENC_DV_PRESET) {
|
if (output->modes[i].timings_type == VPBE_ENC_CUSTOM_TIMINGS) {
|
||||||
if (j == preset_info->index)
|
if (j == timings->index)
|
||||||
break;
|
break;
|
||||||
j++;
|
j++;
|
||||||
}
|
}
|
||||||
|
@ -437,9 +421,8 @@ static int vpbe_enum_dv_presets(struct vpbe_device *vpbe_dev,
|
||||||
|
|
||||||
if (i == output->num_modes)
|
if (i == output->num_modes)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
timings->timings = output->modes[i].dv_timings;
|
||||||
return v4l_fill_dv_preset_info(output->modes[i].timings.dv_preset,
|
return 0;
|
||||||
preset_info);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -489,10 +472,10 @@ static int vpbe_s_std(struct vpbe_device *vpbe_dev, v4l2_std_id *std_id)
|
||||||
*/
|
*/
|
||||||
static int vpbe_g_std(struct vpbe_device *vpbe_dev, v4l2_std_id *std_id)
|
static int vpbe_g_std(struct vpbe_device *vpbe_dev, v4l2_std_id *std_id)
|
||||||
{
|
{
|
||||||
struct vpbe_enc_mode_info cur_timings = vpbe_dev->current_timings;
|
struct vpbe_enc_mode_info *cur_timings = &vpbe_dev->current_timings;
|
||||||
|
|
||||||
if (cur_timings.timings_type & VPBE_ENC_STD) {
|
if (cur_timings->timings_type & VPBE_ENC_STD) {
|
||||||
*std_id = cur_timings.timings.std_id;
|
*std_id = cur_timings->std_id;
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -511,7 +494,7 @@ static int vpbe_set_mode(struct vpbe_device *vpbe_dev,
|
||||||
{
|
{
|
||||||
struct vpbe_enc_mode_info *preset_mode = NULL;
|
struct vpbe_enc_mode_info *preset_mode = NULL;
|
||||||
struct vpbe_config *cfg = vpbe_dev->cfg;
|
struct vpbe_config *cfg = vpbe_dev->cfg;
|
||||||
struct v4l2_dv_preset dv_preset;
|
struct v4l2_dv_timings dv_timings;
|
||||||
struct osd_state *osd_device;
|
struct osd_state *osd_device;
|
||||||
int out_index = vpbe_dev->current_out_index;
|
int out_index = vpbe_dev->current_out_index;
|
||||||
int ret = 0;
|
int ret = 0;
|
||||||
|
@ -530,11 +513,12 @@ static int vpbe_set_mode(struct vpbe_device *vpbe_dev,
|
||||||
*/
|
*/
|
||||||
if (preset_mode->timings_type & VPBE_ENC_STD)
|
if (preset_mode->timings_type & VPBE_ENC_STD)
|
||||||
return vpbe_s_std(vpbe_dev,
|
return vpbe_s_std(vpbe_dev,
|
||||||
&preset_mode->timings.std_id);
|
&preset_mode->std_id);
|
||||||
if (preset_mode->timings_type & VPBE_ENC_DV_PRESET) {
|
if (preset_mode->timings_type &
|
||||||
dv_preset.preset =
|
VPBE_ENC_CUSTOM_TIMINGS) {
|
||||||
preset_mode->timings.dv_preset;
|
dv_timings =
|
||||||
return vpbe_s_dv_preset(vpbe_dev, &dv_preset);
|
preset_mode->dv_timings;
|
||||||
|
return vpbe_s_dv_timings(vpbe_dev, &dv_timings);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -626,11 +610,11 @@ static int vpbe_initialize(struct device *dev, struct vpbe_device *vpbe_dev)
|
||||||
vpbe_dev->dac_clk = clk_get(vpbe_dev->pdev, "vpss_dac");
|
vpbe_dev->dac_clk = clk_get(vpbe_dev->pdev, "vpss_dac");
|
||||||
if (IS_ERR(vpbe_dev->dac_clk)) {
|
if (IS_ERR(vpbe_dev->dac_clk)) {
|
||||||
ret = PTR_ERR(vpbe_dev->dac_clk);
|
ret = PTR_ERR(vpbe_dev->dac_clk);
|
||||||
goto vpbe_unlock;
|
goto fail_mutex_unlock;
|
||||||
}
|
}
|
||||||
if (clk_enable(vpbe_dev->dac_clk)) {
|
if (clk_enable(vpbe_dev->dac_clk)) {
|
||||||
ret = -ENODEV;
|
ret = -ENODEV;
|
||||||
goto vpbe_unlock;
|
goto fail_mutex_unlock;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -642,7 +626,7 @@ static int vpbe_initialize(struct device *dev, struct vpbe_device *vpbe_dev)
|
||||||
if (ret) {
|
if (ret) {
|
||||||
v4l2_err(dev->driver,
|
v4l2_err(dev->driver,
|
||||||
"Unable to register v4l2 device.\n");
|
"Unable to register v4l2 device.\n");
|
||||||
goto vpbe_fail_clock;
|
goto fail_clk_put;
|
||||||
}
|
}
|
||||||
v4l2_info(&vpbe_dev->v4l2_dev, "vpbe v4l2 device registered\n");
|
v4l2_info(&vpbe_dev->v4l2_dev, "vpbe v4l2 device registered\n");
|
||||||
|
|
||||||
|
@ -658,7 +642,7 @@ static int vpbe_initialize(struct device *dev, struct vpbe_device *vpbe_dev)
|
||||||
v4l2_err(&vpbe_dev->v4l2_dev,
|
v4l2_err(&vpbe_dev->v4l2_dev,
|
||||||
"vpbe unable to init venc sub device\n");
|
"vpbe unable to init venc sub device\n");
|
||||||
ret = -ENODEV;
|
ret = -ENODEV;
|
||||||
goto vpbe_fail_v4l2_device;
|
goto fail_dev_unregister;
|
||||||
}
|
}
|
||||||
/* initialize osd device */
|
/* initialize osd device */
|
||||||
osd_device = vpbe_dev->osd_device;
|
osd_device = vpbe_dev->osd_device;
|
||||||
|
@ -669,7 +653,7 @@ static int vpbe_initialize(struct device *dev, struct vpbe_device *vpbe_dev)
|
||||||
v4l2_err(&vpbe_dev->v4l2_dev,
|
v4l2_err(&vpbe_dev->v4l2_dev,
|
||||||
"unable to initialize the OSD device");
|
"unable to initialize the OSD device");
|
||||||
err = -ENOMEM;
|
err = -ENOMEM;
|
||||||
goto vpbe_fail_v4l2_device;
|
goto fail_dev_unregister;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -685,7 +669,7 @@ static int vpbe_initialize(struct device *dev, struct vpbe_device *vpbe_dev)
|
||||||
v4l2_err(&vpbe_dev->v4l2_dev,
|
v4l2_err(&vpbe_dev->v4l2_dev,
|
||||||
"unable to allocate memory for encoders sub devices");
|
"unable to allocate memory for encoders sub devices");
|
||||||
ret = -ENOMEM;
|
ret = -ENOMEM;
|
||||||
goto vpbe_fail_v4l2_device;
|
goto fail_dev_unregister;
|
||||||
}
|
}
|
||||||
|
|
||||||
i2c_adap = i2c_get_adapter(vpbe_dev->cfg->i2c_adapter_id);
|
i2c_adap = i2c_get_adapter(vpbe_dev->cfg->i2c_adapter_id);
|
||||||
|
@ -711,7 +695,7 @@ static int vpbe_initialize(struct device *dev, struct vpbe_device *vpbe_dev)
|
||||||
" failed to register",
|
" failed to register",
|
||||||
enc_info->module_name);
|
enc_info->module_name);
|
||||||
ret = -ENODEV;
|
ret = -ENODEV;
|
||||||
goto vpbe_fail_sd_register;
|
goto fail_kfree_encoders;
|
||||||
}
|
}
|
||||||
} else
|
} else
|
||||||
v4l2_warn(&vpbe_dev->v4l2_dev, "non-i2c encoders"
|
v4l2_warn(&vpbe_dev->v4l2_dev, "non-i2c encoders"
|
||||||
|
@ -730,7 +714,7 @@ static int vpbe_initialize(struct device *dev, struct vpbe_device *vpbe_dev)
|
||||||
"amplifier %s failed to register",
|
"amplifier %s failed to register",
|
||||||
amp_info->module_name);
|
amp_info->module_name);
|
||||||
ret = -ENODEV;
|
ret = -ENODEV;
|
||||||
goto vpbe_fail_amp_register;
|
goto fail_kfree_encoders;
|
||||||
}
|
}
|
||||||
v4l2_info(&vpbe_dev->v4l2_dev,
|
v4l2_info(&vpbe_dev->v4l2_dev,
|
||||||
"v4l2 sub device %s registered\n",
|
"v4l2 sub device %s registered\n",
|
||||||
|
@ -770,16 +754,14 @@ static int vpbe_initialize(struct device *dev, struct vpbe_device *vpbe_dev)
|
||||||
/* TBD handling of bootargs for default output and mode */
|
/* TBD handling of bootargs for default output and mode */
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
vpbe_fail_amp_register:
|
fail_kfree_encoders:
|
||||||
kfree(vpbe_dev->amp);
|
|
||||||
vpbe_fail_sd_register:
|
|
||||||
kfree(vpbe_dev->encoders);
|
kfree(vpbe_dev->encoders);
|
||||||
vpbe_fail_v4l2_device:
|
fail_dev_unregister:
|
||||||
v4l2_device_unregister(&vpbe_dev->v4l2_dev);
|
v4l2_device_unregister(&vpbe_dev->v4l2_dev);
|
||||||
vpbe_fail_clock:
|
fail_clk_put:
|
||||||
if (strcmp(vpbe_dev->cfg->module_name, "dm644x-vpbe-display") != 0)
|
if (strcmp(vpbe_dev->cfg->module_name, "dm644x-vpbe-display") != 0)
|
||||||
clk_put(vpbe_dev->dac_clk);
|
clk_put(vpbe_dev->dac_clk);
|
||||||
vpbe_unlock:
|
fail_mutex_unlock:
|
||||||
mutex_unlock(&vpbe_dev->lock);
|
mutex_unlock(&vpbe_dev->lock);
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
@ -810,9 +792,9 @@ static struct vpbe_device_ops vpbe_dev_ops = {
|
||||||
.enum_outputs = vpbe_enum_outputs,
|
.enum_outputs = vpbe_enum_outputs,
|
||||||
.set_output = vpbe_set_output,
|
.set_output = vpbe_set_output,
|
||||||
.get_output = vpbe_get_output,
|
.get_output = vpbe_get_output,
|
||||||
.s_dv_preset = vpbe_s_dv_preset,
|
.s_dv_timings = vpbe_s_dv_timings,
|
||||||
.g_dv_preset = vpbe_g_dv_preset,
|
.g_dv_timings = vpbe_g_dv_timings,
|
||||||
.enum_dv_presets = vpbe_enum_dv_presets,
|
.enum_dv_timings = vpbe_enum_dv_timings,
|
||||||
.s_std = vpbe_s_std,
|
.s_std = vpbe_s_std,
|
||||||
.g_std = vpbe_g_std,
|
.g_std = vpbe_g_std,
|
||||||
.initialize = vpbe_initialize,
|
.initialize = vpbe_initialize,
|
||||||
|
|
|
@ -393,7 +393,7 @@ vpbe_disp_calculate_scale_factor(struct vpbe_display *disp_dev,
|
||||||
int h_scale;
|
int h_scale;
|
||||||
int v_scale;
|
int v_scale;
|
||||||
|
|
||||||
v4l2_std_id standard_id = vpbe_dev->current_timings.timings.std_id;
|
v4l2_std_id standard_id = vpbe_dev->current_timings.std_id;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Application initially set the image format. Current display
|
* Application initially set the image format. Current display
|
||||||
|
@ -637,7 +637,7 @@ static int vpbe_display_s_crop(struct file *file, void *priv,
|
||||||
struct vpbe_device *vpbe_dev = disp_dev->vpbe_dev;
|
struct vpbe_device *vpbe_dev = disp_dev->vpbe_dev;
|
||||||
struct osd_layer_config *cfg = &layer->layer_info.config;
|
struct osd_layer_config *cfg = &layer->layer_info.config;
|
||||||
struct osd_state *osd_device = disp_dev->osd_device;
|
struct osd_state *osd_device = disp_dev->osd_device;
|
||||||
struct v4l2_rect *rect = &crop->c;
|
struct v4l2_rect rect = crop->c;
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev,
|
v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev,
|
||||||
|
@ -648,21 +648,21 @@ static int vpbe_display_s_crop(struct file *file, void *priv,
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (rect->top < 0)
|
if (rect.top < 0)
|
||||||
rect->top = 0;
|
rect.top = 0;
|
||||||
if (rect->left < 0)
|
if (rect.left < 0)
|
||||||
rect->left = 0;
|
rect.left = 0;
|
||||||
|
|
||||||
vpbe_disp_check_window_params(disp_dev, rect);
|
vpbe_disp_check_window_params(disp_dev, &rect);
|
||||||
|
|
||||||
osd_device->ops.get_layer_config(osd_device,
|
osd_device->ops.get_layer_config(osd_device,
|
||||||
layer->layer_info.id, cfg);
|
layer->layer_info.id, cfg);
|
||||||
|
|
||||||
vpbe_disp_calculate_scale_factor(disp_dev, layer,
|
vpbe_disp_calculate_scale_factor(disp_dev, layer,
|
||||||
rect->width,
|
rect.width,
|
||||||
rect->height);
|
rect.height);
|
||||||
vpbe_disp_adj_position(disp_dev, layer, rect->top,
|
vpbe_disp_adj_position(disp_dev, layer, rect.top,
|
||||||
rect->left);
|
rect.left);
|
||||||
ret = osd_device->ops.set_layer_config(osd_device,
|
ret = osd_device->ops.set_layer_config(osd_device,
|
||||||
layer->layer_info.id, cfg);
|
layer->layer_info.id, cfg);
|
||||||
if (ret < 0) {
|
if (ret < 0) {
|
||||||
|
@ -943,7 +943,7 @@ static int vpbe_display_g_std(struct file *file, void *priv,
|
||||||
|
|
||||||
/* Get the standard from the current encoder */
|
/* Get the standard from the current encoder */
|
||||||
if (vpbe_dev->current_timings.timings_type & VPBE_ENC_STD) {
|
if (vpbe_dev->current_timings.timings_type & VPBE_ENC_STD) {
|
||||||
*std_id = vpbe_dev->current_timings.timings.std_id;
|
*std_id = vpbe_dev->current_timings.std_id;
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1029,29 +1029,29 @@ static int vpbe_display_g_output(struct file *file, void *priv,
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* vpbe_display_enum_dv_presets - Enumerate the dv presets
|
* vpbe_display_enum_dv_timings - Enumerate the dv timings
|
||||||
*
|
*
|
||||||
* enum the preset in the current encoder. Return the status. 0 - success
|
* enum the timings in the current encoder. Return the status. 0 - success
|
||||||
* -EINVAL on error
|
* -EINVAL on error
|
||||||
*/
|
*/
|
||||||
static int
|
static int
|
||||||
vpbe_display_enum_dv_presets(struct file *file, void *priv,
|
vpbe_display_enum_dv_timings(struct file *file, void *priv,
|
||||||
struct v4l2_dv_enum_preset *preset)
|
struct v4l2_enum_dv_timings *timings)
|
||||||
{
|
{
|
||||||
struct vpbe_fh *fh = priv;
|
struct vpbe_fh *fh = priv;
|
||||||
struct vpbe_device *vpbe_dev = fh->disp_dev->vpbe_dev;
|
struct vpbe_device *vpbe_dev = fh->disp_dev->vpbe_dev;
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "VIDIOC_ENUM_DV_PRESETS\n");
|
v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "VIDIOC_ENUM_DV_TIMINGS\n");
|
||||||
|
|
||||||
/* Enumerate outputs */
|
/* Enumerate outputs */
|
||||||
if (NULL == vpbe_dev->ops.enum_dv_presets)
|
if (NULL == vpbe_dev->ops.enum_dv_timings)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
||||||
ret = vpbe_dev->ops.enum_dv_presets(vpbe_dev, preset);
|
ret = vpbe_dev->ops.enum_dv_timings(vpbe_dev, timings);
|
||||||
if (ret) {
|
if (ret) {
|
||||||
v4l2_err(&vpbe_dev->v4l2_dev,
|
v4l2_err(&vpbe_dev->v4l2_dev,
|
||||||
"Failed to enumerate dv presets info\n");
|
"Failed to enumerate dv timings info\n");
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1059,21 +1059,21 @@ vpbe_display_enum_dv_presets(struct file *file, void *priv,
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* vpbe_display_s_dv_preset - Set the dv presets
|
* vpbe_display_s_dv_timings - Set the dv timings
|
||||||
*
|
*
|
||||||
* Set the preset in the current encoder. Return the status. 0 - success
|
* Set the timings in the current encoder. Return the status. 0 - success
|
||||||
* -EINVAL on error
|
* -EINVAL on error
|
||||||
*/
|
*/
|
||||||
static int
|
static int
|
||||||
vpbe_display_s_dv_preset(struct file *file, void *priv,
|
vpbe_display_s_dv_timings(struct file *file, void *priv,
|
||||||
struct v4l2_dv_preset *preset)
|
struct v4l2_dv_timings *timings)
|
||||||
{
|
{
|
||||||
struct vpbe_fh *fh = priv;
|
struct vpbe_fh *fh = priv;
|
||||||
struct vpbe_layer *layer = fh->layer;
|
struct vpbe_layer *layer = fh->layer;
|
||||||
struct vpbe_device *vpbe_dev = fh->disp_dev->vpbe_dev;
|
struct vpbe_device *vpbe_dev = fh->disp_dev->vpbe_dev;
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "VIDIOC_S_DV_PRESETS\n");
|
v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "VIDIOC_S_DV_TIMINGS\n");
|
||||||
|
|
||||||
|
|
||||||
/* If streaming is started, return error */
|
/* If streaming is started, return error */
|
||||||
|
@ -1083,13 +1083,13 @@ vpbe_display_s_dv_preset(struct file *file, void *priv,
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Set the given standard in the encoder */
|
/* Set the given standard in the encoder */
|
||||||
if (!vpbe_dev->ops.s_dv_preset)
|
if (!vpbe_dev->ops.s_dv_timings)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
||||||
ret = vpbe_dev->ops.s_dv_preset(vpbe_dev, preset);
|
ret = vpbe_dev->ops.s_dv_timings(vpbe_dev, timings);
|
||||||
if (ret) {
|
if (ret) {
|
||||||
v4l2_err(&vpbe_dev->v4l2_dev,
|
v4l2_err(&vpbe_dev->v4l2_dev,
|
||||||
"Failed to set the dv presets info\n");
|
"Failed to set the dv timings info\n");
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
}
|
}
|
||||||
/* set the current norm to zero to be consistent. If STD is used
|
/* set the current norm to zero to be consistent. If STD is used
|
||||||
|
@ -1101,26 +1101,25 @@ vpbe_display_s_dv_preset(struct file *file, void *priv,
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* vpbe_display_g_dv_preset - Set the dv presets
|
* vpbe_display_g_dv_timings - Set the dv timings
|
||||||
*
|
*
|
||||||
* Get the preset in the current encoder. Return the status. 0 - success
|
* Get the timings in the current encoder. Return the status. 0 - success
|
||||||
* -EINVAL on error
|
* -EINVAL on error
|
||||||
*/
|
*/
|
||||||
static int
|
static int
|
||||||
vpbe_display_g_dv_preset(struct file *file, void *priv,
|
vpbe_display_g_dv_timings(struct file *file, void *priv,
|
||||||
struct v4l2_dv_preset *dv_preset)
|
struct v4l2_dv_timings *dv_timings)
|
||||||
{
|
{
|
||||||
struct vpbe_fh *fh = priv;
|
struct vpbe_fh *fh = priv;
|
||||||
struct vpbe_device *vpbe_dev = fh->disp_dev->vpbe_dev;
|
struct vpbe_device *vpbe_dev = fh->disp_dev->vpbe_dev;
|
||||||
|
|
||||||
v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "VIDIOC_G_DV_PRESETS\n");
|
v4l2_dbg(1, debug, &vpbe_dev->v4l2_dev, "VIDIOC_G_DV_TIMINGS\n");
|
||||||
|
|
||||||
/* Get the given standard in the encoder */
|
/* Get the given standard in the encoder */
|
||||||
|
|
||||||
if (vpbe_dev->current_timings.timings_type &
|
if (vpbe_dev->current_timings.timings_type &
|
||||||
VPBE_ENC_DV_PRESET) {
|
VPBE_ENC_CUSTOM_TIMINGS) {
|
||||||
dv_preset->preset =
|
*dv_timings = vpbe_dev->current_timings.dv_timings;
|
||||||
vpbe_dev->current_timings.timings.dv_preset;
|
|
||||||
} else {
|
} else {
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
}
|
}
|
||||||
|
@ -1572,9 +1571,9 @@ static const struct v4l2_ioctl_ops vpbe_ioctl_ops = {
|
||||||
.vidioc_enum_output = vpbe_display_enum_output,
|
.vidioc_enum_output = vpbe_display_enum_output,
|
||||||
.vidioc_s_output = vpbe_display_s_output,
|
.vidioc_s_output = vpbe_display_s_output,
|
||||||
.vidioc_g_output = vpbe_display_g_output,
|
.vidioc_g_output = vpbe_display_g_output,
|
||||||
.vidioc_s_dv_preset = vpbe_display_s_dv_preset,
|
.vidioc_s_dv_timings = vpbe_display_s_dv_timings,
|
||||||
.vidioc_g_dv_preset = vpbe_display_g_dv_preset,
|
.vidioc_g_dv_timings = vpbe_display_g_dv_timings,
|
||||||
.vidioc_enum_dv_presets = vpbe_display_enum_dv_presets,
|
.vidioc_enum_dv_timings = vpbe_display_enum_dv_timings,
|
||||||
#ifdef CONFIG_VIDEO_ADV_DEBUG
|
#ifdef CONFIG_VIDEO_ADV_DEBUG
|
||||||
.vidioc_g_register = vpbe_display_g_register,
|
.vidioc_g_register = vpbe_display_g_register,
|
||||||
.vidioc_s_register = vpbe_display_s_register,
|
.vidioc_s_register = vpbe_display_s_register,
|
||||||
|
@ -1639,8 +1638,7 @@ static __devinit int init_vpbe_layer(int i, struct vpbe_display *disp_dev,
|
||||||
VPBE_ENC_STD) {
|
VPBE_ENC_STD) {
|
||||||
vbd->tvnorms = (V4L2_STD_525_60 | V4L2_STD_625_50);
|
vbd->tvnorms = (V4L2_STD_525_60 | V4L2_STD_625_50);
|
||||||
vbd->current_norm =
|
vbd->current_norm =
|
||||||
disp_dev->vpbe_dev->
|
disp_dev->vpbe_dev->current_timings.std_id;
|
||||||
current_timings.timings.std_id;
|
|
||||||
} else
|
} else
|
||||||
vbd->current_norm = 0;
|
vbd->current_norm = 0;
|
||||||
|
|
||||||
|
|
|
@ -298,7 +298,7 @@ static int venc_set_480p59_94(struct v4l2_subdev *sd)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
||||||
/* Setup clock at VPSS & VENC for SD */
|
/* Setup clock at VPSS & VENC for SD */
|
||||||
if (pdata->setup_clock(VPBE_ENC_DV_PRESET, V4L2_DV_480P59_94) < 0)
|
if (pdata->setup_clock(VPBE_ENC_CUSTOM_TIMINGS, 27000000) < 0)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
||||||
venc_enabledigitaloutput(sd, 0);
|
venc_enabledigitaloutput(sd, 0);
|
||||||
|
@ -345,7 +345,7 @@ static int venc_set_576p50(struct v4l2_subdev *sd)
|
||||||
(pdata->venc_type != VPBE_VERSION_2))
|
(pdata->venc_type != VPBE_VERSION_2))
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
/* Setup clock at VPSS & VENC for SD */
|
/* Setup clock at VPSS & VENC for SD */
|
||||||
if (pdata->setup_clock(VPBE_ENC_DV_PRESET, V4L2_DV_576P50) < 0)
|
if (pdata->setup_clock(VPBE_ENC_CUSTOM_TIMINGS, 27000000) < 0)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
||||||
venc_enabledigitaloutput(sd, 0);
|
venc_enabledigitaloutput(sd, 0);
|
||||||
|
@ -385,7 +385,7 @@ static int venc_set_720p60_internal(struct v4l2_subdev *sd)
|
||||||
struct venc_state *venc = to_state(sd);
|
struct venc_state *venc = to_state(sd);
|
||||||
struct venc_platform_data *pdata = venc->pdata;
|
struct venc_platform_data *pdata = venc->pdata;
|
||||||
|
|
||||||
if (pdata->setup_clock(VPBE_ENC_DV_PRESET, V4L2_DV_720P60) < 0)
|
if (pdata->setup_clock(VPBE_ENC_CUSTOM_TIMINGS, 74250000) < 0)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
||||||
venc_enabledigitaloutput(sd, 0);
|
venc_enabledigitaloutput(sd, 0);
|
||||||
|
@ -413,7 +413,7 @@ static int venc_set_1080i30_internal(struct v4l2_subdev *sd)
|
||||||
struct venc_state *venc = to_state(sd);
|
struct venc_state *venc = to_state(sd);
|
||||||
struct venc_platform_data *pdata = venc->pdata;
|
struct venc_platform_data *pdata = venc->pdata;
|
||||||
|
|
||||||
if (pdata->setup_clock(VPBE_ENC_DV_PRESET, V4L2_DV_1080P30) < 0)
|
if (pdata->setup_clock(VPBE_ENC_CUSTOM_TIMINGS, 74250000) < 0)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
||||||
venc_enabledigitaloutput(sd, 0);
|
venc_enabledigitaloutput(sd, 0);
|
||||||
|
@ -446,26 +446,27 @@ static int venc_s_std_output(struct v4l2_subdev *sd, v4l2_std_id norm)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int venc_s_dv_preset(struct v4l2_subdev *sd,
|
static int venc_s_dv_timings(struct v4l2_subdev *sd,
|
||||||
struct v4l2_dv_preset *dv_preset)
|
struct v4l2_dv_timings *dv_timings)
|
||||||
{
|
{
|
||||||
struct venc_state *venc = to_state(sd);
|
struct venc_state *venc = to_state(sd);
|
||||||
|
u32 height = dv_timings->bt.height;
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
v4l2_dbg(debug, 1, sd, "venc_s_dv_preset\n");
|
v4l2_dbg(debug, 1, sd, "venc_s_dv_timings\n");
|
||||||
|
|
||||||
if (dv_preset->preset == V4L2_DV_576P50)
|
if (height == 576)
|
||||||
return venc_set_576p50(sd);
|
return venc_set_576p50(sd);
|
||||||
else if (dv_preset->preset == V4L2_DV_480P59_94)
|
else if (height == 480)
|
||||||
return venc_set_480p59_94(sd);
|
return venc_set_480p59_94(sd);
|
||||||
else if ((dv_preset->preset == V4L2_DV_720P60) &&
|
else if ((height == 720) &&
|
||||||
(venc->pdata->venc_type == VPBE_VERSION_2)) {
|
(venc->pdata->venc_type == VPBE_VERSION_2)) {
|
||||||
/* TBD setup internal 720p mode here */
|
/* TBD setup internal 720p mode here */
|
||||||
ret = venc_set_720p60_internal(sd);
|
ret = venc_set_720p60_internal(sd);
|
||||||
/* for DM365 VPBE, there is DAC inside */
|
/* for DM365 VPBE, there is DAC inside */
|
||||||
vdaccfg_write(sd, VDAC_CONFIG_HD_V2);
|
vdaccfg_write(sd, VDAC_CONFIG_HD_V2);
|
||||||
return ret;
|
return ret;
|
||||||
} else if ((dv_preset->preset == V4L2_DV_1080I30) &&
|
} else if ((height == 1080) &&
|
||||||
(venc->pdata->venc_type == VPBE_VERSION_2)) {
|
(venc->pdata->venc_type == VPBE_VERSION_2)) {
|
||||||
/* TBD setup internal 1080i mode here */
|
/* TBD setup internal 1080i mode here */
|
||||||
ret = venc_set_1080i30_internal(sd);
|
ret = venc_set_1080i30_internal(sd);
|
||||||
|
@ -518,7 +519,7 @@ static const struct v4l2_subdev_core_ops venc_core_ops = {
|
||||||
static const struct v4l2_subdev_video_ops venc_video_ops = {
|
static const struct v4l2_subdev_video_ops venc_video_ops = {
|
||||||
.s_routing = venc_s_routing,
|
.s_routing = venc_s_routing,
|
||||||
.s_std_output = venc_s_std_output,
|
.s_std_output = venc_s_std_output,
|
||||||
.s_dv_preset = venc_s_dv_preset,
|
.s_dv_timings = venc_s_dv_timings,
|
||||||
};
|
};
|
||||||
|
|
||||||
static const struct v4l2_subdev_ops venc_ops = {
|
static const struct v4l2_subdev_ops venc_ops = {
|
||||||
|
|
|
@ -1669,6 +1669,7 @@ static int vpfe_s_crop(struct file *file, void *priv,
|
||||||
const struct v4l2_crop *crop)
|
const struct v4l2_crop *crop)
|
||||||
{
|
{
|
||||||
struct vpfe_device *vpfe_dev = video_drvdata(file);
|
struct vpfe_device *vpfe_dev = video_drvdata(file);
|
||||||
|
struct v4l2_rect rect = crop->c;
|
||||||
int ret = 0;
|
int ret = 0;
|
||||||
|
|
||||||
v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_s_crop\n");
|
v4l2_dbg(1, debug, &vpfe_dev->v4l2_dev, "vpfe_s_crop\n");
|
||||||
|
@ -1684,7 +1685,7 @@ static int vpfe_s_crop(struct file *file, void *priv,
|
||||||
if (ret)
|
if (ret)
|
||||||
return ret;
|
return ret;
|
||||||
|
|
||||||
if (crop->c.top < 0 || crop->c.left < 0) {
|
if (rect.top < 0 || rect.left < 0) {
|
||||||
v4l2_err(&vpfe_dev->v4l2_dev,
|
v4l2_err(&vpfe_dev->v4l2_dev,
|
||||||
"doesn't support negative values for top & left\n");
|
"doesn't support negative values for top & left\n");
|
||||||
ret = -EINVAL;
|
ret = -EINVAL;
|
||||||
|
@ -1692,26 +1693,26 @@ static int vpfe_s_crop(struct file *file, void *priv,
|
||||||
}
|
}
|
||||||
|
|
||||||
/* adjust the width to 16 pixel boundary */
|
/* adjust the width to 16 pixel boundary */
|
||||||
crop->c.width = ((crop->c.width + 15) & ~0xf);
|
rect.width = ((rect.width + 15) & ~0xf);
|
||||||
|
|
||||||
/* make sure parameters are valid */
|
/* make sure parameters are valid */
|
||||||
if ((crop->c.left + crop->c.width >
|
if ((rect.left + rect.width >
|
||||||
vpfe_dev->std_info.active_pixels) ||
|
vpfe_dev->std_info.active_pixels) ||
|
||||||
(crop->c.top + crop->c.height >
|
(rect.top + rect.height >
|
||||||
vpfe_dev->std_info.active_lines)) {
|
vpfe_dev->std_info.active_lines)) {
|
||||||
v4l2_err(&vpfe_dev->v4l2_dev, "Error in S_CROP params\n");
|
v4l2_err(&vpfe_dev->v4l2_dev, "Error in S_CROP params\n");
|
||||||
ret = -EINVAL;
|
ret = -EINVAL;
|
||||||
goto unlock_out;
|
goto unlock_out;
|
||||||
}
|
}
|
||||||
ccdc_dev->hw_ops.set_image_window(&crop->c);
|
ccdc_dev->hw_ops.set_image_window(&rect);
|
||||||
vpfe_dev->fmt.fmt.pix.width = crop->c.width;
|
vpfe_dev->fmt.fmt.pix.width = rect.width;
|
||||||
vpfe_dev->fmt.fmt.pix.height = crop->c.height;
|
vpfe_dev->fmt.fmt.pix.height = rect.height;
|
||||||
vpfe_dev->fmt.fmt.pix.bytesperline =
|
vpfe_dev->fmt.fmt.pix.bytesperline =
|
||||||
ccdc_dev->hw_ops.get_line_length();
|
ccdc_dev->hw_ops.get_line_length();
|
||||||
vpfe_dev->fmt.fmt.pix.sizeimage =
|
vpfe_dev->fmt.fmt.pix.sizeimage =
|
||||||
vpfe_dev->fmt.fmt.pix.bytesperline *
|
vpfe_dev->fmt.fmt.pix.bytesperline *
|
||||||
vpfe_dev->fmt.fmt.pix.height;
|
vpfe_dev->fmt.fmt.pix.height;
|
||||||
vpfe_dev->crop = crop->c;
|
vpfe_dev->crop = rect;
|
||||||
unlock_out:
|
unlock_out:
|
||||||
mutex_unlock(&vpfe_dev->lock);
|
mutex_unlock(&vpfe_dev->lock);
|
||||||
return ret;
|
return ret;
|
||||||
|
|
|
@ -311,12 +311,13 @@ static int vpif_start_streaming(struct vb2_queue *vq, unsigned int count)
|
||||||
}
|
}
|
||||||
|
|
||||||
/* configure 1 or 2 channel mode */
|
/* configure 1 or 2 channel mode */
|
||||||
ret = vpif_config_data->setup_input_channel_mode
|
if (vpif_config_data->setup_input_channel_mode) {
|
||||||
(vpif->std_info.ycmux_mode);
|
ret = vpif_config_data->
|
||||||
|
setup_input_channel_mode(vpif->std_info.ycmux_mode);
|
||||||
if (ret < 0) {
|
if (ret < 0) {
|
||||||
vpif_dbg(1, debug, "can't set vpif channel mode\n");
|
vpif_dbg(1, debug, "can't set vpif channel mode\n");
|
||||||
return ret;
|
return ret;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Call vpif_set_params function to set the parameters and addresses */
|
/* Call vpif_set_params function to set the parameters and addresses */
|
||||||
|
@ -863,13 +864,11 @@ static unsigned int vpif_poll(struct file *filep, poll_table * wait)
|
||||||
*/
|
*/
|
||||||
static int vpif_open(struct file *filep)
|
static int vpif_open(struct file *filep)
|
||||||
{
|
{
|
||||||
struct vpif_capture_config *config = vpif_dev->platform_data;
|
|
||||||
struct video_device *vdev = video_devdata(filep);
|
struct video_device *vdev = video_devdata(filep);
|
||||||
struct common_obj *common;
|
struct common_obj *common;
|
||||||
struct video_obj *vid_ch;
|
struct video_obj *vid_ch;
|
||||||
struct channel_obj *ch;
|
struct channel_obj *ch;
|
||||||
struct vpif_fh *fh;
|
struct vpif_fh *fh;
|
||||||
int i;
|
|
||||||
|
|
||||||
vpif_dbg(2, debug, "vpif_open\n");
|
vpif_dbg(2, debug, "vpif_open\n");
|
||||||
|
|
||||||
|
@ -878,26 +877,6 @@ static int vpif_open(struct file *filep)
|
||||||
vid_ch = &ch->video;
|
vid_ch = &ch->video;
|
||||||
common = &ch->common[VPIF_VIDEO_INDEX];
|
common = &ch->common[VPIF_VIDEO_INDEX];
|
||||||
|
|
||||||
if (NULL == ch->curr_subdev_info) {
|
|
||||||
/**
|
|
||||||
* search through the sub device to see a registered
|
|
||||||
* sub device and make it as current sub device
|
|
||||||
*/
|
|
||||||
for (i = 0; i < config->subdev_count; i++) {
|
|
||||||
if (vpif_obj.sd[i]) {
|
|
||||||
/* the sub device is registered */
|
|
||||||
ch->curr_subdev_info = &config->subdev_info[i];
|
|
||||||
/* make first input as the current input */
|
|
||||||
vid_ch->input_idx = 0;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (i == config->subdev_count) {
|
|
||||||
vpif_err("No sub device registered\n");
|
|
||||||
return -ENOENT;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Allocate memory for the file handle object */
|
/* Allocate memory for the file handle object */
|
||||||
fh = kzalloc(sizeof(struct vpif_fh), GFP_KERNEL);
|
fh = kzalloc(sizeof(struct vpif_fh), GFP_KERNEL);
|
||||||
if (NULL == fh) {
|
if (NULL == fh) {
|
||||||
|
@ -997,6 +976,7 @@ static int vpif_reqbufs(struct file *file, void *priv,
|
||||||
struct common_obj *common;
|
struct common_obj *common;
|
||||||
u8 index = 0;
|
u8 index = 0;
|
||||||
struct vb2_queue *q;
|
struct vb2_queue *q;
|
||||||
|
int ret;
|
||||||
|
|
||||||
vpif_dbg(2, debug, "vpif_reqbufs\n");
|
vpif_dbg(2, debug, "vpif_reqbufs\n");
|
||||||
|
|
||||||
|
@ -1036,8 +1016,12 @@ static int vpif_reqbufs(struct file *file, void *priv,
|
||||||
q->mem_ops = &vb2_dma_contig_memops;
|
q->mem_ops = &vb2_dma_contig_memops;
|
||||||
q->buf_struct_size = sizeof(struct vpif_cap_buffer);
|
q->buf_struct_size = sizeof(struct vpif_cap_buffer);
|
||||||
|
|
||||||
vb2_queue_init(q);
|
ret = vb2_queue_init(q);
|
||||||
|
if (ret) {
|
||||||
|
vpif_err("vpif_capture: vb2_queue_init() failed\n");
|
||||||
|
vb2_dma_contig_cleanup_ctx(common->alloc_ctx);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
/* Set io allowed member of file handle to TRUE */
|
/* Set io allowed member of file handle to TRUE */
|
||||||
fh->io_allowed[index] = 1;
|
fh->io_allowed[index] = 1;
|
||||||
/* Increment io usrs member of channel object to 1 */
|
/* Increment io usrs member of channel object to 1 */
|
||||||
|
@ -1175,10 +1159,9 @@ static int vpif_streamon(struct file *file, void *priv,
|
||||||
return ret;
|
return ret;
|
||||||
|
|
||||||
/* Enable streamon on the sub device */
|
/* Enable streamon on the sub device */
|
||||||
ret = v4l2_subdev_call(vpif_obj.sd[ch->curr_sd_index], video,
|
ret = v4l2_subdev_call(ch->sd, video, s_stream, 1);
|
||||||
s_stream, 1);
|
|
||||||
|
|
||||||
if (ret && (ret != -ENOIOCTLCMD)) {
|
if (ret && ret != -ENOIOCTLCMD && ret != -ENODEV) {
|
||||||
vpif_dbg(1, debug, "stream on failed in subdev\n");
|
vpif_dbg(1, debug, "stream on failed in subdev\n");
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
@ -1238,73 +1221,105 @@ static int vpif_streamoff(struct file *file, void *priv,
|
||||||
|
|
||||||
common->started = 0;
|
common->started = 0;
|
||||||
|
|
||||||
ret = v4l2_subdev_call(vpif_obj.sd[ch->curr_sd_index], video,
|
ret = v4l2_subdev_call(ch->sd, video, s_stream, 0);
|
||||||
s_stream, 0);
|
|
||||||
|
|
||||||
if (ret && (ret != -ENOIOCTLCMD))
|
if (ret && ret != -ENOIOCTLCMD && ret != -ENODEV)
|
||||||
vpif_dbg(1, debug, "stream off failed in subdev\n");
|
vpif_dbg(1, debug, "stream off failed in subdev\n");
|
||||||
|
|
||||||
return vb2_streamoff(&common->buffer_queue, buftype);
|
return vb2_streamoff(&common->buffer_queue, buftype);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* vpif_map_sub_device_to_input() - Maps sub device to input
|
* vpif_input_to_subdev() - Maps input to sub device
|
||||||
* @ch - ptr to channel
|
* @vpif_cfg - global config ptr
|
||||||
* @config - ptr to capture configuration
|
* @chan_cfg - channel config ptr
|
||||||
* @input_index - Given input index from application
|
* @input_index - Given input index from application
|
||||||
* @sub_device_index - index into sd table
|
|
||||||
*
|
*
|
||||||
* lookup the sub device information for a given input index.
|
* lookup the sub device information for a given input index.
|
||||||
* we report all the inputs to application. inputs table also
|
* we report all the inputs to application. inputs table also
|
||||||
* has sub device name for the each input
|
* has sub device name for the each input
|
||||||
*/
|
*/
|
||||||
static struct vpif_subdev_info *vpif_map_sub_device_to_input(
|
static int vpif_input_to_subdev(
|
||||||
struct channel_obj *ch,
|
struct vpif_capture_config *vpif_cfg,
|
||||||
struct vpif_capture_config *vpif_cfg,
|
struct vpif_capture_chan_config *chan_cfg,
|
||||||
int input_index,
|
int input_index)
|
||||||
int *sub_device_index)
|
|
||||||
{
|
{
|
||||||
struct vpif_capture_chan_config *chan_cfg;
|
struct vpif_subdev_info *subdev_info;
|
||||||
struct vpif_subdev_info *subdev_info = NULL;
|
const char *subdev_name;
|
||||||
const char *subdev_name = NULL;
|
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
vpif_dbg(2, debug, "vpif_map_sub_device_to_input\n");
|
vpif_dbg(2, debug, "vpif_input_to_subdev\n");
|
||||||
|
|
||||||
chan_cfg = &vpif_cfg->chan_config[ch->channel_id];
|
subdev_name = chan_cfg->inputs[input_index].subdev_name;
|
||||||
|
if (subdev_name == NULL)
|
||||||
/**
|
return -1;
|
||||||
* search through the inputs to find the sub device supporting
|
|
||||||
* the input
|
|
||||||
*/
|
|
||||||
for (i = 0; i < chan_cfg->input_count; i++) {
|
|
||||||
/* For each sub device, loop through input */
|
|
||||||
if (i == input_index) {
|
|
||||||
subdev_name = chan_cfg->inputs[i].subdev_name;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* if reached maximum. return null */
|
|
||||||
if (i == chan_cfg->input_count || (NULL == subdev_name))
|
|
||||||
return subdev_info;
|
|
||||||
|
|
||||||
/* loop through the sub device list to get the sub device info */
|
/* loop through the sub device list to get the sub device info */
|
||||||
for (i = 0; i < vpif_cfg->subdev_count; i++) {
|
for (i = 0; i < vpif_cfg->subdev_count; i++) {
|
||||||
subdev_info = &vpif_cfg->subdev_info[i];
|
subdev_info = &vpif_cfg->subdev_info[i];
|
||||||
if (!strcmp(subdev_info->name, subdev_name))
|
if (!strcmp(subdev_info->name, subdev_name))
|
||||||
break;
|
return i;
|
||||||
|
}
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* vpif_set_input() - Select an input
|
||||||
|
* @vpif_cfg - global config ptr
|
||||||
|
* @ch - channel
|
||||||
|
* @_index - Given input index from application
|
||||||
|
*
|
||||||
|
* Select the given input.
|
||||||
|
*/
|
||||||
|
static int vpif_set_input(
|
||||||
|
struct vpif_capture_config *vpif_cfg,
|
||||||
|
struct channel_obj *ch,
|
||||||
|
int index)
|
||||||
|
{
|
||||||
|
struct vpif_capture_chan_config *chan_cfg =
|
||||||
|
&vpif_cfg->chan_config[ch->channel_id];
|
||||||
|
struct vpif_subdev_info *subdev_info = NULL;
|
||||||
|
struct v4l2_subdev *sd = NULL;
|
||||||
|
u32 input = 0, output = 0;
|
||||||
|
int sd_index;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
sd_index = vpif_input_to_subdev(vpif_cfg, chan_cfg, index);
|
||||||
|
if (sd_index >= 0) {
|
||||||
|
sd = vpif_obj.sd[sd_index];
|
||||||
|
subdev_info = &vpif_cfg->subdev_info[sd_index];
|
||||||
}
|
}
|
||||||
|
|
||||||
if (i == vpif_cfg->subdev_count)
|
/* first setup input path from sub device to vpif */
|
||||||
return subdev_info;
|
if (sd && vpif_cfg->setup_input_path) {
|
||||||
|
ret = vpif_cfg->setup_input_path(ch->channel_id,
|
||||||
|
subdev_info->name);
|
||||||
|
if (ret < 0) {
|
||||||
|
vpif_dbg(1, debug, "couldn't setup input path for the" \
|
||||||
|
" sub device %s, for input index %d\n",
|
||||||
|
subdev_info->name, index);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
/* check if the sub device is registered */
|
if (sd) {
|
||||||
if (NULL == vpif_obj.sd[i])
|
input = chan_cfg->inputs[index].input_route;
|
||||||
return NULL;
|
output = chan_cfg->inputs[index].output_route;
|
||||||
|
ret = v4l2_subdev_call(sd, video, s_routing,
|
||||||
|
input, output, 0);
|
||||||
|
if (ret < 0 && ret != -ENOIOCTLCMD) {
|
||||||
|
vpif_dbg(1, debug, "Failed to set input\n");
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
ch->input_idx = index;
|
||||||
|
ch->sd = sd;
|
||||||
|
/* copy interface parameters to vpif */
|
||||||
|
ch->vpifparams.iface = chan_cfg->vpif_if;
|
||||||
|
|
||||||
*sub_device_index = i;
|
/* update tvnorms from the sub device input info */
|
||||||
return subdev_info;
|
ch->video_dev->tvnorms = chan_cfg->inputs[index].input.std;
|
||||||
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -1324,12 +1339,16 @@ static int vpif_querystd(struct file *file, void *priv, v4l2_std_id *std_id)
|
||||||
vpif_dbg(2, debug, "vpif_querystd\n");
|
vpif_dbg(2, debug, "vpif_querystd\n");
|
||||||
|
|
||||||
/* Call querystd function of decoder device */
|
/* Call querystd function of decoder device */
|
||||||
ret = v4l2_subdev_call(vpif_obj.sd[ch->curr_sd_index], video,
|
ret = v4l2_subdev_call(ch->sd, video, querystd, std_id);
|
||||||
querystd, std_id);
|
|
||||||
if (ret < 0)
|
|
||||||
vpif_dbg(1, debug, "Failed to set standard for sub devices\n");
|
|
||||||
|
|
||||||
return ret;
|
if (ret == -ENOIOCTLCMD || ret == -ENODEV)
|
||||||
|
return -ENODATA;
|
||||||
|
if (ret) {
|
||||||
|
vpif_dbg(1, debug, "Failed to query standard for sub devices\n");
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -1397,11 +1416,12 @@ static int vpif_s_std(struct file *file, void *priv, v4l2_std_id *std_id)
|
||||||
vpif_config_format(ch);
|
vpif_config_format(ch);
|
||||||
|
|
||||||
/* set standard in the sub device */
|
/* set standard in the sub device */
|
||||||
ret = v4l2_subdev_call(vpif_obj.sd[ch->curr_sd_index], core,
|
ret = v4l2_subdev_call(ch->sd, core, s_std, *std_id);
|
||||||
s_std, *std_id);
|
if (ret && ret != -ENOIOCTLCMD && ret != -ENODEV) {
|
||||||
if (ret < 0)
|
|
||||||
vpif_dbg(1, debug, "Failed to set standard for sub devices\n");
|
vpif_dbg(1, debug, "Failed to set standard for sub devices\n");
|
||||||
return ret;
|
return ret;
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -1441,10 +1461,8 @@ static int vpif_g_input(struct file *file, void *priv, unsigned int *index)
|
||||||
{
|
{
|
||||||
struct vpif_fh *fh = priv;
|
struct vpif_fh *fh = priv;
|
||||||
struct channel_obj *ch = fh->channel;
|
struct channel_obj *ch = fh->channel;
|
||||||
struct video_obj *vid_ch = &ch->video;
|
|
||||||
|
|
||||||
*index = vid_ch->input_idx;
|
|
||||||
|
|
||||||
|
*index = ch->input_idx;
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1461,13 +1479,13 @@ static int vpif_s_input(struct file *file, void *priv, unsigned int index)
|
||||||
struct vpif_fh *fh = priv;
|
struct vpif_fh *fh = priv;
|
||||||
struct channel_obj *ch = fh->channel;
|
struct channel_obj *ch = fh->channel;
|
||||||
struct common_obj *common = &ch->common[VPIF_VIDEO_INDEX];
|
struct common_obj *common = &ch->common[VPIF_VIDEO_INDEX];
|
||||||
struct video_obj *vid_ch = &ch->video;
|
int ret;
|
||||||
struct vpif_subdev_info *subdev_info;
|
|
||||||
int ret = 0, sd_index = 0;
|
|
||||||
u32 input = 0, output = 0;
|
|
||||||
|
|
||||||
chan_cfg = &config->chan_config[ch->channel_id];
|
chan_cfg = &config->chan_config[ch->channel_id];
|
||||||
|
|
||||||
|
if (index >= chan_cfg->input_count)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
if (common->started) {
|
if (common->started) {
|
||||||
vpif_err("Streaming in progress\n");
|
vpif_err("Streaming in progress\n");
|
||||||
return -EBUSY;
|
return -EBUSY;
|
||||||
|
@ -1486,45 +1504,7 @@ static int vpif_s_input(struct file *file, void *priv, unsigned int index)
|
||||||
return ret;
|
return ret;
|
||||||
|
|
||||||
fh->initialized = 1;
|
fh->initialized = 1;
|
||||||
subdev_info = vpif_map_sub_device_to_input(ch, config, index,
|
return vpif_set_input(config, ch, index);
|
||||||
&sd_index);
|
|
||||||
if (NULL == subdev_info) {
|
|
||||||
vpif_dbg(1, debug,
|
|
||||||
"couldn't lookup sub device for the input index\n");
|
|
||||||
return -EINVAL;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* first setup input path from sub device to vpif */
|
|
||||||
if (config->setup_input_path) {
|
|
||||||
ret = config->setup_input_path(ch->channel_id,
|
|
||||||
subdev_info->name);
|
|
||||||
if (ret < 0) {
|
|
||||||
vpif_dbg(1, debug, "couldn't setup input path for the"
|
|
||||||
" sub device %s, for input index %d\n",
|
|
||||||
subdev_info->name, index);
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
if (subdev_info->can_route) {
|
|
||||||
input = subdev_info->input;
|
|
||||||
output = subdev_info->output;
|
|
||||||
ret = v4l2_subdev_call(vpif_obj.sd[sd_index], video, s_routing,
|
|
||||||
input, output, 0);
|
|
||||||
if (ret < 0) {
|
|
||||||
vpif_dbg(1, debug, "Failed to set input\n");
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
vid_ch->input_idx = index;
|
|
||||||
ch->curr_subdev_info = subdev_info;
|
|
||||||
ch->curr_sd_index = sd_index;
|
|
||||||
/* copy interface parameters to vpif */
|
|
||||||
ch->vpifparams.iface = subdev_info->vpif_if;
|
|
||||||
|
|
||||||
/* update tvnorms from the sub device input info */
|
|
||||||
ch->video_dev->tvnorms = chan_cfg->inputs[index].input.std;
|
|
||||||
return ret;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -1655,9 +1635,11 @@ static int vpif_querycap(struct file *file, void *priv,
|
||||||
{
|
{
|
||||||
struct vpif_capture_config *config = vpif_dev->platform_data;
|
struct vpif_capture_config *config = vpif_dev->platform_data;
|
||||||
|
|
||||||
cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
|
cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
|
||||||
strlcpy(cap->driver, "vpif capture", sizeof(cap->driver));
|
cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
|
||||||
strlcpy(cap->bus_info, "VPIF Platform", sizeof(cap->bus_info));
|
snprintf(cap->driver, sizeof(cap->driver), "%s", dev_name(vpif_dev));
|
||||||
|
snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
|
||||||
|
dev_name(vpif_dev));
|
||||||
strlcpy(cap->card, config->card_name, sizeof(cap->card));
|
strlcpy(cap->card, config->card_name, sizeof(cap->card));
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
|
@ -1730,9 +1712,12 @@ vpif_enum_dv_timings(struct file *file, void *priv,
|
||||||
{
|
{
|
||||||
struct vpif_fh *fh = priv;
|
struct vpif_fh *fh = priv;
|
||||||
struct channel_obj *ch = fh->channel;
|
struct channel_obj *ch = fh->channel;
|
||||||
|
int ret;
|
||||||
|
|
||||||
return v4l2_subdev_call(vpif_obj.sd[ch->curr_sd_index],
|
ret = v4l2_subdev_call(ch->sd, video, enum_dv_timings, timings);
|
||||||
video, enum_dv_timings, timings);
|
if (ret == -ENOIOCTLCMD && ret == -ENODEV)
|
||||||
|
return -EINVAL;
|
||||||
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -1747,9 +1732,12 @@ vpif_query_dv_timings(struct file *file, void *priv,
|
||||||
{
|
{
|
||||||
struct vpif_fh *fh = priv;
|
struct vpif_fh *fh = priv;
|
||||||
struct channel_obj *ch = fh->channel;
|
struct channel_obj *ch = fh->channel;
|
||||||
|
int ret;
|
||||||
|
|
||||||
return v4l2_subdev_call(vpif_obj.sd[ch->curr_sd_index],
|
ret = v4l2_subdev_call(ch->sd, video, query_dv_timings, timings);
|
||||||
video, query_dv_timings, timings);
|
if (ret == -ENOIOCTLCMD && ret == -ENODEV)
|
||||||
|
return -ENODATA;
|
||||||
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -1775,13 +1763,9 @@ static int vpif_s_dv_timings(struct file *file, void *priv,
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Configure subdevice timings, if any */
|
/* Configure subdevice timings, if any */
|
||||||
ret = v4l2_subdev_call(vpif_obj.sd[ch->curr_sd_index],
|
ret = v4l2_subdev_call(ch->sd, video, s_dv_timings, timings);
|
||||||
video, s_dv_timings, timings);
|
if (ret == -ENOIOCTLCMD || ret == -ENODEV)
|
||||||
if (ret == -ENOIOCTLCMD) {
|
ret = 0;
|
||||||
vpif_dbg(2, debug, "Custom DV timings not supported by "
|
|
||||||
"subdevice\n");
|
|
||||||
return -EINVAL;
|
|
||||||
}
|
|
||||||
if (ret < 0) {
|
if (ret < 0) {
|
||||||
vpif_dbg(2, debug, "Error setting custom DV timings\n");
|
vpif_dbg(2, debug, "Error setting custom DV timings\n");
|
||||||
return ret;
|
return ret;
|
||||||
|
@ -1906,8 +1890,7 @@ static int vpif_dbg_g_register(struct file *file, void *priv,
|
||||||
struct vpif_fh *fh = priv;
|
struct vpif_fh *fh = priv;
|
||||||
struct channel_obj *ch = fh->channel;
|
struct channel_obj *ch = fh->channel;
|
||||||
|
|
||||||
return v4l2_subdev_call(vpif_obj.sd[ch->curr_sd_index], core,
|
return v4l2_subdev_call(ch->sd, core, g_register, reg);
|
||||||
g_register, reg);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -1924,8 +1907,7 @@ static int vpif_dbg_s_register(struct file *file, void *priv,
|
||||||
struct vpif_fh *fh = priv;
|
struct vpif_fh *fh = priv;
|
||||||
struct channel_obj *ch = fh->channel;
|
struct channel_obj *ch = fh->channel;
|
||||||
|
|
||||||
return v4l2_subdev_call(vpif_obj.sd[ch->curr_sd_index], core,
|
return v4l2_subdev_call(ch->sd, core, s_register, reg);
|
||||||
s_register, reg);
|
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -2063,7 +2045,8 @@ static __init int vpif_probe(struct platform_device *pdev)
|
||||||
{
|
{
|
||||||
struct vpif_subdev_info *subdevdata;
|
struct vpif_subdev_info *subdevdata;
|
||||||
struct vpif_capture_config *config;
|
struct vpif_capture_config *config;
|
||||||
int i, j, k, m, q, err;
|
int i, j, k, err;
|
||||||
|
int res_idx = 0;
|
||||||
struct i2c_adapter *i2c_adap;
|
struct i2c_adapter *i2c_adap;
|
||||||
struct channel_obj *ch;
|
struct channel_obj *ch;
|
||||||
struct common_obj *common;
|
struct common_obj *common;
|
||||||
|
@ -2086,18 +2069,19 @@ static __init int vpif_probe(struct platform_device *pdev)
|
||||||
return err;
|
return err;
|
||||||
}
|
}
|
||||||
|
|
||||||
k = 0;
|
while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, res_idx))) {
|
||||||
while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, k))) {
|
|
||||||
for (i = res->start; i <= res->end; i++) {
|
for (i = res->start; i <= res->end; i++) {
|
||||||
if (request_irq(i, vpif_channel_isr, IRQF_SHARED,
|
if (request_irq(i, vpif_channel_isr, IRQF_SHARED,
|
||||||
"VPIF_Capture",
|
"VPIF_Capture", (void *)
|
||||||
(void *)(&vpif_obj.dev[k]->channel_id))) {
|
(&vpif_obj.dev[res_idx]->channel_id))) {
|
||||||
err = -EBUSY;
|
err = -EBUSY;
|
||||||
i--;
|
for (j = 0; j < i; j++)
|
||||||
|
free_irq(j, (void *)
|
||||||
|
(&vpif_obj.dev[res_idx]->channel_id));
|
||||||
goto vpif_int_err;
|
goto vpif_int_err;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
k++;
|
res_idx++;
|
||||||
}
|
}
|
||||||
|
|
||||||
for (i = 0; i < VPIF_CAPTURE_MAX_DEVICES; i++) {
|
for (i = 0; i < VPIF_CAPTURE_MAX_DEVICES; i++) {
|
||||||
|
@ -2111,7 +2095,7 @@ static __init int vpif_probe(struct platform_device *pdev)
|
||||||
video_device_release(ch->video_dev);
|
video_device_release(ch->video_dev);
|
||||||
}
|
}
|
||||||
err = -ENOMEM;
|
err = -ENOMEM;
|
||||||
goto vpif_dev_alloc_err;
|
goto vpif_int_err;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Initialize field of video device */
|
/* Initialize field of video device */
|
||||||
|
@ -2142,24 +2126,6 @@ static __init int vpif_probe(struct platform_device *pdev)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
for (j = 0; j < VPIF_CAPTURE_MAX_DEVICES; j++) {
|
|
||||||
ch = vpif_obj.dev[j];
|
|
||||||
ch->channel_id = j;
|
|
||||||
common = &(ch->common[VPIF_VIDEO_INDEX]);
|
|
||||||
spin_lock_init(&common->irqlock);
|
|
||||||
mutex_init(&common->lock);
|
|
||||||
ch->video_dev->lock = &common->lock;
|
|
||||||
/* Initialize prio member of channel object */
|
|
||||||
v4l2_prio_init(&ch->prio);
|
|
||||||
err = video_register_device(ch->video_dev,
|
|
||||||
VFL_TYPE_GRABBER, (j ? 1 : 0));
|
|
||||||
if (err)
|
|
||||||
goto probe_out;
|
|
||||||
|
|
||||||
video_set_drvdata(ch->video_dev, ch);
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
i2c_adap = i2c_get_adapter(1);
|
i2c_adap = i2c_get_adapter(1);
|
||||||
config = pdev->dev.platform_data;
|
config = pdev->dev.platform_data;
|
||||||
|
|
||||||
|
@ -2169,7 +2135,7 @@ static __init int vpif_probe(struct platform_device *pdev)
|
||||||
if (vpif_obj.sd == NULL) {
|
if (vpif_obj.sd == NULL) {
|
||||||
vpif_err("unable to allocate memory for subdevice pointers\n");
|
vpif_err("unable to allocate memory for subdevice pointers\n");
|
||||||
err = -ENOMEM;
|
err = -ENOMEM;
|
||||||
goto probe_out;
|
goto vpif_sd_error;
|
||||||
}
|
}
|
||||||
|
|
||||||
for (i = 0; i < subdev_count; i++) {
|
for (i = 0; i < subdev_count; i++) {
|
||||||
|
@ -2186,19 +2152,32 @@ static __init int vpif_probe(struct platform_device *pdev)
|
||||||
}
|
}
|
||||||
v4l2_info(&vpif_obj.v4l2_dev, "registered sub device %s\n",
|
v4l2_info(&vpif_obj.v4l2_dev, "registered sub device %s\n",
|
||||||
subdevdata->name);
|
subdevdata->name);
|
||||||
|
|
||||||
if (vpif_obj.sd[i])
|
|
||||||
vpif_obj.sd[i]->grp_id = 1 << i;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
for (j = 0; j < VPIF_CAPTURE_MAX_DEVICES; j++) {
|
||||||
|
ch = vpif_obj.dev[j];
|
||||||
|
ch->channel_id = j;
|
||||||
|
common = &(ch->common[VPIF_VIDEO_INDEX]);
|
||||||
|
spin_lock_init(&common->irqlock);
|
||||||
|
mutex_init(&common->lock);
|
||||||
|
ch->video_dev->lock = &common->lock;
|
||||||
|
/* Initialize prio member of channel object */
|
||||||
|
v4l2_prio_init(&ch->prio);
|
||||||
|
video_set_drvdata(ch->video_dev, ch);
|
||||||
|
|
||||||
|
/* select input 0 */
|
||||||
|
err = vpif_set_input(config, ch, 0);
|
||||||
|
if (err)
|
||||||
|
goto probe_out;
|
||||||
|
|
||||||
|
err = video_register_device(ch->video_dev,
|
||||||
|
VFL_TYPE_GRABBER, (j ? 1 : 0));
|
||||||
|
if (err)
|
||||||
|
goto probe_out;
|
||||||
|
}
|
||||||
v4l2_info(&vpif_obj.v4l2_dev, "VPIF capture driver initialized\n");
|
v4l2_info(&vpif_obj.v4l2_dev, "VPIF capture driver initialized\n");
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
probe_subdev_out:
|
|
||||||
/* free sub devices memory */
|
|
||||||
kfree(vpif_obj.sd);
|
|
||||||
|
|
||||||
j = VPIF_CAPTURE_MAX_DEVICES;
|
|
||||||
probe_out:
|
probe_out:
|
||||||
for (k = 0; k < j; k++) {
|
for (k = 0; k < j; k++) {
|
||||||
/* Get the pointer to the channel object */
|
/* Get the pointer to the channel object */
|
||||||
|
@ -2206,22 +2185,23 @@ static __init int vpif_probe(struct platform_device *pdev)
|
||||||
/* Unregister video device */
|
/* Unregister video device */
|
||||||
video_unregister_device(ch->video_dev);
|
video_unregister_device(ch->video_dev);
|
||||||
}
|
}
|
||||||
|
probe_subdev_out:
|
||||||
|
/* free sub devices memory */
|
||||||
|
kfree(vpif_obj.sd);
|
||||||
|
|
||||||
vpif_dev_alloc_err:
|
vpif_sd_error:
|
||||||
k = VPIF_CAPTURE_MAX_DEVICES-1;
|
for (i = 0; i < VPIF_CAPTURE_MAX_DEVICES; i++) {
|
||||||
res = platform_get_resource(pdev, IORESOURCE_IRQ, k);
|
ch = vpif_obj.dev[i];
|
||||||
i = res->end;
|
/* Note: does nothing if ch->video_dev == NULL */
|
||||||
|
video_device_release(ch->video_dev);
|
||||||
vpif_int_err:
|
|
||||||
for (q = k; q >= 0; q--) {
|
|
||||||
for (m = i; m >= (int)res->start; m--)
|
|
||||||
free_irq(m, (void *)(&vpif_obj.dev[q]->channel_id));
|
|
||||||
|
|
||||||
res = platform_get_resource(pdev, IORESOURCE_IRQ, q-1);
|
|
||||||
if (res)
|
|
||||||
i = res->end;
|
|
||||||
}
|
}
|
||||||
|
vpif_int_err:
|
||||||
v4l2_device_unregister(&vpif_obj.v4l2_dev);
|
v4l2_device_unregister(&vpif_obj.v4l2_dev);
|
||||||
|
for (i = 0; i < res_idx; i++) {
|
||||||
|
res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
|
||||||
|
for (j = res->start; j <= res->end; j++)
|
||||||
|
free_irq(j, (void *)(&vpif_obj.dev[i]->channel_id));
|
||||||
|
}
|
||||||
return err;
|
return err;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -54,8 +54,6 @@ struct video_obj {
|
||||||
/* Currently selected or default standard */
|
/* Currently selected or default standard */
|
||||||
v4l2_std_id stdid;
|
v4l2_std_id stdid;
|
||||||
struct v4l2_dv_timings dv_timings;
|
struct v4l2_dv_timings dv_timings;
|
||||||
/* This is to track the last input that is passed to application */
|
|
||||||
u32 input_idx;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
struct vpif_cap_buffer {
|
struct vpif_cap_buffer {
|
||||||
|
@ -119,10 +117,10 @@ struct channel_obj {
|
||||||
u8 initialized;
|
u8 initialized;
|
||||||
/* Identifies channel */
|
/* Identifies channel */
|
||||||
enum vpif_channel_id channel_id;
|
enum vpif_channel_id channel_id;
|
||||||
/* index into sd table */
|
/* Current input */
|
||||||
int curr_sd_index;
|
u32 input_idx;
|
||||||
/* ptr to current sub device information */
|
/* subdev corresponding to the current input, may be NULL */
|
||||||
struct vpif_subdev_info *curr_subdev_info;
|
struct v4l2_subdev *sd;
|
||||||
/* vpif configuration params */
|
/* vpif configuration params */
|
||||||
struct vpif_params vpifparams;
|
struct vpif_params vpifparams;
|
||||||
/* common object array */
|
/* common object array */
|
||||||
|
@ -159,10 +157,6 @@ struct vpif_config_params {
|
||||||
u32 video_limit[VPIF_CAPTURE_NUM_CHANNELS];
|
u32 video_limit[VPIF_CAPTURE_NUM_CHANNELS];
|
||||||
u8 max_device_type;
|
u8 max_device_type;
|
||||||
};
|
};
|
||||||
/* Struct which keeps track of the line numbers for the sliced vbi service */
|
|
||||||
struct vpif_service_line {
|
|
||||||
u16 service_id;
|
|
||||||
u16 service_line[2];
|
|
||||||
};
|
|
||||||
#endif /* End of __KERNEL__ */
|
#endif /* End of __KERNEL__ */
|
||||||
#endif /* VPIF_CAPTURE_H */
|
#endif /* VPIF_CAPTURE_H */
|
||||||
|
|
|
@ -280,12 +280,13 @@ static int vpif_start_streaming(struct vb2_queue *vq, unsigned int count)
|
||||||
}
|
}
|
||||||
|
|
||||||
/* clock settings */
|
/* clock settings */
|
||||||
ret =
|
if (vpif_config_data->set_clock) {
|
||||||
vpif_config_data->set_clock(ch->vpifparams.std_info.ycmux_mode,
|
ret = vpif_config_data->set_clock(ch->vpifparams.std_info.
|
||||||
ch->vpifparams.std_info.hd_sd);
|
ycmux_mode, ch->vpifparams.std_info.hd_sd);
|
||||||
if (ret < 0) {
|
if (ret < 0) {
|
||||||
vpif_err("can't set clock\n");
|
vpif_err("can't set clock\n");
|
||||||
return ret;
|
return ret;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/* set the parameters and addresses */
|
/* set the parameters and addresses */
|
||||||
|
@ -307,7 +308,7 @@ static int vpif_start_streaming(struct vb2_queue *vq, unsigned int count)
|
||||||
channel2_intr_assert();
|
channel2_intr_assert();
|
||||||
channel2_intr_enable(1);
|
channel2_intr_enable(1);
|
||||||
enable_channel2(1);
|
enable_channel2(1);
|
||||||
if (vpif_config_data->ch2_clip_en)
|
if (vpif_config_data->chan_config[VPIF_CHANNEL2_VIDEO].clip_en)
|
||||||
channel2_clipping_enable(1);
|
channel2_clipping_enable(1);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -316,7 +317,7 @@ static int vpif_start_streaming(struct vb2_queue *vq, unsigned int count)
|
||||||
channel3_intr_assert();
|
channel3_intr_assert();
|
||||||
channel3_intr_enable(1);
|
channel3_intr_enable(1);
|
||||||
enable_channel3(1);
|
enable_channel3(1);
|
||||||
if (vpif_config_data->ch3_clip_en)
|
if (vpif_config_data->chan_config[VPIF_CHANNEL3_VIDEO].clip_en)
|
||||||
channel3_clipping_enable(1);
|
channel3_clipping_enable(1);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -826,9 +827,11 @@ static int vpif_querycap(struct file *file, void *priv,
|
||||||
{
|
{
|
||||||
struct vpif_display_config *config = vpif_dev->platform_data;
|
struct vpif_display_config *config = vpif_dev->platform_data;
|
||||||
|
|
||||||
cap->capabilities = V4L2_CAP_VIDEO_OUTPUT | V4L2_CAP_STREAMING;
|
cap->device_caps = V4L2_CAP_VIDEO_OUTPUT | V4L2_CAP_STREAMING;
|
||||||
strlcpy(cap->driver, "vpif display", sizeof(cap->driver));
|
cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
|
||||||
strlcpy(cap->bus_info, "Platform", sizeof(cap->bus_info));
|
snprintf(cap->driver, sizeof(cap->driver), "%s", dev_name(vpif_dev));
|
||||||
|
snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
|
||||||
|
dev_name(vpif_dev));
|
||||||
strlcpy(cap->card, config->card_name, sizeof(cap->card));
|
strlcpy(cap->card, config->card_name, sizeof(cap->card));
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
|
@ -935,6 +938,7 @@ static int vpif_reqbufs(struct file *file, void *priv,
|
||||||
enum v4l2_field field;
|
enum v4l2_field field;
|
||||||
struct vb2_queue *q;
|
struct vb2_queue *q;
|
||||||
u8 index = 0;
|
u8 index = 0;
|
||||||
|
int ret;
|
||||||
|
|
||||||
/* This file handle has not initialized the channel,
|
/* This file handle has not initialized the channel,
|
||||||
It is not allowed to do settings */
|
It is not allowed to do settings */
|
||||||
|
@ -980,8 +984,12 @@ static int vpif_reqbufs(struct file *file, void *priv,
|
||||||
q->mem_ops = &vb2_dma_contig_memops;
|
q->mem_ops = &vb2_dma_contig_memops;
|
||||||
q->buf_struct_size = sizeof(struct vpif_disp_buffer);
|
q->buf_struct_size = sizeof(struct vpif_disp_buffer);
|
||||||
|
|
||||||
vb2_queue_init(q);
|
ret = vb2_queue_init(q);
|
||||||
|
if (ret) {
|
||||||
|
vpif_err("vpif_display: vb2_queue_init() failed\n");
|
||||||
|
vb2_dma_contig_cleanup_ctx(common->alloc_ctx);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
/* Set io allowed member of file handle to TRUE */
|
/* Set io allowed member of file handle to TRUE */
|
||||||
fh->io_allowed[index] = 1;
|
fh->io_allowed[index] = 1;
|
||||||
/* Increment io usrs member of channel object to 1 */
|
/* Increment io usrs member of channel object to 1 */
|
||||||
|
@ -1173,14 +1181,16 @@ static int vpif_streamoff(struct file *file, void *priv,
|
||||||
if (buftype == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
|
if (buftype == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
|
||||||
/* disable channel */
|
/* disable channel */
|
||||||
if (VPIF_CHANNEL2_VIDEO == ch->channel_id) {
|
if (VPIF_CHANNEL2_VIDEO == ch->channel_id) {
|
||||||
if (vpif_config_data->ch2_clip_en)
|
if (vpif_config_data->
|
||||||
|
chan_config[VPIF_CHANNEL2_VIDEO].clip_en)
|
||||||
channel2_clipping_enable(0);
|
channel2_clipping_enable(0);
|
||||||
enable_channel2(0);
|
enable_channel2(0);
|
||||||
channel2_intr_enable(0);
|
channel2_intr_enable(0);
|
||||||
}
|
}
|
||||||
if ((VPIF_CHANNEL3_VIDEO == ch->channel_id) ||
|
if ((VPIF_CHANNEL3_VIDEO == ch->channel_id) ||
|
||||||
(2 == common->started)) {
|
(2 == common->started)) {
|
||||||
if (vpif_config_data->ch3_clip_en)
|
if (vpif_config_data->
|
||||||
|
chan_config[VPIF_CHANNEL3_VIDEO].clip_en)
|
||||||
channel3_clipping_enable(0);
|
channel3_clipping_enable(0);
|
||||||
enable_channel3(0);
|
enable_channel3(0);
|
||||||
channel3_intr_enable(0);
|
channel3_intr_enable(0);
|
||||||
|
@ -1213,49 +1223,126 @@ static int vpif_enum_output(struct file *file, void *fh,
|
||||||
{
|
{
|
||||||
|
|
||||||
struct vpif_display_config *config = vpif_dev->platform_data;
|
struct vpif_display_config *config = vpif_dev->platform_data;
|
||||||
|
struct vpif_display_chan_config *chan_cfg;
|
||||||
|
struct vpif_fh *vpif_handler = fh;
|
||||||
|
struct channel_obj *ch = vpif_handler->channel;
|
||||||
|
|
||||||
if (output->index >= config->output_count) {
|
chan_cfg = &config->chan_config[ch->channel_id];
|
||||||
|
if (output->index >= chan_cfg->output_count) {
|
||||||
vpif_dbg(1, debug, "Invalid output index\n");
|
vpif_dbg(1, debug, "Invalid output index\n");
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
}
|
}
|
||||||
|
|
||||||
strcpy(output->name, config->output[output->index]);
|
*output = chan_cfg->outputs[output->index].output;
|
||||||
output->type = V4L2_OUTPUT_TYPE_ANALOG;
|
return 0;
|
||||||
output->std = VPIF_V4L2_STD;
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* vpif_output_to_subdev() - Maps output to sub device
|
||||||
|
* @vpif_cfg - global config ptr
|
||||||
|
* @chan_cfg - channel config ptr
|
||||||
|
* @index - Given output index from application
|
||||||
|
*
|
||||||
|
* lookup the sub device information for a given output index.
|
||||||
|
* we report all the output to application. output table also
|
||||||
|
* has sub device name for the each output
|
||||||
|
*/
|
||||||
|
static int
|
||||||
|
vpif_output_to_subdev(struct vpif_display_config *vpif_cfg,
|
||||||
|
struct vpif_display_chan_config *chan_cfg, int index)
|
||||||
|
{
|
||||||
|
struct vpif_subdev_info *subdev_info;
|
||||||
|
const char *subdev_name;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
vpif_dbg(2, debug, "vpif_output_to_subdev\n");
|
||||||
|
|
||||||
|
if (chan_cfg->outputs == NULL)
|
||||||
|
return -1;
|
||||||
|
|
||||||
|
subdev_name = chan_cfg->outputs[index].subdev_name;
|
||||||
|
if (subdev_name == NULL)
|
||||||
|
return -1;
|
||||||
|
|
||||||
|
/* loop through the sub device list to get the sub device info */
|
||||||
|
for (i = 0; i < vpif_cfg->subdev_count; i++) {
|
||||||
|
subdev_info = &vpif_cfg->subdevinfo[i];
|
||||||
|
if (!strcmp(subdev_info->name, subdev_name))
|
||||||
|
return i;
|
||||||
|
}
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* vpif_set_output() - Select an output
|
||||||
|
* @vpif_cfg - global config ptr
|
||||||
|
* @ch - channel
|
||||||
|
* @index - Given output index from application
|
||||||
|
*
|
||||||
|
* Select the given output.
|
||||||
|
*/
|
||||||
|
static int vpif_set_output(struct vpif_display_config *vpif_cfg,
|
||||||
|
struct channel_obj *ch, int index)
|
||||||
|
{
|
||||||
|
struct vpif_display_chan_config *chan_cfg =
|
||||||
|
&vpif_cfg->chan_config[ch->channel_id];
|
||||||
|
struct vpif_subdev_info *subdev_info = NULL;
|
||||||
|
struct v4l2_subdev *sd = NULL;
|
||||||
|
u32 input = 0, output = 0;
|
||||||
|
int sd_index;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
sd_index = vpif_output_to_subdev(vpif_cfg, chan_cfg, index);
|
||||||
|
if (sd_index >= 0) {
|
||||||
|
sd = vpif_obj.sd[sd_index];
|
||||||
|
subdev_info = &vpif_cfg->subdevinfo[sd_index];
|
||||||
|
}
|
||||||
|
|
||||||
|
if (sd) {
|
||||||
|
input = chan_cfg->outputs[index].input_route;
|
||||||
|
output = chan_cfg->outputs[index].output_route;
|
||||||
|
ret = v4l2_subdev_call(sd, video, s_routing, input, output, 0);
|
||||||
|
if (ret < 0 && ret != -ENOIOCTLCMD) {
|
||||||
|
vpif_err("Failed to set output\n");
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
ch->output_idx = index;
|
||||||
|
ch->sd = sd;
|
||||||
|
if (chan_cfg->outputs != NULL)
|
||||||
|
/* update tvnorms from the sub device output info */
|
||||||
|
ch->video_dev->tvnorms = chan_cfg->outputs[index].output.std;
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int vpif_s_output(struct file *file, void *priv, unsigned int i)
|
static int vpif_s_output(struct file *file, void *priv, unsigned int i)
|
||||||
{
|
{
|
||||||
|
struct vpif_display_config *config = vpif_dev->platform_data;
|
||||||
|
struct vpif_display_chan_config *chan_cfg;
|
||||||
struct vpif_fh *fh = priv;
|
struct vpif_fh *fh = priv;
|
||||||
struct channel_obj *ch = fh->channel;
|
struct channel_obj *ch = fh->channel;
|
||||||
struct video_obj *vid_ch = &ch->video;
|
|
||||||
struct common_obj *common = &ch->common[VPIF_VIDEO_INDEX];
|
struct common_obj *common = &ch->common[VPIF_VIDEO_INDEX];
|
||||||
int ret = 0;
|
|
||||||
|
chan_cfg = &config->chan_config[ch->channel_id];
|
||||||
|
|
||||||
|
if (i >= chan_cfg->output_count)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
if (common->started) {
|
if (common->started) {
|
||||||
vpif_err("Streaming in progress\n");
|
vpif_err("Streaming in progress\n");
|
||||||
return -EBUSY;
|
return -EBUSY;
|
||||||
}
|
}
|
||||||
|
|
||||||
ret = v4l2_device_call_until_err(&vpif_obj.v4l2_dev, 1, video,
|
return vpif_set_output(config, ch, i);
|
||||||
s_routing, 0, i, 0);
|
|
||||||
|
|
||||||
if (ret < 0)
|
|
||||||
vpif_err("Failed to set output standard\n");
|
|
||||||
|
|
||||||
vid_ch->output_id = i;
|
|
||||||
return ret;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static int vpif_g_output(struct file *file, void *priv, unsigned int *i)
|
static int vpif_g_output(struct file *file, void *priv, unsigned int *i)
|
||||||
{
|
{
|
||||||
struct vpif_fh *fh = priv;
|
struct vpif_fh *fh = priv;
|
||||||
struct channel_obj *ch = fh->channel;
|
struct channel_obj *ch = fh->channel;
|
||||||
struct video_obj *vid_ch = &ch->video;
|
|
||||||
|
|
||||||
*i = vid_ch->output_id;
|
*i = ch->output_idx;
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
@ -1290,10 +1377,12 @@ vpif_enum_dv_timings(struct file *file, void *priv,
|
||||||
{
|
{
|
||||||
struct vpif_fh *fh = priv;
|
struct vpif_fh *fh = priv;
|
||||||
struct channel_obj *ch = fh->channel;
|
struct channel_obj *ch = fh->channel;
|
||||||
struct video_obj *vid_ch = &ch->video;
|
int ret;
|
||||||
|
|
||||||
return v4l2_subdev_call(vpif_obj.sd[vid_ch->output_id],
|
ret = v4l2_subdev_call(ch->sd, video, enum_dv_timings, timings);
|
||||||
video, enum_dv_timings, timings);
|
if (ret == -ENOIOCTLCMD && ret == -ENODEV)
|
||||||
|
return -EINVAL;
|
||||||
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -1319,13 +1408,9 @@ static int vpif_s_dv_timings(struct file *file, void *priv,
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Configure subdevice timings, if any */
|
/* Configure subdevice timings, if any */
|
||||||
ret = v4l2_subdev_call(vpif_obj.sd[vid_ch->output_id],
|
ret = v4l2_subdev_call(ch->sd, video, s_dv_timings, timings);
|
||||||
video, s_dv_timings, timings);
|
if (ret == -ENOIOCTLCMD || ret == -ENODEV)
|
||||||
if (ret == -ENOIOCTLCMD) {
|
ret = 0;
|
||||||
vpif_dbg(2, debug, "Custom DV timings not supported by "
|
|
||||||
"subdevice\n");
|
|
||||||
return -EINVAL;
|
|
||||||
}
|
|
||||||
if (ret < 0) {
|
if (ret < 0) {
|
||||||
vpif_dbg(2, debug, "Error setting custom DV timings\n");
|
vpif_dbg(2, debug, "Error setting custom DV timings\n");
|
||||||
return ret;
|
return ret;
|
||||||
|
@ -1450,10 +1535,8 @@ static int vpif_dbg_g_register(struct file *file, void *priv,
|
||||||
struct v4l2_dbg_register *reg){
|
struct v4l2_dbg_register *reg){
|
||||||
struct vpif_fh *fh = priv;
|
struct vpif_fh *fh = priv;
|
||||||
struct channel_obj *ch = fh->channel;
|
struct channel_obj *ch = fh->channel;
|
||||||
struct video_obj *vid_ch = &ch->video;
|
|
||||||
|
|
||||||
return v4l2_subdev_call(vpif_obj.sd[vid_ch->output_id], core,
|
return v4l2_subdev_call(ch->sd, core, g_register, reg);
|
||||||
g_register, reg);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -1469,10 +1552,8 @@ static int vpif_dbg_s_register(struct file *file, void *priv,
|
||||||
struct v4l2_dbg_register *reg){
|
struct v4l2_dbg_register *reg){
|
||||||
struct vpif_fh *fh = priv;
|
struct vpif_fh *fh = priv;
|
||||||
struct channel_obj *ch = fh->channel;
|
struct channel_obj *ch = fh->channel;
|
||||||
struct video_obj *vid_ch = &ch->video;
|
|
||||||
|
|
||||||
return v4l2_subdev_call(vpif_obj.sd[vid_ch->output_id], core,
|
return v4l2_subdev_call(ch->sd, core, s_register, reg);
|
||||||
s_register, reg);
|
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -1536,9 +1617,6 @@ static struct video_device vpif_video_template = {
|
||||||
.name = "vpif",
|
.name = "vpif",
|
||||||
.fops = &vpif_fops,
|
.fops = &vpif_fops,
|
||||||
.ioctl_ops = &vpif_ioctl_ops,
|
.ioctl_ops = &vpif_ioctl_ops,
|
||||||
.tvnorms = VPIF_V4L2_STD,
|
|
||||||
.current_norm = V4L2_STD_625_50,
|
|
||||||
|
|
||||||
};
|
};
|
||||||
|
|
||||||
/*Configure the channels, buffer sizei, request irq */
|
/*Configure the channels, buffer sizei, request irq */
|
||||||
|
@ -1611,7 +1689,8 @@ static __init int vpif_probe(struct platform_device *pdev)
|
||||||
{
|
{
|
||||||
struct vpif_subdev_info *subdevdata;
|
struct vpif_subdev_info *subdevdata;
|
||||||
struct vpif_display_config *config;
|
struct vpif_display_config *config;
|
||||||
int i, j = 0, k, q, m, err = 0;
|
int i, j = 0, k, err = 0;
|
||||||
|
int res_idx = 0;
|
||||||
struct i2c_adapter *i2c_adap;
|
struct i2c_adapter *i2c_adap;
|
||||||
struct common_obj *common;
|
struct common_obj *common;
|
||||||
struct channel_obj *ch;
|
struct channel_obj *ch;
|
||||||
|
@ -1634,21 +1713,22 @@ static __init int vpif_probe(struct platform_device *pdev)
|
||||||
return err;
|
return err;
|
||||||
}
|
}
|
||||||
|
|
||||||
k = 0;
|
while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, res_idx))) {
|
||||||
while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, k))) {
|
|
||||||
for (i = res->start; i <= res->end; i++) {
|
for (i = res->start; i <= res->end; i++) {
|
||||||
if (request_irq(i, vpif_channel_isr, IRQF_SHARED,
|
if (request_irq(i, vpif_channel_isr, IRQF_SHARED,
|
||||||
"VPIF_Display",
|
"VPIF_Display", (void *)
|
||||||
(void *)(&vpif_obj.dev[k]->channel_id))) {
|
(&vpif_obj.dev[res_idx]->channel_id))) {
|
||||||
err = -EBUSY;
|
err = -EBUSY;
|
||||||
|
for (j = 0; j < i; j++)
|
||||||
|
free_irq(j, (void *)
|
||||||
|
(&vpif_obj.dev[res_idx]->channel_id));
|
||||||
goto vpif_int_err;
|
goto vpif_int_err;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
k++;
|
res_idx++;
|
||||||
}
|
}
|
||||||
|
|
||||||
for (i = 0; i < VPIF_DISPLAY_MAX_DEVICES; i++) {
|
for (i = 0; i < VPIF_DISPLAY_MAX_DEVICES; i++) {
|
||||||
|
|
||||||
/* Get the pointer to the channel object */
|
/* Get the pointer to the channel object */
|
||||||
ch = vpif_obj.dev[i];
|
ch = vpif_obj.dev[i];
|
||||||
|
|
||||||
|
@ -1694,6 +1774,32 @@ static __init int vpif_probe(struct platform_device *pdev)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
i2c_adap = i2c_get_adapter(1);
|
||||||
|
config = pdev->dev.platform_data;
|
||||||
|
subdev_count = config->subdev_count;
|
||||||
|
subdevdata = config->subdevinfo;
|
||||||
|
vpif_obj.sd = kzalloc(sizeof(struct v4l2_subdev *) * subdev_count,
|
||||||
|
GFP_KERNEL);
|
||||||
|
if (vpif_obj.sd == NULL) {
|
||||||
|
vpif_err("unable to allocate memory for subdevice pointers\n");
|
||||||
|
err = -ENOMEM;
|
||||||
|
goto vpif_sd_error;
|
||||||
|
}
|
||||||
|
|
||||||
|
for (i = 0; i < subdev_count; i++) {
|
||||||
|
vpif_obj.sd[i] = v4l2_i2c_new_subdev_board(&vpif_obj.v4l2_dev,
|
||||||
|
i2c_adap,
|
||||||
|
&subdevdata[i].board_info,
|
||||||
|
NULL);
|
||||||
|
if (!vpif_obj.sd[i]) {
|
||||||
|
vpif_err("Error registering v4l2 subdevice\n");
|
||||||
|
goto probe_subdev_out;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (vpif_obj.sd[i])
|
||||||
|
vpif_obj.sd[i]->grp_id = 1 << i;
|
||||||
|
}
|
||||||
|
|
||||||
for (j = 0; j < VPIF_DISPLAY_MAX_DEVICES; j++) {
|
for (j = 0; j < VPIF_DISPLAY_MAX_DEVICES; j++) {
|
||||||
ch = vpif_obj.dev[j];
|
ch = vpif_obj.dev[j];
|
||||||
/* Initialize field of the channel objects */
|
/* Initialize field of the channel objects */
|
||||||
|
@ -1715,6 +1821,8 @@ static __init int vpif_probe(struct platform_device *pdev)
|
||||||
|
|
||||||
}
|
}
|
||||||
ch->initialized = 0;
|
ch->initialized = 0;
|
||||||
|
if (subdev_count)
|
||||||
|
ch->sd = vpif_obj.sd[0];
|
||||||
ch->channel_id = j;
|
ch->channel_id = j;
|
||||||
if (j < 2)
|
if (j < 2)
|
||||||
ch->common[VPIF_VIDEO_INDEX].numbuffers =
|
ch->common[VPIF_VIDEO_INDEX].numbuffers =
|
||||||
|
@ -1729,6 +1837,12 @@ static __init int vpif_probe(struct platform_device *pdev)
|
||||||
ch->common[VPIF_VIDEO_INDEX].fmt.type =
|
ch->common[VPIF_VIDEO_INDEX].fmt.type =
|
||||||
V4L2_BUF_TYPE_VIDEO_OUTPUT;
|
V4L2_BUF_TYPE_VIDEO_OUTPUT;
|
||||||
ch->video_dev->lock = &common->lock;
|
ch->video_dev->lock = &common->lock;
|
||||||
|
video_set_drvdata(ch->video_dev, ch);
|
||||||
|
|
||||||
|
/* select output 0 */
|
||||||
|
err = vpif_set_output(config, ch, 0);
|
||||||
|
if (err)
|
||||||
|
goto probe_out;
|
||||||
|
|
||||||
/* register video device */
|
/* register video device */
|
||||||
vpif_dbg(1, debug, "channel=%x,channel->video_dev=%x\n",
|
vpif_dbg(1, debug, "channel=%x,channel->video_dev=%x\n",
|
||||||
|
@ -1738,42 +1852,12 @@ static __init int vpif_probe(struct platform_device *pdev)
|
||||||
VFL_TYPE_GRABBER, (j ? 3 : 2));
|
VFL_TYPE_GRABBER, (j ? 3 : 2));
|
||||||
if (err < 0)
|
if (err < 0)
|
||||||
goto probe_out;
|
goto probe_out;
|
||||||
|
|
||||||
video_set_drvdata(ch->video_dev, ch);
|
|
||||||
}
|
|
||||||
|
|
||||||
i2c_adap = i2c_get_adapter(1);
|
|
||||||
config = pdev->dev.platform_data;
|
|
||||||
subdev_count = config->subdev_count;
|
|
||||||
subdevdata = config->subdevinfo;
|
|
||||||
vpif_obj.sd = kzalloc(sizeof(struct v4l2_subdev *) * subdev_count,
|
|
||||||
GFP_KERNEL);
|
|
||||||
if (vpif_obj.sd == NULL) {
|
|
||||||
vpif_err("unable to allocate memory for subdevice pointers\n");
|
|
||||||
err = -ENOMEM;
|
|
||||||
goto probe_out;
|
|
||||||
}
|
|
||||||
|
|
||||||
for (i = 0; i < subdev_count; i++) {
|
|
||||||
vpif_obj.sd[i] = v4l2_i2c_new_subdev_board(&vpif_obj.v4l2_dev,
|
|
||||||
i2c_adap,
|
|
||||||
&subdevdata[i].board_info,
|
|
||||||
NULL);
|
|
||||||
if (!vpif_obj.sd[i]) {
|
|
||||||
vpif_err("Error registering v4l2 subdevice\n");
|
|
||||||
goto probe_subdev_out;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (vpif_obj.sd[i])
|
|
||||||
vpif_obj.sd[i]->grp_id = 1 << i;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
v4l2_info(&vpif_obj.v4l2_dev,
|
v4l2_info(&vpif_obj.v4l2_dev,
|
||||||
" VPIF display driver initialized\n");
|
" VPIF display driver initialized\n");
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
probe_subdev_out:
|
|
||||||
kfree(vpif_obj.sd);
|
|
||||||
probe_out:
|
probe_out:
|
||||||
for (k = 0; k < j; k++) {
|
for (k = 0; k < j; k++) {
|
||||||
ch = vpif_obj.dev[k];
|
ch = vpif_obj.dev[k];
|
||||||
|
@ -1781,14 +1865,21 @@ static __init int vpif_probe(struct platform_device *pdev)
|
||||||
video_device_release(ch->video_dev);
|
video_device_release(ch->video_dev);
|
||||||
ch->video_dev = NULL;
|
ch->video_dev = NULL;
|
||||||
}
|
}
|
||||||
|
probe_subdev_out:
|
||||||
|
kfree(vpif_obj.sd);
|
||||||
|
vpif_sd_error:
|
||||||
|
for (i = 0; i < VPIF_DISPLAY_MAX_DEVICES; i++) {
|
||||||
|
ch = vpif_obj.dev[i];
|
||||||
|
/* Note: does nothing if ch->video_dev == NULL */
|
||||||
|
video_device_release(ch->video_dev);
|
||||||
|
}
|
||||||
vpif_int_err:
|
vpif_int_err:
|
||||||
v4l2_device_unregister(&vpif_obj.v4l2_dev);
|
v4l2_device_unregister(&vpif_obj.v4l2_dev);
|
||||||
vpif_err("VPIF IRQ request failed\n");
|
vpif_err("VPIF IRQ request failed\n");
|
||||||
for (q = k; k >= 0; k--) {
|
for (i = 0; i < res_idx; i++) {
|
||||||
for (m = i; m >= res->start; m--)
|
res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
|
||||||
free_irq(m, (void *)(&vpif_obj.dev[k]->channel_id));
|
for (j = res->start; j <= res->end; j++)
|
||||||
res = platform_get_resource(pdev, IORESOURCE_IRQ, k-1);
|
free_irq(j, (void *)(&vpif_obj.dev[i]->channel_id));
|
||||||
m = res->end;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
return err;
|
return err;
|
||||||
|
|
|
@ -62,13 +62,6 @@ struct video_obj {
|
||||||
v4l2_std_id stdid; /* Currently selected or default
|
v4l2_std_id stdid; /* Currently selected or default
|
||||||
* standard */
|
* standard */
|
||||||
struct v4l2_dv_timings dv_timings;
|
struct v4l2_dv_timings dv_timings;
|
||||||
u32 output_id; /* Current output id */
|
|
||||||
};
|
|
||||||
|
|
||||||
struct vbi_obj {
|
|
||||||
int num_services;
|
|
||||||
struct vpif_vbi_params vbiparams; /* vpif parameters for the raw
|
|
||||||
* vbi data */
|
|
||||||
};
|
};
|
||||||
|
|
||||||
struct vpif_disp_buffer {
|
struct vpif_disp_buffer {
|
||||||
|
@ -131,12 +124,13 @@ struct channel_obj {
|
||||||
* which is being displayed */
|
* which is being displayed */
|
||||||
u8 initialized; /* flag to indicate whether
|
u8 initialized; /* flag to indicate whether
|
||||||
* encoder is initialized */
|
* encoder is initialized */
|
||||||
|
u32 output_idx; /* Current output index */
|
||||||
|
struct v4l2_subdev *sd; /* Current output subdev(may be NULL) */
|
||||||
|
|
||||||
enum vpif_channel_id channel_id;/* Identifies channel */
|
enum vpif_channel_id channel_id;/* Identifies channel */
|
||||||
struct vpif_params vpifparams;
|
struct vpif_params vpifparams;
|
||||||
struct common_obj common[VPIF_NUMOBJECTS];
|
struct common_obj common[VPIF_NUMOBJECTS];
|
||||||
struct video_obj video;
|
struct video_obj video;
|
||||||
struct vbi_obj vbi;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
/* File handle structure */
|
/* File handle structure */
|
||||||
|
@ -168,12 +162,4 @@ struct vpif_config_params {
|
||||||
u8 min_numbuffers;
|
u8 min_numbuffers;
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Struct which keeps track of the line numbers for the sliced vbi service */
|
|
||||||
struct vpif_service_line {
|
|
||||||
u16 service_id;
|
|
||||||
u16 service_line[2];
|
|
||||||
u16 enc_service_id;
|
|
||||||
u8 bytestowrite;
|
|
||||||
};
|
|
||||||
|
|
||||||
#endif /* DAVINCIHD_DISPLAY_H */
|
#endif /* DAVINCIHD_DISPLAY_H */
|
||||||
|
|
|
@ -212,7 +212,7 @@ void gsc_hw_set_in_image_format(struct gsc_ctx *ctx)
|
||||||
else
|
else
|
||||||
cfg |= GSC_IN_YUV422_3P;
|
cfg |= GSC_IN_YUV422_3P;
|
||||||
break;
|
break;
|
||||||
};
|
}
|
||||||
|
|
||||||
writel(cfg, dev->regs + GSC_IN_CON);
|
writel(cfg, dev->regs + GSC_IN_CON);
|
||||||
}
|
}
|
||||||
|
@ -332,7 +332,7 @@ void gsc_hw_set_out_image_format(struct gsc_ctx *ctx)
|
||||||
case 3:
|
case 3:
|
||||||
cfg |= GSC_OUT_YUV420_3P;
|
cfg |= GSC_OUT_YUV420_3P;
|
||||||
break;
|
break;
|
||||||
};
|
}
|
||||||
|
|
||||||
end_set:
|
end_set:
|
||||||
writel(cfg, dev->regs + GSC_OUT_CON);
|
writel(cfg, dev->regs + GSC_OUT_CON);
|
||||||
|
|
|
@ -864,7 +864,7 @@ int vidioc_s_fbuf(struct file *file, void *priv, const struct v4l2_framebuffer *
|
||||||
{
|
{
|
||||||
struct viu_fh *fh = priv;
|
struct viu_fh *fh = priv;
|
||||||
struct viu_dev *dev = fh->dev;
|
struct viu_dev *dev = fh->dev;
|
||||||
struct v4l2_framebuffer *fb = arg;
|
const struct v4l2_framebuffer *fb = arg;
|
||||||
struct viu_fmt *fmt;
|
struct viu_fmt *fmt;
|
||||||
|
|
||||||
if (!capable(CAP_SYS_ADMIN) && !capable(CAP_SYS_RAWIO))
|
if (!capable(CAP_SYS_ADMIN) && !capable(CAP_SYS_RAWIO))
|
||||||
|
|
|
@ -397,8 +397,7 @@ static void device_isr(unsigned long priv)
|
||||||
curr_ctx = v4l2_m2m_get_curr_priv(m2mtest_dev->m2m_dev);
|
curr_ctx = v4l2_m2m_get_curr_priv(m2mtest_dev->m2m_dev);
|
||||||
|
|
||||||
if (NULL == curr_ctx) {
|
if (NULL == curr_ctx) {
|
||||||
printk(KERN_ERR
|
pr_err("Instance released before the end of transaction\n");
|
||||||
"Instance released before the end of transaction\n");
|
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -894,7 +893,7 @@ static int m2mtest_open(struct file *file)
|
||||||
|
|
||||||
if (mutex_lock_interruptible(&dev->dev_mutex))
|
if (mutex_lock_interruptible(&dev->dev_mutex))
|
||||||
return -ERESTARTSYS;
|
return -ERESTARTSYS;
|
||||||
ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
|
ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
|
||||||
if (!ctx) {
|
if (!ctx) {
|
||||||
rc = -ENOMEM;
|
rc = -ENOMEM;
|
||||||
goto open_unlock;
|
goto open_unlock;
|
||||||
|
@ -1020,7 +1019,7 @@ static int m2mtest_probe(struct platform_device *pdev)
|
||||||
struct video_device *vfd;
|
struct video_device *vfd;
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
dev = kzalloc(sizeof *dev, GFP_KERNEL);
|
dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
|
||||||
if (!dev)
|
if (!dev)
|
||||||
return -ENOMEM;
|
return -ENOMEM;
|
||||||
|
|
||||||
|
@ -1028,7 +1027,7 @@ static int m2mtest_probe(struct platform_device *pdev)
|
||||||
|
|
||||||
ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
|
ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
|
||||||
if (ret)
|
if (ret)
|
||||||
goto free_dev;
|
return ret;
|
||||||
|
|
||||||
atomic_set(&dev->num_inst, 0);
|
atomic_set(&dev->num_inst, 0);
|
||||||
mutex_init(&dev->dev_mutex);
|
mutex_init(&dev->dev_mutex);
|
||||||
|
@ -1067,15 +1066,13 @@ static int m2mtest_probe(struct platform_device *pdev)
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
v4l2_m2m_release(dev->m2m_dev);
|
|
||||||
err_m2m:
|
err_m2m:
|
||||||
|
v4l2_m2m_release(dev->m2m_dev);
|
||||||
video_unregister_device(dev->vfd);
|
video_unregister_device(dev->vfd);
|
||||||
rel_vdev:
|
rel_vdev:
|
||||||
video_device_release(vfd);
|
video_device_release(vfd);
|
||||||
unreg_dev:
|
unreg_dev:
|
||||||
v4l2_device_unregister(&dev->v4l2_dev);
|
v4l2_device_unregister(&dev->v4l2_dev);
|
||||||
free_dev:
|
|
||||||
kfree(dev);
|
|
||||||
|
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
@ -1090,7 +1087,6 @@ static int m2mtest_remove(struct platform_device *pdev)
|
||||||
del_timer_sync(&dev->timer);
|
del_timer_sync(&dev->timer);
|
||||||
video_unregister_device(dev->vfd);
|
video_unregister_device(dev->vfd);
|
||||||
v4l2_device_unregister(&dev->v4l2_dev);
|
v4l2_device_unregister(&dev->v4l2_dev);
|
||||||
kfree(dev);
|
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
|
@ -27,13 +27,13 @@
|
||||||
#ifndef OMAP3_ISP_REG_H
|
#ifndef OMAP3_ISP_REG_H
|
||||||
#define OMAP3_ISP_REG_H
|
#define OMAP3_ISP_REG_H
|
||||||
|
|
||||||
#include <plat/omap34xx.h>
|
|
||||||
|
|
||||||
|
|
||||||
#define CM_CAM_MCLK_HZ 172800000 /* Hz */
|
#define CM_CAM_MCLK_HZ 172800000 /* Hz */
|
||||||
|
|
||||||
/* ISP Submodules offset */
|
/* ISP Submodules offset */
|
||||||
|
|
||||||
|
#define L4_34XX_BASE 0x48000000
|
||||||
|
#define OMAP3430_ISP_BASE (L4_34XX_BASE + 0xBC000)
|
||||||
|
|
||||||
#define OMAP3ISP_REG_BASE OMAP3430_ISP_BASE
|
#define OMAP3ISP_REG_BASE OMAP3430_ISP_BASE
|
||||||
#define OMAP3ISP_REG(offset) (OMAP3ISP_REG_BASE + (offset))
|
#define OMAP3ISP_REG(offset) (OMAP3ISP_REG_BASE + (offset))
|
||||||
|
|
||||||
|
|
|
@ -177,7 +177,9 @@ static int fimc_capture_config_update(struct fimc_ctx *ctx)
|
||||||
|
|
||||||
void fimc_capture_irq_handler(struct fimc_dev *fimc, int deq_buf)
|
void fimc_capture_irq_handler(struct fimc_dev *fimc, int deq_buf)
|
||||||
{
|
{
|
||||||
|
struct v4l2_subdev *csis = fimc->pipeline.subdevs[IDX_CSIS];
|
||||||
struct fimc_vid_cap *cap = &fimc->vid_cap;
|
struct fimc_vid_cap *cap = &fimc->vid_cap;
|
||||||
|
struct fimc_frame *f = &cap->ctx->d_frame;
|
||||||
struct fimc_vid_buffer *v_buf;
|
struct fimc_vid_buffer *v_buf;
|
||||||
struct timeval *tv;
|
struct timeval *tv;
|
||||||
struct timespec ts;
|
struct timespec ts;
|
||||||
|
@ -216,6 +218,25 @@ void fimc_capture_irq_handler(struct fimc_dev *fimc, int deq_buf)
|
||||||
if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
|
if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
|
||||||
cap->buf_index = 0;
|
cap->buf_index = 0;
|
||||||
}
|
}
|
||||||
|
/*
|
||||||
|
* Set up a buffer at MIPI-CSIS if current image format
|
||||||
|
* requires the frame embedded data capture.
|
||||||
|
*/
|
||||||
|
if (f->fmt->mdataplanes && !list_empty(&cap->active_buf_q)) {
|
||||||
|
unsigned int plane = ffs(f->fmt->mdataplanes) - 1;
|
||||||
|
unsigned int size = f->payload[plane];
|
||||||
|
s32 index = fimc_hw_get_frame_index(fimc);
|
||||||
|
void *vaddr;
|
||||||
|
|
||||||
|
list_for_each_entry(v_buf, &cap->active_buf_q, list) {
|
||||||
|
if (v_buf->index != index)
|
||||||
|
continue;
|
||||||
|
vaddr = vb2_plane_vaddr(&v_buf->vb, plane);
|
||||||
|
v4l2_subdev_call(csis, video, s_rx_buffer,
|
||||||
|
vaddr, &size);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
if (cap->active_buf_cnt == 0) {
|
if (cap->active_buf_cnt == 0) {
|
||||||
if (deq_buf)
|
if (deq_buf)
|
||||||
|
@ -351,6 +372,8 @@ static int queue_setup(struct vb2_queue *vq, const struct v4l2_format *pfmt,
|
||||||
unsigned int size = (wh * fmt->depth[i]) / 8;
|
unsigned int size = (wh * fmt->depth[i]) / 8;
|
||||||
if (pixm)
|
if (pixm)
|
||||||
sizes[i] = max(size, pixm->plane_fmt[i].sizeimage);
|
sizes[i] = max(size, pixm->plane_fmt[i].sizeimage);
|
||||||
|
else if (fimc_fmt_is_user_defined(fmt->color))
|
||||||
|
sizes[i] = frame->payload[i];
|
||||||
else
|
else
|
||||||
sizes[i] = max_t(u32, size, frame->payload[i]);
|
sizes[i] = max_t(u32, size, frame->payload[i]);
|
||||||
|
|
||||||
|
@ -611,10 +634,10 @@ static struct fimc_fmt *fimc_capture_try_format(struct fimc_ctx *ctx,
|
||||||
u32 mask = FMT_FLAGS_CAM;
|
u32 mask = FMT_FLAGS_CAM;
|
||||||
struct fimc_fmt *ffmt;
|
struct fimc_fmt *ffmt;
|
||||||
|
|
||||||
/* Color conversion from/to JPEG is not supported */
|
/* Conversion from/to JPEG or User Defined format is not supported */
|
||||||
if (code && ctx->s_frame.fmt && pad == FIMC_SD_PAD_SOURCE &&
|
if (code && ctx->s_frame.fmt && pad == FIMC_SD_PAD_SOURCE &&
|
||||||
fimc_fmt_is_jpeg(ctx->s_frame.fmt->color))
|
fimc_fmt_is_user_defined(ctx->s_frame.fmt->color))
|
||||||
*code = V4L2_MBUS_FMT_JPEG_1X8;
|
*code = ctx->s_frame.fmt->mbus_code;
|
||||||
|
|
||||||
if (fourcc && *fourcc != V4L2_PIX_FMT_JPEG && pad != FIMC_SD_PAD_SINK)
|
if (fourcc && *fourcc != V4L2_PIX_FMT_JPEG && pad != FIMC_SD_PAD_SINK)
|
||||||
mask |= FMT_FLAGS_M2M;
|
mask |= FMT_FLAGS_M2M;
|
||||||
|
@ -628,18 +651,19 @@ static struct fimc_fmt *fimc_capture_try_format(struct fimc_ctx *ctx,
|
||||||
*fourcc = ffmt->fourcc;
|
*fourcc = ffmt->fourcc;
|
||||||
|
|
||||||
if (pad == FIMC_SD_PAD_SINK) {
|
if (pad == FIMC_SD_PAD_SINK) {
|
||||||
max_w = fimc_fmt_is_jpeg(ffmt->color) ?
|
max_w = fimc_fmt_is_user_defined(ffmt->color) ?
|
||||||
pl->scaler_dis_w : pl->scaler_en_w;
|
pl->scaler_dis_w : pl->scaler_en_w;
|
||||||
/* Apply the camera input interface pixel constraints */
|
/* Apply the camera input interface pixel constraints */
|
||||||
v4l_bound_align_image(width, max_t(u32, *width, 32), max_w, 4,
|
v4l_bound_align_image(width, max_t(u32, *width, 32), max_w, 4,
|
||||||
height, max_t(u32, *height, 32),
|
height, max_t(u32, *height, 32),
|
||||||
FIMC_CAMIF_MAX_HEIGHT,
|
FIMC_CAMIF_MAX_HEIGHT,
|
||||||
fimc_fmt_is_jpeg(ffmt->color) ? 3 : 1,
|
fimc_fmt_is_user_defined(ffmt->color) ?
|
||||||
|
3 : 1,
|
||||||
0);
|
0);
|
||||||
return ffmt;
|
return ffmt;
|
||||||
}
|
}
|
||||||
/* Can't scale or crop in transparent (JPEG) transfer mode */
|
/* Can't scale or crop in transparent (JPEG) transfer mode */
|
||||||
if (fimc_fmt_is_jpeg(ffmt->color)) {
|
if (fimc_fmt_is_user_defined(ffmt->color)) {
|
||||||
*width = ctx->s_frame.f_width;
|
*width = ctx->s_frame.f_width;
|
||||||
*height = ctx->s_frame.f_height;
|
*height = ctx->s_frame.f_height;
|
||||||
return ffmt;
|
return ffmt;
|
||||||
|
@ -684,7 +708,7 @@ static void fimc_capture_try_selection(struct fimc_ctx *ctx,
|
||||||
u32 max_sc_h, max_sc_v;
|
u32 max_sc_h, max_sc_v;
|
||||||
|
|
||||||
/* In JPEG transparent transfer mode cropping is not supported */
|
/* In JPEG transparent transfer mode cropping is not supported */
|
||||||
if (fimc_fmt_is_jpeg(ctx->d_frame.fmt->color)) {
|
if (fimc_fmt_is_user_defined(ctx->d_frame.fmt->color)) {
|
||||||
r->width = sink->f_width;
|
r->width = sink->f_width;
|
||||||
r->height = sink->f_height;
|
r->height = sink->f_height;
|
||||||
r->left = r->top = 0;
|
r->left = r->top = 0;
|
||||||
|
@ -847,6 +871,48 @@ static int fimc_pipeline_try_format(struct fimc_ctx *ctx,
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* fimc_get_sensor_frame_desc - query the sensor for media bus frame parameters
|
||||||
|
* @sensor: pointer to the sensor subdev
|
||||||
|
* @plane_fmt: provides plane sizes corresponding to the frame layout entries
|
||||||
|
* @try: true to set the frame parameters, false to query only
|
||||||
|
*
|
||||||
|
* This function is used by this driver only for compressed/blob data formats.
|
||||||
|
*/
|
||||||
|
static int fimc_get_sensor_frame_desc(struct v4l2_subdev *sensor,
|
||||||
|
struct v4l2_plane_pix_format *plane_fmt,
|
||||||
|
unsigned int num_planes, bool try)
|
||||||
|
{
|
||||||
|
struct v4l2_mbus_frame_desc fd;
|
||||||
|
int i, ret;
|
||||||
|
|
||||||
|
for (i = 0; i < num_planes; i++)
|
||||||
|
fd.entry[i].length = plane_fmt[i].sizeimage;
|
||||||
|
|
||||||
|
if (try)
|
||||||
|
ret = v4l2_subdev_call(sensor, pad, set_frame_desc, 0, &fd);
|
||||||
|
else
|
||||||
|
ret = v4l2_subdev_call(sensor, pad, get_frame_desc, 0, &fd);
|
||||||
|
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
if (num_planes != fd.num_entries)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
for (i = 0; i < num_planes; i++)
|
||||||
|
plane_fmt[i].sizeimage = fd.entry[i].length;
|
||||||
|
|
||||||
|
if (fd.entry[0].length > FIMC_MAX_JPEG_BUF_SIZE) {
|
||||||
|
v4l2_err(sensor->v4l2_dev, "Unsupported buffer size: %u\n",
|
||||||
|
fd.entry[0].length);
|
||||||
|
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
static int fimc_cap_g_fmt_mplane(struct file *file, void *fh,
|
static int fimc_cap_g_fmt_mplane(struct file *file, void *fh,
|
||||||
struct v4l2_format *f)
|
struct v4l2_format *f)
|
||||||
{
|
{
|
||||||
|
@ -865,7 +931,7 @@ static int fimc_cap_try_fmt_mplane(struct file *file, void *fh,
|
||||||
struct v4l2_mbus_framefmt mf;
|
struct v4l2_mbus_framefmt mf;
|
||||||
struct fimc_fmt *ffmt = NULL;
|
struct fimc_fmt *ffmt = NULL;
|
||||||
|
|
||||||
if (pix->pixelformat == V4L2_PIX_FMT_JPEG) {
|
if (fimc_jpeg_fourcc(pix->pixelformat)) {
|
||||||
fimc_capture_try_format(ctx, &pix->width, &pix->height,
|
fimc_capture_try_format(ctx, &pix->width, &pix->height,
|
||||||
NULL, &pix->pixelformat,
|
NULL, &pix->pixelformat,
|
||||||
FIMC_SD_PAD_SINK);
|
FIMC_SD_PAD_SINK);
|
||||||
|
@ -879,25 +945,32 @@ static int fimc_cap_try_fmt_mplane(struct file *file, void *fh,
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
||||||
if (!fimc->vid_cap.user_subdev_api) {
|
if (!fimc->vid_cap.user_subdev_api) {
|
||||||
mf.width = pix->width;
|
mf.width = pix->width;
|
||||||
mf.height = pix->height;
|
mf.height = pix->height;
|
||||||
mf.code = ffmt->mbus_code;
|
mf.code = ffmt->mbus_code;
|
||||||
fimc_md_graph_lock(fimc);
|
fimc_md_graph_lock(fimc);
|
||||||
fimc_pipeline_try_format(ctx, &mf, &ffmt, false);
|
fimc_pipeline_try_format(ctx, &mf, &ffmt, false);
|
||||||
fimc_md_graph_unlock(fimc);
|
fimc_md_graph_unlock(fimc);
|
||||||
|
pix->width = mf.width;
|
||||||
pix->width = mf.width;
|
pix->height = mf.height;
|
||||||
pix->height = mf.height;
|
|
||||||
if (ffmt)
|
if (ffmt)
|
||||||
pix->pixelformat = ffmt->fourcc;
|
pix->pixelformat = ffmt->fourcc;
|
||||||
}
|
}
|
||||||
|
|
||||||
fimc_adjust_mplane_format(ffmt, pix->width, pix->height, pix);
|
fimc_adjust_mplane_format(ffmt, pix->width, pix->height, pix);
|
||||||
|
|
||||||
|
if (ffmt->flags & FMT_FLAGS_COMPRESSED)
|
||||||
|
fimc_get_sensor_frame_desc(fimc->pipeline.subdevs[IDX_SENSOR],
|
||||||
|
pix->plane_fmt, ffmt->memplanes, true);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void fimc_capture_mark_jpeg_xfer(struct fimc_ctx *ctx, bool jpeg)
|
static void fimc_capture_mark_jpeg_xfer(struct fimc_ctx *ctx,
|
||||||
|
enum fimc_color_fmt color)
|
||||||
{
|
{
|
||||||
|
bool jpeg = fimc_fmt_is_user_defined(color);
|
||||||
|
|
||||||
ctx->scaler.enabled = !jpeg;
|
ctx->scaler.enabled = !jpeg;
|
||||||
fimc_ctrls_activate(ctx, !jpeg);
|
fimc_ctrls_activate(ctx, !jpeg);
|
||||||
|
|
||||||
|
@ -920,7 +993,7 @@ static int fimc_capture_set_format(struct fimc_dev *fimc, struct v4l2_format *f)
|
||||||
return -EBUSY;
|
return -EBUSY;
|
||||||
|
|
||||||
/* Pre-configure format at camera interface input, for JPEG only */
|
/* Pre-configure format at camera interface input, for JPEG only */
|
||||||
if (pix->pixelformat == V4L2_PIX_FMT_JPEG) {
|
if (fimc_jpeg_fourcc(pix->pixelformat)) {
|
||||||
fimc_capture_try_format(ctx, &pix->width, &pix->height,
|
fimc_capture_try_format(ctx, &pix->width, &pix->height,
|
||||||
NULL, &pix->pixelformat,
|
NULL, &pix->pixelformat,
|
||||||
FIMC_SD_PAD_SINK);
|
FIMC_SD_PAD_SINK);
|
||||||
|
@ -953,7 +1026,16 @@ static int fimc_capture_set_format(struct fimc_dev *fimc, struct v4l2_format *f)
|
||||||
}
|
}
|
||||||
|
|
||||||
fimc_adjust_mplane_format(ff->fmt, pix->width, pix->height, pix);
|
fimc_adjust_mplane_format(ff->fmt, pix->width, pix->height, pix);
|
||||||
for (i = 0; i < ff->fmt->colplanes; i++)
|
|
||||||
|
if (ff->fmt->flags & FMT_FLAGS_COMPRESSED) {
|
||||||
|
ret = fimc_get_sensor_frame_desc(fimc->pipeline.subdevs[IDX_SENSOR],
|
||||||
|
pix->plane_fmt, ff->fmt->memplanes,
|
||||||
|
true);
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
for (i = 0; i < ff->fmt->memplanes; i++)
|
||||||
ff->payload[i] = pix->plane_fmt[i].sizeimage;
|
ff->payload[i] = pix->plane_fmt[i].sizeimage;
|
||||||
|
|
||||||
set_frame_bounds(ff, pix->width, pix->height);
|
set_frame_bounds(ff, pix->width, pix->height);
|
||||||
|
@ -961,7 +1043,7 @@ static int fimc_capture_set_format(struct fimc_dev *fimc, struct v4l2_format *f)
|
||||||
if (!(ctx->state & FIMC_COMPOSE))
|
if (!(ctx->state & FIMC_COMPOSE))
|
||||||
set_frame_crop(ff, 0, 0, pix->width, pix->height);
|
set_frame_crop(ff, 0, 0, pix->width, pix->height);
|
||||||
|
|
||||||
fimc_capture_mark_jpeg_xfer(ctx, fimc_fmt_is_jpeg(ff->fmt->color));
|
fimc_capture_mark_jpeg_xfer(ctx, ff->fmt->color);
|
||||||
|
|
||||||
/* Reset cropping and set format at the camera interface input */
|
/* Reset cropping and set format at the camera interface input */
|
||||||
if (!fimc->vid_cap.user_subdev_api) {
|
if (!fimc->vid_cap.user_subdev_api) {
|
||||||
|
@ -1063,6 +1145,23 @@ static int fimc_pipeline_validate(struct fimc_dev *fimc)
|
||||||
src_fmt.format.height != sink_fmt.format.height ||
|
src_fmt.format.height != sink_fmt.format.height ||
|
||||||
src_fmt.format.code != sink_fmt.format.code)
|
src_fmt.format.code != sink_fmt.format.code)
|
||||||
return -EPIPE;
|
return -EPIPE;
|
||||||
|
|
||||||
|
if (sd == fimc->pipeline.subdevs[IDX_SENSOR] &&
|
||||||
|
fimc_user_defined_mbus_fmt(src_fmt.format.code)) {
|
||||||
|
struct v4l2_plane_pix_format plane_fmt[FIMC_MAX_PLANES];
|
||||||
|
struct fimc_frame *frame = &vid_cap->ctx->d_frame;
|
||||||
|
unsigned int i;
|
||||||
|
|
||||||
|
ret = fimc_get_sensor_frame_desc(sd, plane_fmt,
|
||||||
|
frame->fmt->memplanes,
|
||||||
|
false);
|
||||||
|
if (ret < 0)
|
||||||
|
return -EPIPE;
|
||||||
|
|
||||||
|
for (i = 0; i < frame->fmt->memplanes; i++)
|
||||||
|
if (frame->payload[i] < plane_fmt[i].sizeimage)
|
||||||
|
return -EPIPE;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
@ -1424,7 +1523,7 @@ static int fimc_subdev_set_fmt(struct v4l2_subdev *sd,
|
||||||
/* Update RGB Alpha control state and value range */
|
/* Update RGB Alpha control state and value range */
|
||||||
fimc_alpha_ctrl_update(ctx);
|
fimc_alpha_ctrl_update(ctx);
|
||||||
|
|
||||||
fimc_capture_mark_jpeg_xfer(ctx, fimc_fmt_is_jpeg(ffmt->color));
|
fimc_capture_mark_jpeg_xfer(ctx, ffmt->color);
|
||||||
|
|
||||||
ff = fmt->pad == FIMC_SD_PAD_SINK ?
|
ff = fmt->pad == FIMC_SD_PAD_SINK ?
|
||||||
&ctx->s_frame : &ctx->d_frame;
|
&ctx->s_frame : &ctx->d_frame;
|
||||||
|
|
|
@ -184,7 +184,17 @@ static struct fimc_fmt fimc_formats[] = {
|
||||||
.memplanes = 1,
|
.memplanes = 1,
|
||||||
.colplanes = 1,
|
.colplanes = 1,
|
||||||
.mbus_code = V4L2_MBUS_FMT_JPEG_1X8,
|
.mbus_code = V4L2_MBUS_FMT_JPEG_1X8,
|
||||||
.flags = FMT_FLAGS_CAM,
|
.flags = FMT_FLAGS_CAM | FMT_FLAGS_COMPRESSED,
|
||||||
|
}, {
|
||||||
|
.name = "S5C73MX interleaved UYVY/JPEG",
|
||||||
|
.fourcc = V4L2_PIX_FMT_S5C_UYVY_JPG,
|
||||||
|
.color = FIMC_FMT_YUYV_JPEG,
|
||||||
|
.depth = { 8 },
|
||||||
|
.memplanes = 2,
|
||||||
|
.colplanes = 1,
|
||||||
|
.mdataplanes = 0x2, /* plane 1 holds frame meta data */
|
||||||
|
.mbus_code = V4L2_MBUS_FMT_S5C_UYVY_JPEG_1X8,
|
||||||
|
.flags = FMT_FLAGS_CAM | FMT_FLAGS_COMPRESSED,
|
||||||
},
|
},
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -371,7 +381,7 @@ int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
|
||||||
default:
|
default:
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
}
|
}
|
||||||
} else {
|
} else if (!frame->fmt->mdataplanes) {
|
||||||
if (frame->fmt->memplanes >= 2)
|
if (frame->fmt->memplanes >= 2)
|
||||||
paddr->cb = vb2_dma_contig_plane_dma_addr(vb, 1);
|
paddr->cb = vb2_dma_contig_plane_dma_addr(vb, 1);
|
||||||
|
|
||||||
|
@ -698,6 +708,11 @@ int fimc_fill_format(struct fimc_frame *frame, struct v4l2_format *f)
|
||||||
if (frame->fmt->colplanes == 1) /* packed formats */
|
if (frame->fmt->colplanes == 1) /* packed formats */
|
||||||
bpl = (bpl * frame->fmt->depth[0]) / 8;
|
bpl = (bpl * frame->fmt->depth[0]) / 8;
|
||||||
pixm->plane_fmt[i].bytesperline = bpl;
|
pixm->plane_fmt[i].bytesperline = bpl;
|
||||||
|
|
||||||
|
if (frame->fmt->flags & FMT_FLAGS_COMPRESSED) {
|
||||||
|
pixm->plane_fmt[i].sizeimage = frame->payload[i];
|
||||||
|
continue;
|
||||||
|
}
|
||||||
pixm->plane_fmt[i].sizeimage = (frame->o_width *
|
pixm->plane_fmt[i].sizeimage = (frame->o_width *
|
||||||
frame->o_height * frame->fmt->depth[i]) / 8;
|
frame->o_height * frame->fmt->depth[i]) / 8;
|
||||||
}
|
}
|
||||||
|
|
|
@ -40,6 +40,8 @@
|
||||||
#define SCALER_MAX_VRATIO 64
|
#define SCALER_MAX_VRATIO 64
|
||||||
#define DMA_MIN_SIZE 8
|
#define DMA_MIN_SIZE 8
|
||||||
#define FIMC_CAMIF_MAX_HEIGHT 0x2000
|
#define FIMC_CAMIF_MAX_HEIGHT 0x2000
|
||||||
|
#define FIMC_MAX_JPEG_BUF_SIZE (10 * SZ_1M)
|
||||||
|
#define FIMC_MAX_PLANES 3
|
||||||
|
|
||||||
/* indices to the clocks array */
|
/* indices to the clocks array */
|
||||||
enum {
|
enum {
|
||||||
|
@ -83,7 +85,7 @@ enum fimc_datapath {
|
||||||
};
|
};
|
||||||
|
|
||||||
enum fimc_color_fmt {
|
enum fimc_color_fmt {
|
||||||
FIMC_FMT_RGB444 = 0x10,
|
FIMC_FMT_RGB444 = 0x10,
|
||||||
FIMC_FMT_RGB555,
|
FIMC_FMT_RGB555,
|
||||||
FIMC_FMT_RGB565,
|
FIMC_FMT_RGB565,
|
||||||
FIMC_FMT_RGB666,
|
FIMC_FMT_RGB666,
|
||||||
|
@ -95,14 +97,15 @@ enum fimc_color_fmt {
|
||||||
FIMC_FMT_CBYCRY422,
|
FIMC_FMT_CBYCRY422,
|
||||||
FIMC_FMT_CRYCBY422,
|
FIMC_FMT_CRYCBY422,
|
||||||
FIMC_FMT_YCBCR444_LOCAL,
|
FIMC_FMT_YCBCR444_LOCAL,
|
||||||
FIMC_FMT_JPEG = 0x40,
|
FIMC_FMT_RAW8 = 0x40,
|
||||||
FIMC_FMT_RAW8 = 0x80,
|
|
||||||
FIMC_FMT_RAW10,
|
FIMC_FMT_RAW10,
|
||||||
FIMC_FMT_RAW12,
|
FIMC_FMT_RAW12,
|
||||||
|
FIMC_FMT_JPEG = 0x80,
|
||||||
|
FIMC_FMT_YUYV_JPEG = 0x100,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
#define fimc_fmt_is_user_defined(x) (!!((x) & 0x180))
|
||||||
#define fimc_fmt_is_rgb(x) (!!((x) & 0x10))
|
#define fimc_fmt_is_rgb(x) (!!((x) & 0x10))
|
||||||
#define fimc_fmt_is_jpeg(x) (!!((x) & 0x40))
|
|
||||||
|
|
||||||
#define IS_M2M(__strt) ((__strt) == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE || \
|
#define IS_M2M(__strt) ((__strt) == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE || \
|
||||||
__strt == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
|
__strt == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
|
||||||
|
@ -139,6 +142,7 @@ enum fimc_color_fmt {
|
||||||
* @memplanes: number of physically non-contiguous data planes
|
* @memplanes: number of physically non-contiguous data planes
|
||||||
* @colplanes: number of physically contiguous data planes
|
* @colplanes: number of physically contiguous data planes
|
||||||
* @depth: per plane driver's private 'number of bits per pixel'
|
* @depth: per plane driver's private 'number of bits per pixel'
|
||||||
|
* @mdataplanes: bitmask indicating meta data plane(s), (1 << plane_no)
|
||||||
* @flags: flags indicating which operation mode format applies to
|
* @flags: flags indicating which operation mode format applies to
|
||||||
*/
|
*/
|
||||||
struct fimc_fmt {
|
struct fimc_fmt {
|
||||||
|
@ -149,12 +153,14 @@ struct fimc_fmt {
|
||||||
u16 memplanes;
|
u16 memplanes;
|
||||||
u16 colplanes;
|
u16 colplanes;
|
||||||
u8 depth[VIDEO_MAX_PLANES];
|
u8 depth[VIDEO_MAX_PLANES];
|
||||||
|
u16 mdataplanes;
|
||||||
u16 flags;
|
u16 flags;
|
||||||
#define FMT_FLAGS_CAM (1 << 0)
|
#define FMT_FLAGS_CAM (1 << 0)
|
||||||
#define FMT_FLAGS_M2M_IN (1 << 1)
|
#define FMT_FLAGS_M2M_IN (1 << 1)
|
||||||
#define FMT_FLAGS_M2M_OUT (1 << 2)
|
#define FMT_FLAGS_M2M_OUT (1 << 2)
|
||||||
#define FMT_FLAGS_M2M (1 << 1 | 1 << 2)
|
#define FMT_FLAGS_M2M (1 << 1 | 1 << 2)
|
||||||
#define FMT_HAS_ALPHA (1 << 3)
|
#define FMT_HAS_ALPHA (1 << 3)
|
||||||
|
#define FMT_FLAGS_COMPRESSED (1 << 4)
|
||||||
};
|
};
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -272,7 +278,7 @@ struct fimc_frame {
|
||||||
u32 offs_v;
|
u32 offs_v;
|
||||||
u32 width;
|
u32 width;
|
||||||
u32 height;
|
u32 height;
|
||||||
unsigned long payload[VIDEO_MAX_PLANES];
|
unsigned int payload[VIDEO_MAX_PLANES];
|
||||||
struct fimc_addr paddr;
|
struct fimc_addr paddr;
|
||||||
struct fimc_dma_offset dma_offset;
|
struct fimc_dma_offset dma_offset;
|
||||||
struct fimc_fmt *fmt;
|
struct fimc_fmt *fmt;
|
||||||
|
@ -577,6 +583,18 @@ static inline int tiled_fmt(struct fimc_fmt *fmt)
|
||||||
return fmt->fourcc == V4L2_PIX_FMT_NV12MT;
|
return fmt->fourcc == V4L2_PIX_FMT_NV12MT;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static inline bool fimc_jpeg_fourcc(u32 pixelformat)
|
||||||
|
{
|
||||||
|
return (pixelformat == V4L2_PIX_FMT_JPEG ||
|
||||||
|
pixelformat == V4L2_PIX_FMT_S5C_UYVY_JPG);
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline bool fimc_user_defined_mbus_fmt(u32 code)
|
||||||
|
{
|
||||||
|
return (code == V4L2_MBUS_FMT_JPEG_1X8 ||
|
||||||
|
code == V4L2_MBUS_FMT_S5C_UYVY_JPEG_1X8);
|
||||||
|
}
|
||||||
|
|
||||||
/* Return the alpha component bit mask */
|
/* Return the alpha component bit mask */
|
||||||
static inline int fimc_get_alpha_mask(struct fimc_fmt *fmt)
|
static inline int fimc_get_alpha_mask(struct fimc_fmt *fmt)
|
||||||
{
|
{
|
||||||
|
|
|
@ -551,30 +551,31 @@ static int fimc_m2m_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr)
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int fimc_m2m_s_crop(struct file *file, void *fh, const struct v4l2_crop *cr)
|
static int fimc_m2m_s_crop(struct file *file, void *fh, const struct v4l2_crop *crop)
|
||||||
{
|
{
|
||||||
struct fimc_ctx *ctx = fh_to_ctx(fh);
|
struct fimc_ctx *ctx = fh_to_ctx(fh);
|
||||||
struct fimc_dev *fimc = ctx->fimc_dev;
|
struct fimc_dev *fimc = ctx->fimc_dev;
|
||||||
|
struct v4l2_crop cr = *crop;
|
||||||
struct fimc_frame *f;
|
struct fimc_frame *f;
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
ret = fimc_m2m_try_crop(ctx, cr);
|
ret = fimc_m2m_try_crop(ctx, &cr);
|
||||||
if (ret)
|
if (ret)
|
||||||
return ret;
|
return ret;
|
||||||
|
|
||||||
f = (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ?
|
f = (cr.type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ?
|
||||||
&ctx->s_frame : &ctx->d_frame;
|
&ctx->s_frame : &ctx->d_frame;
|
||||||
|
|
||||||
/* Check to see if scaling ratio is within supported range */
|
/* Check to see if scaling ratio is within supported range */
|
||||||
if (fimc_ctx_state_is_set(FIMC_DST_FMT | FIMC_SRC_FMT, ctx)) {
|
if (fimc_ctx_state_is_set(FIMC_DST_FMT | FIMC_SRC_FMT, ctx)) {
|
||||||
if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
|
if (cr.type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
|
||||||
ret = fimc_check_scaler_ratio(ctx, cr->c.width,
|
ret = fimc_check_scaler_ratio(ctx, cr.c.width,
|
||||||
cr->c.height, ctx->d_frame.width,
|
cr.c.height, ctx->d_frame.width,
|
||||||
ctx->d_frame.height, ctx->rotation);
|
ctx->d_frame.height, ctx->rotation);
|
||||||
} else {
|
} else {
|
||||||
ret = fimc_check_scaler_ratio(ctx, ctx->s_frame.width,
|
ret = fimc_check_scaler_ratio(ctx, ctx->s_frame.width,
|
||||||
ctx->s_frame.height, cr->c.width,
|
ctx->s_frame.height, cr.c.width,
|
||||||
cr->c.height, ctx->rotation);
|
cr.c.height, ctx->rotation);
|
||||||
}
|
}
|
||||||
if (ret) {
|
if (ret) {
|
||||||
v4l2_err(&fimc->m2m.vfd, "Out of scaler range\n");
|
v4l2_err(&fimc->m2m.vfd, "Out of scaler range\n");
|
||||||
|
@ -582,10 +583,10 @@ static int fimc_m2m_s_crop(struct file *file, void *fh, const struct v4l2_crop *
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
f->offs_h = cr->c.left;
|
f->offs_h = cr.c.left;
|
||||||
f->offs_v = cr->c.top;
|
f->offs_v = cr.c.top;
|
||||||
f->width = cr->c.width;
|
f->width = cr.c.width;
|
||||||
f->height = cr->c.height;
|
f->height = cr.c.height;
|
||||||
|
|
||||||
fimc_ctx_state_set(FIMC_PARAMS, ctx);
|
fimc_ctx_state_set(FIMC_PARAMS, ctx);
|
||||||
|
|
||||||
|
|
|
@ -625,7 +625,7 @@ int fimc_hw_set_camera_source(struct fimc_dev *fimc,
|
||||||
cfg |= FIMC_REG_CISRCFMT_ITU601_16BIT;
|
cfg |= FIMC_REG_CISRCFMT_ITU601_16BIT;
|
||||||
} /* else defaults to ITU-R BT.656 8-bit */
|
} /* else defaults to ITU-R BT.656 8-bit */
|
||||||
} else if (cam->bus_type == FIMC_MIPI_CSI2) {
|
} else if (cam->bus_type == FIMC_MIPI_CSI2) {
|
||||||
if (fimc_fmt_is_jpeg(f->fmt->color))
|
if (fimc_fmt_is_user_defined(f->fmt->color))
|
||||||
cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT;
|
cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -680,6 +680,7 @@ int fimc_hw_set_camera_type(struct fimc_dev *fimc,
|
||||||
tmp = FIMC_REG_CSIIMGFMT_YCBCR422_8BIT;
|
tmp = FIMC_REG_CSIIMGFMT_YCBCR422_8BIT;
|
||||||
break;
|
break;
|
||||||
case V4L2_MBUS_FMT_JPEG_1X8:
|
case V4L2_MBUS_FMT_JPEG_1X8:
|
||||||
|
case V4L2_MBUS_FMT_S5C_UYVY_JPEG_1X8:
|
||||||
tmp = FIMC_REG_CSIIMGFMT_USER(1);
|
tmp = FIMC_REG_CSIIMGFMT_USER(1);
|
||||||
cfg |= FIMC_REG_CIGCTRL_CAM_JPEG;
|
cfg |= FIMC_REG_CIGCTRL_CAM_JPEG;
|
||||||
break;
|
break;
|
||||||
|
@ -744,13 +745,13 @@ void fimc_hw_dis_capture(struct fimc_dev *dev)
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Return an index to the buffer actually being written. */
|
/* Return an index to the buffer actually being written. */
|
||||||
u32 fimc_hw_get_frame_index(struct fimc_dev *dev)
|
s32 fimc_hw_get_frame_index(struct fimc_dev *dev)
|
||||||
{
|
{
|
||||||
u32 reg;
|
s32 reg;
|
||||||
|
|
||||||
if (dev->variant->has_cistatus2) {
|
if (dev->variant->has_cistatus2) {
|
||||||
reg = readl(dev->regs + FIMC_REG_CISTATUS2) & 0x3F;
|
reg = readl(dev->regs + FIMC_REG_CISTATUS2) & 0x3f;
|
||||||
return reg > 0 ? --reg : reg;
|
return reg - 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
reg = readl(dev->regs + FIMC_REG_CISTATUS);
|
reg = readl(dev->regs + FIMC_REG_CISTATUS);
|
||||||
|
@ -759,6 +760,18 @@ u32 fimc_hw_get_frame_index(struct fimc_dev *dev)
|
||||||
FIMC_REG_CISTATUS_FRAMECNT_SHIFT;
|
FIMC_REG_CISTATUS_FRAMECNT_SHIFT;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/* Return an index to the buffer being written previously. */
|
||||||
|
s32 fimc_hw_get_prev_frame_index(struct fimc_dev *dev)
|
||||||
|
{
|
||||||
|
s32 reg;
|
||||||
|
|
||||||
|
if (!dev->variant->has_cistatus2)
|
||||||
|
return -1;
|
||||||
|
|
||||||
|
reg = readl(dev->regs + FIMC_REG_CISTATUS2);
|
||||||
|
return ((reg >> 7) & 0x3f) - 1;
|
||||||
|
}
|
||||||
|
|
||||||
/* Locking: the caller holds fimc->slock */
|
/* Locking: the caller holds fimc->slock */
|
||||||
void fimc_activate_capture(struct fimc_ctx *ctx)
|
void fimc_activate_capture(struct fimc_ctx *ctx)
|
||||||
{
|
{
|
||||||
|
|
|
@ -307,7 +307,8 @@ void fimc_hw_clear_irq(struct fimc_dev *dev);
|
||||||
void fimc_hw_enable_scaler(struct fimc_dev *dev, bool on);
|
void fimc_hw_enable_scaler(struct fimc_dev *dev, bool on);
|
||||||
void fimc_hw_activate_input_dma(struct fimc_dev *dev, bool on);
|
void fimc_hw_activate_input_dma(struct fimc_dev *dev, bool on);
|
||||||
void fimc_hw_dis_capture(struct fimc_dev *dev);
|
void fimc_hw_dis_capture(struct fimc_dev *dev);
|
||||||
u32 fimc_hw_get_frame_index(struct fimc_dev *dev);
|
s32 fimc_hw_get_frame_index(struct fimc_dev *dev);
|
||||||
|
s32 fimc_hw_get_prev_frame_index(struct fimc_dev *dev);
|
||||||
void fimc_activate_capture(struct fimc_ctx *ctx);
|
void fimc_activate_capture(struct fimc_ctx *ctx);
|
||||||
void fimc_deactivate_capture(struct fimc_dev *fimc);
|
void fimc_deactivate_capture(struct fimc_dev *fimc);
|
||||||
|
|
||||||
|
|
|
@ -2,7 +2,7 @@
|
||||||
* Samsung S5P/EXYNOS4 SoC series MIPI-CSI receiver driver
|
* Samsung S5P/EXYNOS4 SoC series MIPI-CSI receiver driver
|
||||||
*
|
*
|
||||||
* Copyright (C) 2011 - 2012 Samsung Electronics Co., Ltd.
|
* Copyright (C) 2011 - 2012 Samsung Electronics Co., Ltd.
|
||||||
* Sylwester Nawrocki, <s.nawrocki@samsung.com>
|
* Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||||
*
|
*
|
||||||
* This program is free software; you can redistribute it and/or modify
|
* This program is free software; you can redistribute it and/or modify
|
||||||
* it under the terms of the GNU General Public License version 2 as
|
* it under the terms of the GNU General Public License version 2 as
|
||||||
|
@ -98,6 +98,11 @@ MODULE_PARM_DESC(debug, "Debug level (0-2)");
|
||||||
#define CSIS_MAX_PIX_WIDTH 0xffff
|
#define CSIS_MAX_PIX_WIDTH 0xffff
|
||||||
#define CSIS_MAX_PIX_HEIGHT 0xffff
|
#define CSIS_MAX_PIX_HEIGHT 0xffff
|
||||||
|
|
||||||
|
/* Non-image packet data buffers */
|
||||||
|
#define S5PCSIS_PKTDATA_ODD 0x2000
|
||||||
|
#define S5PCSIS_PKTDATA_EVEN 0x3000
|
||||||
|
#define S5PCSIS_PKTDATA_SIZE SZ_4K
|
||||||
|
|
||||||
enum {
|
enum {
|
||||||
CSIS_CLK_MUX,
|
CSIS_CLK_MUX,
|
||||||
CSIS_CLK_GATE,
|
CSIS_CLK_GATE,
|
||||||
|
@ -110,8 +115,8 @@ static char *csi_clock_name[] = {
|
||||||
#define NUM_CSIS_CLOCKS ARRAY_SIZE(csi_clock_name)
|
#define NUM_CSIS_CLOCKS ARRAY_SIZE(csi_clock_name)
|
||||||
|
|
||||||
static const char * const csis_supply_name[] = {
|
static const char * const csis_supply_name[] = {
|
||||||
"vdd11", /* 1.1V or 1.2V (s5pc100) MIPI CSI suppply */
|
"vddcore", /* CSIS Core (1.0V, 1.1V or 1.2V) suppply */
|
||||||
"vdd18", /* VDD 1.8V and MIPI CSI PLL supply */
|
"vddio", /* CSIS I/O and PLL (1.8V) supply */
|
||||||
};
|
};
|
||||||
#define CSIS_NUM_SUPPLIES ARRAY_SIZE(csis_supply_name)
|
#define CSIS_NUM_SUPPLIES ARRAY_SIZE(csis_supply_name)
|
||||||
|
|
||||||
|
@ -144,12 +149,18 @@ static const struct s5pcsis_event s5pcsis_events[] = {
|
||||||
};
|
};
|
||||||
#define S5PCSIS_NUM_EVENTS ARRAY_SIZE(s5pcsis_events)
|
#define S5PCSIS_NUM_EVENTS ARRAY_SIZE(s5pcsis_events)
|
||||||
|
|
||||||
|
struct csis_pktbuf {
|
||||||
|
u32 *data;
|
||||||
|
unsigned int len;
|
||||||
|
};
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* struct csis_state - the driver's internal state data structure
|
* struct csis_state - the driver's internal state data structure
|
||||||
* @lock: mutex serializing the subdev and power management operations,
|
* @lock: mutex serializing the subdev and power management operations,
|
||||||
* protecting @format and @flags members
|
* protecting @format and @flags members
|
||||||
* @pads: CSIS pads array
|
* @pads: CSIS pads array
|
||||||
* @sd: v4l2_subdev associated with CSIS device instance
|
* @sd: v4l2_subdev associated with CSIS device instance
|
||||||
|
* @index: the hardware instance index
|
||||||
* @pdev: CSIS platform device
|
* @pdev: CSIS platform device
|
||||||
* @regs: mmaped I/O registers memory
|
* @regs: mmaped I/O registers memory
|
||||||
* @supplies: CSIS regulator supplies
|
* @supplies: CSIS regulator supplies
|
||||||
|
@ -159,12 +170,14 @@ static const struct s5pcsis_event s5pcsis_events[] = {
|
||||||
* @csis_fmt: current CSIS pixel format
|
* @csis_fmt: current CSIS pixel format
|
||||||
* @format: common media bus format for the source and sink pad
|
* @format: common media bus format for the source and sink pad
|
||||||
* @slock: spinlock protecting structure members below
|
* @slock: spinlock protecting structure members below
|
||||||
|
* @pkt_buf: the frame embedded (non-image) data buffer
|
||||||
* @events: MIPI-CSIS event (error) counters
|
* @events: MIPI-CSIS event (error) counters
|
||||||
*/
|
*/
|
||||||
struct csis_state {
|
struct csis_state {
|
||||||
struct mutex lock;
|
struct mutex lock;
|
||||||
struct media_pad pads[CSIS_PADS_NUM];
|
struct media_pad pads[CSIS_PADS_NUM];
|
||||||
struct v4l2_subdev sd;
|
struct v4l2_subdev sd;
|
||||||
|
u8 index;
|
||||||
struct platform_device *pdev;
|
struct platform_device *pdev;
|
||||||
void __iomem *regs;
|
void __iomem *regs;
|
||||||
struct regulator_bulk_data supplies[CSIS_NUM_SUPPLIES];
|
struct regulator_bulk_data supplies[CSIS_NUM_SUPPLIES];
|
||||||
|
@ -175,6 +188,7 @@ struct csis_state {
|
||||||
struct v4l2_mbus_framefmt format;
|
struct v4l2_mbus_framefmt format;
|
||||||
|
|
||||||
struct spinlock slock;
|
struct spinlock slock;
|
||||||
|
struct csis_pktbuf pkt_buf;
|
||||||
struct s5pcsis_event events[S5PCSIS_NUM_EVENTS];
|
struct s5pcsis_event events[S5PCSIS_NUM_EVENTS];
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -202,7 +216,11 @@ static const struct csis_pix_format s5pcsis_formats[] = {
|
||||||
.code = V4L2_MBUS_FMT_JPEG_1X8,
|
.code = V4L2_MBUS_FMT_JPEG_1X8,
|
||||||
.fmt_reg = S5PCSIS_CFG_FMT_USER(1),
|
.fmt_reg = S5PCSIS_CFG_FMT_USER(1),
|
||||||
.data_alignment = 32,
|
.data_alignment = 32,
|
||||||
},
|
}, {
|
||||||
|
.code = V4L2_MBUS_FMT_S5C_UYVY_JPEG_1X8,
|
||||||
|
.fmt_reg = S5PCSIS_CFG_FMT_USER(1),
|
||||||
|
.data_alignment = 32,
|
||||||
|
}
|
||||||
};
|
};
|
||||||
|
|
||||||
#define s5pcsis_write(__csis, __r, __v) writel(__v, __csis->regs + __r)
|
#define s5pcsis_write(__csis, __r, __v) writel(__v, __csis->regs + __r)
|
||||||
|
@ -266,7 +284,7 @@ static void __s5pcsis_set_format(struct csis_state *state)
|
||||||
struct v4l2_mbus_framefmt *mf = &state->format;
|
struct v4l2_mbus_framefmt *mf = &state->format;
|
||||||
u32 val;
|
u32 val;
|
||||||
|
|
||||||
v4l2_dbg(1, debug, &state->sd, "fmt: %d, %d x %d\n",
|
v4l2_dbg(1, debug, &state->sd, "fmt: %#x, %d x %d\n",
|
||||||
mf->code, mf->width, mf->height);
|
mf->code, mf->width, mf->height);
|
||||||
|
|
||||||
/* Color format */
|
/* Color format */
|
||||||
|
@ -304,8 +322,10 @@ static void s5pcsis_set_params(struct csis_state *state)
|
||||||
val |= S5PCSIS_CTRL_ALIGN_32BIT;
|
val |= S5PCSIS_CTRL_ALIGN_32BIT;
|
||||||
else /* 24-bits */
|
else /* 24-bits */
|
||||||
val &= ~S5PCSIS_CTRL_ALIGN_32BIT;
|
val &= ~S5PCSIS_CTRL_ALIGN_32BIT;
|
||||||
/* Not using external clock. */
|
|
||||||
val &= ~S5PCSIS_CTRL_WCLK_EXTCLK;
|
val &= ~S5PCSIS_CTRL_WCLK_EXTCLK;
|
||||||
|
if (pdata->wclk_source)
|
||||||
|
val |= S5PCSIS_CTRL_WCLK_EXTCLK;
|
||||||
s5pcsis_write(state, S5PCSIS_CTRL, val);
|
s5pcsis_write(state, S5PCSIS_CTRL, val);
|
||||||
|
|
||||||
/* Update the shadow register. */
|
/* Update the shadow register. */
|
||||||
|
@ -529,6 +549,22 @@ static int s5pcsis_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static int s5pcsis_s_rx_buffer(struct v4l2_subdev *sd, void *buf,
|
||||||
|
unsigned int *size)
|
||||||
|
{
|
||||||
|
struct csis_state *state = sd_to_csis_state(sd);
|
||||||
|
unsigned long flags;
|
||||||
|
|
||||||
|
*size = min_t(unsigned int, *size, S5PCSIS_PKTDATA_SIZE);
|
||||||
|
|
||||||
|
spin_lock_irqsave(&state->slock, flags);
|
||||||
|
state->pkt_buf.data = buf;
|
||||||
|
state->pkt_buf.len = *size;
|
||||||
|
spin_unlock_irqrestore(&state->slock, flags);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
static int s5pcsis_log_status(struct v4l2_subdev *sd)
|
static int s5pcsis_log_status(struct v4l2_subdev *sd)
|
||||||
{
|
{
|
||||||
struct csis_state *state = sd_to_csis_state(sd);
|
struct csis_state *state = sd_to_csis_state(sd);
|
||||||
|
@ -566,6 +602,7 @@ static struct v4l2_subdev_pad_ops s5pcsis_pad_ops = {
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct v4l2_subdev_video_ops s5pcsis_video_ops = {
|
static struct v4l2_subdev_video_ops s5pcsis_video_ops = {
|
||||||
|
.s_rx_buffer = s5pcsis_s_rx_buffer,
|
||||||
.s_stream = s5pcsis_s_stream,
|
.s_stream = s5pcsis_s_stream,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -578,13 +615,26 @@ static struct v4l2_subdev_ops s5pcsis_subdev_ops = {
|
||||||
static irqreturn_t s5pcsis_irq_handler(int irq, void *dev_id)
|
static irqreturn_t s5pcsis_irq_handler(int irq, void *dev_id)
|
||||||
{
|
{
|
||||||
struct csis_state *state = dev_id;
|
struct csis_state *state = dev_id;
|
||||||
|
struct csis_pktbuf *pktbuf = &state->pkt_buf;
|
||||||
unsigned long flags;
|
unsigned long flags;
|
||||||
u32 status;
|
u32 status;
|
||||||
|
|
||||||
status = s5pcsis_read(state, S5PCSIS_INTSRC);
|
status = s5pcsis_read(state, S5PCSIS_INTSRC);
|
||||||
|
|
||||||
spin_lock_irqsave(&state->slock, flags);
|
spin_lock_irqsave(&state->slock, flags);
|
||||||
|
|
||||||
|
if ((status & S5PCSIS_INTSRC_NON_IMAGE_DATA) && pktbuf->data) {
|
||||||
|
u32 offset;
|
||||||
|
|
||||||
|
if (status & S5PCSIS_INTSRC_EVEN)
|
||||||
|
offset = S5PCSIS_PKTDATA_EVEN;
|
||||||
|
else
|
||||||
|
offset = S5PCSIS_PKTDATA_ODD;
|
||||||
|
|
||||||
|
memcpy(pktbuf->data, state->regs + offset, pktbuf->len);
|
||||||
|
pktbuf->data = NULL;
|
||||||
|
rmb();
|
||||||
|
}
|
||||||
|
|
||||||
/* Update the event/error counters */
|
/* Update the event/error counters */
|
||||||
if ((status & S5PCSIS_INTSRC_ERRORS) || debug) {
|
if ((status & S5PCSIS_INTSRC_ERRORS) || debug) {
|
||||||
int i;
|
int i;
|
||||||
|
@ -620,14 +670,15 @@ static int __devinit s5pcsis_probe(struct platform_device *pdev)
|
||||||
spin_lock_init(&state->slock);
|
spin_lock_init(&state->slock);
|
||||||
|
|
||||||
state->pdev = pdev;
|
state->pdev = pdev;
|
||||||
|
state->index = max(0, pdev->id);
|
||||||
|
|
||||||
pdata = pdev->dev.platform_data;
|
pdata = pdev->dev.platform_data;
|
||||||
if (pdata == NULL || pdata->phy_enable == NULL) {
|
if (pdata == NULL) {
|
||||||
dev_err(&pdev->dev, "Platform data not fully specified\n");
|
dev_err(&pdev->dev, "Platform data not fully specified\n");
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
}
|
}
|
||||||
|
|
||||||
if ((pdev->id == 1 && pdata->lanes > CSIS1_MAX_LANES) ||
|
if ((state->index == 1 && pdata->lanes > CSIS1_MAX_LANES) ||
|
||||||
pdata->lanes > CSIS0_MAX_LANES) {
|
pdata->lanes > CSIS0_MAX_LANES) {
|
||||||
dev_err(&pdev->dev, "Unsupported number of data lanes: %d\n",
|
dev_err(&pdev->dev, "Unsupported number of data lanes: %d\n",
|
||||||
pdata->lanes);
|
pdata->lanes);
|
||||||
|
@ -710,7 +761,6 @@ static int __devinit s5pcsis_probe(struct platform_device *pdev)
|
||||||
|
|
||||||
static int s5pcsis_pm_suspend(struct device *dev, bool runtime)
|
static int s5pcsis_pm_suspend(struct device *dev, bool runtime)
|
||||||
{
|
{
|
||||||
struct s5p_platform_mipi_csis *pdata = dev->platform_data;
|
|
||||||
struct platform_device *pdev = to_platform_device(dev);
|
struct platform_device *pdev = to_platform_device(dev);
|
||||||
struct v4l2_subdev *sd = platform_get_drvdata(pdev);
|
struct v4l2_subdev *sd = platform_get_drvdata(pdev);
|
||||||
struct csis_state *state = sd_to_csis_state(sd);
|
struct csis_state *state = sd_to_csis_state(sd);
|
||||||
|
@ -722,7 +772,7 @@ static int s5pcsis_pm_suspend(struct device *dev, bool runtime)
|
||||||
mutex_lock(&state->lock);
|
mutex_lock(&state->lock);
|
||||||
if (state->flags & ST_POWERED) {
|
if (state->flags & ST_POWERED) {
|
||||||
s5pcsis_stop_stream(state);
|
s5pcsis_stop_stream(state);
|
||||||
ret = pdata->phy_enable(state->pdev, false);
|
ret = s5p_csis_phy_enable(state->index, false);
|
||||||
if (ret)
|
if (ret)
|
||||||
goto unlock;
|
goto unlock;
|
||||||
ret = regulator_bulk_disable(CSIS_NUM_SUPPLIES,
|
ret = regulator_bulk_disable(CSIS_NUM_SUPPLIES,
|
||||||
|
@ -741,7 +791,6 @@ static int s5pcsis_pm_suspend(struct device *dev, bool runtime)
|
||||||
|
|
||||||
static int s5pcsis_pm_resume(struct device *dev, bool runtime)
|
static int s5pcsis_pm_resume(struct device *dev, bool runtime)
|
||||||
{
|
{
|
||||||
struct s5p_platform_mipi_csis *pdata = dev->platform_data;
|
|
||||||
struct platform_device *pdev = to_platform_device(dev);
|
struct platform_device *pdev = to_platform_device(dev);
|
||||||
struct v4l2_subdev *sd = platform_get_drvdata(pdev);
|
struct v4l2_subdev *sd = platform_get_drvdata(pdev);
|
||||||
struct csis_state *state = sd_to_csis_state(sd);
|
struct csis_state *state = sd_to_csis_state(sd);
|
||||||
|
@ -759,7 +808,7 @@ static int s5pcsis_pm_resume(struct device *dev, bool runtime)
|
||||||
state->supplies);
|
state->supplies);
|
||||||
if (ret)
|
if (ret)
|
||||||
goto unlock;
|
goto unlock;
|
||||||
ret = pdata->phy_enable(state->pdev, true);
|
ret = s5p_csis_phy_enable(state->index, true);
|
||||||
if (!ret) {
|
if (!ret) {
|
||||||
state->flags |= ST_POWERED;
|
state->flags |= ST_POWERED;
|
||||||
} else {
|
} else {
|
||||||
|
|
|
@ -507,7 +507,7 @@ static int vidioc_g_crop(struct file *file, void *prv, struct v4l2_crop *cr)
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int vidioc_try_crop(struct file *file, void *prv, struct v4l2_crop *cr)
|
static int vidioc_try_crop(struct file *file, void *prv, const struct v4l2_crop *cr)
|
||||||
{
|
{
|
||||||
struct g2d_ctx *ctx = prv;
|
struct g2d_ctx *ctx = prv;
|
||||||
struct g2d_dev *dev = ctx->dev;
|
struct g2d_dev *dev = ctx->dev;
|
||||||
|
|
|
@ -1353,7 +1353,7 @@ static int s5p_jpeg_probe(struct platform_device *pdev)
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
dev_dbg(&pdev->dev, "clock source %p\n", jpeg->clk);
|
dev_dbg(&pdev->dev, "clock source %p\n", jpeg->clk);
|
||||||
clk_enable(jpeg->clk);
|
clk_prepare_enable(jpeg->clk);
|
||||||
|
|
||||||
/* v4l2 device */
|
/* v4l2 device */
|
||||||
ret = v4l2_device_register(&pdev->dev, &jpeg->v4l2_dev);
|
ret = v4l2_device_register(&pdev->dev, &jpeg->v4l2_dev);
|
||||||
|
@ -1460,7 +1460,7 @@ static int s5p_jpeg_probe(struct platform_device *pdev)
|
||||||
v4l2_device_unregister(&jpeg->v4l2_dev);
|
v4l2_device_unregister(&jpeg->v4l2_dev);
|
||||||
|
|
||||||
clk_get_rollback:
|
clk_get_rollback:
|
||||||
clk_disable(jpeg->clk);
|
clk_disable_unprepare(jpeg->clk);
|
||||||
clk_put(jpeg->clk);
|
clk_put(jpeg->clk);
|
||||||
|
|
||||||
return ret;
|
return ret;
|
||||||
|
@ -1480,7 +1480,7 @@ static int s5p_jpeg_remove(struct platform_device *pdev)
|
||||||
v4l2_m2m_release(jpeg->m2m_dev);
|
v4l2_m2m_release(jpeg->m2m_dev);
|
||||||
v4l2_device_unregister(&jpeg->v4l2_dev);
|
v4l2_device_unregister(&jpeg->v4l2_dev);
|
||||||
|
|
||||||
clk_disable(jpeg->clk);
|
clk_disable_unprepare(jpeg->clk);
|
||||||
clk_put(jpeg->clk);
|
clk_put(jpeg->clk);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
|
|
|
@ -1,5 +1,6 @@
|
||||||
obj-$(CONFIG_VIDEO_SAMSUNG_S5P_MFC) := s5p-mfc.o
|
obj-$(CONFIG_VIDEO_SAMSUNG_S5P_MFC) := s5p-mfc.o
|
||||||
s5p-mfc-y += s5p_mfc.o s5p_mfc_intr.o s5p_mfc_opr.o
|
s5p-mfc-y += s5p_mfc.o s5p_mfc_intr.o
|
||||||
s5p-mfc-y += s5p_mfc_dec.o s5p_mfc_enc.o
|
s5p-mfc-y += s5p_mfc_dec.o s5p_mfc_enc.o
|
||||||
s5p-mfc-y += s5p_mfc_ctrl.o s5p_mfc_cmd.o
|
s5p-mfc-y += s5p_mfc_ctrl.o s5p_mfc_pm.o
|
||||||
s5p-mfc-y += s5p_mfc_pm.o s5p_mfc_shm.o
|
s5p-mfc-y += s5p_mfc_opr.o s5p_mfc_opr_v5.o s5p_mfc_opr_v6.o
|
||||||
|
s5p-mfc-y += s5p_mfc_cmd.o s5p_mfc_cmd_v5.o s5p_mfc_cmd_v6.o
|
||||||
|
|
408
drivers/media/platform/s5p-mfc/regs-mfc-v6.h
Normal file
408
drivers/media/platform/s5p-mfc/regs-mfc-v6.h
Normal file
|
@ -0,0 +1,408 @@
|
||||||
|
/*
|
||||||
|
* Register definition file for Samsung MFC V6.x Interface (FIMV) driver
|
||||||
|
*
|
||||||
|
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
|
||||||
|
* http://www.samsung.com/
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License version 2 as
|
||||||
|
* published by the Free Software Foundation.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _REGS_FIMV_V6_H
|
||||||
|
#define _REGS_FIMV_V6_H
|
||||||
|
|
||||||
|
#include <linux/kernel.h>
|
||||||
|
#include <linux/sizes.h>
|
||||||
|
|
||||||
|
#define S5P_FIMV_REG_SIZE_V6 (S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR)
|
||||||
|
#define S5P_FIMV_REG_COUNT_V6 ((S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR) / 4)
|
||||||
|
|
||||||
|
/* Number of bits that the buffer address should be shifted for particular
|
||||||
|
* MFC buffers. */
|
||||||
|
#define S5P_FIMV_MEM_OFFSET_V6 0
|
||||||
|
|
||||||
|
#define S5P_FIMV_START_ADDR_V6 0x0000
|
||||||
|
#define S5P_FIMV_END_ADDR_V6 0xfd80
|
||||||
|
|
||||||
|
#define S5P_FIMV_REG_CLEAR_BEGIN_V6 0xf000
|
||||||
|
#define S5P_FIMV_REG_CLEAR_COUNT_V6 1024
|
||||||
|
|
||||||
|
/* Codec Common Registers */
|
||||||
|
#define S5P_FIMV_RISC_ON_V6 0x0000
|
||||||
|
#define S5P_FIMV_RISC2HOST_INT_V6 0x003C
|
||||||
|
#define S5P_FIMV_HOST2RISC_INT_V6 0x0044
|
||||||
|
#define S5P_FIMV_RISC_BASE_ADDRESS_V6 0x0054
|
||||||
|
|
||||||
|
#define S5P_FIMV_MFC_RESET_V6 0x1070
|
||||||
|
|
||||||
|
#define S5P_FIMV_HOST2RISC_CMD_V6 0x1100
|
||||||
|
#define S5P_FIMV_H2R_CMD_EMPTY_V6 0
|
||||||
|
#define S5P_FIMV_H2R_CMD_SYS_INIT_V6 1
|
||||||
|
#define S5P_FIMV_H2R_CMD_OPEN_INSTANCE_V6 2
|
||||||
|
#define S5P_FIMV_CH_SEQ_HEADER_V6 3
|
||||||
|
#define S5P_FIMV_CH_INIT_BUFS_V6 4
|
||||||
|
#define S5P_FIMV_CH_FRAME_START_V6 5
|
||||||
|
#define S5P_FIMV_H2R_CMD_CLOSE_INSTANCE_V6 6
|
||||||
|
#define S5P_FIMV_H2R_CMD_SLEEP_V6 7
|
||||||
|
#define S5P_FIMV_H2R_CMD_WAKEUP_V6 8
|
||||||
|
#define S5P_FIMV_CH_LAST_FRAME_V6 9
|
||||||
|
#define S5P_FIMV_H2R_CMD_FLUSH_V6 10
|
||||||
|
/* RMVME: REALLOC used? */
|
||||||
|
#define S5P_FIMV_CH_FRAME_START_REALLOC_V6 5
|
||||||
|
|
||||||
|
#define S5P_FIMV_RISC2HOST_CMD_V6 0x1104
|
||||||
|
#define S5P_FIMV_R2H_CMD_EMPTY_V6 0
|
||||||
|
#define S5P_FIMV_R2H_CMD_SYS_INIT_RET_V6 1
|
||||||
|
#define S5P_FIMV_R2H_CMD_OPEN_INSTANCE_RET_V6 2
|
||||||
|
#define S5P_FIMV_R2H_CMD_SEQ_DONE_RET_V6 3
|
||||||
|
#define S5P_FIMV_R2H_CMD_INIT_BUFFERS_RET_V6 4
|
||||||
|
|
||||||
|
#define S5P_FIMV_R2H_CMD_CLOSE_INSTANCE_RET_V6 6
|
||||||
|
#define S5P_FIMV_R2H_CMD_SLEEP_RET_V6 7
|
||||||
|
#define S5P_FIMV_R2H_CMD_WAKEUP_RET_V6 8
|
||||||
|
#define S5P_FIMV_R2H_CMD_COMPLETE_SEQ_RET_V6 9
|
||||||
|
#define S5P_FIMV_R2H_CMD_DPB_FLUSH_RET_V6 10
|
||||||
|
#define S5P_FIMV_R2H_CMD_NAL_ABORT_RET_V6 11
|
||||||
|
#define S5P_FIMV_R2H_CMD_FW_STATUS_RET_V6 12
|
||||||
|
#define S5P_FIMV_R2H_CMD_FRAME_DONE_RET_V6 13
|
||||||
|
#define S5P_FIMV_R2H_CMD_FIELD_DONE_RET_V6 14
|
||||||
|
#define S5P_FIMV_R2H_CMD_SLICE_DONE_RET_V6 15
|
||||||
|
#define S5P_FIMV_R2H_CMD_ENC_BUFFER_FUL_RET_V6 16
|
||||||
|
#define S5P_FIMV_R2H_CMD_ERR_RET_V6 32
|
||||||
|
|
||||||
|
#define S5P_FIMV_FW_VERSION_V6 0xf000
|
||||||
|
|
||||||
|
#define S5P_FIMV_INSTANCE_ID_V6 0xf008
|
||||||
|
#define S5P_FIMV_CODEC_TYPE_V6 0xf00c
|
||||||
|
#define S5P_FIMV_CONTEXT_MEM_ADDR_V6 0xf014
|
||||||
|
#define S5P_FIMV_CONTEXT_MEM_SIZE_V6 0xf018
|
||||||
|
#define S5P_FIMV_PIXEL_FORMAT_V6 0xf020
|
||||||
|
|
||||||
|
#define S5P_FIMV_METADATA_ENABLE_V6 0xf024
|
||||||
|
#define S5P_FIMV_DBG_BUFFER_ADDR_V6 0xf030
|
||||||
|
#define S5P_FIMV_DBG_BUFFER_SIZE_V6 0xf034
|
||||||
|
#define S5P_FIMV_RET_INSTANCE_ID_V6 0xf070
|
||||||
|
|
||||||
|
#define S5P_FIMV_ERROR_CODE_V6 0xf074
|
||||||
|
#define S5P_FIMV_ERR_WARNINGS_START_V6 160
|
||||||
|
#define S5P_FIMV_ERR_DEC_MASK_V6 0xffff
|
||||||
|
#define S5P_FIMV_ERR_DEC_SHIFT_V6 0
|
||||||
|
#define S5P_FIMV_ERR_DSPL_MASK_V6 0xffff0000
|
||||||
|
#define S5P_FIMV_ERR_DSPL_SHIFT_V6 16
|
||||||
|
|
||||||
|
#define S5P_FIMV_DBG_BUFFER_OUTPUT_SIZE_V6 0xf078
|
||||||
|
#define S5P_FIMV_METADATA_STATUS_V6 0xf07C
|
||||||
|
#define S5P_FIMV_METADATA_ADDR_MB_INFO_V6 0xf080
|
||||||
|
#define S5P_FIMV_METADATA_SIZE_MB_INFO_V6 0xf084
|
||||||
|
|
||||||
|
/* Decoder Registers */
|
||||||
|
#define S5P_FIMV_D_CRC_CTRL_V6 0xf0b0
|
||||||
|
#define S5P_FIMV_D_DEC_OPTIONS_V6 0xf0b4
|
||||||
|
#define S5P_FIMV_D_OPT_FMO_ASO_CTRL_MASK_V6 4
|
||||||
|
#define S5P_FIMV_D_OPT_DDELAY_EN_SHIFT_V6 3
|
||||||
|
#define S5P_FIMV_D_OPT_LF_CTRL_SHIFT_V6 1
|
||||||
|
#define S5P_FIMV_D_OPT_LF_CTRL_MASK_V6 0x3
|
||||||
|
#define S5P_FIMV_D_OPT_TILE_MODE_SHIFT_V6 0
|
||||||
|
|
||||||
|
#define S5P_FIMV_D_DISPLAY_DELAY_V6 0xf0b8
|
||||||
|
|
||||||
|
#define S5P_FIMV_D_SET_FRAME_WIDTH_V6 0xf0bc
|
||||||
|
#define S5P_FIMV_D_SET_FRAME_HEIGHT_V6 0xf0c0
|
||||||
|
|
||||||
|
#define S5P_FIMV_D_SEI_ENABLE_V6 0xf0c4
|
||||||
|
|
||||||
|
/* Buffer setting registers */
|
||||||
|
#define S5P_FIMV_D_MIN_NUM_DPB_V6 0xf0f0
|
||||||
|
#define S5P_FIMV_D_MIN_LUMA_DPB_SIZE_V6 0xf0f4
|
||||||
|
#define S5P_FIMV_D_MIN_CHROMA_DPB_SIZE_V6 0xf0f8
|
||||||
|
#define S5P_FIMV_D_MVC_NUM_VIEWS_V6 0xf0fc
|
||||||
|
#define S5P_FIMV_D_MIN_NUM_MV_V6 0xf100
|
||||||
|
#define S5P_FIMV_D_NUM_DPB_V6 0xf130
|
||||||
|
#define S5P_FIMV_D_LUMA_DPB_SIZE_V6 0xf134
|
||||||
|
#define S5P_FIMV_D_CHROMA_DPB_SIZE_V6 0xf138
|
||||||
|
#define S5P_FIMV_D_MV_BUFFER_SIZE_V6 0xf13c
|
||||||
|
|
||||||
|
#define S5P_FIMV_D_LUMA_DPB_V6 0xf140
|
||||||
|
#define S5P_FIMV_D_CHROMA_DPB_V6 0xf240
|
||||||
|
#define S5P_FIMV_D_MV_BUFFER_V6 0xf340
|
||||||
|
|
||||||
|
#define S5P_FIMV_D_SCRATCH_BUFFER_ADDR_V6 0xf440
|
||||||
|
#define S5P_FIMV_D_SCRATCH_BUFFER_SIZE_V6 0xf444
|
||||||
|
#define S5P_FIMV_D_METADATA_BUFFER_ADDR_V6 0xf448
|
||||||
|
#define S5P_FIMV_D_METADATA_BUFFER_SIZE_V6 0xf44c
|
||||||
|
#define S5P_FIMV_D_NUM_MV_V6 0xf478
|
||||||
|
#define S5P_FIMV_D_CPB_BUFFER_ADDR_V6 0xf4b0
|
||||||
|
#define S5P_FIMV_D_CPB_BUFFER_SIZE_V6 0xf4b4
|
||||||
|
|
||||||
|
#define S5P_FIMV_D_AVAILABLE_DPB_FLAG_UPPER_V6 0xf4b8
|
||||||
|
#define S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER_V6 0xf4bc
|
||||||
|
#define S5P_FIMV_D_CPB_BUFFER_OFFSET_V6 0xf4c0
|
||||||
|
#define S5P_FIMV_D_SLICE_IF_ENABLE_V6 0xf4c4
|
||||||
|
#define S5P_FIMV_D_PICTURE_TAG_V6 0xf4c8
|
||||||
|
#define S5P_FIMV_D_STREAM_DATA_SIZE_V6 0xf4d0
|
||||||
|
|
||||||
|
/* Display information register */
|
||||||
|
#define S5P_FIMV_D_DISPLAY_FRAME_WIDTH_V6 0xf500
|
||||||
|
#define S5P_FIMV_D_DISPLAY_FRAME_HEIGHT_V6 0xf504
|
||||||
|
|
||||||
|
/* Display status */
|
||||||
|
#define S5P_FIMV_D_DISPLAY_STATUS_V6 0xf508
|
||||||
|
|
||||||
|
#define S5P_FIMV_D_DISPLAY_LUMA_ADDR_V6 0xf50c
|
||||||
|
#define S5P_FIMV_D_DISPLAY_CHROMA_ADDR_V6 0xf510
|
||||||
|
|
||||||
|
#define S5P_FIMV_D_DISPLAY_FRAME_TYPE_V6 0xf514
|
||||||
|
|
||||||
|
#define S5P_FIMV_D_DISPLAY_CROP_INFO1_V6 0xf518
|
||||||
|
#define S5P_FIMV_D_DISPLAY_CROP_INFO2_V6 0xf51c
|
||||||
|
#define S5P_FIMV_D_DISPLAY_PICTURE_PROFILE_V6 0xf520
|
||||||
|
#define S5P_FIMV_D_DISPLAY_LUMA_CRC_TOP_V6 0xf524
|
||||||
|
#define S5P_FIMV_D_DISPLAY_CHROMA_CRC_TOP_V6 0xf528
|
||||||
|
#define S5P_FIMV_D_DISPLAY_LUMA_CRC_BOT_V6 0xf52c
|
||||||
|
#define S5P_FIMV_D_DISPLAY_CHROMA_CRC_BOT_V6 0xf530
|
||||||
|
#define S5P_FIMV_D_DISPLAY_ASPECT_RATIO_V6 0xf534
|
||||||
|
#define S5P_FIMV_D_DISPLAY_EXTENDED_AR_V6 0xf538
|
||||||
|
|
||||||
|
/* Decoded picture information register */
|
||||||
|
#define S5P_FIMV_D_DECODED_FRAME_WIDTH_V6 0xf53c
|
||||||
|
#define S5P_FIMV_D_DECODED_FRAME_HEIGHT_V6 0xf540
|
||||||
|
#define S5P_FIMV_D_DECODED_STATUS_V6 0xf544
|
||||||
|
#define S5P_FIMV_DEC_CRC_GEN_MASK_V6 0x1
|
||||||
|
#define S5P_FIMV_DEC_CRC_GEN_SHIFT_V6 6
|
||||||
|
|
||||||
|
#define S5P_FIMV_D_DECODED_LUMA_ADDR_V6 0xf548
|
||||||
|
#define S5P_FIMV_D_DECODED_CHROMA_ADDR_V6 0xf54c
|
||||||
|
|
||||||
|
#define S5P_FIMV_D_DECODED_FRAME_TYPE_V6 0xf550
|
||||||
|
#define S5P_FIMV_DECODE_FRAME_MASK_V6 7
|
||||||
|
|
||||||
|
#define S5P_FIMV_D_DECODED_CROP_INFO1_V6 0xf554
|
||||||
|
#define S5P_FIMV_D_DECODED_CROP_INFO2_V6 0xf558
|
||||||
|
#define S5P_FIMV_D_DECODED_PICTURE_PROFILE_V6 0xf55c
|
||||||
|
#define S5P_FIMV_D_DECODED_NAL_SIZE_V6 0xf560
|
||||||
|
#define S5P_FIMV_D_DECODED_LUMA_CRC_TOP_V6 0xf564
|
||||||
|
#define S5P_FIMV_D_DECODED_CHROMA_CRC_TOP_V6 0xf568
|
||||||
|
#define S5P_FIMV_D_DECODED_LUMA_CRC_BOT_V6 0xf56c
|
||||||
|
#define S5P_FIMV_D_DECODED_CHROMA_CRC_BOT_V6 0xf570
|
||||||
|
|
||||||
|
/* Returned value register for specific setting */
|
||||||
|
#define S5P_FIMV_D_RET_PICTURE_TAG_TOP_V6 0xf574
|
||||||
|
#define S5P_FIMV_D_RET_PICTURE_TAG_BOT_V6 0xf578
|
||||||
|
#define S5P_FIMV_D_RET_PICTURE_TIME_TOP_V6 0xf57c
|
||||||
|
#define S5P_FIMV_D_RET_PICTURE_TIME_BOT_V6 0xf580
|
||||||
|
#define S5P_FIMV_D_CHROMA_FORMAT_V6 0xf588
|
||||||
|
#define S5P_FIMV_D_MPEG4_INFO_V6 0xf58c
|
||||||
|
#define S5P_FIMV_D_H264_INFO_V6 0xf590
|
||||||
|
|
||||||
|
#define S5P_FIMV_D_METADATA_ADDR_CONCEALED_MB_V6 0xf594
|
||||||
|
#define S5P_FIMV_D_METADATA_SIZE_CONCEALED_MB_V6 0xf598
|
||||||
|
#define S5P_FIMV_D_METADATA_ADDR_VC1_PARAM_V6 0xf59c
|
||||||
|
#define S5P_FIMV_D_METADATA_SIZE_VC1_PARAM_V6 0xf5a0
|
||||||
|
#define S5P_FIMV_D_METADATA_ADDR_SEI_NAL_V6 0xf5a4
|
||||||
|
#define S5P_FIMV_D_METADATA_SIZE_SEI_NAL_V6 0xf5a8
|
||||||
|
#define S5P_FIMV_D_METADATA_ADDR_VUI_V6 0xf5ac
|
||||||
|
#define S5P_FIMV_D_METADATA_SIZE_VUI_V6 0xf5b0
|
||||||
|
|
||||||
|
#define S5P_FIMV_D_MVC_VIEW_ID_V6 0xf5b4
|
||||||
|
|
||||||
|
/* SEI related information */
|
||||||
|
#define S5P_FIMV_D_FRAME_PACK_SEI_AVAIL_V6 0xf5f0
|
||||||
|
#define S5P_FIMV_D_FRAME_PACK_ARRGMENT_ID_V6 0xf5f4
|
||||||
|
#define S5P_FIMV_D_FRAME_PACK_SEI_INFO_V6 0xf5f8
|
||||||
|
#define S5P_FIMV_D_FRAME_PACK_GRID_POS_V6 0xf5fc
|
||||||
|
|
||||||
|
/* Encoder Registers */
|
||||||
|
#define S5P_FIMV_E_FRAME_WIDTH_V6 0xf770
|
||||||
|
#define S5P_FIMV_E_FRAME_HEIGHT_V6 0xf774
|
||||||
|
#define S5P_FIMV_E_CROPPED_FRAME_WIDTH_V6 0xf778
|
||||||
|
#define S5P_FIMV_E_CROPPED_FRAME_HEIGHT_V6 0xf77c
|
||||||
|
#define S5P_FIMV_E_FRAME_CROP_OFFSET_V6 0xf780
|
||||||
|
#define S5P_FIMV_E_ENC_OPTIONS_V6 0xf784
|
||||||
|
#define S5P_FIMV_E_PICTURE_PROFILE_V6 0xf788
|
||||||
|
#define S5P_FIMV_E_FIXED_PICTURE_QP_V6 0xf790
|
||||||
|
|
||||||
|
#define S5P_FIMV_E_RC_CONFIG_V6 0xf794
|
||||||
|
#define S5P_FIMV_E_RC_QP_BOUND_V6 0xf798
|
||||||
|
#define S5P_FIMV_E_RC_RPARAM_V6 0xf79c
|
||||||
|
#define S5P_FIMV_E_MB_RC_CONFIG_V6 0xf7a0
|
||||||
|
#define S5P_FIMV_E_PADDING_CTRL_V6 0xf7a4
|
||||||
|
#define S5P_FIMV_E_MV_HOR_RANGE_V6 0xf7ac
|
||||||
|
#define S5P_FIMV_E_MV_VER_RANGE_V6 0xf7b0
|
||||||
|
|
||||||
|
#define S5P_FIMV_E_VBV_BUFFER_SIZE_V6 0xf84c
|
||||||
|
#define S5P_FIMV_E_VBV_INIT_DELAY_V6 0xf850
|
||||||
|
#define S5P_FIMV_E_NUM_DPB_V6 0xf890
|
||||||
|
#define S5P_FIMV_E_LUMA_DPB_V6 0xf8c0
|
||||||
|
#define S5P_FIMV_E_CHROMA_DPB_V6 0xf904
|
||||||
|
#define S5P_FIMV_E_ME_BUFFER_V6 0xf948
|
||||||
|
|
||||||
|
#define S5P_FIMV_E_SCRATCH_BUFFER_ADDR_V6 0xf98c
|
||||||
|
#define S5P_FIMV_E_SCRATCH_BUFFER_SIZE_V6 0xf990
|
||||||
|
#define S5P_FIMV_E_TMV_BUFFER0_V6 0xf994
|
||||||
|
#define S5P_FIMV_E_TMV_BUFFER1_V6 0xf998
|
||||||
|
#define S5P_FIMV_E_SOURCE_LUMA_ADDR_V6 0xf9f0
|
||||||
|
#define S5P_FIMV_E_SOURCE_CHROMA_ADDR_V6 0xf9f4
|
||||||
|
#define S5P_FIMV_E_STREAM_BUFFER_ADDR_V6 0xf9f8
|
||||||
|
#define S5P_FIMV_E_STREAM_BUFFER_SIZE_V6 0xf9fc
|
||||||
|
#define S5P_FIMV_E_ROI_BUFFER_ADDR_V6 0xfA00
|
||||||
|
|
||||||
|
#define S5P_FIMV_E_PARAM_CHANGE_V6 0xfa04
|
||||||
|
#define S5P_FIMV_E_IR_SIZE_V6 0xfa08
|
||||||
|
#define S5P_FIMV_E_GOP_CONFIG_V6 0xfa0c
|
||||||
|
#define S5P_FIMV_E_MSLICE_MODE_V6 0xfa10
|
||||||
|
#define S5P_FIMV_E_MSLICE_SIZE_MB_V6 0xfa14
|
||||||
|
#define S5P_FIMV_E_MSLICE_SIZE_BITS_V6 0xfa18
|
||||||
|
#define S5P_FIMV_E_FRAME_INSERTION_V6 0xfa1c
|
||||||
|
|
||||||
|
#define S5P_FIMV_E_RC_FRAME_RATE_V6 0xfa20
|
||||||
|
#define S5P_FIMV_E_RC_BIT_RATE_V6 0xfa24
|
||||||
|
#define S5P_FIMV_E_RC_QP_OFFSET_V6 0xfa28
|
||||||
|
#define S5P_FIMV_E_RC_ROI_CTRL_V6 0xfa2c
|
||||||
|
#define S5P_FIMV_E_PICTURE_TAG_V6 0xfa30
|
||||||
|
#define S5P_FIMV_E_BIT_COUNT_ENABLE_V6 0xfa34
|
||||||
|
#define S5P_FIMV_E_MAX_BIT_COUNT_V6 0xfa38
|
||||||
|
#define S5P_FIMV_E_MIN_BIT_COUNT_V6 0xfa3c
|
||||||
|
|
||||||
|
#define S5P_FIMV_E_METADATA_BUFFER_ADDR_V6 0xfa40
|
||||||
|
#define S5P_FIMV_E_METADATA_BUFFER_SIZE_V6 0xfa44
|
||||||
|
#define S5P_FIMV_E_STREAM_SIZE_V6 0xfa80
|
||||||
|
#define S5P_FIMV_E_SLICE_TYPE_V6 0xfa84
|
||||||
|
#define S5P_FIMV_E_PICTURE_COUNT_V6 0xfa88
|
||||||
|
#define S5P_FIMV_E_RET_PICTURE_TAG_V6 0xfa8c
|
||||||
|
#define S5P_FIMV_E_STREAM_BUFFER_WRITE_POINTER_V6 0xfa90
|
||||||
|
|
||||||
|
#define S5P_FIMV_E_ENCODED_SOURCE_LUMA_ADDR_V6 0xfa94
|
||||||
|
#define S5P_FIMV_E_ENCODED_SOURCE_CHROMA_ADDR_V6 0xfa98
|
||||||
|
#define S5P_FIMV_E_RECON_LUMA_DPB_ADDR_V6 0xfa9c
|
||||||
|
#define S5P_FIMV_E_RECON_CHROMA_DPB_ADDR_V6 0xfaa0
|
||||||
|
#define S5P_FIMV_E_METADATA_ADDR_ENC_SLICE_V6 0xfaa4
|
||||||
|
#define S5P_FIMV_E_METADATA_SIZE_ENC_SLICE_V6 0xfaa8
|
||||||
|
|
||||||
|
#define S5P_FIMV_E_MPEG4_OPTIONS_V6 0xfb10
|
||||||
|
#define S5P_FIMV_E_MPEG4_HEC_PERIOD_V6 0xfb14
|
||||||
|
#define S5P_FIMV_E_ASPECT_RATIO_V6 0xfb50
|
||||||
|
#define S5P_FIMV_E_EXTENDED_SAR_V6 0xfb54
|
||||||
|
|
||||||
|
#define S5P_FIMV_E_H264_OPTIONS_V6 0xfb58
|
||||||
|
#define S5P_FIMV_E_H264_LF_ALPHA_OFFSET_V6 0xfb5c
|
||||||
|
#define S5P_FIMV_E_H264_LF_BETA_OFFSET_V6 0xfb60
|
||||||
|
#define S5P_FIMV_E_H264_I_PERIOD_V6 0xfb64
|
||||||
|
|
||||||
|
#define S5P_FIMV_E_H264_FMO_SLICE_GRP_MAP_TYPE_V6 0xfb68
|
||||||
|
#define S5P_FIMV_E_H264_FMO_NUM_SLICE_GRP_MINUS1_V6 0xfb6c
|
||||||
|
#define S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_DIR_V6 0xfb70
|
||||||
|
#define S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_RATE_MINUS1_V6 0xfb74
|
||||||
|
#define S5P_FIMV_E_H264_FMO_RUN_LENGTH_MINUS1_0_V6 0xfb78
|
||||||
|
#define S5P_FIMV_E_H264_FMO_RUN_LENGTH_MINUS1_1_V6 0xfb7c
|
||||||
|
#define S5P_FIMV_E_H264_FMO_RUN_LENGTH_MINUS1_2_V6 0xfb80
|
||||||
|
#define S5P_FIMV_E_H264_FMO_RUN_LENGTH_MINUS1_3_V6 0xfb84
|
||||||
|
|
||||||
|
#define S5P_FIMV_E_H264_ASO_SLICE_ORDER_0_V6 0xfb88
|
||||||
|
#define S5P_FIMV_E_H264_ASO_SLICE_ORDER_1_V6 0xfb8c
|
||||||
|
#define S5P_FIMV_E_H264_ASO_SLICE_ORDER_2_V6 0xfb90
|
||||||
|
#define S5P_FIMV_E_H264_ASO_SLICE_ORDER_3_V6 0xfb94
|
||||||
|
#define S5P_FIMV_E_H264_ASO_SLICE_ORDER_4_V6 0xfb98
|
||||||
|
#define S5P_FIMV_E_H264_ASO_SLICE_ORDER_5_V6 0xfb9c
|
||||||
|
#define S5P_FIMV_E_H264_ASO_SLICE_ORDER_6_V6 0xfba0
|
||||||
|
#define S5P_FIMV_E_H264_ASO_SLICE_ORDER_7_V6 0xfba4
|
||||||
|
|
||||||
|
#define S5P_FIMV_E_H264_CHROMA_QP_OFFSET_V6 0xfba8
|
||||||
|
#define S5P_FIMV_E_H264_NUM_T_LAYER_V6 0xfbac
|
||||||
|
|
||||||
|
#define S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER0_V6 0xfbb0
|
||||||
|
#define S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER1_V6 0xfbb4
|
||||||
|
#define S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER2_V6 0xfbb8
|
||||||
|
#define S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER3_V6 0xfbbc
|
||||||
|
#define S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER4_V6 0xfbc0
|
||||||
|
#define S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER5_V6 0xfbc4
|
||||||
|
#define S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER6_V6 0xfbc8
|
||||||
|
|
||||||
|
#define S5P_FIMV_E_H264_FRAME_PACKING_SEI_INFO_V6 0xfc4c
|
||||||
|
#define S5P_FIMV_ENC_FP_ARRANGEMENT_TYPE_SIDE_BY_SIDE_V6 0
|
||||||
|
#define S5P_FIMV_ENC_FP_ARRANGEMENT_TYPE_TOP_BOTTOM_V6 1
|
||||||
|
#define S5P_FIMV_ENC_FP_ARRANGEMENT_TYPE_TEMPORAL_V6 2
|
||||||
|
|
||||||
|
#define S5P_FIMV_E_MVC_FRAME_QP_VIEW1_V6 0xfd40
|
||||||
|
#define S5P_FIMV_E_MVC_RC_FRAME_RATE_VIEW1_V6 0xfd44
|
||||||
|
#define S5P_FIMV_E_MVC_RC_BIT_RATE_VIEW1_V6 0xfd48
|
||||||
|
#define S5P_FIMV_E_MVC_RC_QBOUND_VIEW1_V6 0xfd4c
|
||||||
|
#define S5P_FIMV_E_MVC_RC_RPARA_VIEW1_V6 0xfd50
|
||||||
|
#define S5P_FIMV_E_MVC_INTER_VIEW_PREDICTION_ON_V6 0xfd80
|
||||||
|
|
||||||
|
/* Codec numbers */
|
||||||
|
#define S5P_FIMV_CODEC_NONE_V6 -1
|
||||||
|
|
||||||
|
|
||||||
|
#define S5P_FIMV_CODEC_H264_DEC_V6 0
|
||||||
|
#define S5P_FIMV_CODEC_H264_MVC_DEC_V6 1
|
||||||
|
|
||||||
|
#define S5P_FIMV_CODEC_MPEG4_DEC_V6 3
|
||||||
|
#define S5P_FIMV_CODEC_FIMV1_DEC_V6 4
|
||||||
|
#define S5P_FIMV_CODEC_FIMV2_DEC_V6 5
|
||||||
|
#define S5P_FIMV_CODEC_FIMV3_DEC_V6 6
|
||||||
|
#define S5P_FIMV_CODEC_FIMV4_DEC_V6 7
|
||||||
|
#define S5P_FIMV_CODEC_H263_DEC_V6 8
|
||||||
|
#define S5P_FIMV_CODEC_VC1RCV_DEC_V6 9
|
||||||
|
#define S5P_FIMV_CODEC_VC1_DEC_V6 10
|
||||||
|
/* FIXME: Add 11~12 */
|
||||||
|
#define S5P_FIMV_CODEC_MPEG2_DEC_V6 13
|
||||||
|
#define S5P_FIMV_CODEC_VP8_DEC_V6 14
|
||||||
|
/* FIXME: Add 15~16 */
|
||||||
|
#define S5P_FIMV_CODEC_H264_ENC_V6 20
|
||||||
|
#define S5P_FIMV_CODEC_H264_MVC_ENC_V6 21
|
||||||
|
|
||||||
|
#define S5P_FIMV_CODEC_MPEG4_ENC_V6 23
|
||||||
|
#define S5P_FIMV_CODEC_H263_ENC_V6 24
|
||||||
|
|
||||||
|
#define S5P_FIMV_NV12M_HALIGN_V6 16
|
||||||
|
#define S5P_FIMV_NV12MT_HALIGN_V6 16
|
||||||
|
#define S5P_FIMV_NV12MT_VALIGN_V6 16
|
||||||
|
|
||||||
|
#define S5P_FIMV_TMV_BUFFER_ALIGN_V6 16
|
||||||
|
#define S5P_FIMV_LUMA_DPB_BUFFER_ALIGN_V6 256
|
||||||
|
#define S5P_FIMV_CHROMA_DPB_BUFFER_ALIGN_V6 256
|
||||||
|
#define S5P_FIMV_ME_BUFFER_ALIGN_V6 256
|
||||||
|
#define S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6 256
|
||||||
|
|
||||||
|
#define S5P_FIMV_LUMA_MB_TO_PIXEL_V6 256
|
||||||
|
#define S5P_FIMV_CHROMA_MB_TO_PIXEL_V6 128
|
||||||
|
#define S5P_FIMV_NUM_TMV_BUFFERS_V6 2
|
||||||
|
|
||||||
|
#define S5P_FIMV_MAX_FRAME_SIZE_V6 (2 * SZ_1M)
|
||||||
|
#define S5P_FIMV_NUM_PIXELS_IN_MB_ROW_V6 16
|
||||||
|
#define S5P_FIMV_NUM_PIXELS_IN_MB_COL_V6 16
|
||||||
|
|
||||||
|
/* Buffer size requirements defined by hardware */
|
||||||
|
#define S5P_FIMV_TMV_BUFFER_SIZE_V6(w, h) (((w) + 1) * ((h) + 1) * 8)
|
||||||
|
#define S5P_FIMV_ME_BUFFER_SIZE_V6(imw, imh, mbw, mbh) \
|
||||||
|
((DIV_ROUND_UP(imw, 64) * DIV_ROUND_UP(imh, 64) * 256) + \
|
||||||
|
(DIV_ROUND_UP((mbw) * (mbh), 32) * 16))
|
||||||
|
#define S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V6(w, h) (((w) * 192) + 64)
|
||||||
|
#define S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_DEC_V6(w, h) \
|
||||||
|
((w) * ((h) * 64 + 144) + (2048/16 * (h) * 64) + \
|
||||||
|
(2048/16 * 256 + 8320))
|
||||||
|
#define S5P_FIMV_SCRATCH_BUF_SIZE_VC1_DEC_V6(w, h) \
|
||||||
|
(2096 * ((w) + (h) + 1))
|
||||||
|
#define S5P_FIMV_SCRATCH_BUF_SIZE_H263_DEC_V6(w, h) ((w) * 400)
|
||||||
|
#define S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V6(w, h) \
|
||||||
|
((w) * 32 + (h) * 128 + (((w) + 1) / 2) * 64 + 2112)
|
||||||
|
#define S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V6(w, h) \
|
||||||
|
(((w) * 64) + (((w) + 1) * 16) + (4096 * 16))
|
||||||
|
#define S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_ENC_V6(w, h) \
|
||||||
|
(((w) * 16) + (((w) + 1) * 16))
|
||||||
|
|
||||||
|
/* MFC Context buffer sizes */
|
||||||
|
#define MFC_CTX_BUF_SIZE_V6 (28 * SZ_1K) /* 28KB */
|
||||||
|
#define MFC_H264_DEC_CTX_BUF_SIZE_V6 (2 * SZ_1M) /* 2MB */
|
||||||
|
#define MFC_OTHER_DEC_CTX_BUF_SIZE_V6 (20 * SZ_1K) /* 20KB */
|
||||||
|
#define MFC_H264_ENC_CTX_BUF_SIZE_V6 (100 * SZ_1K) /* 100KB */
|
||||||
|
#define MFC_OTHER_ENC_CTX_BUF_SIZE_V6 (12 * SZ_1K) /* 12KB */
|
||||||
|
|
||||||
|
/* MFCv6 variant defines */
|
||||||
|
#define MAX_FW_SIZE_V6 (SZ_1M) /* 1MB */
|
||||||
|
#define MAX_CPB_SIZE_V6 (3 * SZ_1M) /* 3MB */
|
||||||
|
#define MFC_VERSION_V6 0x61
|
||||||
|
#define MFC_NUM_PORTS_V6 1
|
||||||
|
|
||||||
|
#endif /* _REGS_FIMV_V6_H */
|
|
@ -12,6 +12,9 @@
|
||||||
#ifndef _REGS_FIMV_H
|
#ifndef _REGS_FIMV_H
|
||||||
#define _REGS_FIMV_H
|
#define _REGS_FIMV_H
|
||||||
|
|
||||||
|
#include <linux/kernel.h>
|
||||||
|
#include <linux/sizes.h>
|
||||||
|
|
||||||
#define S5P_FIMV_REG_SIZE (S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR)
|
#define S5P_FIMV_REG_SIZE (S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR)
|
||||||
#define S5P_FIMV_REG_COUNT ((S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR) / 4)
|
#define S5P_FIMV_REG_COUNT ((S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR) / 4)
|
||||||
|
|
||||||
|
@ -144,6 +147,7 @@
|
||||||
#define S5P_FIMV_ENC_PROFILE_H264_MAIN 0
|
#define S5P_FIMV_ENC_PROFILE_H264_MAIN 0
|
||||||
#define S5P_FIMV_ENC_PROFILE_H264_HIGH 1
|
#define S5P_FIMV_ENC_PROFILE_H264_HIGH 1
|
||||||
#define S5P_FIMV_ENC_PROFILE_H264_BASELINE 2
|
#define S5P_FIMV_ENC_PROFILE_H264_BASELINE 2
|
||||||
|
#define S5P_FIMV_ENC_PROFILE_H264_CONSTRAINED_BASELINE 3
|
||||||
#define S5P_FIMV_ENC_PROFILE_MPEG4_SIMPLE 0
|
#define S5P_FIMV_ENC_PROFILE_MPEG4_SIMPLE 0
|
||||||
#define S5P_FIMV_ENC_PROFILE_MPEG4_ADVANCED_SIMPLE 1
|
#define S5P_FIMV_ENC_PROFILE_MPEG4_ADVANCED_SIMPLE 1
|
||||||
#define S5P_FIMV_ENC_PIC_STRUCT 0x083c /* picture field/frame flag */
|
#define S5P_FIMV_ENC_PIC_STRUCT 0x083c /* picture field/frame flag */
|
||||||
|
@ -213,6 +217,7 @@
|
||||||
#define S5P_FIMV_DEC_STATUS_RESOLUTION_MASK (3<<4)
|
#define S5P_FIMV_DEC_STATUS_RESOLUTION_MASK (3<<4)
|
||||||
#define S5P_FIMV_DEC_STATUS_RESOLUTION_INC (1<<4)
|
#define S5P_FIMV_DEC_STATUS_RESOLUTION_INC (1<<4)
|
||||||
#define S5P_FIMV_DEC_STATUS_RESOLUTION_DEC (2<<4)
|
#define S5P_FIMV_DEC_STATUS_RESOLUTION_DEC (2<<4)
|
||||||
|
#define S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT 4
|
||||||
|
|
||||||
/* Decode frame address */
|
/* Decode frame address */
|
||||||
#define S5P_FIMV_DECODE_Y_ADR 0x2024
|
#define S5P_FIMV_DECODE_Y_ADR 0x2024
|
||||||
|
@ -377,6 +382,16 @@
|
||||||
#define S5P_FIMV_R2H_CMD_EDFU_INIT_RET 16
|
#define S5P_FIMV_R2H_CMD_EDFU_INIT_RET 16
|
||||||
#define S5P_FIMV_R2H_CMD_ERR_RET 32
|
#define S5P_FIMV_R2H_CMD_ERR_RET 32
|
||||||
|
|
||||||
|
/* Dummy definition for MFCv6 compatibilty */
|
||||||
|
#define S5P_FIMV_CODEC_H264_MVC_DEC -1
|
||||||
|
#define S5P_FIMV_R2H_CMD_FIELD_DONE_RET -1
|
||||||
|
#define S5P_FIMV_MFC_RESET -1
|
||||||
|
#define S5P_FIMV_RISC_ON -1
|
||||||
|
#define S5P_FIMV_RISC_BASE_ADDRESS -1
|
||||||
|
#define S5P_FIMV_CODEC_VP8_DEC -1
|
||||||
|
#define S5P_FIMV_REG_CLEAR_BEGIN 0
|
||||||
|
#define S5P_FIMV_REG_CLEAR_COUNT 0
|
||||||
|
|
||||||
/* Error handling defines */
|
/* Error handling defines */
|
||||||
#define S5P_FIMV_ERR_WARNINGS_START 145
|
#define S5P_FIMV_ERR_WARNINGS_START 145
|
||||||
#define S5P_FIMV_ERR_DEC_MASK 0xFFFF
|
#define S5P_FIMV_ERR_DEC_MASK 0xFFFF
|
||||||
|
@ -414,5 +429,31 @@
|
||||||
#define S5P_FIMV_SHARED_EXTENDED_SAR 0x0078
|
#define S5P_FIMV_SHARED_EXTENDED_SAR 0x0078
|
||||||
#define S5P_FIMV_SHARED_H264_I_PERIOD 0x009C
|
#define S5P_FIMV_SHARED_H264_I_PERIOD 0x009C
|
||||||
#define S5P_FIMV_SHARED_RC_CONTROL_CONFIG 0x00A0
|
#define S5P_FIMV_SHARED_RC_CONTROL_CONFIG 0x00A0
|
||||||
|
#define S5P_FIMV_SHARED_DISP_FRAME_TYPE_SHIFT 2
|
||||||
|
|
||||||
|
/* Offset used by the hardware to store addresses */
|
||||||
|
#define MFC_OFFSET_SHIFT 11
|
||||||
|
|
||||||
|
#define FIRMWARE_ALIGN (128 * SZ_1K) /* 128KB */
|
||||||
|
#define MFC_H264_CTX_BUF_SIZE (600 * SZ_1K) /* 600KB per H264 instance */
|
||||||
|
#define MFC_CTX_BUF_SIZE (10 * SZ_1K) /* 10KB per instance */
|
||||||
|
#define DESC_BUF_SIZE (128 * SZ_1K) /* 128KB for DESC buffer */
|
||||||
|
#define SHARED_BUF_SIZE (8 * SZ_1K) /* 8KB for shared buffer */
|
||||||
|
|
||||||
|
#define DEF_CPB_SIZE (256 * SZ_1K) /* 256KB */
|
||||||
|
#define MAX_CPB_SIZE (4 * SZ_1M) /* 4MB */
|
||||||
|
#define MAX_FW_SIZE (384 * SZ_1K)
|
||||||
|
|
||||||
|
#define MFC_VERSION 0x51
|
||||||
|
#define MFC_NUM_PORTS 2
|
||||||
|
|
||||||
|
#define S5P_FIMV_SHARED_FRAME_PACK_SEI_AVAIL 0x16C
|
||||||
|
#define S5P_FIMV_SHARED_FRAME_PACK_ARRGMENT_ID 0x170
|
||||||
|
#define S5P_FIMV_SHARED_FRAME_PACK_SEI_INFO 0x174
|
||||||
|
#define S5P_FIMV_SHARED_FRAME_PACK_GRID_POS 0x178
|
||||||
|
|
||||||
|
/* Values for resolution change in display status */
|
||||||
|
#define S5P_FIMV_RES_INCREASE 1
|
||||||
|
#define S5P_FIMV_RES_DECREASE 2
|
||||||
|
|
||||||
#endif /* _REGS_FIMV_H */
|
#endif /* _REGS_FIMV_H */
|
||||||
|
|
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Reference in a new issue