mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-29 04:09:39 +00:00
Qualcomm ARM64 DeviceTree updates for v5.17
This introduces initial support for the brand new Snapdragon 8 Gen 1, aka SM8450 platform, with SMP, CPUfreq, cluster idling, low speed buses, TLMM pinctrl, SMMU, regulators, clocks, power-domains, UFS storage and USB currently supported. SDM845 adds new support for Sony Xperia XZ2, XZ2C and XZ3. The Lenovo Yoga C630 gains a few audio related fixes. The PMIC's VADC channels are described as thermal zones. OnePlus devices gains msm-id and board-id, to facilitate a single firmware image for the multiple devices. On SM8350 the Sony Xperia 1 III and 5 III, as well as initial description of Microsoft's Surface Duo 2 are introduced. On the platform side, LLCC, QUP nodes, redistributor stride and all the low-speed QUPs are added MSM8996 gained various regulator fixes, and adsp firmware name to faciliate pushing firmware to linux-firmware. Xiaomi Mi Note 2 gained touchkey controller definition. On SDM660 the Xiaomi Redmi Note 7 gained power and volume keys, RPM and regulator definitions, USB, eMMC and SD-card and a simple-framebuffer description. MSM8916 has the mmc aliases corrected, to stop the storage devices to move around and the RPM sleep stats memory is described. Support for the Samsung J5 2015 smartphone is introduced. SM6350 validation errors are fixed and and description of the audio, compute and modem remoteprocs are added. A couple new revisions of the SC7180 based Google devices are added. The SC7280 platform gains venus and a few fixes. The CRD development device is introduced, with the EC, touchscreen and touchpad. On SM8250 CPU opp-tables, for scaling L3 cache and DDR frequency based on CPU frequency, are added. As is TX, RX macros and SoundWire blocks and used to enable audio on the SM8350 MTP. -----BEGIN PGP SIGNATURE----- iQJPBAABCAA5FiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmHDQQobHGJqb3JuLmFu ZGVyc3NvbkBsaW5hcm8ub3JnAAoJEAsfOT8Nma3FzJAQANU2GokY9/BRKTNJjZFj CIvSBWpBD6wAzqdWqIJBRSbhWDO58Oyu1qRMOw5iylKCqkb89vbcKorpwq6/8l7j Sttox8iRtd/N5GqgwwFB109DSWs6TqRd4rnbYd9au3c21RSLYYgLa1v9f6OobdZi vbY6DQBTHYYClLPYvn5iUMy6JGTFsR5EAjcEJj0cZ1178tKP0Do38Hldeo/wvX37 oqA1GXG3uCtbYKG+gJcNSfwvOo9q0ki5oacGuUWVOWkL+Vj2LiMbhhzDJlu8tF8M VzAy3o6UN2+hquJVxQsfs5wfgcLVK/IdMyjiaEe5GZd9SWmtSt4n+CUQ0ZkDPBfR KkIOci4M0WoHlmY/IPELS9MfDxdDeJn+u8v8jpM/vEZMOSCZiBFcvNPPD7aBP9VK c+f8eVf21NGxfZ4zA9bkp9aBACyv4zfjo/iFd3TmT1P78sDOJMI7pG3APHOYY9Fc ZKT9uTcca9KgVzTZcLzvD69OudrHP9pw6QdT4OT1fy/EPtj2+9hHN+cfty+iAtDN sgIcFmWBryO6OctgF+CA/FuojYi6PB2WOfvECljnmQwfIxDnz/6EGbbG97yH0FZr TE4BasLkdQZZPrTxgj1kpu++CrkFeUhpsEciQjDxYoCJ3mFAXNws6prxKpTh1jcg dalfKkiEX1ww3WsfciUb0X/V =/hGD -----END PGP SIGNATURE----- Merge tag 'qcom-arm64-for-5.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt Qualcomm ARM64 DeviceTree updates for v5.17 This introduces initial support for the brand new Snapdragon 8 Gen 1, aka SM8450 platform, with SMP, CPUfreq, cluster idling, low speed buses, TLMM pinctrl, SMMU, regulators, clocks, power-domains, UFS storage and USB currently supported. SDM845 adds new support for Sony Xperia XZ2, XZ2C and XZ3. The Lenovo Yoga C630 gains a few audio related fixes. The PMIC's VADC channels are described as thermal zones. OnePlus devices gains msm-id and board-id, to facilitate a single firmware image for the multiple devices. On SM8350 the Sony Xperia 1 III and 5 III, as well as initial description of Microsoft's Surface Duo 2 are introduced. On the platform side, LLCC, QUP nodes, redistributor stride and all the low-speed QUPs are added MSM8996 gained various regulator fixes, and adsp firmware name to faciliate pushing firmware to linux-firmware. Xiaomi Mi Note 2 gained touchkey controller definition. On SDM660 the Xiaomi Redmi Note 7 gained power and volume keys, RPM and regulator definitions, USB, eMMC and SD-card and a simple-framebuffer description. MSM8916 has the mmc aliases corrected, to stop the storage devices to move around and the RPM sleep stats memory is described. Support for the Samsung J5 2015 smartphone is introduced. SM6350 validation errors are fixed and and description of the audio, compute and modem remoteprocs are added. A couple new revisions of the SC7180 based Google devices are added. The SC7280 platform gains venus and a few fixes. The CRD development device is introduced, with the EC, touchscreen and touchpad. On SM8250 CPU opp-tables, for scaling L3 cache and DDR frequency based on CPU frequency, are added. As is TX, RX macros and SoundWire blocks and used to enable audio on the SM8350 MTP. * tag 'qcom-arm64-for-5.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (92 commits) arm64: dts: qcom: sm6125: Avoid using missing SM6125_VDDCX arm64: dts: qcom: sm8450-qrd: Enable USB nodes arm64: dts: qcom: sm8450: Add usb nodes arm64: dts: qcom: sm8450: add i2c13 and i2c14 device nodes arm64: dts: qcom: sm8450: add cpufreq support arm64: dts: qcom: sm8450: Add rpmhpd node arm64: dts: qcom: sm8450-qrd: enable ufs nodes arm64: dts: qcom: sm8450: add ufs nodes arm64: dts: qcom: sm8450-qrd: Add rpmh regulator nodes arm64: dts: qcom: Add base SM8450 QRD DTS arm64: dts: qcom: sm8450: add smmu nodes arm64: dts: qcom: sm8450: Add reserved memory nodes arm64: dts: qcom: sm8450: Add tlmm nodes arm64: dts: qcom: Add base SM8450 DTSI arm64: dts: qcom: ipq6018: Fix gpio-ranges property arm64: dts: qcom: sdm845: add QFPROM chipset specific compatible arm64: dts: qcom: sdm845: mtp: Add vadc channels and thermal zones arm64: dts: qcom: pm8998: Add ADC Thermal Monitor node arm64: qcom: dts: drop legacy property #stream-id-cells Revert "arm64: dts: qcom: sm8350: Specify clock-frequency for arch timer" ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
c03b7ba969
82 changed files with 6157 additions and 114 deletions
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@ -202,8 +202,10 @@ properties:
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- items:
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- enum:
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- qcom,sc7280-crd
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- qcom,sc7280-idp
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- qcom,sc7280-idp2
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- google,hoglin
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- google,piglin
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- google,senor
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- const: qcom,sc7280
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85
Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml
Normal file
85
Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml
Normal file
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@ -0,0 +1,85 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8450.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Global Clock & Reset Controller Binding for SM8450
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maintainers:
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- Vinod Koul <vkoul@kernel.org>
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description: |
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Qualcomm global clock control module which supports the clocks, resets and
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power domains on SM8450
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See also:
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- dt-bindings/clock/qcom,gcc-sm8450.h
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properties:
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compatible:
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const: qcom,gcc-sm8450
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clocks:
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items:
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- description: Board XO source
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- description: Sleep clock source
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- description: PCIE 0 Pipe clock source (Optional clock)
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- description: PCIE 1 Pipe clock source (Optional clock)
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- description: PCIE 1 Phy Auxillary clock source (Optional clock)
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- description: UFS Phy Rx symbol 0 clock source (Optional clock)
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- description: UFS Phy Rx symbol 1 clock source (Optional clock)
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- description: UFS Phy Tx symbol 0 clock source (Optional clock)
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- description: USB3 Phy wrapper pipe clock source (Optional clock)
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minItems: 2
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clock-names:
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items:
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- const: bi_tcxo
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- const: sleep_clk
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- const: pcie_0_pipe_clk # Optional clock
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- const: pcie_1_pipe_clk # Optional clock
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- const: pcie_1_phy_aux_clk # Optional clock
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- const: ufs_phy_rx_symbol_0_clk # Optional clock
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- const: ufs_phy_rx_symbol_1_clk # Optional clock
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- const: ufs_phy_tx_symbol_0_clk # Optional clock
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- const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock
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minItems: 2
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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clock-controller@100000 {
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compatible = "qcom,gcc-sm8450";
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reg = <0x00100000 0x001f4200>;
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clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
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clock-names = "bi_tcxo", "sleep_clk";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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@ -15,6 +15,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8910.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a3u-eur.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a5u-eur.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-j5.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-serranove.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb
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@ -57,6 +58,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r3.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r3-lte.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r2.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r3.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r4.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r0.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-kb.dtb
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@ -64,9 +66,14 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-lte.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r3.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r3-kb.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r3-lte.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r9.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r9-kb.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r9-lte.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-r4.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-r9.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r4.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r5.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r9.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r1.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r1-lte.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r2.dtb
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@ -78,6 +85,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp2.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7280-crd.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-ganges-kirin.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-discovery.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-pioneer.dtb
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@ -91,6 +99,9 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm845-oneplus-enchilada.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm845-oneplus-fajita.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-akari.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-akatsuki.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-apollo.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb
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@ -106,4 +117,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx203.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx206.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sm8350-hdk.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sm8350-microsoft-surface-duo2.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sm8350-mtp.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx214.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx215.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sm8450-qrd.dtb
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@ -166,6 +166,7 @@ bluetooth {
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&adsp_pil {
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status = "okay";
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firmware-name = "qcom/apq8096/adsp.mbn";
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};
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&blsp2_i2c1 {
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@ -232,6 +233,7 @@ &hdmi_phy {
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&hsusb_phy1 {
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status = "okay";
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vdd-supply = <&vreg_l28a_0p925>;
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vdda-pll-supply = <&vreg_l12a_1p8>;
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vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
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};
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@ -239,6 +241,7 @@ &hsusb_phy1 {
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&hsusb_phy2 {
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status = "okay";
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vdd-supply = <&vreg_l28a_0p925>;
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vdda-pll-supply = <&vreg_l12a_1p8>;
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vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
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};
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@ -632,6 +635,8 @@ &pm8994_mpps {
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&pm8994_spmi_regulators {
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qcom,saw-reg = <&saw3>;
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vdd_s11-supply = <&vph_pwr>;
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s9 {
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qcom,saw-slave;
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};
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@ -640,6 +645,7 @@ s10 {
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};
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s11 {
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qcom,saw-leader;
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regulator-name = "VDD_APCC";
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regulator-always-on;
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regulator-min-microvolt = <980000>;
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regulator-max-microvolt = <980000>;
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@ -672,6 +678,8 @@ pinconf {
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};
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&pmi8994_spmi_regulators {
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vdd_s2-supply = <&vph_pwr>;
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vdd_gfx: s2@1700 {
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reg = <0x1700 0x100>;
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regulator-name = "VDD_GFX";
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@ -709,7 +717,7 @@ pm8994-regulators {
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vdd_l17_l29-supply = <&vph_pwr_bbyp>;
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vdd_l20_l21-supply = <&vph_pwr_bbyp>;
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vdd_l25-supply = <&vreg_s3a_1p3>;
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vdd_lvs1_lvs2-supply = <&vreg_s4a_1p8>;
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vdd_lvs1_2-supply = <&vreg_s4a_1p8>;
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vreg_s3a_1p3: s3 {
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regulator-name = "vreg_s3a_1p3";
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|
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@ -220,7 +220,7 @@ tlmm: pinctrl@1000000 {
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&tlmm 0 80>;
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gpio-ranges = <&tlmm 0 0 80>;
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interrupt-controller;
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#interrupt-cells = <2>;
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|
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@ -230,6 +230,18 @@ pcie_phy1: phy@8e200 {
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};
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};
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mdio: mdio@90000 {
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compatible = "qcom,ipq4019-mdio";
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reg = <0x00090000 0x64>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&gcc GCC_MDIO_AHB_CLK>;
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clock-names = "gcc_mdio_ahb_clk";
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status = "disabled";
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};
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prng: rng@e3000 {
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compatible = "qcom,prng-ee";
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reg = <0x000e3000 0x1000>;
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209
arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts
Normal file
209
arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts
Normal file
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@ -0,0 +1,209 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/dts-v1/;
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#include "msm8916-pm8916.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Samsung Galaxy J5 (2015)";
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compatible = "samsung,j5", "qcom,msm8916";
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chassis-type = "handset";
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aliases {
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serial0 = &blsp1_uart2;
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};
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chosen {
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stdout-path = "serial0";
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
/* Additional memory used by Samsung firmware modifications */
|
||||
tz-apps@85500000 {
|
||||
reg = <0x0 0x85500000 0x0 0xb00000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gpio_keys_default>;
|
||||
|
||||
label = "GPIO Buttons";
|
||||
|
||||
volume-up {
|
||||
label = "Volume Up";
|
||||
gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
};
|
||||
|
||||
home-key {
|
||||
lable = "Home Key";
|
||||
gpios = <&msmgpio 109 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_HOMEPAGE>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pm8916_resin {
|
||||
status = "okay";
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
};
|
||||
|
||||
/* FIXME: Replace with SM5703 MUIC when driver is available */
|
||||
&pm8916_usbin {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pronto {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhc_1 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
|
||||
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;
|
||||
};
|
||||
|
||||
&sdhc_2 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
|
||||
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
|
||||
|
||||
cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&usb {
|
||||
status = "okay";
|
||||
dr_mode = "peripheral";
|
||||
extcon = <&pm8916_usbin>;
|
||||
};
|
||||
|
||||
&usb_hs_phy {
|
||||
extcon = <&pm8916_usbin>;
|
||||
qcom,init-seq = /bits/ 8 <0x1 0x19 0x2 0x0b>;
|
||||
};
|
||||
|
||||
&smd_rpm_regulators {
|
||||
vdd_l1_l2_l3-supply = <&pm8916_s3>;
|
||||
vdd_l4_l5_l6-supply = <&pm8916_s4>;
|
||||
vdd_l7-supply = <&pm8916_s4>;
|
||||
|
||||
s3 {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
};
|
||||
|
||||
s4 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2100000>;
|
||||
};
|
||||
|
||||
l1 {
|
||||
regulator-min-microvolt = <1225000>;
|
||||
regulator-max-microvolt = <1225000>;
|
||||
};
|
||||
|
||||
l2 {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
};
|
||||
|
||||
l4 {
|
||||
regulator-min-microvolt = <2050000>;
|
||||
regulator-max-microvolt = <2050000>;
|
||||
};
|
||||
|
||||
l5 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
l6 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
l7 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
l8 {
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2900000>;
|
||||
};
|
||||
|
||||
l9 {
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
l10 {
|
||||
regulator-min-microvolt = <2700000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
};
|
||||
|
||||
l11 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2950000>;
|
||||
regulator-allow-set-load;
|
||||
regulator-system-load = <200000>;
|
||||
};
|
||||
|
||||
l12 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2950000>;
|
||||
};
|
||||
|
||||
l13 {
|
||||
regulator-min-microvolt = <3075000>;
|
||||
regulator-max-microvolt = <3075000>;
|
||||
};
|
||||
|
||||
l14 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
l15 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
l16 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
l17 {
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
};
|
||||
|
||||
l18 {
|
||||
regulator-min-microvolt = <2700000>;
|
||||
regulator-max-microvolt = <2700000>;
|
||||
};
|
||||
};
|
||||
|
||||
&msmgpio {
|
||||
gpio_keys_default: gpio-keys-default {
|
||||
pins = "gpio107", "gpio109";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
|
@ -23,6 +23,7 @@
|
|||
/ {
|
||||
model = "Samsung Galaxy S4 Mini Value Edition";
|
||||
compatible = "samsung,serranove", "qcom,msm8916";
|
||||
chassis-type = "handset";
|
||||
|
||||
aliases {
|
||||
serial0 = &blsp1_uart2;
|
||||
|
|
|
|||
|
|
@ -19,8 +19,8 @@ / {
|
|||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
|
||||
sdhc2 = &sdhc_2; /* SDC2 SD card slot */
|
||||
mmc0 = &sdhc_1; /* SDC1 eMMC slot */
|
||||
mmc1 = &sdhc_2; /* SDC2 SD card slot */
|
||||
};
|
||||
|
||||
chosen { };
|
||||
|
|
@ -453,6 +453,11 @@ rpm_msg_ram: sram@60000 {
|
|||
reg = <0x00060000 0x8000>;
|
||||
};
|
||||
|
||||
sram@290000 {
|
||||
compatible = "qcom,msm8916-rpm-stats";
|
||||
reg = <0x00290000 0x10000>;
|
||||
};
|
||||
|
||||
bimc: interconnect@400000 {
|
||||
compatible = "qcom,msm8916-bimc";
|
||||
reg = <0x00400000 0x62000>;
|
||||
|
|
|
|||
|
|
@ -42,7 +42,6 @@ framebuffer0: framebuffer@3404000 {
|
|||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
input-name = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
autorepeat;
|
||||
|
|
|
|||
|
|
@ -62,7 +62,6 @@ divclk4: divclk4 {
|
|||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
input-name = "gpio-keys";
|
||||
autorepeat;
|
||||
|
||||
volupkey {
|
||||
|
|
|
|||
|
|
@ -29,7 +29,6 @@ / {
|
|||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
input-name = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
autorepeat;
|
||||
|
|
@ -223,7 +222,7 @@ pm8994_regulators: pm8994-regulators {
|
|||
vdd_l17_l29-supply = <&pmi8994_bby>;
|
||||
vdd_l20_l21-supply = <&pmi8994_bby>;
|
||||
vdd_l25-supply = <&pm8994_s3>;
|
||||
vdd_lvs1_lvs2-supply = <&pm8994_s4>;
|
||||
vdd_lvs1_2-supply = <&pm8994_s4>;
|
||||
|
||||
/* S1, S2, S6 and S12 are managed by RPMPD */
|
||||
|
||||
|
|
|
|||
|
|
@ -184,6 +184,7 @@ &camera2_rst {
|
|||
&hsusb_phy1 {
|
||||
status = "okay";
|
||||
|
||||
vdd-supply = <&pm8994_l28>;
|
||||
vdda-pll-supply = <&pm8994_l12>;
|
||||
vdda-phy-dpdm-supply = <&pm8994_l24>;
|
||||
};
|
||||
|
|
@ -589,9 +590,27 @@ pmi-gpio10-nc {
|
|||
};
|
||||
};
|
||||
|
||||
&pmi8994_spmi_regulators {
|
||||
&pm8994_spmi_regulators {
|
||||
qcom,saw-reg = <&saw3>;
|
||||
|
||||
pm8994_s9: s9 {
|
||||
qcom,saw-slave;
|
||||
};
|
||||
|
||||
pm8994_s10: s10 {
|
||||
qcom,saw-slave;
|
||||
};
|
||||
|
||||
pm8994_s11: s11 {
|
||||
qcom,saw-leader;
|
||||
regulator-name = "vdd_apcc";
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <470000>;
|
||||
regulator-max-microvolt = <1140000>;
|
||||
};
|
||||
};
|
||||
|
||||
&pmi8994_spmi_regulators {
|
||||
vdd_gfx:
|
||||
pmi8994_s2: s2 {
|
||||
/* Pinned to a high value for now to avoid random crashes. */
|
||||
|
|
@ -600,21 +619,6 @@ pmi8994_s2: s2 {
|
|||
regulator-name = "vdd_gfx";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
pmi8994_s9: s9 {
|
||||
qcom,saw-slave;
|
||||
};
|
||||
|
||||
pmi8994_s10: s10 {
|
||||
qcom,saw-slave;
|
||||
};
|
||||
|
||||
pmi8994_s11: s11 {
|
||||
qcom,saw-leader;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <470000>;
|
||||
regulator-max-microvolt = <1140000>;
|
||||
};
|
||||
};
|
||||
|
||||
&pmi8994_wled {
|
||||
|
|
|
|||
|
|
@ -207,8 +207,8 @@ &blsp2_i2c3 {
|
|||
status = "okay";
|
||||
label = "TYPEC_I2C";
|
||||
|
||||
typec: tusb320@47 {
|
||||
compatible = "ti,tusb320";
|
||||
typec: tusb320l@47 {
|
||||
compatible = "ti,tusb320l";
|
||||
reg = <0x47>;
|
||||
interrupt-parent = <&tlmm>;
|
||||
interrupts = <63 IRQ_TYPE_EDGE_RISING>;
|
||||
|
|
|
|||
|
|
@ -60,6 +60,20 @@ &adsp_pil {
|
|||
};
|
||||
|
||||
&blsp2_i2c6 {
|
||||
touchkey: touchkey@28 {
|
||||
compatible = "cypress,sf3155";
|
||||
reg = <0x28>;
|
||||
interrupt-parent = <&tlmm>;
|
||||
interrupts = <77 IRQ_TYPE_EDGE_FALLING>;
|
||||
avdd-supply = <&vreg_l6a_1p8>;
|
||||
vdd-supply = <&vdd_3v2_tp>;
|
||||
linux,keycodes = <KEY_BACK KEY_MENU>;
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&touchkey_default>;
|
||||
pinctrl-1 = <&touchkey_sleep>;
|
||||
};
|
||||
|
||||
touchscreen: atmel-mxt-ts@4a {
|
||||
compatible = "atmel,maxtouch";
|
||||
reg = <0x4a>;
|
||||
|
|
@ -416,6 +430,20 @@ &tlmm {
|
|||
"RFFE1_DATA", /* GPIO_148 */
|
||||
"RFFE1_CLK"; /* GPIO_149 */
|
||||
|
||||
touchkey_default: touchkey_default {
|
||||
pins = "gpio77";
|
||||
function = "gpio";
|
||||
drive-strength = <16>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
touchkey_sleep: touchkey_sleep {
|
||||
pins = "gpio77";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
touchscreen_default: touchscreen_default {
|
||||
pins = "gpio75", "gpio125";
|
||||
function = "gpio";
|
||||
|
|
|
|||
|
|
@ -962,7 +962,6 @@ hdmi_phy: hdmi-phy@9a0600 {
|
|||
|
||||
gpu: gpu@b00000 {
|
||||
compatible = "qcom,adreno-530.2", "qcom,adreno";
|
||||
#stream-id-cells = <16>;
|
||||
|
||||
reg = <0x00b00000 0x3f000>;
|
||||
reg-names = "kgsl_3d0_reg_memory";
|
||||
|
|
@ -987,9 +986,6 @@ gpu: gpu@b00000 {
|
|||
nvmem-cells = <&speedbin_efuse>;
|
||||
nvmem-cell-names = "speed_bin";
|
||||
|
||||
qcom,gpu-quirk-two-pass-use-wfi;
|
||||
qcom,gpu-quirk-fault-detect-mask;
|
||||
|
||||
operating-points-v2 = <&gpu_opp_table>;
|
||||
|
||||
status = "disabled";
|
||||
|
|
|
|||
|
|
@ -102,6 +102,7 @@ pm8005_s1: s1 { /* VDD_GFX supply */
|
|||
&qusb2phy {
|
||||
status = "okay";
|
||||
|
||||
vdd-supply = <&vreg_l1a_0p875>;
|
||||
vdda-pll-supply = <&vreg_l12a_1p8>;
|
||||
vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -29,7 +29,6 @@ extcon_usb: extcon-usb {
|
|||
|
||||
gpio-hall-sensors {
|
||||
compatible = "gpio-keys";
|
||||
input-name = "hall-sensors";
|
||||
label = "Hall sensors";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hall_sensor1_default>;
|
||||
|
|
@ -46,7 +45,6 @@ hall-sensor1 {
|
|||
|
||||
gpio-kb-extra-keys {
|
||||
compatible = "gpio-keys";
|
||||
input-name = "extra-kb-keys";
|
||||
label = "Keyboard extra keys";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gpio_kb_pins_extra>;
|
||||
|
|
@ -102,7 +100,6 @@ alt {
|
|||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
input-name = "side-buttons";
|
||||
label = "Side buttons";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -260,6 +260,7 @@ pinconf {
|
|||
&qusb2phy {
|
||||
status = "okay";
|
||||
|
||||
vdd-supply = <&vreg_l1a_0p875>;
|
||||
vdda-pll-supply = <&vreg_l12a_1p8>;
|
||||
vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -93,7 +93,6 @@ vph_pwr: vph-pwr-regulator {
|
|||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
input-name = "gpio-keys";
|
||||
label = "Side buttons";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vol_down_pin_a>, <&cam_focus_pin_a>,
|
||||
|
|
@ -126,7 +125,6 @@ camera-focus {
|
|||
|
||||
gpio-hall-sensor {
|
||||
compatible = "gpio-keys";
|
||||
input-name = "hall-sensors";
|
||||
label = "Hall sensors";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hall_sensor0_default>;
|
||||
|
|
|
|||
|
|
@ -1446,7 +1446,6 @@ adreno_gpu: gpu@5000000 {
|
|||
iommus = <&adreno_smmu 0>;
|
||||
operating-points-v2 = <&gpu_opp_table>;
|
||||
power-domains = <&rpmpd MSM8998_VDDMX>;
|
||||
#stream-id-cells = <16>;
|
||||
status = "disabled";
|
||||
|
||||
gpu_opp_table: opp-table {
|
||||
|
|
|
|||
|
|
@ -54,14 +54,24 @@ pon: pon@800 {
|
|||
mode-bootloader = <0x2>;
|
||||
mode-recovery = <0x1>;
|
||||
|
||||
pwrkey {
|
||||
pon_pwrkey: pwrkey {
|
||||
compatible = "qcom,pm8941-pwrkey";
|
||||
interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
|
||||
debounce = <15625>;
|
||||
bias-pull-up;
|
||||
linux,code = <KEY_POWER>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pon_resin: resin {
|
||||
compatible = "qcom,pm8941-resin";
|
||||
interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
|
||||
debounce = <15625>;
|
||||
bias-pull-up;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
pm660_temp: temp-alarm@2400 {
|
||||
|
|
|
|||
|
|
@ -84,6 +84,16 @@ adc-chan@6 {
|
|||
};
|
||||
};
|
||||
|
||||
pm8998_adc_tm: adc-tm@3400 {
|
||||
compatible = "qcom,spmi-adc-tm-hc";
|
||||
reg = <0x3400>;
|
||||
interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rtc@6000 {
|
||||
compatible = "qcom,pm8941-rtc";
|
||||
reg = <0x6000>, <0x6100>;
|
||||
|
|
|
|||
|
|
@ -19,16 +19,17 @@ pmk8350_pon: pon@1300 {
|
|||
compatible = "qcom,pm8998-pon";
|
||||
reg = <0x1300>;
|
||||
|
||||
pwrkey {
|
||||
pon_pwrkey: pwrkey {
|
||||
compatible = "qcom,pmk8350-pwrkey";
|
||||
interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>;
|
||||
linux,code = <KEY_POWER>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
resin {
|
||||
pon_resin: resin {
|
||||
compatible = "qcom,pmk8350-resin";
|
||||
interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>;
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -7,6 +7,8 @@
|
|||
|
||||
/dts-v1/;
|
||||
|
||||
#include "sc7180.dtsi"
|
||||
#include "sc7180-trogdor-ti-sn65dsi86.dtsi"
|
||||
#include "sc7180-trogdor-homestar.dtsi"
|
||||
|
||||
/ {
|
||||
|
|
|
|||
|
|
@ -7,9 +7,11 @@
|
|||
|
||||
/dts-v1/;
|
||||
|
||||
#include "sc7180.dtsi"
|
||||
#include "sc7180-trogdor-ti-sn65dsi86.dtsi"
|
||||
#include "sc7180-trogdor-homestar.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google Homestar (rev3+)";
|
||||
compatible = "google,homestar", "qcom,sc7180";
|
||||
model = "Google Homestar (rev3)";
|
||||
compatible = "google,homestar-rev3", "qcom,sc7180";
|
||||
};
|
||||
|
|
|
|||
21
arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r4.dts
Normal file
21
arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r4.dts
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Google Homestar board device tree source
|
||||
*
|
||||
* Copyright 2021 Google LLC.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "sc7180.dtsi"
|
||||
#include "sc7180-trogdor-parade-ps8640.dtsi"
|
||||
#include "sc7180-trogdor-homestar.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google Homestar (rev4+)";
|
||||
compatible = "google,homestar", "qcom,sc7180";
|
||||
};
|
||||
|
||||
&pp3300_brij_ps8640 {
|
||||
regulator-enable-ramp-delay = <4000>;
|
||||
};
|
||||
|
|
@ -5,13 +5,10 @@
|
|||
* Copyright 2021 Google LLC.
|
||||
*/
|
||||
|
||||
#include "sc7180.dtsi"
|
||||
|
||||
ap_ec_spi: &spi6 {};
|
||||
ap_h1_spi: &spi0 {};
|
||||
|
||||
#include "sc7180-trogdor.dtsi"
|
||||
#include "sc7180-trogdor-ti-sn65dsi86.dtsi"
|
||||
|
||||
/ {
|
||||
/* BOARD-SPECIFIC TOP LEVEL NODES */
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@
|
|||
* Copyright 2020 Google LLC.
|
||||
*/
|
||||
|
||||
#include "sc7180-trogdor-lazor-limozeen-nots.dts"
|
||||
#include "sc7180-trogdor-lazor-limozeen-nots-r5.dts"
|
||||
|
||||
/ {
|
||||
model = "Google Lazor Limozeen without Touchscreen (rev4)";
|
||||
|
|
|
|||
|
|
@ -0,0 +1,31 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Google Lazor Limozeen board device tree source
|
||||
*
|
||||
* Copyright 2021 Google LLC.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "sc7180.dtsi"
|
||||
#include "sc7180-trogdor-ti-sn65dsi86.dtsi"
|
||||
#include "sc7180-trogdor-lazor.dtsi"
|
||||
#include "sc7180-trogdor-lte-sku.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google Lazor Limozeen without Touchscreen (rev5 - rev8)";
|
||||
/* No sku5 post-rev5 */
|
||||
compatible = "google,lazor-rev5-sku5", "google,lazor-rev5-sku6",
|
||||
"google,lazor-rev6-sku6", "google,lazor-rev7-sku6",
|
||||
"google,lazor-rev8-sku6", "qcom,sc7180";
|
||||
};
|
||||
|
||||
/delete-node/&ap_ts;
|
||||
|
||||
&panel {
|
||||
compatible = "innolux,n116bca-ea1", "innolux,n116bge";
|
||||
};
|
||||
|
||||
&sdhc_2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -2,17 +2,19 @@
|
|||
/*
|
||||
* Google Lazor Limozeen board device tree source
|
||||
*
|
||||
* Copyright 2020 Google LLC.
|
||||
* Copyright 2021 Google LLC.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "sc7180.dtsi"
|
||||
#include "sc7180-trogdor-parade-ps8640.dtsi"
|
||||
#include "sc7180-trogdor-lazor.dtsi"
|
||||
#include "sc7180-trogdor-lte-sku.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google Lazor Limozeen without Touchscreen";
|
||||
compatible = "google,lazor-sku6", "google,lazor-sku5", "qcom,sc7180";
|
||||
model = "Google Lazor Limozeen without Touchscreen (rev9+)";
|
||||
compatible = "google,lazor-sku6", "qcom,sc7180";
|
||||
};
|
||||
|
||||
/delete-node/&ap_ts;
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Google Lazor Limozeen board device tree source
|
||||
*
|
||||
* Copyright 2021 Google LLC.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "sc7180.dtsi"
|
||||
#include "sc7180-trogdor-ti-sn65dsi86.dtsi"
|
||||
#include "sc7180-trogdor-lazor.dtsi"
|
||||
#include "sc7180-trogdor-lte-sku.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google Lazor Limozeen (rev4 - rev8)";
|
||||
compatible = "google,lazor-rev4-sku4", "google,lazor-rev5-sku4",
|
||||
"google,lazor-rev6-sku4", "google,lazor-rev7-sku4",
|
||||
"google,lazor-rev8-sku4", "qcom,sc7180";
|
||||
};
|
||||
|
||||
/delete-node/&ap_ts;
|
||||
|
||||
&ap_ts_pen_1v8 {
|
||||
ap_ts: touchscreen@10 {
|
||||
compatible = "elan,ekth3500";
|
||||
reg = <0x10>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ts_int_l>, <&ts_reset_l>;
|
||||
|
||||
interrupt-parent = <&tlmm>;
|
||||
interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
vcc33-supply = <&pp3300_ts>;
|
||||
|
||||
reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&panel {
|
||||
compatible = "auo,b116xa01";
|
||||
};
|
||||
|
||||
&sdhc_2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -2,16 +2,18 @@
|
|||
/*
|
||||
* Google Lazor Limozeen board device tree source
|
||||
*
|
||||
* Copyright 2020 Google LLC.
|
||||
* Copyright 2021 Google LLC.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "sc7180.dtsi"
|
||||
#include "sc7180-trogdor-parade-ps8640.dtsi"
|
||||
#include "sc7180-trogdor-lazor.dtsi"
|
||||
#include "sc7180-trogdor-lte-sku.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google Lazor Limozeen";
|
||||
model = "Google Lazor Limozeen (rev9+)";
|
||||
compatible = "google,lazor-sku4", "qcom,sc7180";
|
||||
};
|
||||
|
||||
|
|
@ -7,6 +7,8 @@
|
|||
|
||||
/dts-v1/;
|
||||
|
||||
#include "sc7180.dtsi"
|
||||
#include "sc7180-trogdor-ti-sn65dsi86.dtsi"
|
||||
#include "sc7180-trogdor-lazor.dtsi"
|
||||
|
||||
/ {
|
||||
|
|
|
|||
|
|
@ -7,6 +7,8 @@
|
|||
|
||||
/dts-v1/;
|
||||
|
||||
#include "sc7180.dtsi"
|
||||
#include "sc7180-trogdor-ti-sn65dsi86.dtsi"
|
||||
#include "sc7180-trogdor-lazor.dtsi"
|
||||
|
||||
/ {
|
||||
|
|
|
|||
|
|
@ -7,12 +7,17 @@
|
|||
|
||||
/dts-v1/;
|
||||
|
||||
#include "sc7180.dtsi"
|
||||
#include "sc7180-trogdor-ti-sn65dsi86.dtsi"
|
||||
#include "sc7180-trogdor-lazor.dtsi"
|
||||
#include "sc7180-lite.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google Lazor (rev3+) with KB Backlight";
|
||||
compatible = "google,lazor-sku2", "qcom,sc7180";
|
||||
model = "Google Lazor (rev3 - 8) with KB Backlight";
|
||||
compatible = "google,lazor-rev3-sku2", "google,lazor-rev4-sku2",
|
||||
"google,lazor-rev5-sku2", "google,lazor-rev6-sku2",
|
||||
"google,lazor-rev7-sku2", "google,lazor-rev8-sku2",
|
||||
"qcom,sc7180";
|
||||
};
|
||||
|
||||
&keyboard_backlight {
|
||||
|
|
|
|||
|
|
@ -7,12 +7,17 @@
|
|||
|
||||
/dts-v1/;
|
||||
|
||||
#include "sc7180.dtsi"
|
||||
#include "sc7180-trogdor-ti-sn65dsi86.dtsi"
|
||||
#include "sc7180-trogdor-lazor.dtsi"
|
||||
#include "sc7180-trogdor-lte-sku.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google Lazor (rev3+) with LTE";
|
||||
compatible = "google,lazor-sku0", "qcom,sc7180";
|
||||
model = "Google Lazor (rev3 - 8) with LTE";
|
||||
compatible = "google,lazor-rev3-sku0", "google,lazor-rev4-sku0",
|
||||
"google,lazor-rev5-sku0", "google,lazor-rev6-sku0",
|
||||
"google,lazor-rev7-sku0", "google,lazor-rev8-sku0",
|
||||
"qcom,sc7180";
|
||||
};
|
||||
|
||||
&ap_sar_sensor {
|
||||
|
|
|
|||
|
|
@ -7,10 +7,14 @@
|
|||
|
||||
/dts-v1/;
|
||||
|
||||
#include "sc7180.dtsi"
|
||||
#include "sc7180-trogdor-ti-sn65dsi86.dtsi"
|
||||
#include "sc7180-trogdor-lazor.dtsi"
|
||||
#include "sc7180-lite.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google Lazor (rev3+)";
|
||||
compatible = "google,lazor", "qcom,sc7180";
|
||||
model = "Google Lazor (rev3 - 8)";
|
||||
compatible = "google,lazor-rev3", "google,lazor-rev4",
|
||||
"google,lazor-rev5", "google,lazor-rev6", "google,lazor-rev7",
|
||||
"google,lazor-rev8", "qcom,sc7180";
|
||||
};
|
||||
|
|
|
|||
22
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-kb.dts
Normal file
22
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-kb.dts
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Google Lazor board device tree source
|
||||
*
|
||||
* Copyright 2020 Google LLC.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "sc7180.dtsi"
|
||||
#include "sc7180-trogdor-parade-ps8640.dtsi"
|
||||
#include "sc7180-trogdor-lazor.dtsi"
|
||||
#include "sc7180-lite.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google Lazor (rev9+) with KB Backlight";
|
||||
compatible = "google,lazor-sku2", "qcom,sc7180";
|
||||
};
|
||||
|
||||
&keyboard_backlight {
|
||||
status = "okay";
|
||||
};
|
||||
30
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts
Normal file
30
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts
Normal file
|
|
@ -0,0 +1,30 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Google Lazor board device tree source
|
||||
*
|
||||
* Copyright 2021 Google LLC.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "sc7180.dtsi"
|
||||
#include "sc7180-trogdor-parade-ps8640.dtsi"
|
||||
#include "sc7180-trogdor-lazor.dtsi"
|
||||
#include "sc7180-trogdor-lte-sku.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google Lazor (rev9+) with LTE";
|
||||
compatible = "google,lazor-sku0", "qcom,sc7180";
|
||||
};
|
||||
|
||||
&ap_sar_sensor {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ap_sar_sensor_i2c {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&keyboard_backlight {
|
||||
status = "okay";
|
||||
};
|
||||
18
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9.dts
Normal file
18
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9.dts
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Google Lazor board device tree source
|
||||
*
|
||||
* Copyright 2021 Google LLC.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "sc7180.dtsi"
|
||||
#include "sc7180-trogdor-parade-ps8640.dtsi"
|
||||
#include "sc7180-trogdor-lazor.dtsi"
|
||||
#include "sc7180-lite.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google Lazor (rev9+)";
|
||||
compatible = "google,lazor", "qcom,sc7180";
|
||||
};
|
||||
|
|
@ -5,13 +5,10 @@
|
|||
* Copyright 2020 Google LLC.
|
||||
*/
|
||||
|
||||
#include "sc7180.dtsi"
|
||||
|
||||
ap_ec_spi: &spi6 {};
|
||||
ap_h1_spi: &spi0 {};
|
||||
|
||||
#include "sc7180-trogdor.dtsi"
|
||||
#include "sc7180-trogdor-ti-sn65dsi86.dtsi"
|
||||
|
||||
&ap_sar_sensor {
|
||||
semtech,cs0-ground;
|
||||
|
|
|
|||
|
|
@ -5,6 +5,8 @@
|
|||
* Copyright 2021 Google LLC.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
pp3300_brij_ps8640: pp3300-brij-ps8640 {
|
||||
compatible = "regulator-fixed";
|
||||
|
|
|
|||
|
|
@ -5,9 +5,10 @@
|
|||
* Copyright 2021 Google LLC.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
&dsi0_out {
|
||||
remote-endpoint = <&sn65dsi86_in>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
|
||||
edp_brij_i2c: &i2c2 {
|
||||
|
|
|
|||
|
|
@ -603,6 +603,10 @@ &dsi0 {
|
|||
vdda-supply = <&vdda_mipi_dsi0_1p2>;
|
||||
};
|
||||
|
||||
&dsi0_out {
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
|
||||
&dsi_phy {
|
||||
status = "okay";
|
||||
vdds-supply = <&vdda_mipi_dsi0_pll>;
|
||||
|
|
|
|||
|
|
@ -1952,7 +1952,6 @@ glink-edge {
|
|||
|
||||
gpu: gpu@5000000 {
|
||||
compatible = "qcom,adreno-618.0", "qcom,adreno";
|
||||
#stream-id-cells = <16>;
|
||||
reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>,
|
||||
<0 0x05061000 0 0x800>;
|
||||
reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
|
||||
|
|
|
|||
93
arch/arm64/boot/dts/qcom/sc7280-crd.dts
Normal file
93
arch/arm64/boot/dts/qcom/sc7280-crd.dts
Normal file
|
|
@ -0,0 +1,93 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* sc7280 CRD board device tree source
|
||||
*
|
||||
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "sc7280-idp.dtsi"
|
||||
#include "sc7280-idp-ec-h1.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. sc7280 CRD platform";
|
||||
compatible = "qcom,sc7280-crd", "google,hoglin", "qcom,sc7280";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart5;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
ap_tp_i2c: &i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
trackpad: trackpad@15 {
|
||||
compatible = "hid-over-i2c";
|
||||
reg = <0x15>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&tp_int_odl>;
|
||||
|
||||
interrupt-parent = <&tlmm>;
|
||||
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
|
||||
|
||||
post-power-on-delay-ms = <20>;
|
||||
hid-descr-addr = <0x0001>;
|
||||
vdd-supply = <&vreg_l18b_1p8>;
|
||||
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
ap_ts_pen_1v8: &i2c13 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
ap_ts: touchscreen@5c {
|
||||
compatible = "hid-over-i2c";
|
||||
reg = <0x5c>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ts_int_l>, <&ts_reset_l>;
|
||||
|
||||
interrupt-parent = <&tlmm>;
|
||||
interrupts = <55 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
post-power-on-delay-ms = <500>;
|
||||
hid-descr-addr = <0x0000>;
|
||||
|
||||
vdd-supply = <&vreg_l19b_1p8>;
|
||||
};
|
||||
};
|
||||
|
||||
&nvme_3v3_regulator {
|
||||
gpio = <&tlmm 51 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&nvme_pwren {
|
||||
pins = "gpio51";
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
tp_int_odl: tp-int-odl {
|
||||
pins = "gpio7";
|
||||
function = "gpio";
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
ts_int_l: ts-int-l {
|
||||
pins = "gpio55";
|
||||
function = "gpio";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
ts_reset_l: ts-reset-l {
|
||||
pins = "gpio54";
|
||||
function = "gpio";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
105
arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi
Normal file
105
arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi
Normal file
|
|
@ -0,0 +1,105 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* sc7280 EC/H1 over SPI (common between IDP2 and CRD)
|
||||
*
|
||||
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
ap_ec_spi: &spi10 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs_gpio_init_high>, <&qup_spi10_cs_gpio>;
|
||||
cs-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
|
||||
|
||||
cros_ec: ec@0 {
|
||||
compatible = "google,cros-ec-spi";
|
||||
reg = <0>;
|
||||
interrupt-parent = <&tlmm>;
|
||||
interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ap_ec_int_l>;
|
||||
spi-max-frequency = <3000000>;
|
||||
|
||||
cros_ec_pwm: ec-pwm {
|
||||
compatible = "google,cros-ec-pwm";
|
||||
#pwm-cells = <1>;
|
||||
};
|
||||
|
||||
i2c_tunnel: i2c-tunnel {
|
||||
compatible = "google,cros-ec-i2c-tunnel";
|
||||
google,remote-bus = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
typec {
|
||||
compatible = "google,cros-ec-typec";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
usb_c0: connector@0 {
|
||||
compatible = "usb-c-connector";
|
||||
reg = <0>;
|
||||
label = "left";
|
||||
power-role = "dual";
|
||||
data-role = "host";
|
||||
try-power-role = "source";
|
||||
};
|
||||
|
||||
usb_c1: connector@1 {
|
||||
compatible = "usb-c-connector";
|
||||
reg = <1>;
|
||||
label = "right";
|
||||
power-role = "dual";
|
||||
data-role = "host";
|
||||
try-power-role = "source";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#include <arm/cros-ec-keyboard.dtsi>
|
||||
#include <arm/cros-ec-sbs.dtsi>
|
||||
|
||||
ap_h1_spi: &spi14 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs_gpio_init_high>, <&qup_spi14_cs_gpio>;
|
||||
cs-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
|
||||
|
||||
cr50: tpm@0 {
|
||||
compatible = "google,cr50";
|
||||
reg = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&h1_ap_int_odl>;
|
||||
spi-max-frequency = <800000>;
|
||||
interrupt-parent = <&tlmm>;
|
||||
interrupts = <104 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
ap_ec_int_l: ap-ec-int-l {
|
||||
pins = "gpio18";
|
||||
function = "gpio";
|
||||
input-enable;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
h1_ap_int_odl: h1-ap-int-odl {
|
||||
pins = "gpio104";
|
||||
function = "gpio";
|
||||
input-enable;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high {
|
||||
pins = "gpio43";
|
||||
output-high;
|
||||
};
|
||||
|
||||
qup_spi14_cs_gpio_init_high: qup-spi14-cs-gpio-init-high {
|
||||
pins = "gpio59";
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
|
@ -8,6 +8,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "sc7280-idp.dtsi"
|
||||
#include "sc7280-idp-ec-h1.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. sc7280 IDP SKU2 platform";
|
||||
|
|
|
|||
|
|
@ -129,6 +129,11 @@ wlan_fw_mem: memory@80c00000 {
|
|||
no-map;
|
||||
};
|
||||
|
||||
video_mem: memory@8b200000 {
|
||||
reg = <0x0 0x8b200000 0x0 0x500000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
ipa_fw_mem: memory@8b700000 {
|
||||
reg = <0 0x8b700000 0 0x10000>;
|
||||
no-map;
|
||||
|
|
@ -574,9 +579,10 @@ gcc: clock-controller@100000 {
|
|||
reg = <0 0x00100000 0 0x1f0000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
|
||||
<0>, <0>, <0>, <0>, <0>, <0>;
|
||||
<0>, <&pcie1_lane 0>,
|
||||
<0>, <0>, <0>, <0>;
|
||||
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
|
||||
"pcie_0_pipe_clk", "pcie_1_pipe-clk",
|
||||
"pcie_0_pipe_clk", "pcie_1_pipe_clk",
|
||||
"ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk",
|
||||
"ufs_phy_tx_symbol_0_clk",
|
||||
"usb3_phy_wrapper_gcc_usb30_pipe_clk";
|
||||
|
|
@ -1592,10 +1598,10 @@ pcie1: pci@1c08000 {
|
|||
interrupt-names = "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
|
||||
<&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
|
||||
|
|
@ -1747,7 +1753,6 @@ lpass_ag_noc: interconnect@3c40000 {
|
|||
|
||||
gpu: gpu@3d00000 {
|
||||
compatible = "qcom,adreno-635.0", "qcom,adreno";
|
||||
#stream-id-cells = <16>;
|
||||
reg = <0 0x03d00000 0 0x40000>,
|
||||
<0 0x03d9e000 0 0x1000>,
|
||||
<0 0x03d61000 0 0x800>;
|
||||
|
|
@ -2675,6 +2680,76 @@ usb_1_dwc3: usb@a600000 {
|
|||
};
|
||||
};
|
||||
|
||||
venus: video-codec@aa00000 {
|
||||
compatible = "qcom,sc7280-venus";
|
||||
reg = <0 0x0aa00000 0 0xd0600>;
|
||||
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>,
|
||||
<&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>,
|
||||
<&videocc VIDEO_CC_VENUS_AHB_CLK>,
|
||||
<&videocc VIDEO_CC_MVS0_CORE_CLK>,
|
||||
<&videocc VIDEO_CC_MVS0_AXI_CLK>;
|
||||
clock-names = "core", "bus", "iface",
|
||||
"vcodec_core", "vcodec_bus";
|
||||
|
||||
power-domains = <&videocc MVSC_GDSC>,
|
||||
<&videocc MVS0_GDSC>,
|
||||
<&rpmhpd SC7280_CX>;
|
||||
power-domain-names = "venus", "vcodec0", "cx";
|
||||
operating-points-v2 = <&venus_opp_table>;
|
||||
|
||||
interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>,
|
||||
<&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnect-names = "cpu-cfg", "video-mem";
|
||||
|
||||
iommus = <&apps_smmu 0x2180 0x20>,
|
||||
<&apps_smmu 0x2184 0x20>;
|
||||
memory-region = <&video_mem>;
|
||||
|
||||
video-decoder {
|
||||
compatible = "venus-decoder";
|
||||
};
|
||||
|
||||
video-encoder {
|
||||
compatible = "venus-encoder";
|
||||
};
|
||||
|
||||
video-firmware {
|
||||
iommus = <&apps_smmu 0x21a2 0x0>;
|
||||
};
|
||||
|
||||
venus_opp_table: venus-opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-133330000 {
|
||||
opp-hz = /bits/ 64 <133330000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
|
||||
opp-240000000 {
|
||||
opp-hz = /bits/ 64 <240000000>;
|
||||
required-opps = <&rpmhpd_opp_svs>;
|
||||
};
|
||||
|
||||
opp-335000000 {
|
||||
opp-hz = /bits/ 64 <335000000>;
|
||||
required-opps = <&rpmhpd_opp_svs_l1>;
|
||||
};
|
||||
|
||||
opp-424000000 {
|
||||
opp-hz = /bits/ 64 <424000000>;
|
||||
required-opps = <&rpmhpd_opp_nom>;
|
||||
};
|
||||
|
||||
opp-460000048 {
|
||||
opp-hz = /bits/ 64 <460000048>;
|
||||
required-opps = <&rpmhpd_opp_turbo>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
videocc: clock-controller@aaf0000 {
|
||||
compatible = "qcom,sc7280-videocc";
|
||||
reg = <0 0xaaf0000 0 0x10000>;
|
||||
|
|
|
|||
|
|
@ -90,7 +90,6 @@ cam_vana_rear_vreg: cam_vana_rear_vreg {
|
|||
gpio_keys {
|
||||
status = "okay";
|
||||
compatible = "gpio-keys";
|
||||
input-name = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
|
|
@ -215,14 +214,14 @@ &blsp2_uart1 {
|
|||
/* HCI Bluetooth */
|
||||
};
|
||||
|
||||
&pon {
|
||||
volup {
|
||||
compatible = "qcom,pm8941-resin";
|
||||
interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
|
||||
debounce = <15625>;
|
||||
bias-pull-up;
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
};
|
||||
&pon_pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pon_resin {
|
||||
status = "okay";
|
||||
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
};
|
||||
|
||||
&qusb2phy {
|
||||
|
|
|
|||
|
|
@ -19,6 +19,11 @@ / {
|
|||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
mmc1 = &sdhc_1;
|
||||
mmc2 = &sdhc_2;
|
||||
};
|
||||
|
||||
chosen { };
|
||||
|
||||
clocks {
|
||||
|
|
@ -1014,7 +1019,6 @@ sd-cd {
|
|||
|
||||
adreno_gpu: gpu@5000000 {
|
||||
compatible = "qcom,adreno-508.0", "qcom,adreno";
|
||||
#stream-id-cells = <16>;
|
||||
|
||||
reg = <0x05000000 0x40000>;
|
||||
reg-names = "kgsl_3d0_reg_memory";
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
/ {
|
||||
model = "Sony Xperia 10 Plus";
|
||||
compatible = "sony,mermaid-row", "qcom,sdm636";
|
||||
chassis-type = "handset";
|
||||
|
||||
/* SDM636 v1 */
|
||||
qcom,msm-id = <345 0>;
|
||||
|
|
|
|||
|
|
@ -1,11 +1,16 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2020, Alexey Minnekhanov <alexey.min@gmail.com>
|
||||
* Copyright (c) 2021, Dang Huynh <danct12@riseup.net>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "sdm660.dtsi"
|
||||
#include "pm660.dtsi"
|
||||
#include "pm660l.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/input/gpio-keys.h>
|
||||
|
||||
/ {
|
||||
model = "Xiaomi Redmi Note 7";
|
||||
|
|
@ -17,7 +22,41 @@ aliases {
|
|||
};
|
||||
|
||||
chosen {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
stdout-path = "serial0:115200n8";
|
||||
|
||||
framebuffer0: framebuffer@9d400000 {
|
||||
compatible = "simple-framebuffer";
|
||||
reg = <0 0x9d400000 0 (1080 * 2340 * 4)>;
|
||||
width = <1080>;
|
||||
height = <2340>;
|
||||
stride = <(1080 * 4)>;
|
||||
format = "a8r8g8b8";
|
||||
};
|
||||
};
|
||||
|
||||
vph_pwr: vph-pwr-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vph_pwr";
|
||||
regulator-min-microvolt = <3700000>;
|
||||
regulator-max-microvolt = <3700000>;
|
||||
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
volup {
|
||||
label = "Volume Up";
|
||||
gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
debounce-interval = <15>;
|
||||
};
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
|
|
@ -33,6 +72,20 @@ ramoops@a0000000 {
|
|||
ftrace-size = <0x0>;
|
||||
pmsg-size = <0x20000>;
|
||||
};
|
||||
|
||||
framebuffer_mem: memory@9d400000 {
|
||||
reg = <0x0 0x9d400000 0x0 0x23ff000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* Until we hook up type-c detection, we
|
||||
* have to stick with this. But it works.
|
||||
*/
|
||||
extcon_usb: extcon-usb {
|
||||
compatible = "linux,extcon-usb-gpio";
|
||||
id-gpio = <&tlmm 58 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -40,6 +93,304 @@ &blsp1_uart2 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&pon_pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pon_resin {
|
||||
status = "okay";
|
||||
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
};
|
||||
|
||||
&qusb2phy {
|
||||
status = "okay";
|
||||
|
||||
vdd-supply = <&vreg_l1b_0p925>;
|
||||
vdda-phy-dpdm-supply = <&vreg_l7b_3p125>;
|
||||
};
|
||||
|
||||
&rpm_requests {
|
||||
pm660l-regulators {
|
||||
compatible = "qcom,rpm-pm660l-regulators";
|
||||
|
||||
vdd_s1-supply = <&vph_pwr>;
|
||||
vdd_s2-supply = <&vph_pwr>;
|
||||
vdd_s3_s4-supply = <&vph_pwr>;
|
||||
vdd_s5-supply = <&vph_pwr>;
|
||||
vdd_s6-supply = <&vph_pwr>;
|
||||
|
||||
vdd_l1_l9_l10-supply = <&vreg_s2b_1p05>;
|
||||
vdd_l2-supply = <&vreg_bob>;
|
||||
vdd_l3_l5_l7_l8-supply = <&vreg_bob>;
|
||||
vdd_l4_l6-supply = <&vreg_bob>;
|
||||
vdd_bob-supply = <&vph_pwr>;
|
||||
|
||||
vreg_s1b_1p125: s1 {
|
||||
regulator-min-microvolt = <1125000>;
|
||||
regulator-max-microvolt = <1125000>;
|
||||
regulator-enable-ramp-delay = <200>;
|
||||
};
|
||||
|
||||
vreg_s2b_1p05: s2 {
|
||||
regulator-min-microvolt = <1050000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
regulator-enable-ramp-delay = <200>;
|
||||
};
|
||||
|
||||
/* LDOs */
|
||||
vreg_l1b_0p925: l1 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <925000>;
|
||||
regulator-enable-ramp-delay = <250>;
|
||||
regulator-allow-set-load;
|
||||
};
|
||||
|
||||
/* SDHCI 3.3V signal doesn't seem to be supported. */
|
||||
vreg_l2b_2p95: l2 {
|
||||
regulator-min-microvolt = <1648000>;
|
||||
regulator-max-microvolt = <2696000>;
|
||||
regulator-enable-ramp-delay = <250>;
|
||||
regulator-allow-set-load;
|
||||
};
|
||||
|
||||
vreg_l3b_3p3: l3 {
|
||||
regulator-min-microvolt = <1700000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-enable-ramp-delay = <250>;
|
||||
regulator-allow-set-load;
|
||||
};
|
||||
|
||||
vreg_l4b_2p95: l4 {
|
||||
regulator-min-microvolt = <2944000>;
|
||||
regulator-max-microvolt = <2952000>;
|
||||
regulator-enable-ramp-delay = <250>;
|
||||
|
||||
regulator-min-microamp = <200>;
|
||||
regulator-max-microamp = <600000>;
|
||||
regulator-system-load = <570000>;
|
||||
regulator-allow-set-load;
|
||||
};
|
||||
|
||||
/*
|
||||
* Downstream specifies a range of 1721-3600mV,
|
||||
* but the only assigned consumers are SDHCI2 VMMC
|
||||
* and Coresight QPDI that both request pinned 2.95V.
|
||||
* Tighten the range to 1.8-3.328 (closest to 3.3) to
|
||||
* make the mmc driver happy.
|
||||
*/
|
||||
vreg_l5b_2p95: l5 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3328000>;
|
||||
regulator-enable-ramp-delay = <250>;
|
||||
regulator-allow-set-load;
|
||||
regulator-system-load = <800000>;
|
||||
};
|
||||
|
||||
vreg_l7b_3p125: l7 {
|
||||
regulator-min-microvolt = <2700000>;
|
||||
regulator-max-microvolt = <3125000>;
|
||||
regulator-enable-ramp-delay = <250>;
|
||||
};
|
||||
|
||||
vreg_l8b_3p3: l8 {
|
||||
regulator-min-microvolt = <3200000>;
|
||||
regulator-max-microvolt = <3400000>;
|
||||
regulator-enable-ramp-delay = <250>;
|
||||
};
|
||||
|
||||
vreg_bob: bob {
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3600000>;
|
||||
regulator-enable-ramp-delay = <500>;
|
||||
};
|
||||
};
|
||||
|
||||
pm660-regulators {
|
||||
compatible = "qcom,rpm-pm660-regulators";
|
||||
|
||||
vdd_s1-supply = <&vph_pwr>;
|
||||
vdd_s2-supply = <&vph_pwr>;
|
||||
vdd_s3-supply = <&vph_pwr>;
|
||||
vdd_s4-supply = <&vph_pwr>;
|
||||
vdd_s5-supply = <&vph_pwr>;
|
||||
vdd_s6-supply = <&vph_pwr>;
|
||||
|
||||
vdd_l1_l6_l7-supply = <&vreg_s5a_1p35>;
|
||||
vdd_l2_l3-supply = <&vreg_s2b_1p05>;
|
||||
vdd_l5-supply = <&vreg_s2b_1p05>;
|
||||
vdd_l8_l9_l10_l11_l12_l13_l14-supply = <&vreg_s4a_2p04>;
|
||||
vdd_l15_l16_l17_l18_l19-supply = <&vreg_bob>;
|
||||
|
||||
/*
|
||||
* S1A (FTAPC0), S2A (FTAPC1), S3A (HFAPC1) are managed
|
||||
* by the Core Power Reduction hardened (CPRh) and the
|
||||
* Operating State Manager (OSM) HW automatically.
|
||||
*/
|
||||
|
||||
vreg_s4a_2p04: s4 {
|
||||
regulator-min-microvolt = <1805000>;
|
||||
regulator-max-microvolt = <2040000>;
|
||||
regulator-enable-ramp-delay = <200>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vreg_s5a_1p35: s5 {
|
||||
regulator-min-microvolt = <1224000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-enable-ramp-delay = <200>;
|
||||
};
|
||||
|
||||
vreg_s6a_0p87: s6 {
|
||||
regulator-min-microvolt = <504000>;
|
||||
regulator-max-microvolt = <992000>;
|
||||
regulator-enable-ramp-delay = <150>;
|
||||
};
|
||||
|
||||
/* LDOs */
|
||||
vreg_l1a_1p225: l1 {
|
||||
regulator-min-microvolt = <1150000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
regulator-enable-ramp-delay = <250>;
|
||||
regulator-allow-set-load;
|
||||
};
|
||||
|
||||
vreg_l2a_1p0: l2 {
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <1010000>;
|
||||
regulator-enable-ramp-delay = <250>;
|
||||
};
|
||||
|
||||
vreg_l3a_1p0: l3 {
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <1010000>;
|
||||
regulator-enable-ramp-delay = <250>;
|
||||
};
|
||||
|
||||
vreg_l5a_0p848: l5 {
|
||||
regulator-min-microvolt = <525000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-enable-ramp-delay = <250>;
|
||||
};
|
||||
|
||||
vreg_l6a_1p3: l6 {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1370000>;
|
||||
regulator-allow-set-load;
|
||||
regulator-enable-ramp-delay = <250>;
|
||||
};
|
||||
|
||||
vreg_l7a_1p2: l7 {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-enable-ramp-delay = <250>;
|
||||
};
|
||||
|
||||
vreg_l8a_1p8: l8 {
|
||||
regulator-min-microvolt = <1750000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-enable-ramp-delay = <250>;
|
||||
regulator-system-load = <325000>;
|
||||
regulator-allow-set-load;
|
||||
};
|
||||
|
||||
vreg_l9a_1p8: l9 {
|
||||
regulator-min-microvolt = <1750000>;
|
||||
regulator-max-microvolt = <1900000>;
|
||||
regulator-enable-ramp-delay = <250>;
|
||||
regulator-allow-set-load;
|
||||
};
|
||||
|
||||
vreg_l10a_1p8: l10 {
|
||||
regulator-min-microvolt = <1780000>;
|
||||
regulator-max-microvolt = <1950000>;
|
||||
regulator-enable-ramp-delay = <250>;
|
||||
regulator-allow-set-load;
|
||||
};
|
||||
|
||||
vreg_l11a_1p8: l11 {
|
||||
regulator-min-microvolt = <1780000>;
|
||||
regulator-max-microvolt = <1950000>;
|
||||
regulator-enable-ramp-delay = <250>;
|
||||
};
|
||||
|
||||
vreg_l12a_1p8: l12 {
|
||||
regulator-min-microvolt = <1780000>;
|
||||
regulator-max-microvolt = <1950000>;
|
||||
regulator-enable-ramp-delay = <250>;
|
||||
};
|
||||
|
||||
/* This gives power to the LPDDR4: never turn it off! */
|
||||
vreg_l13a_1p8: l13 {
|
||||
regulator-min-microvolt = <1780000>;
|
||||
regulator-max-microvolt = <1950000>;
|
||||
regulator-enable-ramp-delay = <250>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vreg_l14a_1p8: l14 {
|
||||
regulator-min-microvolt = <1710000>;
|
||||
regulator-max-microvolt = <1900000>;
|
||||
regulator-enable-ramp-delay = <250>;
|
||||
};
|
||||
|
||||
vreg_l15a_1p8: l15 {
|
||||
regulator-min-microvolt = <1650000>;
|
||||
regulator-max-microvolt = <2950000>;
|
||||
regulator-enable-ramp-delay = <250>;
|
||||
};
|
||||
|
||||
vreg_l16a_2p7: l16 {
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-enable-ramp-delay = <250>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vreg_l17a_1p8: l17 {
|
||||
regulator-min-microvolt = <1648000>;
|
||||
regulator-max-microvolt = <2952000>;
|
||||
regulator-enable-ramp-delay = <250>;
|
||||
};
|
||||
|
||||
vreg_l19a_3p3: l19 {
|
||||
regulator-min-microvolt = <3312000>;
|
||||
regulator-max-microvolt = <3400000>;
|
||||
regulator-enable-ramp-delay = <250>;
|
||||
regulator-allow-set-load;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sdhc_1 {
|
||||
status = "okay";
|
||||
supports-cqe;
|
||||
|
||||
mmc-hs200-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
mmc-hs400-enhanced-strobe;
|
||||
|
||||
vmmc-supply = <&vreg_l4b_2p95>;
|
||||
vqmmc-supply = <&vreg_l8a_1p8>;
|
||||
};
|
||||
|
||||
&sdhc_2 {
|
||||
status = "okay";
|
||||
|
||||
vmmc-supply = <&vreg_l5b_2p95>;
|
||||
vqmmc-supply = <&vreg_l2b_2p95>;
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
gpio-reserved-ranges = <8 4>;
|
||||
};
|
||||
|
||||
&usb3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_dwc3 {
|
||||
dr_mode = "peripheral";
|
||||
extcon = <&extcon_usb>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -9,6 +9,8 @@
|
|||
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
|
||||
#include "sdm845.dtsi"
|
||||
#include "pm8998.dtsi"
|
||||
#include "pmi8998.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. SDM845 MTP";
|
||||
|
|
@ -45,6 +47,68 @@ vreg_s4a_1p8: pm8998-smps4 {
|
|||
|
||||
vin-supply = <&vph_pwr>;
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
xo_thermal: xo-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
|
||||
thermal-sensors = <&pm8998_adc_tm 1>;
|
||||
|
||||
trips {
|
||||
trip-point {
|
||||
temperature = <125000>;
|
||||
hysteresis = <10000>;
|
||||
type = "passive";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
msm_thermal: msm-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
|
||||
thermal-sensors = <&pm8998_adc_tm 2>;
|
||||
|
||||
trips {
|
||||
trip-point {
|
||||
temperature = <125000>;
|
||||
hysteresis = <10000>;
|
||||
type = "passive";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pa_thermal: pa-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
|
||||
thermal-sensors = <&pm8998_adc_tm 3>;
|
||||
|
||||
trips {
|
||||
trip-point {
|
||||
temperature = <125000>;
|
||||
hysteresis = <10000>;
|
||||
type = "passive";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
quiet_thermal: quiet-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
|
||||
thermal-sensors = <&pm8998_adc_tm 4>;
|
||||
|
||||
trips {
|
||||
trip-point {
|
||||
temperature = <125000>;
|
||||
hysteresis = <10000>;
|
||||
type = "passive";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&adsp_pas {
|
||||
|
|
@ -467,6 +531,82 @@ &mss_pil {
|
|||
firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mbn";
|
||||
};
|
||||
|
||||
&pm8998_adc {
|
||||
adc-chan@4c {
|
||||
reg = <ADC5_XO_THERM_100K_PU>;
|
||||
label = "xo_therm";
|
||||
qcom,ratiometric;
|
||||
qcom,hw-settle-time-us = <200>;
|
||||
};
|
||||
|
||||
adc-chan@4d {
|
||||
reg = <ADC5_AMUX_THM1_100K_PU>;
|
||||
label = "msm_therm";
|
||||
qcom,ratiometric;
|
||||
qcom,hw-settle-time-us = <200>;
|
||||
};
|
||||
|
||||
adc-chan@4f {
|
||||
reg = <ADC5_AMUX_THM3_100K_PU>;
|
||||
label = "pa_therm1";
|
||||
qcom,ratiometric;
|
||||
qcom,hw-settle-time-us = <200>;
|
||||
};
|
||||
|
||||
adc-chan@51 {
|
||||
reg = <ADC5_AMUX_THM5_100K_PU>;
|
||||
label = "quiet_therm";
|
||||
qcom,ratiometric;
|
||||
qcom,hw-settle-time-us = <200>;
|
||||
};
|
||||
|
||||
adc-chan@83 {
|
||||
reg = <ADC5_VPH_PWR>;
|
||||
label = "vph_pwr";
|
||||
qcom,ratiometric;
|
||||
qcom,hw-settle-time-us = <200>;
|
||||
};
|
||||
|
||||
adc-chan@85 {
|
||||
reg = <ADC5_VCOIN>;
|
||||
label = "vcoin";
|
||||
qcom,ratiometric;
|
||||
qcom,hw-settle-time-us = <200>;
|
||||
};
|
||||
};
|
||||
|
||||
&pm8998_adc_tm {
|
||||
status = "okay";
|
||||
|
||||
xo-thermistor@1 {
|
||||
reg = <1>;
|
||||
io-channels = <&pm8998_adc ADC5_XO_THERM_100K_PU>;
|
||||
qcom,ratiometric;
|
||||
qcom,hw-settle-time-us = <200>;
|
||||
};
|
||||
|
||||
msm-thermistor@2 {
|
||||
reg = <2>;
|
||||
io-channels = <&pm8998_adc ADC5_AMUX_THM1_100K_PU>;
|
||||
qcom,ratiometric;
|
||||
qcom,hw-settle-time-us = <200>;
|
||||
};
|
||||
|
||||
pa-thermistor@3 {
|
||||
reg = <3>;
|
||||
io-channels = <&pm8998_adc ADC5_AMUX_THM3_100K_PU>;
|
||||
qcom,ratiometric;
|
||||
qcom,hw-settle-time-us = <200>;
|
||||
};
|
||||
|
||||
quiet-thermistor@4 {
|
||||
reg = <4>;
|
||||
io-channels = <&pm8998_adc ADC5_AMUX_THM5_100K_PU>;
|
||||
qcom,ratiometric;
|
||||
qcom,hw-settle-time-us = <200>;
|
||||
};
|
||||
};
|
||||
|
||||
&qupv3_id_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -646,6 +646,7 @@ mux {
|
|||
|
||||
&venus {
|
||||
status = "okay";
|
||||
firmware-name = "qcom/sdm845/oneplus6/venus.mbn";
|
||||
};
|
||||
|
||||
&wifi {
|
||||
|
|
|
|||
|
|
@ -11,6 +11,8 @@ / {
|
|||
model = "OnePlus 6";
|
||||
compatible = "oneplus,enchilada", "qcom,sdm845";
|
||||
chassis-type = "handset";
|
||||
qcom,msm-id = <0x141 0x20001>;
|
||||
qcom,board-id = <8 0 17819 22>;
|
||||
};
|
||||
|
||||
&display_panel {
|
||||
|
|
|
|||
|
|
@ -11,6 +11,8 @@ / {
|
|||
model = "OnePlus 6T";
|
||||
compatible = "oneplus,fajita", "qcom,sdm845";
|
||||
chassis-type = "handset";
|
||||
qcom,msm-id = <0x141 0x20001>;
|
||||
qcom,board-id = <8 0 18801 41>;
|
||||
};
|
||||
|
||||
&display_panel {
|
||||
|
|
|
|||
13
arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akari.dts
Normal file
13
arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akari.dts
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "sdm845-sony-xperia-tama.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Sony Xperia XZ2";
|
||||
compatible = "sony,akari-row", "qcom,sdm845";
|
||||
};
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "sdm845-sony-xperia-tama.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Sony Xperia XZ3";
|
||||
compatible = "sony,akatsuki-row", "qcom,sdm845";
|
||||
};
|
||||
|
||||
/* For the future: WLED + LAB/IBB/OLEDB are not used on Akatsuki */
|
||||
&vreg_l14a_1p8 {
|
||||
regulator-min-microvolt = <1840000>;
|
||||
regulator-max-microvolt = <1840000>;
|
||||
};
|
||||
|
||||
&vreg_l22a_2p8 {
|
||||
regulator-min-microvolt = <2700000>;
|
||||
regulator-max-microvolt = <2700000>;
|
||||
};
|
||||
|
||||
&vreg_l28a_2p8 {
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
};
|
||||
13
arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-apollo.dts
Normal file
13
arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-apollo.dts
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "sdm845-sony-xperia-tama.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Sony Xperia XZ2 Compact";
|
||||
compatible = "sony,apollo-row", "qcom,sdm845";
|
||||
};
|
||||
438
arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi
Normal file
438
arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi
Normal file
|
|
@ -0,0 +1,438 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
|
||||
#include "sdm845.dtsi"
|
||||
#include "pm8005.dtsi"
|
||||
#include "pm8998.dtsi"
|
||||
#include "pmi8998.dtsi"
|
||||
|
||||
/ {
|
||||
qcom,msm-id = <321 0x20001>; /* SDM845 v2.1 */
|
||||
qcom,board-id = <8 0>;
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
/* Neither Camera Focus, nor Camera Shutter seem to work... */
|
||||
|
||||
vol-down {
|
||||
label = "volume_down";
|
||||
gpios = <&pm8998_gpio 5 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
debounce-interval = <15>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
};
|
||||
|
||||
vph_pwr: vph-pwr-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vph_pwr";
|
||||
regulator-min-microvolt = <3700000>;
|
||||
regulator-max-microvolt = <3700000>;
|
||||
};
|
||||
|
||||
vreg_s4a_1p8: pm8998-smps4 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vreg_s4a_1p8";
|
||||
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
vin-supply = <&vph_pwr>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
/* SONY was cool and didn't diverge from MTP this time, yay! */
|
||||
cont_splash_mem: memory@9d400000 {
|
||||
reg = <0x0 0x9d400000 0x0 0x2400000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
ramoops@ffc00000 {
|
||||
compatible = "ramoops";
|
||||
reg = <0x0 0xffc00000 0x0 0x100000>;
|
||||
record-size = <0x10000>;
|
||||
console-size = <0x60000>;
|
||||
ftrace-size = <0x10000>;
|
||||
pmsg-size = <0x20000>;
|
||||
ecc-size = <16>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&apps_rsc {
|
||||
pm8998-rpmh-regulators {
|
||||
compatible = "qcom,pm8998-rpmh-regulators";
|
||||
qcom,pmic-id = "a";
|
||||
|
||||
vdd-s1-supply = <&vph_pwr>;
|
||||
vdd-s2-supply = <&vph_pwr>;
|
||||
vdd-s3-supply = <&vph_pwr>;
|
||||
vdd-s4-supply = <&vph_pwr>;
|
||||
vdd-s5-supply = <&vph_pwr>;
|
||||
vdd-s6-supply = <&vph_pwr>;
|
||||
vdd-s7-supply = <&vph_pwr>;
|
||||
vdd-s8-supply = <&vph_pwr>;
|
||||
vdd-s9-supply = <&vph_pwr>;
|
||||
vdd-s10-supply = <&vph_pwr>;
|
||||
vdd-s11-supply = <&vph_pwr>;
|
||||
vdd-s12-supply = <&vph_pwr>;
|
||||
vdd-s13-supply = <&vph_pwr>;
|
||||
vdd-l1-l27-supply = <&vreg_s7a_0p9>;
|
||||
vdd-l2-l8-l17-supply = <&vreg_s3a_1p3>;
|
||||
vdd-l3-l11-supply = <&vreg_s7a_0p9>;
|
||||
vdd-l4-l5-supply = <&vreg_s7a_0p9>;
|
||||
vdd-l6-supply = <&vph_pwr>;
|
||||
vdd-l7-l12-l14-l15-supply = <&vreg_s5a_1p9>;
|
||||
vdd-l9-supply = <&vreg_s5a_1p9>;
|
||||
vdd-l10-l23-l25-supply = <&src_vreg_bob>;
|
||||
vdd-l13-l19-l21-supply = <&src_vreg_bob>;
|
||||
vdd-l16-l28-supply = <&src_vreg_bob>;
|
||||
vdd-l18-l22-supply = <&src_vreg_bob>;
|
||||
vdd-l20-l24-supply = <&src_vreg_bob>;
|
||||
vdd-l26-supply = <&vreg_s3a_1p3>;
|
||||
vin-lvs-1-2-supply = <&vreg_s4a_1p8>;
|
||||
|
||||
vreg_s2a_1p1: smps2 {
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
};
|
||||
|
||||
vreg_s3a_1p3: smps3 {
|
||||
regulator-min-microvolt = <1352000>;
|
||||
regulator-max-microvolt = <1352000>;
|
||||
};
|
||||
|
||||
vreg_s5a_1p9: smps5 {
|
||||
regulator-min-microvolt = <1904000>;
|
||||
regulator-max-microvolt = <2040000>;
|
||||
};
|
||||
|
||||
vreg_s7a_0p9: smps7 {
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1028000>;
|
||||
};
|
||||
|
||||
vreg_l1a_0p9: ldo1 {
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <880000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l2a_1p2: ldo2 {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vreg_l3a_1p0: ldo3 {
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l5a_0p8: ldo5 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l6a_1p8: ldo6 {
|
||||
regulator-min-microvolt = <1856000>;
|
||||
regulator-max-microvolt = <1856000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l7a_1p8: ldo7 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l8a_1p2: ldo8 {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1248000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l9a_1p7: ldo9 {
|
||||
regulator-min-microvolt = <1704000>;
|
||||
regulator-max-microvolt = <2928000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l10a_1p7: ldo10 {
|
||||
regulator-min-microvolt = <1704000>;
|
||||
regulator-max-microvolt = <2928000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l11a_1p0: ldo11 {
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1048000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l12a_1p8: ldo12 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l13a_1p8: ldo13 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2960000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l14a_1p8: ldo14 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l15a_1p8: ldo15 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l16a_2p7: ldo16 {
|
||||
regulator-min-microvolt = <2704000>;
|
||||
regulator-max-microvolt = <2704000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l17a_1p3: ldo17 {
|
||||
regulator-min-microvolt = <1304000>;
|
||||
regulator-max-microvolt = <1304000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l18a_2p7: ldo18 {
|
||||
regulator-min-microvolt = <2704000>;
|
||||
regulator-max-microvolt = <2960000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l19a_2p7: ldo19 {
|
||||
regulator-min-microvolt = <2700000>;
|
||||
regulator-max-microvolt = <2700000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
|
||||
/*
|
||||
* The driver *really* doesn't want this regualtor to exist,
|
||||
* saying that it could not get the current voltage (-ENOTRECOVERABLE)
|
||||
* even though it surely is used on these devices (as a voltage
|
||||
* source for camera autofocus)
|
||||
*/
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vreg_l20a_2p7: ldo20 {
|
||||
regulator-min-microvolt = <2704000>;
|
||||
regulator-max-microvolt = <2960000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l21a_2p7: ldo21 {
|
||||
regulator-min-microvolt = <2704000>;
|
||||
regulator-max-microvolt = <2960000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l22a_2p8: ldo22 {
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l23a_3p0: ldo23 {
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3312000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l24a_3p1: ldo24 {
|
||||
regulator-min-microvolt = <3088000>;
|
||||
regulator-max-microvolt = <3088000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l25a_3p0: ldo25 {
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3312000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l26a_1p2: ldo26 {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l28a_2p8: ldo28 {
|
||||
regulator-min-microvolt = <2856000>;
|
||||
regulator-max-microvolt = <3008000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_lvs1a_1p8: lvs1 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_lvs2a_1p8: lvs2 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
pmi8998-rpmh-regulators {
|
||||
compatible = "qcom,pmi8998-rpmh-regulators";
|
||||
qcom,pmic-id = "b";
|
||||
|
||||
src_vreg_bob: bob {
|
||||
regulator-min-microvolt = <3312000>;
|
||||
regulator-max-microvolt = <3600000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
pm8005-rpmh-regulators {
|
||||
compatible = "qcom,pm8005-rpmh-regulators";
|
||||
qcom,pmic-id = "c";
|
||||
|
||||
vdd-s1-supply = <&vph_pwr>;
|
||||
vdd-s2-supply = <&vph_pwr>;
|
||||
vdd-s3-supply = <&vph_pwr>;
|
||||
vdd-s4-supply = <&vph_pwr>;
|
||||
|
||||
vreg_s3c_0p6: smps3 {
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <600000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gcc {
|
||||
protected-clocks = <GCC_QSPI_CORE_CLK>,
|
||||
<GCC_QSPI_CORE_CLK_SRC>,
|
||||
<GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
|
||||
<GCC_LPASS_Q6_AXI_CLK>,
|
||||
<GCC_LPASS_SWAY_CLK>;
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
/* Synaptics touchscreen @ 2c, 3c */
|
||||
};
|
||||
|
||||
&i2c10 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
/* Qcom SMB1355 @ 8, c */
|
||||
/* NXP PN547 NFC @ 28 */
|
||||
/* Renesas IDTP9221 Qi charger @ 61 */
|
||||
};
|
||||
|
||||
&i2c14 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
/* SONY ToF sensor @ 52 */
|
||||
/* AMS TCS3490 RGB+IR color sensor @ 72 */
|
||||
};
|
||||
|
||||
&qupv3_id_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qupv3_id_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhc_2 {
|
||||
status = "okay";
|
||||
|
||||
vmmc-supply = <&vreg_l21a_2p7>;
|
||||
vqmmc-supply = <&vreg_l13a_1p8>;
|
||||
cd-gpios = <&tlmm 126 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-0 = <&sdc2_default_state>;
|
||||
pinctrl-names = "default";
|
||||
bus-width = <4>;
|
||||
no-sdio;
|
||||
no-emmc;
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
gpio-reserved-ranges = <0 4>, <81 4>;
|
||||
|
||||
sdc2_default_state: sdc2-default-state {
|
||||
clk {
|
||||
pins = "sdc2_clk";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
cmd {
|
||||
pins = "sdc2_cmd";
|
||||
drive-strength = <10>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
data {
|
||||
pins = "sdc2_data";
|
||||
drive-strength = <10>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart6 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart9 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* BIG WARNING! DO NOT TOUCH UFS, YOUR DEVICE WILL DIE! */
|
||||
&ufs_mem_hc { status = "disabled"; };
|
||||
&ufs_mem_phy { status = "disabled"; };
|
||||
|
||||
&usb_1 {
|
||||
status = "okay";
|
||||
|
||||
qcom,select-utmi-as-pipe-clk;
|
||||
};
|
||||
|
||||
&usb_1_dwc3 {
|
||||
dr_mode = "peripheral";
|
||||
|
||||
maximum-speed = "high-speed";
|
||||
phys = <&usb_1_hsphy>;
|
||||
phy-names = "usb2-phy";
|
||||
};
|
||||
|
||||
&usb_1_hsphy {
|
||||
status = "okay";
|
||||
|
||||
vdd-supply = <&vreg_l1a_0p9>;
|
||||
vdda-pll-supply = <&vreg_l12a_1p8>;
|
||||
vdda-phy-dpdm-supply = <&vreg_l24a_3p1>;
|
||||
};
|
||||
|
|
@ -514,6 +514,7 @@ &usb_1_qmpphy {
|
|||
|
||||
&venus {
|
||||
status = "okay";
|
||||
firmware-name = "qcom/sdm845/beryllium/venus.mbn";
|
||||
};
|
||||
|
||||
&wcd9340{
|
||||
|
|
|
|||
|
|
@ -1078,7 +1078,7 @@ gcc: clock-controller@100000 {
|
|||
};
|
||||
|
||||
qfprom@784000 {
|
||||
compatible = "qcom,qfprom";
|
||||
compatible = "qcom,sdm845-qfprom", "qcom,qfprom";
|
||||
reg = <0 0x00784000 0 0x8ff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -4415,7 +4415,6 @@ dsi1_phy: dsi-phy@ae96400 {
|
|||
|
||||
gpu: gpu@5000000 {
|
||||
compatible = "qcom,adreno-630.2", "qcom,adreno";
|
||||
#stream-id-cells = <16>;
|
||||
|
||||
reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>;
|
||||
reg-names = "kgsl_3d0_reg_memory", "cx_mem";
|
||||
|
|
|
|||
|
|
@ -523,6 +523,10 @@ dai@0 {
|
|||
dai@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
dai@2 {
|
||||
reg = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&sound {
|
||||
|
|
@ -535,6 +539,7 @@ &sound {
|
|||
"SpkrLeft IN", "SPK1 OUT",
|
||||
"SpkrRight IN", "SPK2 OUT",
|
||||
"MM_DL1", "MultiMedia1 Playback",
|
||||
"MM_DL3", "MultiMedia3 Playback",
|
||||
"MultiMedia2 Capture", "MM_UL2";
|
||||
|
||||
mm1-dai-link {
|
||||
|
|
@ -551,6 +556,13 @@ cpu {
|
|||
};
|
||||
};
|
||||
|
||||
mm3-dai-link {
|
||||
link-name = "MultiMedia3";
|
||||
cpu {
|
||||
sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>;
|
||||
};
|
||||
};
|
||||
|
||||
slim-dai-link {
|
||||
link-name = "SLIM Playback";
|
||||
cpu {
|
||||
|
|
@ -580,6 +592,21 @@ codec {
|
|||
sound-dai = <&wcd9340 1>;
|
||||
};
|
||||
};
|
||||
|
||||
slim-wcd-dai-link {
|
||||
link-name = "SLIM WCD Playback";
|
||||
cpu {
|
||||
sound-dai = <&q6afedai SLIMBUS_1_RX>;
|
||||
};
|
||||
|
||||
platform {
|
||||
sound-dai = <&q6routing>;
|
||||
};
|
||||
|
||||
codec {
|
||||
sound-dai = <&wcd9340 2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
|
|
@ -744,6 +771,9 @@ &wcd9340{
|
|||
vdd-tx-supply = <&vreg_s4a_1p8>;
|
||||
vdd-rx-supply = <&vreg_s4a_1p8>;
|
||||
vdd-io-supply = <&vreg_s4a_1p8>;
|
||||
qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
|
||||
qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
|
||||
qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
|
||||
|
||||
swm: swm@c85 {
|
||||
left_spkr: wsa8810-left{
|
||||
|
|
|
|||
|
|
@ -42,7 +42,6 @@ extcon_usb: extcon-usb {
|
|||
gpio-keys {
|
||||
status = "okay";
|
||||
compatible = "gpio-keys";
|
||||
input-name = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
autorepeat;
|
||||
|
|
|
|||
|
|
@ -302,6 +302,56 @@ rpmcc: clock-controller {
|
|||
compatible = "qcom,rpmcc-sm6125", "qcom,rpmcc";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
rpmpd: power-controller {
|
||||
compatible = "qcom,sm6125-rpmpd";
|
||||
#power-domain-cells = <1>;
|
||||
operating-points-v2 = <&rpmpd_opp_table>;
|
||||
|
||||
rpmpd_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
rpmpd_opp_ret: opp1 {
|
||||
opp-level = <RPM_SMD_LEVEL_RETENTION>;
|
||||
};
|
||||
|
||||
rpmpd_opp_ret_plus: opp2 {
|
||||
opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
|
||||
};
|
||||
|
||||
rpmpd_opp_min_svs: opp3 {
|
||||
opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
|
||||
};
|
||||
|
||||
rpmpd_opp_low_svs: opp4 {
|
||||
opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
|
||||
};
|
||||
|
||||
rpmpd_opp_svs: opp5 {
|
||||
opp-level = <RPM_SMD_LEVEL_SVS>;
|
||||
};
|
||||
|
||||
rpmpd_opp_svs_plus: opp6 {
|
||||
opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
|
||||
};
|
||||
|
||||
rpmpd_opp_nom: opp7 {
|
||||
opp-level = <RPM_SMD_LEVEL_NOM>;
|
||||
};
|
||||
|
||||
rpmpd_opp_nom_plus: opp8 {
|
||||
opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
|
||||
};
|
||||
|
||||
rpmpd_opp_turbo: opp9 {
|
||||
opp-level = <RPM_SMD_LEVEL_TURBO>;
|
||||
};
|
||||
|
||||
rpmpd_opp_turbo_no_cpr: opp10 {
|
||||
opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -398,6 +448,9 @@ sdhc_1: sdhci@4744000 {
|
|||
<&gcc GCC_SDCC1_APPS_CLK>,
|
||||
<&xo_board>;
|
||||
clock-names = "iface", "core", "xo";
|
||||
|
||||
power-domains = <&rpmpd 0>;
|
||||
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
status = "disabled";
|
||||
|
|
@ -421,6 +474,8 @@ sdhc_2: sdhci@4784000 {
|
|||
pinctrl-1 = <&sdc2_state_off>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
|
||||
power-domains = <&rpmpd 0>;
|
||||
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -361,6 +361,80 @@ smem {
|
|||
hwlocks = <&tcsr_mutex 3>;
|
||||
};
|
||||
|
||||
smp2p-adsp {
|
||||
compatible = "qcom,smp2p";
|
||||
qcom,smem = <443>, <429>;
|
||||
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
|
||||
IPCC_MPROC_SIGNAL_SMP2P
|
||||
IRQ_TYPE_EDGE_RISING>;
|
||||
mboxes = <&ipcc IPCC_CLIENT_LPASS
|
||||
IPCC_MPROC_SIGNAL_SMP2P>;
|
||||
|
||||
qcom,local-pid = <0>;
|
||||
qcom,remote-pid = <2>;
|
||||
|
||||
smp2p_adsp_out: master-kernel {
|
||||
qcom,entry-name = "master-kernel";
|
||||
#qcom,smem-state-cells = <1>;
|
||||
};
|
||||
|
||||
smp2p_adsp_in: slave-kernel {
|
||||
qcom,entry-name = "slave-kernel";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
smp2p-cdsp {
|
||||
compatible = "qcom,smp2p";
|
||||
qcom,smem = <94>, <432>;
|
||||
interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
|
||||
IPCC_MPROC_SIGNAL_SMP2P
|
||||
IRQ_TYPE_EDGE_RISING>;
|
||||
mboxes = <&ipcc IPCC_CLIENT_CDSP
|
||||
IPCC_MPROC_SIGNAL_SMP2P>;
|
||||
|
||||
qcom,local-pid = <0>;
|
||||
qcom,remote-pid = <5>;
|
||||
|
||||
smp2p_cdsp_out: master-kernel {
|
||||
qcom,entry-name = "master-kernel";
|
||||
#qcom,smem-state-cells = <1>;
|
||||
};
|
||||
|
||||
smp2p_cdsp_in: slave-kernel {
|
||||
qcom,entry-name = "slave-kernel";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
smp2p-mpss {
|
||||
compatible = "qcom,smp2p";
|
||||
qcom,smem = <435>, <428>;
|
||||
|
||||
interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
|
||||
IPCC_MPROC_SIGNAL_SMP2P
|
||||
IRQ_TYPE_EDGE_RISING>;
|
||||
mboxes = <&ipcc IPCC_CLIENT_MPSS
|
||||
IPCC_MPROC_SIGNAL_SMP2P>;
|
||||
|
||||
qcom,local-pid = <0>;
|
||||
qcom,remote-pid = <1>;
|
||||
|
||||
modem_smp2p_out: master-kernel {
|
||||
qcom,entry-name = "master-kernel";
|
||||
#qcom,smem-state-cells = <1>;
|
||||
};
|
||||
|
||||
modem_smp2p_in: slave-kernel {
|
||||
qcom,entry-name = "slave-kernel";
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc@0 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
|
@ -473,6 +547,211 @@ tcsr_mutex: hwlock@1f40000 {
|
|||
#hwlock-cells = <1>;
|
||||
};
|
||||
|
||||
adsp: remoteproc@3000000 {
|
||||
compatible = "qcom,sm6350-adsp-pas";
|
||||
reg = <0 0x03000000 0 0x100>;
|
||||
|
||||
interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
|
||||
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
|
||||
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
|
||||
<&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "wdog", "fatal", "ready",
|
||||
"handover", "stop-ack";
|
||||
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "xo";
|
||||
|
||||
power-domains = <&rpmhpd SM6350_LCX>,
|
||||
<&rpmhpd SM6350_LMX>;
|
||||
power-domain-names = "lcx", "lmx";
|
||||
|
||||
memory-region = <&pil_adsp_mem>;
|
||||
|
||||
qcom,qmp = <&aoss_qmp>;
|
||||
|
||||
qcom,smem-states = <&smp2p_adsp_out 0>;
|
||||
qcom,smem-state-names = "stop";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
glink-edge {
|
||||
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
|
||||
IPCC_MPROC_SIGNAL_GLINK_QMP
|
||||
IRQ_TYPE_EDGE_RISING>;
|
||||
mboxes = <&ipcc IPCC_CLIENT_LPASS
|
||||
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
||||
|
||||
label = "lpass";
|
||||
qcom,remote-pid = <2>;
|
||||
|
||||
fastrpc {
|
||||
compatible = "qcom,fastrpc";
|
||||
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
||||
label = "adsp";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compute-cb@3 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <3>;
|
||||
iommus = <&apps_smmu 0x1003 0x0>;
|
||||
};
|
||||
|
||||
compute-cb@4 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <4>;
|
||||
iommus = <&apps_smmu 0x1004 0x0>;
|
||||
};
|
||||
|
||||
compute-cb@5 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <5>;
|
||||
iommus = <&apps_smmu 0x1005 0x0>;
|
||||
qcom,nsessions = <5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mpss: remoteproc@4080000 {
|
||||
compatible = "qcom,sm6350-mpss-pas";
|
||||
reg = <0x0 0x04080000 0x0 0x4040>;
|
||||
|
||||
interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
|
||||
<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
|
||||
<&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
|
||||
<&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
|
||||
<&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
|
||||
<&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "wdog", "fatal", "ready", "handover",
|
||||
"stop-ack", "shutdown-ack";
|
||||
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "xo";
|
||||
|
||||
power-domains = <&rpmhpd SM6350_CX>,
|
||||
<&rpmhpd SM6350_MSS>;
|
||||
power-domain-names = "cx", "mss";
|
||||
|
||||
memory-region = <&pil_modem_mem>;
|
||||
|
||||
qcom,qmp = <&aoss_qmp>;
|
||||
|
||||
qcom,smem-states = <&modem_smp2p_out 0>;
|
||||
qcom,smem-state-names = "stop";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
glink-edge {
|
||||
interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
|
||||
IPCC_MPROC_SIGNAL_GLINK_QMP
|
||||
IRQ_TYPE_EDGE_RISING>;
|
||||
mboxes = <&ipcc IPCC_CLIENT_MPSS
|
||||
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
||||
label = "modem";
|
||||
qcom,remote-pid = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
cdsp: remoteproc@8300000 {
|
||||
compatible = "qcom,sm6350-cdsp-pas";
|
||||
reg = <0 0x08300000 0 0x10000>;
|
||||
|
||||
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
|
||||
<&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
|
||||
<&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
|
||||
<&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "wdog", "fatal", "ready",
|
||||
"handover", "stop-ack";
|
||||
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "xo";
|
||||
|
||||
power-domains = <&rpmhpd SM6350_CX>,
|
||||
<&rpmhpd SM6350_MX>;
|
||||
power-domain-names = "cx", "mx";
|
||||
|
||||
memory-region = <&pil_cdsp_mem>;
|
||||
|
||||
qcom,qmp = <&aoss_qmp>;
|
||||
|
||||
qcom,smem-states = <&smp2p_cdsp_out 0>;
|
||||
qcom,smem-state-names = "stop";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
glink-edge {
|
||||
interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
|
||||
IPCC_MPROC_SIGNAL_GLINK_QMP
|
||||
IRQ_TYPE_EDGE_RISING>;
|
||||
mboxes = <&ipcc IPCC_CLIENT_CDSP
|
||||
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
||||
|
||||
label = "cdsp";
|
||||
qcom,remote-pid = <5>;
|
||||
|
||||
fastrpc {
|
||||
compatible = "qcom,fastrpc";
|
||||
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
||||
label = "cdsp";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compute-cb@1 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <1>;
|
||||
iommus = <&apps_smmu 0x1401 0x20>;
|
||||
};
|
||||
|
||||
compute-cb@2 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <2>;
|
||||
iommus = <&apps_smmu 0x1402 0x20>;
|
||||
};
|
||||
|
||||
compute-cb@3 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <3>;
|
||||
iommus = <&apps_smmu 0x1403 0x20>;
|
||||
};
|
||||
|
||||
compute-cb@4 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <4>;
|
||||
iommus = <&apps_smmu 0x1404 0x20>;
|
||||
};
|
||||
|
||||
compute-cb@5 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <5>;
|
||||
iommus = <&apps_smmu 0x1405 0x20>;
|
||||
};
|
||||
|
||||
compute-cb@6 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <6>;
|
||||
iommus = <&apps_smmu 0x1406 0x20>;
|
||||
};
|
||||
|
||||
compute-cb@7 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <7>;
|
||||
iommus = <&apps_smmu 0x1407 0x20>;
|
||||
};
|
||||
|
||||
compute-cb@8 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <8>;
|
||||
iommus = <&apps_smmu 0x1408 0x20>;
|
||||
};
|
||||
|
||||
/* note: secure cb9 in downstream */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sdhc_2: sdhci@8804000 {
|
||||
compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
|
||||
reg = <0 0x08804000 0 0x1000>;
|
||||
|
|
@ -531,10 +810,10 @@ usb_1_qmpphy: phy@88e9000 {
|
|||
ranges;
|
||||
|
||||
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
|
||||
<&xo_board>,
|
||||
<&rpmhcc RPMH_QLINK_CLK>,
|
||||
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
|
||||
<&xo_board>;
|
||||
clock-names = "aux", "ref", "com_aux", "cfg_ahb";
|
||||
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
|
||||
clock-names = "aux", "cfg_ahb", "ref", "com_aux";
|
||||
|
||||
resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
|
||||
<&gcc GCC_USB3_PHY_PRIM_BCR>;
|
||||
|
|
@ -592,11 +871,12 @@ usb_1: usb@a6f8800 {
|
|||
"sleep";
|
||||
|
||||
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 14 IRQ_TYPE_EDGE_BOTH>,
|
||||
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
|
||||
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
|
||||
"dm_hs_phy_irq", "ss_phy_irq";
|
||||
<&pdc 14 IRQ_TYPE_EDGE_BOTH>;
|
||||
|
||||
interrupt-names = "hs_phy_irq", "ss_phy_irq",
|
||||
"dm_hs_phy_irq", "dp_hs_phy_irq";
|
||||
|
||||
power-domains = <&gcc USB30_PRIM_GDSC>;
|
||||
|
||||
|
|
@ -631,7 +911,7 @@ tsens0: thermal-sensor@c263000 {
|
|||
reg = <0 0x0c263000 0 0x1ff>, /* TM */
|
||||
<0 0x0c222000 0 0x8>; /* SROT */
|
||||
#qcom,sensors = <16>;
|
||||
interrupts = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
|
||||
interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "uplow", "critical";
|
||||
#thermal-sensor-cells = <1>;
|
||||
|
|
@ -642,7 +922,7 @@ tsens1: thermal-sensor@c265000 {
|
|||
reg = <0 0x0c265000 0 0x1ff>, /* TM */
|
||||
<0 0x0c223000 0 0x8>; /* SROT */
|
||||
#qcom,sensors = <16>;
|
||||
interrupts = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
|
||||
interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "uplow", "critical";
|
||||
#thermal-sensor-cells = <1>;
|
||||
|
|
@ -656,7 +936,6 @@ aoss_qmp: power-controller@c300000 {
|
|||
mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
||||
|
||||
#clock-cells = <0>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
spmi_bus: spmi@c440000 {
|
||||
|
|
|
|||
|
|
@ -15,6 +15,7 @@
|
|||
/ {
|
||||
model = "Fairphone 4";
|
||||
compatible = "fairphone,fp4", "qcom,sm7225";
|
||||
chassis-type = "handset";
|
||||
|
||||
/* required for bootloader to select correct board */
|
||||
qcom,msm-id = <434 0x10000>, <459 0x10000>;
|
||||
|
|
@ -52,6 +53,27 @@ volume-up {
|
|||
gpios = <&pm6350_gpios 2 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
/*
|
||||
* The rmtfs memory region in downstream is 'dynamically allocated'
|
||||
* but given the same address every time. Hard code it as this address is
|
||||
* where the modem firmware expects it to be.
|
||||
*/
|
||||
memory@efe01000 {
|
||||
compatible = "qcom,rmtfs-mem";
|
||||
reg = <0 0xefe01000 0 0x600000>;
|
||||
no-map;
|
||||
|
||||
qcom,client-id = <1>;
|
||||
qcom,vmid = <15>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&adsp {
|
||||
status = "okay";
|
||||
firmware-name = "qcom/sm7225/fairphone4/adsp.mdt";
|
||||
};
|
||||
|
||||
&apps_rsc {
|
||||
|
|
@ -268,6 +290,16 @@ vreg_bob: bob {
|
|||
};
|
||||
};
|
||||
|
||||
&cdsp {
|
||||
status = "okay";
|
||||
firmware-name = "qcom/sm7225/fairphone4/cdsp.mdt";
|
||||
};
|
||||
|
||||
&mpss {
|
||||
status = "okay";
|
||||
firmware-name = "qcom/sm7225/fairphone4/modem.mdt";
|
||||
};
|
||||
|
||||
&pm6350_gpios {
|
||||
gpio_keys_pin: gpio-keys-pin {
|
||||
pins = "gpio2";
|
||||
|
|
|
|||
|
|
@ -1785,7 +1785,6 @@ gpu: gpu@2c00000 {
|
|||
compatible = "qcom,adreno-640.1",
|
||||
"qcom,adreno",
|
||||
"amd,imageon";
|
||||
#stream-id-cells = <16>;
|
||||
|
||||
reg = <0 0x02c00000 0 0x40000>;
|
||||
reg-names = "kgsl_3d0_reg_memory";
|
||||
|
|
|
|||
|
|
@ -6,6 +6,9 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
|
||||
#include <dt-bindings/sound/qcom,q6afe.h>
|
||||
#include <dt-bindings/sound/qcom,q6asm.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "sm8250.dtsi"
|
||||
#include "pm8150.dtsi"
|
||||
#include "pm8150b.dtsi"
|
||||
|
|
@ -624,8 +627,196 @@ &slpi {
|
|||
firmware-name = "qcom/sm8250/slpi.mbn";
|
||||
};
|
||||
|
||||
&soc {
|
||||
wcd938x: codec {
|
||||
compatible = "qcom,wcd9380-codec";
|
||||
#sound-dai-cells = <1>;
|
||||
reset-gpios = <&tlmm 32 0>;
|
||||
vdd-buck-supply = <&vreg_s4a_1p8>;
|
||||
vdd-rxtx-supply = <&vreg_s4a_1p8>;
|
||||
vdd-io-supply = <&vreg_s4a_1p8>;
|
||||
vdd-mic-bias-supply = <&vreg_bob>;
|
||||
qcom,micbias1-microvolt = <1800000>;
|
||||
qcom,micbias2-microvolt = <1800000>;
|
||||
qcom,micbias3-microvolt = <1800000>;
|
||||
qcom,micbias4-microvolt = <1800000>;
|
||||
qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
|
||||
qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
|
||||
qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
|
||||
qcom,rx-device = <&wcd_rx>;
|
||||
qcom,tx-device = <&wcd_tx>;
|
||||
};
|
||||
};
|
||||
|
||||
&sound {
|
||||
compatible = "qcom,sm8250-sndcard";
|
||||
model = "SM8250-MTP-WCD9380-WSA8810-VA-DMIC";
|
||||
audio-routing =
|
||||
"SpkrLeft IN", "WSA_SPK1 OUT",
|
||||
"SpkrRight IN", "WSA_SPK2 OUT",
|
||||
"IN1_HPHL", "HPHL_OUT",
|
||||
"IN2_HPHR", "HPHR_OUT",
|
||||
"AMIC1", "MIC BIAS1",
|
||||
"AMIC2", "MIC BIAS2",
|
||||
"AMIC3", "MIC BIAS3",
|
||||
"AMIC4", "MIC BIAS3",
|
||||
"AMIC5", "MIC BIAS4",
|
||||
"TX SWR_ADC0", "ADC1_OUTPUT",
|
||||
"TX SWR_ADC1", "ADC2_OUTPUT",
|
||||
"TX SWR_ADC2", "ADC3_OUTPUT",
|
||||
"TX SWR_ADC3", "ADC4_OUTPUT",
|
||||
"TX SWR_DMIC0", "DMIC1_OUTPUT",
|
||||
"TX SWR_DMIC1", "DMIC2_OUTPUT",
|
||||
"TX SWR_DMIC2", "DMIC3_OUTPUT",
|
||||
"TX SWR_DMIC3", "DMIC4_OUTPUT",
|
||||
"TX SWR_DMIC4", "DMIC5_OUTPUT",
|
||||
"TX SWR_DMIC5", "DMIC6_OUTPUT",
|
||||
"TX SWR_DMIC6", "DMIC7_OUTPUT",
|
||||
"TX SWR_DMIC7", "DMIC8_OUTPUT";
|
||||
|
||||
mm1-dai-link {
|
||||
link-name = "MultiMedia1";
|
||||
cpu {
|
||||
sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>;
|
||||
};
|
||||
};
|
||||
|
||||
mm2-dai-link {
|
||||
link-name = "MultiMedia2";
|
||||
cpu {
|
||||
sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>;
|
||||
};
|
||||
};
|
||||
|
||||
mm3-dai-link {
|
||||
link-name = "MultiMedia3";
|
||||
cpu {
|
||||
sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>;
|
||||
};
|
||||
};
|
||||
|
||||
wcd-playback-dai-link {
|
||||
link-name = "WCD Playback";
|
||||
cpu {
|
||||
sound-dai = <&q6afedai RX_CODEC_DMA_RX_0>;
|
||||
};
|
||||
codec {
|
||||
sound-dai = <&wcd938x 0>, <&swr1 0>, <&rxmacro 0>;
|
||||
};
|
||||
platform {
|
||||
sound-dai = <&q6routing>;
|
||||
};
|
||||
};
|
||||
|
||||
wcd-capture-dai-link {
|
||||
link-name = "WCD Capture";
|
||||
cpu {
|
||||
sound-dai = <&q6afedai TX_CODEC_DMA_TX_3>;
|
||||
};
|
||||
|
||||
codec {
|
||||
sound-dai = <&wcd938x 1>, <&swr2 0>, <&txmacro 0>;
|
||||
};
|
||||
platform {
|
||||
sound-dai = <&q6routing>;
|
||||
};
|
||||
};
|
||||
|
||||
wsa-dai-link {
|
||||
link-name = "WSA Playback";
|
||||
cpu {
|
||||
sound-dai = <&q6afedai WSA_CODEC_DMA_RX_0>;
|
||||
};
|
||||
|
||||
codec {
|
||||
sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&wsamacro 0>;
|
||||
};
|
||||
platform {
|
||||
sound-dai = <&q6routing>;
|
||||
};
|
||||
};
|
||||
|
||||
va-dai-link {
|
||||
link-name = "VA Capture";
|
||||
cpu {
|
||||
sound-dai = <&q6afedai VA_CODEC_DMA_TX_0>;
|
||||
};
|
||||
|
||||
platform {
|
||||
sound-dai = <&q6routing>;
|
||||
};
|
||||
|
||||
codec {
|
||||
sound-dai = <&vamacro 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&swr0 {
|
||||
left_spkr: wsa8810-right@0,3{
|
||||
compatible = "sdw10217211000";
|
||||
reg = <0 3>;
|
||||
powerdown-gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
sound-name-prefix = "SpkrLeft";
|
||||
#sound-dai-cells = <0>;
|
||||
};
|
||||
|
||||
right_spkr: wsa8810-left@0,4{
|
||||
compatible = "sdw10217211000";
|
||||
reg = <0 4>;
|
||||
powerdown-gpios = <&tlmm 127 GPIO_ACTIVE_HIGH>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
sound-name-prefix = "SpkrRight";
|
||||
#sound-dai-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&swr1 {
|
||||
wcd_rx: wcd9380-rx@0,4 {
|
||||
compatible = "sdw20217010d00";
|
||||
reg = <0 4>;
|
||||
qcom,rx-port-mapping = <1 2 3 4 5>;
|
||||
};
|
||||
};
|
||||
|
||||
&swr2 {
|
||||
wcd_tx: wcd9380-tx@0,3 {
|
||||
compatible = "sdw20217010d00";
|
||||
reg = <0 3>;
|
||||
qcom,tx-port-mapping = <2 3 4 5>;
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
gpio-reserved-ranges = <28 4>, <40 4>;
|
||||
|
||||
wcd938x_reset_default: wcd938x_reset_default {
|
||||
mux {
|
||||
pins = "gpio32";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio32";
|
||||
drive-strength = <16>;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
wcd938x_reset_sleep: wcd938x_reset_sleep {
|
||||
mux {
|
||||
pins = "gpio32";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio32";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
output-low;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart12 {
|
||||
|
|
|
|||
|
|
@ -99,6 +99,9 @@ CPU0: cpu@0 {
|
|||
dynamic-power-coefficient = <205>;
|
||||
next-level-cache = <&L2_0>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
|
||||
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
|
||||
#cooling-cells = <2>;
|
||||
L2_0: l2-cache {
|
||||
compatible = "cache";
|
||||
|
|
@ -118,6 +121,9 @@ CPU1: cpu@100 {
|
|||
dynamic-power-coefficient = <205>;
|
||||
next-level-cache = <&L2_100>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
|
||||
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
|
||||
#cooling-cells = <2>;
|
||||
L2_100: l2-cache {
|
||||
compatible = "cache";
|
||||
|
|
@ -134,6 +140,9 @@ CPU2: cpu@200 {
|
|||
dynamic-power-coefficient = <205>;
|
||||
next-level-cache = <&L2_200>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
|
||||
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
|
||||
#cooling-cells = <2>;
|
||||
L2_200: l2-cache {
|
||||
compatible = "cache";
|
||||
|
|
@ -150,6 +159,9 @@ CPU3: cpu@300 {
|
|||
dynamic-power-coefficient = <205>;
|
||||
next-level-cache = <&L2_300>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
|
||||
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
|
||||
#cooling-cells = <2>;
|
||||
L2_300: l2-cache {
|
||||
compatible = "cache";
|
||||
|
|
@ -166,6 +178,9 @@ CPU4: cpu@400 {
|
|||
dynamic-power-coefficient = <379>;
|
||||
next-level-cache = <&L2_400>;
|
||||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
operating-points-v2 = <&cpu4_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
|
||||
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
|
||||
#cooling-cells = <2>;
|
||||
L2_400: l2-cache {
|
||||
compatible = "cache";
|
||||
|
|
@ -182,6 +197,9 @@ CPU5: cpu@500 {
|
|||
dynamic-power-coefficient = <379>;
|
||||
next-level-cache = <&L2_500>;
|
||||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
operating-points-v2 = <&cpu4_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
|
||||
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
|
||||
#cooling-cells = <2>;
|
||||
L2_500: l2-cache {
|
||||
compatible = "cache";
|
||||
|
|
@ -199,6 +217,9 @@ CPU6: cpu@600 {
|
|||
dynamic-power-coefficient = <379>;
|
||||
next-level-cache = <&L2_600>;
|
||||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
operating-points-v2 = <&cpu4_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
|
||||
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
|
||||
#cooling-cells = <2>;
|
||||
L2_600: l2-cache {
|
||||
compatible = "cache";
|
||||
|
|
@ -215,6 +236,9 @@ CPU7: cpu@700 {
|
|||
dynamic-power-coefficient = <444>;
|
||||
next-level-cache = <&L2_700>;
|
||||
qcom,freq-domain = <&cpufreq_hw 2>;
|
||||
operating-points-v2 = <&cpu7_opp_table>;
|
||||
interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
|
||||
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
|
||||
#cooling-cells = <2>;
|
||||
L2_700: l2-cache {
|
||||
compatible = "cache";
|
||||
|
|
@ -259,6 +283,296 @@ core7 {
|
|||
};
|
||||
};
|
||||
|
||||
cpu0_opp_table: cpu0_opp_table {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
cpu0_opp1: opp-300000000 {
|
||||
opp-hz = /bits/ 64 <300000000>;
|
||||
opp-peak-kBps = <800000 9600000>;
|
||||
};
|
||||
|
||||
cpu0_opp2: opp-403200000 {
|
||||
opp-hz = /bits/ 64 <403200000>;
|
||||
opp-peak-kBps = <800000 9600000>;
|
||||
};
|
||||
|
||||
cpu0_opp3: opp-518400000 {
|
||||
opp-hz = /bits/ 64 <518400000>;
|
||||
opp-peak-kBps = <800000 16588800>;
|
||||
};
|
||||
|
||||
cpu0_opp4: opp-614400000 {
|
||||
opp-hz = /bits/ 64 <614400000>;
|
||||
opp-peak-kBps = <800000 16588800>;
|
||||
};
|
||||
|
||||
cpu0_opp5: opp-691200000 {
|
||||
opp-hz = /bits/ 64 <691200000>;
|
||||
opp-peak-kBps = <800000 19660800>;
|
||||
};
|
||||
|
||||
cpu0_opp6: opp-787200000 {
|
||||
opp-hz = /bits/ 64 <787200000>;
|
||||
opp-peak-kBps = <1804000 19660800>;
|
||||
};
|
||||
|
||||
cpu0_opp7: opp-883200000 {
|
||||
opp-hz = /bits/ 64 <883200000>;
|
||||
opp-peak-kBps = <1804000 23347200>;
|
||||
};
|
||||
|
||||
cpu0_opp8: opp-979200000 {
|
||||
opp-hz = /bits/ 64 <979200000>;
|
||||
opp-peak-kBps = <1804000 26419200>;
|
||||
};
|
||||
|
||||
cpu0_opp9: opp-1075200000 {
|
||||
opp-hz = /bits/ 64 <1075200000>;
|
||||
opp-peak-kBps = <1804000 29491200>;
|
||||
};
|
||||
|
||||
cpu0_opp10: opp-1171200000 {
|
||||
opp-hz = /bits/ 64 <1171200000>;
|
||||
opp-peak-kBps = <1804000 32563200>;
|
||||
};
|
||||
|
||||
cpu0_opp11: opp-1248000000 {
|
||||
opp-hz = /bits/ 64 <1248000000>;
|
||||
opp-peak-kBps = <1804000 36249600>;
|
||||
};
|
||||
|
||||
cpu0_opp12: opp-1344000000 {
|
||||
opp-hz = /bits/ 64 <1344000000>;
|
||||
opp-peak-kBps = <2188000 36249600>;
|
||||
};
|
||||
|
||||
cpu0_opp13: opp-1420800000 {
|
||||
opp-hz = /bits/ 64 <1420800000>;
|
||||
opp-peak-kBps = <2188000 39321600>;
|
||||
};
|
||||
|
||||
cpu0_opp14: opp-1516800000 {
|
||||
opp-hz = /bits/ 64 <1516800000>;
|
||||
opp-peak-kBps = <3072000 42393600>;
|
||||
};
|
||||
|
||||
cpu0_opp15: opp-1612800000 {
|
||||
opp-hz = /bits/ 64 <1612800000>;
|
||||
opp-peak-kBps = <3072000 42393600>;
|
||||
};
|
||||
|
||||
cpu0_opp16: opp-1708800000 {
|
||||
opp-hz = /bits/ 64 <1708800000>;
|
||||
opp-peak-kBps = <4068000 42393600>;
|
||||
};
|
||||
|
||||
cpu0_opp17: opp-1804800000 {
|
||||
opp-hz = /bits/ 64 <1804800000>;
|
||||
opp-peak-kBps = <4068000 42393600>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu4_opp_table: cpu4_opp_table {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
cpu4_opp1: opp-710400000 {
|
||||
opp-hz = /bits/ 64 <710400000>;
|
||||
opp-peak-kBps = <1804000 19660800>;
|
||||
};
|
||||
|
||||
cpu4_opp2: opp-825600000 {
|
||||
opp-hz = /bits/ 64 <825600000>;
|
||||
opp-peak-kBps = <2188000 23347200>;
|
||||
};
|
||||
|
||||
cpu4_opp3: opp-940800000 {
|
||||
opp-hz = /bits/ 64 <940800000>;
|
||||
opp-peak-kBps = <2188000 26419200>;
|
||||
};
|
||||
|
||||
cpu4_opp4: opp-1056000000 {
|
||||
opp-hz = /bits/ 64 <1056000000>;
|
||||
opp-peak-kBps = <3072000 26419200>;
|
||||
};
|
||||
|
||||
cpu4_opp5: opp-1171200000 {
|
||||
opp-hz = /bits/ 64 <1171200000>;
|
||||
opp-peak-kBps = <3072000 29491200>;
|
||||
};
|
||||
|
||||
cpu4_opp6: opp-1286400000 {
|
||||
opp-hz = /bits/ 64 <1286400000>;
|
||||
opp-peak-kBps = <4068000 29491200>;
|
||||
};
|
||||
|
||||
cpu4_opp7: opp-1382400000 {
|
||||
opp-hz = /bits/ 64 <1382400000>;
|
||||
opp-peak-kBps = <4068000 32563200>;
|
||||
};
|
||||
|
||||
cpu4_opp8: opp-1478400000 {
|
||||
opp-hz = /bits/ 64 <1478400000>;
|
||||
opp-peak-kBps = <4068000 32563200>;
|
||||
};
|
||||
|
||||
cpu4_opp9: opp-1574400000 {
|
||||
opp-hz = /bits/ 64 <1574400000>;
|
||||
opp-peak-kBps = <5412000 39321600>;
|
||||
};
|
||||
|
||||
cpu4_opp10: opp-1670400000 {
|
||||
opp-hz = /bits/ 64 <1670400000>;
|
||||
opp-peak-kBps = <5412000 42393600>;
|
||||
};
|
||||
|
||||
cpu4_opp11: opp-1766400000 {
|
||||
opp-hz = /bits/ 64 <1766400000>;
|
||||
opp-peak-kBps = <5412000 45465600>;
|
||||
};
|
||||
|
||||
cpu4_opp12: opp-1862400000 {
|
||||
opp-hz = /bits/ 64 <1862400000>;
|
||||
opp-peak-kBps = <6220000 45465600>;
|
||||
};
|
||||
|
||||
cpu4_opp13: opp-1958400000 {
|
||||
opp-hz = /bits/ 64 <1958400000>;
|
||||
opp-peak-kBps = <6220000 48537600>;
|
||||
};
|
||||
|
||||
cpu4_opp14: opp-2054400000 {
|
||||
opp-hz = /bits/ 64 <2054400000>;
|
||||
opp-peak-kBps = <7216000 48537600>;
|
||||
};
|
||||
|
||||
cpu4_opp15: opp-2150400000 {
|
||||
opp-hz = /bits/ 64 <2150400000>;
|
||||
opp-peak-kBps = <7216000 51609600>;
|
||||
};
|
||||
|
||||
cpu4_opp16: opp-2246400000 {
|
||||
opp-hz = /bits/ 64 <2246400000>;
|
||||
opp-peak-kBps = <7216000 51609600>;
|
||||
};
|
||||
|
||||
cpu4_opp17: opp-2342400000 {
|
||||
opp-hz = /bits/ 64 <2342400000>;
|
||||
opp-peak-kBps = <8368000 51609600>;
|
||||
};
|
||||
|
||||
cpu4_opp18: opp-2419200000 {
|
||||
opp-hz = /bits/ 64 <2419200000>;
|
||||
opp-peak-kBps = <8368000 51609600>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu7_opp_table: cpu7_opp_table {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
cpu7_opp1: opp-844800000 {
|
||||
opp-hz = /bits/ 64 <844800000>;
|
||||
opp-peak-kBps = <2188000 19660800>;
|
||||
};
|
||||
|
||||
cpu7_opp2: opp-960000000 {
|
||||
opp-hz = /bits/ 64 <960000000>;
|
||||
opp-peak-kBps = <2188000 26419200>;
|
||||
};
|
||||
|
||||
cpu7_opp3: opp-1075200000 {
|
||||
opp-hz = /bits/ 64 <1075200000>;
|
||||
opp-peak-kBps = <3072000 26419200>;
|
||||
};
|
||||
|
||||
cpu7_opp4: opp-1190400000 {
|
||||
opp-hz = /bits/ 64 <1190400000>;
|
||||
opp-peak-kBps = <3072000 29491200>;
|
||||
};
|
||||
|
||||
cpu7_opp5: opp-1305600000 {
|
||||
opp-hz = /bits/ 64 <1305600000>;
|
||||
opp-peak-kBps = <4068000 32563200>;
|
||||
};
|
||||
|
||||
cpu7_opp6: opp-1401600000 {
|
||||
opp-hz = /bits/ 64 <1401600000>;
|
||||
opp-peak-kBps = <4068000 32563200>;
|
||||
};
|
||||
|
||||
cpu7_opp7: opp-1516800000 {
|
||||
opp-hz = /bits/ 64 <1516800000>;
|
||||
opp-peak-kBps = <4068000 36249600>;
|
||||
};
|
||||
|
||||
cpu7_opp8: opp-1632000000 {
|
||||
opp-hz = /bits/ 64 <1632000000>;
|
||||
opp-peak-kBps = <5412000 39321600>;
|
||||
};
|
||||
|
||||
cpu7_opp9: opp-1747200000 {
|
||||
opp-hz = /bits/ 64 <1708800000>;
|
||||
opp-peak-kBps = <5412000 42393600>;
|
||||
};
|
||||
|
||||
cpu7_opp10: opp-1862400000 {
|
||||
opp-hz = /bits/ 64 <1862400000>;
|
||||
opp-peak-kBps = <6220000 45465600>;
|
||||
};
|
||||
|
||||
cpu7_opp11: opp-1977600000 {
|
||||
opp-hz = /bits/ 64 <1977600000>;
|
||||
opp-peak-kBps = <6220000 48537600>;
|
||||
};
|
||||
|
||||
cpu7_opp12: opp-2073600000 {
|
||||
opp-hz = /bits/ 64 <2073600000>;
|
||||
opp-peak-kBps = <7216000 48537600>;
|
||||
};
|
||||
|
||||
cpu7_opp13: opp-2169600000 {
|
||||
opp-hz = /bits/ 64 <2169600000>;
|
||||
opp-peak-kBps = <7216000 51609600>;
|
||||
};
|
||||
|
||||
cpu7_opp14: opp-2265600000 {
|
||||
opp-hz = /bits/ 64 <2265600000>;
|
||||
opp-peak-kBps = <7216000 51609600>;
|
||||
};
|
||||
|
||||
cpu7_opp15: opp-2361600000 {
|
||||
opp-hz = /bits/ 64 <2361600000>;
|
||||
opp-peak-kBps = <8368000 51609600>;
|
||||
};
|
||||
|
||||
cpu7_opp16: opp-2457600000 {
|
||||
opp-hz = /bits/ 64 <2457600000>;
|
||||
opp-peak-kBps = <8368000 51609600>;
|
||||
};
|
||||
|
||||
cpu7_opp17: opp-2553600000 {
|
||||
opp-hz = /bits/ 64 <2553600000>;
|
||||
opp-peak-kBps = <8368000 51609600>;
|
||||
};
|
||||
|
||||
cpu7_opp18: opp-2649600000 {
|
||||
opp-hz = /bits/ 64 <2649600000>;
|
||||
opp-peak-kBps = <8368000 51609600>;
|
||||
};
|
||||
|
||||
cpu7_opp19: opp-2745600000 {
|
||||
opp-hz = /bits/ 64 <2745600000>;
|
||||
opp-peak-kBps = <8368000 51609600>;
|
||||
};
|
||||
|
||||
cpu7_opp20: opp-2841600000 {
|
||||
opp-hz = /bits/ 64 <2841600000>;
|
||||
opp-peak-kBps = <8368000 51609600>;
|
||||
};
|
||||
};
|
||||
|
||||
firmware {
|
||||
scm: scm {
|
||||
compatible = "qcom,scm";
|
||||
|
|
@ -1831,6 +2145,101 @@ vamacro: codec@3370000 {
|
|||
#sound-dai-cells = <1>;
|
||||
};
|
||||
|
||||
rxmacro: rxmacro@3200000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rx_swr_active>;
|
||||
compatible = "qcom,sm8250-lpass-rx-macro";
|
||||
reg = <0 0x3200000 0 0x1000>;
|
||||
|
||||
clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
||||
<&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
||||
<&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
||||
<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
||||
<&vamacro>;
|
||||
|
||||
clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
|
||||
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <9600000>;
|
||||
clock-output-names = "mclk";
|
||||
#sound-dai-cells = <1>;
|
||||
};
|
||||
|
||||
swr1: soundwire-controller@3210000 {
|
||||
reg = <0 0x3210000 0 0x2000>;
|
||||
compatible = "qcom,soundwire-v1.5.1";
|
||||
interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rxmacro>;
|
||||
clock-names = "iface";
|
||||
label = "RX";
|
||||
qcom,din-ports = <0>;
|
||||
qcom,dout-ports = <5>;
|
||||
|
||||
qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1F 0x1F 0x07 0x00>;
|
||||
qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
|
||||
qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
|
||||
qcom,ports-hstart = /bits/ 8 <0xFF 0x03 0xFF 0xFF 0xFF>;
|
||||
qcom,ports-hstop = /bits/ 8 <0xFF 0x06 0xFF 0xFF 0xFF>;
|
||||
qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xFF 0xFF>;
|
||||
qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0x00 0x01 0xFF 0xFF>;
|
||||
qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
|
||||
qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0x00>;
|
||||
|
||||
#sound-dai-cells = <1>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
txmacro: txmacro@3220000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&tx_swr_active>;
|
||||
compatible = "qcom,sm8250-lpass-tx-macro";
|
||||
reg = <0 0x3220000 0 0x1000>;
|
||||
|
||||
clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
||||
<&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
||||
<&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
||||
<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
||||
<&vamacro>;
|
||||
|
||||
clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
|
||||
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <9600000>;
|
||||
clock-output-names = "mclk";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
#sound-dai-cells = <1>;
|
||||
};
|
||||
|
||||
/* tx macro */
|
||||
swr2: soundwire-controller@3230000 {
|
||||
reg = <0 0x3230000 0 0x2000>;
|
||||
compatible = "qcom,soundwire-v1.5.1";
|
||||
interrupts-extended = <&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "core";
|
||||
|
||||
clocks = <&txmacro>;
|
||||
clock-names = "iface";
|
||||
label = "TX";
|
||||
|
||||
qcom,din-ports = <5>;
|
||||
qcom,dout-ports = <0>;
|
||||
qcom,ports-sinterval-low = /bits/ 8 <0xFF 0x01 0x01 0x03 0x03>;
|
||||
qcom,ports-offset1 = /bits/ 8 <0xFF 0x01 0x00 0x02 0x00>;
|
||||
qcom,ports-offset2 = /bits/ 8 <0xFF 0x00 0x00 0x00 0x00>;
|
||||
qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
|
||||
qcom,ports-hstart = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
|
||||
qcom,ports-hstop = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
|
||||
qcom,ports-word-length = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
|
||||
qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
|
||||
qcom,ports-lane-control = /bits/ 8 <0xFF 0x00 0x01 0x00 0x01>;
|
||||
qcom,port-offset = <1>;
|
||||
#sound-dai-cells = <1>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
aoncc: clock-controller@3380000 {
|
||||
compatible = "qcom,sm8250-lpass-aoncc";
|
||||
reg = <0 0x03380000 0 0x40000>;
|
||||
|
|
@ -1923,12 +2332,73 @@ data {
|
|||
input-enable;
|
||||
};
|
||||
};
|
||||
|
||||
rx_swr_active: rx_swr-active-pins {
|
||||
clk {
|
||||
pins = "gpio3";
|
||||
function = "swr_rx_clk";
|
||||
drive-strength = <2>;
|
||||
slew-rate = <1>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
data {
|
||||
pins = "gpio4", "gpio5";
|
||||
function = "swr_rx_data";
|
||||
drive-strength = <2>;
|
||||
slew-rate = <1>;
|
||||
bias-bus-hold;
|
||||
};
|
||||
};
|
||||
|
||||
tx_swr_active: tx_swr-active-pins {
|
||||
clk {
|
||||
pins = "gpio0";
|
||||
function = "swr_tx_clk";
|
||||
drive-strength = <2>;
|
||||
slew-rate = <1>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
data {
|
||||
pins = "gpio1", "gpio2";
|
||||
function = "swr_tx_data";
|
||||
drive-strength = <2>;
|
||||
slew-rate = <1>;
|
||||
bias-bus-hold;
|
||||
};
|
||||
};
|
||||
|
||||
tx_swr_sleep: tx_swr-sleep-pins {
|
||||
clk {
|
||||
pins = "gpio0";
|
||||
function = "swr_tx_clk";
|
||||
drive-strength = <2>;
|
||||
input-enable;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
data1 {
|
||||
pins = "gpio1";
|
||||
function = "swr_tx_data";
|
||||
drive-strength = <2>;
|
||||
input-enable;
|
||||
bias-bus-hold;
|
||||
};
|
||||
|
||||
data2 {
|
||||
pins = "gpio2";
|
||||
function = "swr_tx_data";
|
||||
drive-strength = <2>;
|
||||
input-enable;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpu: gpu@3d00000 {
|
||||
compatible = "qcom,adreno-650.2",
|
||||
"qcom,adreno";
|
||||
#stream-id-cells = <16>;
|
||||
|
||||
reg = <0 0x03d00000 0 0x40000>;
|
||||
reg-names = "kgsl_3d0_reg_memory";
|
||||
|
|
|
|||
|
|
@ -5,7 +5,6 @@
|
|||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
|
||||
#include "sm8350.dtsi"
|
||||
|
||||
|
|
|
|||
369
arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts
Normal file
369
arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts
Normal file
|
|
@ -0,0 +1,369 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (C) 2021, Microsoft Corporation
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
|
||||
#include "sm8350.dtsi"
|
||||
#include "pm8350.dtsi"
|
||||
#include "pm8350b.dtsi"
|
||||
#include "pm8350c.dtsi"
|
||||
#include "pmk8350.dtsi"
|
||||
#include "pmr735a.dtsi"
|
||||
#include "pmr735b.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Microsoft Surface Duo 2";
|
||||
compatible = "microsoft,surface-duo2", "qcom,sm8350";
|
||||
chassis-type = "handset";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
vph_pwr: vph-pwr-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vph_pwr";
|
||||
regulator-min-microvolt = <3700000>;
|
||||
regulator-max-microvolt = <3700000>;
|
||||
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
|
||||
&adsp {
|
||||
status = "okay";
|
||||
firmware-name = "qcom/sm8350/microsoft/adsp.mbn";
|
||||
};
|
||||
|
||||
&apps_rsc {
|
||||
pm8350-rpmh-regulators {
|
||||
compatible = "qcom,pm8350-rpmh-regulators";
|
||||
qcom,pmic-id = "b";
|
||||
|
||||
vdd-s1-supply = <&vph_pwr>;
|
||||
vdd-s2-supply = <&vph_pwr>;
|
||||
vdd-s3-supply = <&vph_pwr>;
|
||||
vdd-s4-supply = <&vph_pwr>;
|
||||
vdd-s5-supply = <&vph_pwr>;
|
||||
vdd-s6-supply = <&vph_pwr>;
|
||||
vdd-s7-supply = <&vph_pwr>;
|
||||
vdd-s8-supply = <&vph_pwr>;
|
||||
vdd-s9-supply = <&vph_pwr>;
|
||||
vdd-s10-supply = <&vph_pwr>;
|
||||
vdd-s11-supply = <&vph_pwr>;
|
||||
vdd-s12-supply = <&vph_pwr>;
|
||||
|
||||
vdd-l1-l4-supply = <&vreg_s11b_0p95>;
|
||||
vdd-l2-l7-supply = <&vreg_bob>;
|
||||
vdd-l3-l5-supply = <&vreg_bob>;
|
||||
vdd-l6-l9-l10-supply = <&vreg_s11b_0p95>;
|
||||
vdd-l8-supply = <&vreg_s2c_0p8>;
|
||||
|
||||
vreg_s10b_1p8: smps10 {
|
||||
regulator-name = "vreg_s10b_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
vreg_s11b_0p95: smps11 {
|
||||
regulator-name = "vreg_s11b_0p95";
|
||||
regulator-min-microvolt = <752000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
};
|
||||
|
||||
vreg_s12b_1p25: smps12 {
|
||||
regulator-name = "vreg_s12b_1p25";
|
||||
regulator-min-microvolt = <1224000>;
|
||||
regulator-max-microvolt = <1360000>;
|
||||
};
|
||||
|
||||
vreg_l1b_0p88: ldo1 {
|
||||
regulator-name = "vreg_l1b_0p88";
|
||||
regulator-min-microvolt = <912000>;
|
||||
regulator-max-microvolt = <920000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l2b_3p07: ldo2 {
|
||||
regulator-name = "vreg_l2b_3p07";
|
||||
regulator-min-microvolt = <3072000>;
|
||||
regulator-max-microvolt = <3072000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l3b_0p9: ldo3 {
|
||||
regulator-name = "vreg_l3b_0p9";
|
||||
regulator-min-microvolt = <904000>;
|
||||
regulator-max-microvolt = <904000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l5b_0p88: ldo5 {
|
||||
regulator-name = "vreg_l3b_0p9";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <888000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l6b_1p2: ldo6 {
|
||||
regulator-name = "vreg_l6b_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1208000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l7b_2p96: ldo7 {
|
||||
regulator-name = "vreg_l7b_2p96";
|
||||
regulator-min-microvolt = <2400000>;
|
||||
regulator-max-microvolt = <3008000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l9b_1p2: ldo9 {
|
||||
regulator-name = "vreg_l9b_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
pm8350c-rpmh-regulators {
|
||||
compatible = "qcom,pm8350c-rpmh-regulators";
|
||||
qcom,pmic-id = "c";
|
||||
|
||||
vdd-s1-supply = <&vph_pwr>;
|
||||
vdd-s2-supply = <&vph_pwr>;
|
||||
vdd-s3-supply = <&vph_pwr>;
|
||||
vdd-s4-supply = <&vph_pwr>;
|
||||
vdd-s5-supply = <&vph_pwr>;
|
||||
vdd-s6-supply = <&vph_pwr>;
|
||||
vdd-s7-supply = <&vph_pwr>;
|
||||
vdd-s8-supply = <&vph_pwr>;
|
||||
vdd-s9-supply = <&vph_pwr>;
|
||||
vdd-s10-supply = <&vph_pwr>;
|
||||
|
||||
vdd-l1-l12-supply = <&vreg_s1c_1p86>;
|
||||
vdd-l2-l8-supply = <&vreg_s1c_1p86>;
|
||||
vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>;
|
||||
vdd-l6-l9-l11-supply = <&vreg_bob>;
|
||||
vdd-l10-supply = <&vreg_s12b_1p25>;
|
||||
|
||||
vdd-bob-supply = <&vph_pwr>;
|
||||
|
||||
vreg_s1c_1p86: smps1 {
|
||||
regulator-name = "vreg_s1c_1p86";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1952000>;
|
||||
};
|
||||
|
||||
vreg_s2c_0p8: smps2 {
|
||||
regulator-name = "vreg_s2c_0p8";
|
||||
regulator-min-microvolt = <640000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
};
|
||||
|
||||
vreg_s10c_1p05: smps10 {
|
||||
regulator-name = "vreg_s10c_1p05";
|
||||
regulator-min-microvolt = <1048000>;
|
||||
regulator-max-microvolt = <1128000>;
|
||||
};
|
||||
|
||||
vreg_bob: bob {
|
||||
regulator-name = "vreg_bob";
|
||||
regulator-min-microvolt = <3008000>;
|
||||
regulator-max-microvolt = <3960000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l1c_1p8: ldo1 {
|
||||
regulator-name = "vreg_l1c_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l2c_1p8: ldo2 {
|
||||
regulator-name = "vreg_l2c_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l3c_3p0: ldo3 {
|
||||
regulator-name = "vreg_l3c_3p0";
|
||||
regulator-min-microvolt = <3008000>;
|
||||
regulator-max-microvolt = <3008000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l4c_uim1: ldo4 {
|
||||
regulator-name = "vreg_l4c_uim1";
|
||||
regulator-min-microvolt = <1704000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l5c_uim2: ldo5 {
|
||||
regulator-name = "vreg_l5c_uim2";
|
||||
regulator-min-microvolt = <1704000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l6c_1p8: ldo6 {
|
||||
regulator-name = "vreg_l6c_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2960000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l7c_3p0: ldo7 {
|
||||
regulator-name = "vreg_l7c_3p0";
|
||||
regulator-min-microvolt = <3008000>;
|
||||
regulator-max-microvolt = <3008000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l8c_1p8: ldo8 {
|
||||
regulator-name = "vreg_l8c_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l9c_2p96: ldo9 {
|
||||
regulator-name = "vreg_l9c_2p96";
|
||||
regulator-min-microvolt = <2960000>;
|
||||
regulator-max-microvolt = <3008000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l10c_1p2: ldo10 {
|
||||
regulator-name = "vreg_l10c_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l11c_2p96: ldo11 {
|
||||
regulator-name = "vreg_l11c_2p96";
|
||||
regulator-min-microvolt = <2400000>;
|
||||
regulator-max-microvolt = <3008000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l12c_1p8: ldo12 {
|
||||
regulator-name = "vreg_l12c_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l13c_3p0: ldo13 {
|
||||
regulator-name = "vreg_l13c_3p0";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cdsp {
|
||||
status = "okay";
|
||||
firmware-name = "qcom/sm8350/microsoft/cdsp.mbn";
|
||||
};
|
||||
|
||||
&ipa {
|
||||
status = "okay";
|
||||
|
||||
memory-region = <&pil_ipa_fw_mem>;
|
||||
};
|
||||
|
||||
&mpss {
|
||||
status = "okay";
|
||||
firmware-name = "qcom/sm8350/microsoft/modem.mbn";
|
||||
};
|
||||
|
||||
&qupv3_id_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&slpi {
|
||||
status = "okay";
|
||||
firmware-name = "qcom/sm8350/microsoft/slpi.mbn";
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
gpio-reserved-ranges = <4 4>, <12 4>, <56 4>, <76 4>;
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ufs_mem_hc {
|
||||
status = "okay";
|
||||
|
||||
reset-gpios = <&tlmm 203 GPIO_ACTIVE_LOW>;
|
||||
|
||||
vcc-supply = <&vreg_l7b_2p96>;
|
||||
vcc-max-microamp = <800000>;
|
||||
vccq-supply = <&vreg_l9b_1p2>;
|
||||
vccq-max-microamp = <900000>;
|
||||
};
|
||||
|
||||
&ufs_mem_phy {
|
||||
status = "okay";
|
||||
|
||||
vdda-phy-supply = <&vreg_l5b_0p88>;
|
||||
vdda-max-microamp = <91600>;
|
||||
vdda-pll-supply = <&vreg_l6b_1p2>;
|
||||
vdda-pll-max-microamp = <19000>;
|
||||
};
|
||||
|
||||
&usb_1 {
|
||||
status = "okay";
|
||||
dr_mode = "peripheral";
|
||||
};
|
||||
|
||||
&usb_1_hsphy {
|
||||
status = "okay";
|
||||
|
||||
vdda-pll-supply = <&vreg_l5b_0p88>;
|
||||
vdda18-supply = <&vreg_l1c_1p8>;
|
||||
vdda33-supply = <&vreg_l2b_3p07>;
|
||||
};
|
||||
|
||||
&usb_1_qmpphy {
|
||||
status = "okay";
|
||||
|
||||
vdda-phy-supply = <&vreg_l6b_1p2>;
|
||||
vdda-pll-supply = <&vreg_l1b_0p88>;
|
||||
};
|
||||
|
||||
&usb_2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_2_hsphy {
|
||||
status = "okay";
|
||||
|
||||
vdda-pll-supply = <&vreg_l5b_0p88>;
|
||||
vdda18-supply = <&vreg_l1c_1p8>;
|
||||
vdda33-supply = <&vreg_l2b_3p07>;
|
||||
};
|
||||
|
||||
&usb_2_qmpphy {
|
||||
status = "okay";
|
||||
|
||||
vdda-phy-supply = <&vreg_l6b_1p2>;
|
||||
vdda-pll-supply = <&vreg_l5b_0p88>;
|
||||
};
|
||||
|
|
@ -5,7 +5,6 @@
|
|||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
|
||||
#include "sm8350.dtsi"
|
||||
#include "pm8350.dtsi"
|
||||
|
|
@ -290,6 +289,15 @@ &pmk8350_rtc {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&pon_pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pon_resin {
|
||||
status = "okay";
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
};
|
||||
|
||||
&qupv3_id_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,19 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "sm8350-sony-xperia-sagami.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Sony Xperia 5 III";
|
||||
compatible = "sony,pdx214-generic", "qcom,sm8350";
|
||||
};
|
||||
|
||||
&framebuffer {
|
||||
width = <1080>;
|
||||
height = <2520>;
|
||||
stride = <(1080 * 4)>;
|
||||
};
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "sm8350-sony-xperia-sagami.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Sony Xperia 1 III";
|
||||
compatible = "sony,pdx215-generic", "qcom,sm8350";
|
||||
};
|
||||
259
arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi
Normal file
259
arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi
Normal file
|
|
@ -0,0 +1,259 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
|
||||
*/
|
||||
|
||||
#include "sm8350.dtsi"
|
||||
#include "pm8350.dtsi"
|
||||
#include "pm8350b.dtsi"
|
||||
#include "pm8350c.dtsi"
|
||||
#include "pmk8350.dtsi"
|
||||
#include "pmr735a.dtsi"
|
||||
#include "pmr735b.dtsi"
|
||||
|
||||
/ {
|
||||
/*
|
||||
* Yes, you are correct, there is NO MORE {msm,board,pmic}-id on SM8350!
|
||||
* Adding it will cause the bootloader to go crazy and randomly crash
|
||||
* shortly after closing UEFI boot services.. Perhaps that has something
|
||||
* to do with the OS running inside a VM now..?
|
||||
*/
|
||||
|
||||
chassis-type = "handset";
|
||||
|
||||
chosen {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
framebuffer: framebuffer@e1000000 {
|
||||
compatible = "simple-framebuffer";
|
||||
reg = <0 0xe1000000 0 0x2300000>;
|
||||
|
||||
/* The display, even though it's 4K, initializes at 1080-ish p */
|
||||
width = <1096>;
|
||||
height = <2560>;
|
||||
stride = <(1096 * 4)>;
|
||||
format = "a8r8g8b8";
|
||||
/*
|
||||
* That's (going to be) a lot of clocks, but it's necessary due
|
||||
* to unused clk cleanup & no panel driver yet
|
||||
*/
|
||||
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&gcc GCC_DISP_SF_AXI_CLK>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
/* For reasons still unknown, GAssist key and Camera Focus/Shutter don't work.. */
|
||||
|
||||
vol-down {
|
||||
label = "Volume Down";
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
gpios = <&pmk8350_gpios 3 GPIO_ACTIVE_LOW>;
|
||||
debounce-interval = <15>;
|
||||
linux,can-disable;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
cont_splash_mem: memory@e1000000 {
|
||||
reg = <0 0xe1000000 0 0x2300000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
ramoops@ffc00000 {
|
||||
compatible = "ramoops";
|
||||
reg = <0 0xffc00000 0 0x100000>;
|
||||
console-size = <0x40000>;
|
||||
record-size = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&adsp {
|
||||
status = "okay";
|
||||
firmware-name = "qcom/adsp.mbn";
|
||||
};
|
||||
|
||||
&cdsp {
|
||||
status = "okay";
|
||||
firmware-name = "qcom/cdsp.mbn";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <1000000>;
|
||||
|
||||
/* Some subset of SONY IMX663 camera sensor @ 38 */
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
/* Richwave RTC6226 FM Radio Receiver @ 64 */
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
/* Samsung Touchscreen (needs I2C GPI DMA) @ 48 */
|
||||
};
|
||||
|
||||
&i2c11 {
|
||||
status = "okay";
|
||||
clock-frequency = <1000000>;
|
||||
|
||||
cs35l41_l: cs35l41@40 {
|
||||
compatible = "cirrus,cs35l41";
|
||||
reg = <0x40>;
|
||||
interrupt-parent = <&tlmm>;
|
||||
interrupts = <36 IRQ_TYPE_LEVEL_LOW>;
|
||||
reset-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
|
||||
cirrus,boost-peak-milliamp = <4000>;
|
||||
cirrus,boost-ind-nanohenry = <1000>;
|
||||
cirrus,boost-cap-microfarad = <15>;
|
||||
cirrus,asp-sdout-hiz = <3>;
|
||||
cirrus,gpio2-src-select = <2>;
|
||||
cirrus,gpio2-output-enable;
|
||||
#sound-dai-cells = <1>;
|
||||
};
|
||||
|
||||
cs35l41_r: cs35l41@41 {
|
||||
compatible = "cirrus,cs35l41";
|
||||
reg = <0x41>;
|
||||
interrupt-parent = <&tlmm>;
|
||||
interrupts = <36 IRQ_TYPE_LEVEL_LOW>;
|
||||
reset-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
|
||||
cirrus,boost-peak-milliamp = <4000>;
|
||||
cirrus,boost-ind-nanohenry = <1000>;
|
||||
cirrus,boost-cap-microfarad = <15>;
|
||||
cirrus,asp-sdout-hiz = <3>;
|
||||
cirrus,gpio2-src-select = <2>;
|
||||
cirrus,gpio2-output-enable;
|
||||
#sound-dai-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c12 {
|
||||
status = "okay";
|
||||
/* Clock frequency was not specified downstream, let's park it to 100 KHz */
|
||||
clock-frequency = <100000>;
|
||||
|
||||
/* AMS TCS3490 RGB+IR color sensor @ 72 */
|
||||
};
|
||||
|
||||
&i2c13 {
|
||||
status = "okay";
|
||||
/* Clock frequency was not specified downstream, let's park it to 100 KHz */
|
||||
clock-frequency = <100000>;
|
||||
|
||||
/* Qualcomm PM8008i/PM8008j (?) @ 8, 9, c, d */
|
||||
/* Dialog SLG51000 CMIC @ 75 */
|
||||
};
|
||||
|
||||
&i2c15 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
/* NXP SN1X0 NFC @ 28 */
|
||||
};
|
||||
|
||||
&i2c17 {
|
||||
status = "okay";
|
||||
clock-frequency = <1000000>;
|
||||
|
||||
/* Cirrus Logic CS40L25A boosted haptics driver @ 40 */
|
||||
};
|
||||
|
||||
&ipa {
|
||||
status = "okay";
|
||||
memory-region = <&pil_ipa_fw_mem>;
|
||||
firmware-name = "qcom/ipa_fws.mbn";
|
||||
};
|
||||
|
||||
&mpss {
|
||||
status = "okay";
|
||||
firmware-name = "qcom/modem.mbn";
|
||||
};
|
||||
|
||||
&pmk8350_rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pon_pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pon_resin {
|
||||
status = "okay";
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
};
|
||||
|
||||
&qupv3_id_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qupv3_id_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qupv3_id_2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&slpi {
|
||||
status = "okay";
|
||||
firmware-name = "qcom/slpi.mbn";
|
||||
};
|
||||
|
||||
&spi14 {
|
||||
status = "okay";
|
||||
|
||||
/* NXP SN1X0 NFC Secure Element @ 0 */
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
gpio-reserved-ranges = <44 4>;
|
||||
|
||||
ts_int_default: ts-int-default {
|
||||
pin = "gpio23";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
input-enable;
|
||||
};
|
||||
};
|
||||
|
||||
/* BIG WARNING! DO NOT TOUCH UFS, YOUR DEVICE WILL DIE! */
|
||||
&ufs_mem_hc { status = "disabled"; };
|
||||
&ufs_mem_phy { status = "disabled"; };
|
||||
|
||||
/* TODO: Make USB3 work (perhaps needs regulators for higher-current operation?) */
|
||||
&usb_1 {
|
||||
status = "okay";
|
||||
|
||||
qcom,select-utmi-as-pipe-clk;
|
||||
};
|
||||
|
||||
&usb_1_dwc3 {
|
||||
dr_mode = "peripheral";
|
||||
|
||||
maximum-speed = "high-speed";
|
||||
phys = <&usb_1_hsphy>;
|
||||
phy-names = "usb2-phy";
|
||||
};
|
||||
|
||||
&usb_1_hsphy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1_qmpphy {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -6,6 +6,7 @@
|
|||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sm8350.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interconnect/qcom,sm8350.h>
|
||||
#include <dt-bindings/mailbox/qcom-ipcc.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
|
@ -583,8 +584,30 @@ gcc: clock-controller@100000 {
|
|||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
clock-names = "bi_tcxo", "sleep_clk";
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
|
||||
clock-names = "bi_tcxo",
|
||||
"sleep_clk",
|
||||
"pcie_0_pipe_clk",
|
||||
"pcie_1_pipe_clk",
|
||||
"ufs_card_rx_symbol_0_clk",
|
||||
"ufs_card_rx_symbol_1_clk",
|
||||
"ufs_card_tx_symbol_0_clk",
|
||||
"ufs_phy_rx_symbol_0_clk",
|
||||
"ufs_phy_rx_symbol_1_clk",
|
||||
"ufs_phy_tx_symbol_0_clk",
|
||||
"usb3_phy_wrapper_gcc_usb30_pipe_clk",
|
||||
"usb3_uni_phy_sec_gcc_usb30_pipe_clk";
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&sleep_clk>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>;
|
||||
};
|
||||
|
||||
ipcc: mailbox@408000 {
|
||||
|
|
@ -596,17 +619,305 @@ ipcc: mailbox@408000 {
|
|||
#mbox-cells = <2>;
|
||||
};
|
||||
|
||||
qup_opp_table_100mhz: qup-100mhz-opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-50000000 {
|
||||
opp-hz = /bits/ 64 <50000000>;
|
||||
required-opps = <&rpmhpd_opp_min_svs>;
|
||||
};
|
||||
|
||||
opp-75000000 {
|
||||
opp-hz = /bits/ 64 <75000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
|
||||
opp-100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
required-opps = <&rpmhpd_opp_svs>;
|
||||
};
|
||||
};
|
||||
|
||||
qup_opp_table_120mhz: qup-120mhz-opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-50000000 {
|
||||
opp-hz = /bits/ 64 <50000000>;
|
||||
required-opps = <&rpmhpd_opp_min_svs>;
|
||||
};
|
||||
|
||||
opp-75000000 {
|
||||
opp-hz = /bits/ 64 <75000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
|
||||
opp-120000000 {
|
||||
opp-hz = /bits/ 64 <120000000>;
|
||||
required-opps = <&rpmhpd_opp_svs>;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_id_2: geniqup@8c0000 {
|
||||
compatible = "qcom,geni-se-qup";
|
||||
reg = <0x0 0x008c0000 0x0 0x6000>;
|
||||
clock-names = "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
|
||||
iommus = <&apps_smmu 0x5e3 0x0>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
status = "disabled";
|
||||
|
||||
i2c14: i2c@880000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00880000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c14_default>;
|
||||
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi14: spi@880000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0 0x00880000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
|
||||
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SM8350_CX>;
|
||||
operating-points-v2 = <&qup_opp_table_120mhz>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c15: i2c@884000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00884000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c15_default>;
|
||||
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi15: spi@884000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0 0x00884000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
|
||||
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SM8350_CX>;
|
||||
operating-points-v2 = <&qup_opp_table_120mhz>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c16: i2c@888000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00888000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c16_default>;
|
||||
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi16: spi@888000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0 0x00888000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
|
||||
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SM8350_CX>;
|
||||
operating-points-v2 = <&qup_opp_table_100mhz>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c17: i2c@88c000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x0088c000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c17_default>;
|
||||
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi17: spi@88c000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0 0x0088c000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
|
||||
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SM8350_CX>;
|
||||
operating-points-v2 = <&qup_opp_table_100mhz>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* QUP no. 18 seems to be strictly SPI/UART-only */
|
||||
|
||||
spi18: spi@890000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0 0x00890000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
|
||||
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SM8350_CX>;
|
||||
operating-points-v2 = <&qup_opp_table_100mhz>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart18: serial@890000 {
|
||||
compatible = "qcom,geni-uart";
|
||||
reg = <0 0x00890000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_uart18_default>;
|
||||
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SM8350_CX>;
|
||||
operating-points-v2 = <&qup_opp_table_100mhz>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c19: i2c@894000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00894000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c19_default>;
|
||||
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi19: spi@894000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0 0x00894000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
|
||||
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SM8350_CX>;
|
||||
operating-points-v2 = <&qup_opp_table_100mhz>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_id_0: geniqup@9c0000 {
|
||||
compatible = "qcom,geni-se-qup";
|
||||
reg = <0x0 0x009c0000 0x0 0x6000>;
|
||||
clock-names = "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
iommus = <&apps_smmu 0x5a3 0>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
status = "disabled";
|
||||
|
||||
i2c0: i2c@980000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00980000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c0_default>;
|
||||
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi0: spi@980000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0 0x00980000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
|
||||
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SM8350_CX>;
|
||||
operating-points-v2 = <&qup_opp_table_100mhz>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@984000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00984000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c1_default>;
|
||||
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@984000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0 0x00984000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
|
||||
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SM8350_CX>;
|
||||
operating-points-v2 = <&qup_opp_table_100mhz>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@988000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00988000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c2_default>;
|
||||
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi2: spi@988000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0 0x00988000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
|
||||
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SM8350_CX>;
|
||||
operating-points-v2 = <&qup_opp_table_100mhz>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@98c000 {
|
||||
compatible = "qcom,geni-debug-uart";
|
||||
reg = <0 0x0098c000 0 0x4000>;
|
||||
|
|
@ -615,6 +926,140 @@ uart2: serial@98c000 {
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_uart3_default_state>;
|
||||
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SM8350_CX>;
|
||||
operating-points-v2 = <&qup_opp_table_100mhz>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* QUP no. 3 seems to be strictly SPI-only */
|
||||
|
||||
spi3: spi@98c000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0 0x0098c000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
|
||||
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SM8350_CX>;
|
||||
operating-points-v2 = <&qup_opp_table_100mhz>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@990000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00990000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c4_default>;
|
||||
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi4: spi@990000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0 0x00990000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
|
||||
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SM8350_CX>;
|
||||
operating-points-v2 = <&qup_opp_table_100mhz>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c5: i2c@994000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00994000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c5_default>;
|
||||
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi5: spi@994000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0 0x00994000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
|
||||
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SM8350_CX>;
|
||||
operating-points-v2 = <&qup_opp_table_100mhz>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c6: i2c@998000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00998000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c6_default>;
|
||||
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi6: spi@998000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0 0x00998000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
|
||||
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SM8350_CX>;
|
||||
operating-points-v2 = <&qup_opp_table_100mhz>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart6: serial@998000 {
|
||||
compatible = "qcom,geni-uart";
|
||||
reg = <0 0x00998000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_uart6_default>;
|
||||
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SM8350_CX>;
|
||||
operating-points-v2 = <&qup_opp_table_100mhz>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c7: i2c@99c000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x0099c000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c7_default>;
|
||||
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi7: spi@99c000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0 0x0099c000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
|
||||
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SM8350_CX>;
|
||||
operating-points-v2 = <&qup_opp_table_100mhz>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
|
@ -627,23 +1072,167 @@ qupv3_id_1: geniqup@ac0000 {
|
|||
clock-names = "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
iommus = <&apps_smmu 0x43 0>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
status = "disabled";
|
||||
|
||||
i2c8: i2c@a80000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00a80000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c8_default>;
|
||||
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi8: spi@a80000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0 0x00a80000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
|
||||
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SM8350_CX>;
|
||||
operating-points-v2 = <&qup_opp_table_120mhz>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c9: i2c@a84000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00a84000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c9_default>;
|
||||
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi9: spi@a84000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0 0x00a84000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
|
||||
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SM8350_CX>;
|
||||
operating-points-v2 = <&qup_opp_table_100mhz>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c10: i2c@a88000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00a88000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c10_default>;
|
||||
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi10: spi@a88000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0 0x00a88000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
|
||||
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SM8350_CX>;
|
||||
operating-points-v2 = <&qup_opp_table_100mhz>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c11: i2c@a8c000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00a8c000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c11_default>;
|
||||
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi11: spi@a8c000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0 0x00a8c000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
|
||||
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SM8350_CX>;
|
||||
operating-points-v2 = <&qup_opp_table_100mhz>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c12: i2c@a90000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00a90000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c12_default>;
|
||||
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi12: spi@a90000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0 0x00a90000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
||||
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SM8350_CX>;
|
||||
operating-points-v2 = <&qup_opp_table_100mhz>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c13: i2c@a94000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00a94000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c13_default_state>;
|
||||
pinctrl-0 = <&qup_i2c13_default>;
|
||||
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi13: spi@a94000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0 0x00a94000 0 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
|
||||
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SM8350_CX>;
|
||||
operating-points-v2 = <&qup_opp_table_100mhz>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
apps_smmu: iommu@15000000 {
|
||||
|
|
@ -910,7 +1499,7 @@ tsens0: thermal-sensor@c263000 {
|
|||
reg = <0 0x0c263000 0 0x1ff>, /* TM */
|
||||
<0 0x0c222000 0 0x8>; /* SROT */
|
||||
#qcom,sensors = <15>;
|
||||
interrupts = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
|
||||
interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "uplow", "critical";
|
||||
#thermal-sensor-cells = <1>;
|
||||
|
|
@ -921,7 +1510,7 @@ tsens1: thermal-sensor@c265000 {
|
|||
reg = <0 0x0c265000 0 0x1ff>, /* TM */
|
||||
<0 0x0c223000 0 0x8>; /* SROT */
|
||||
#qcom,sensors = <14>;
|
||||
interrupts = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
|
||||
interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "uplow", "critical";
|
||||
#thermal-sensor-cells = <1>;
|
||||
|
|
@ -982,17 +1571,144 @@ tx {
|
|||
};
|
||||
};
|
||||
|
||||
qup_i2c13_default_state: qup-i2c13-default-state {
|
||||
mux {
|
||||
pins = "gpio0", "gpio1";
|
||||
function = "qup13";
|
||||
};
|
||||
qup_uart6_default: qup-uart6-default {
|
||||
pins = "gpio30", "gpio31";
|
||||
function = "qup6";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio0", "gpio1";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
qup_uart18_default: qup-uart18-default {
|
||||
pins = "gpio58", "gpio59";
|
||||
function = "qup18";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
qup_i2c0_default: qup-i2c0-default {
|
||||
pins = "gpio4", "gpio5";
|
||||
function = "qup0";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
qup_i2c1_default: qup-i2c1-default {
|
||||
pins = "gpio8", "gpio9";
|
||||
function = "qup1";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
qup_i2c2_default: qup-i2c2-default {
|
||||
pins = "gpio12", "gpio13";
|
||||
function = "qup2";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
qup_i2c4_default: qup-i2c4-default {
|
||||
pins = "gpio20", "gpio21";
|
||||
function = "qup4";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
qup_i2c5_default: qup-i2c5-default {
|
||||
pins = "gpio24", "gpio25";
|
||||
function = "qup5";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
qup_i2c6_default: qup-i2c6-default {
|
||||
pins = "gpio28", "gpio29";
|
||||
function = "qup6";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
qup_i2c7_default: qup-i2c7-default {
|
||||
pins = "gpio32", "gpio33";
|
||||
function = "qup7";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
qup_i2c8_default: qup-i2c8-default {
|
||||
pins = "gpio36", "gpio37";
|
||||
function = "qup8";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
qup_i2c9_default: qup-i2c9-default {
|
||||
pins = "gpio40", "gpio41";
|
||||
function = "qup9";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
qup_i2c10_default: qup-i2c10-default {
|
||||
pins = "gpio44", "gpio45";
|
||||
function = "qup10";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
qup_i2c11_default: qup-i2c11-default {
|
||||
pins = "gpio48", "gpio49";
|
||||
function = "qup11";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
qup_i2c12_default: qup-i2c12-default {
|
||||
pins = "gpio52", "gpio53";
|
||||
function = "qup12";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
qup_i2c13_default: qup-i2c13-default {
|
||||
pins = "gpio0", "gpio1";
|
||||
function = "qup13";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
qup_i2c14_default: qup-i2c14-default {
|
||||
pins = "gpio56", "gpio57";
|
||||
function = "qup14";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
qup_i2c15_default: qup-i2c15-default {
|
||||
pins = "gpio60", "gpio61";
|
||||
function = "qup15";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
qup_i2c16_default: qup-i2c16-default {
|
||||
pins = "gpio64", "gpio65";
|
||||
function = "qup16";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
qup_i2c17_default: qup-i2c17-default {
|
||||
pins = "gpio72", "gpio73";
|
||||
function = "qup17";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
qup_i2c19_default: qup-i2c19-default {
|
||||
pins = "gpio76", "gpio77";
|
||||
function = "qup19";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -1007,6 +1723,8 @@ intc: interrupt-controller@17a00000 {
|
|||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
#redistributor-regions = <1>;
|
||||
redistributor-stride = <0 0x20000>;
|
||||
reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
|
||||
<0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
|
@ -1514,6 +2232,12 @@ gem_noc: interconnect@9100000 {
|
|||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
system-cache-controller@9200000 {
|
||||
compatible = "qcom,sm8350-llcc";
|
||||
reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
|
||||
reg-names = "llcc_base", "llcc_broadcast_base";
|
||||
};
|
||||
|
||||
usb_1: usb@a6f8800 {
|
||||
compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
|
||||
reg = <0 0x0a6f8800 0 0x400>;
|
||||
|
|
@ -2447,7 +3171,7 @@ camera1_alert0: trip-point0 {
|
|||
};
|
||||
};
|
||||
|
||||
camera-thermal-bottom {
|
||||
cam-thermal-bottom {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
|
||||
|
|
|
|||
398
arch/arm64/boot/dts/qcom/sm8450-qrd.dts
Normal file
398
arch/arm64/boot/dts/qcom/sm8450-qrd.dts
Normal file
|
|
@ -0,0 +1,398 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2021, Linaro Limited
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
|
||||
#include "sm8450.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. SM8450 QRD";
|
||||
compatible = "qcom,sm8450-qrd", "qcom,sm8450";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart7;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
vph_pwr: vph-pwr-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vph_pwr";
|
||||
regulator-min-microvolt = <3700000>;
|
||||
regulator-max-microvolt = <3700000>;
|
||||
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
|
||||
&apps_rsc {
|
||||
pm8350-rpmh-regulators {
|
||||
compatible = "qcom,pm8350-rpmh-regulators";
|
||||
qcom,pmic-id = "b";
|
||||
|
||||
vdd-s1-supply = <&vph_pwr>;
|
||||
vdd-s2-supply = <&vph_pwr>;
|
||||
vdd-s3-supply = <&vph_pwr>;
|
||||
vdd-s4-supply = <&vph_pwr>;
|
||||
vdd-s5-supply = <&vph_pwr>;
|
||||
vdd-s6-supply = <&vph_pwr>;
|
||||
vdd-s7-supply = <&vph_pwr>;
|
||||
vdd-s8-supply = <&vph_pwr>;
|
||||
vdd-s9-supply = <&vph_pwr>;
|
||||
vdd-s10-supply = <&vph_pwr>;
|
||||
vdd-s11-supply = <&vph_pwr>;
|
||||
vdd-s12-supply = <&vph_pwr>;
|
||||
|
||||
vdd-l1-l4-supply = <&vreg_s11b_0p95>;
|
||||
vdd-l2-l7-supply = <&vreg_bob>;
|
||||
vdd-l3-l5-supply = <&vreg_bob>;
|
||||
vdd-l6-l9-l10-supply = <&vreg_s12b_1p25>;
|
||||
vdd-l8-supply = <&vreg_s2h_0p95>;
|
||||
|
||||
vreg_s10b_1p8: smps10 {
|
||||
regulator-name = "vreg_s10b_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
vreg_s11b_0p95: smps11 {
|
||||
regulator-name = "vreg_s11b_0p95";
|
||||
regulator-min-microvolt = <848000>;
|
||||
regulator-max-microvolt = <1104000>;
|
||||
};
|
||||
|
||||
vreg_s12b_1p25: smps12 {
|
||||
regulator-name = "vreg_s12b_1p25";
|
||||
regulator-min-microvolt = <1224000>;
|
||||
regulator-max-microvolt = <1400000>;
|
||||
};
|
||||
|
||||
vreg_l1b_0p91: ldo1 {
|
||||
regulator-name = "vreg_l1b_0p91";
|
||||
regulator-min-microvolt = <912000>;
|
||||
regulator-max-microvolt = <920000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l2b_3p07: ldo2 {
|
||||
regulator-name = "vreg_l2b_3p07";
|
||||
regulator-min-microvolt = <3072000>;
|
||||
regulator-max-microvolt = <3072000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l3b_0p9: ldo3 {
|
||||
regulator-name = "vreg_l3b_0p9";
|
||||
regulator-min-microvolt = <904000>;
|
||||
regulator-max-microvolt = <904000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l5b_0p88: ldo5 {
|
||||
regulator-name = "vreg_l5b_0p88";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <888000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l6b_1p2: ldo6 {
|
||||
regulator-name = "vreg_l6b_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l7b_2p5: ldo7 {
|
||||
regulator-name = "vreg_l7b_2p5";
|
||||
regulator-min-microvolt = <2504000>;
|
||||
regulator-max-microvolt = <2504000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l9b_1p2: ldo9 {
|
||||
regulator-name = "vreg_l9b_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
pm8350c-rpmh-regulators {
|
||||
compatible = "qcom,pm8350c-rpmh-regulators";
|
||||
qcom,pmic-id = "c";
|
||||
|
||||
vdd-s1-supply = <&vph_pwr>;
|
||||
vdd-s2-supply = <&vph_pwr>;
|
||||
vdd-s3-supply = <&vph_pwr>;
|
||||
vdd-s4-supply = <&vph_pwr>;
|
||||
vdd-s5-supply = <&vph_pwr>;
|
||||
vdd-s6-supply = <&vph_pwr>;
|
||||
vdd-s7-supply = <&vph_pwr>;
|
||||
vdd-s8-supply = <&vph_pwr>;
|
||||
vdd-s9-supply = <&vph_pwr>;
|
||||
vdd-s10-supply = <&vph_pwr>;
|
||||
|
||||
vdd-l1-l12-supply = <&vreg_bob>;
|
||||
vdd-l2-l8-supply = <&vreg_bob>;
|
||||
vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>;
|
||||
vdd-l6-l9-l11-supply = <&vreg_bob>;
|
||||
|
||||
vdd-bob-supply = <&vph_pwr>;
|
||||
|
||||
vreg_s1c_1p86: smps1 {
|
||||
regulator-name = "vreg_s1c_1p86";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2024000>;
|
||||
};
|
||||
|
||||
vreg_s10c_1p05: smps10 {
|
||||
regulator-name = "vreg_s10c_1p05";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
};
|
||||
|
||||
vreg_bob: bob {
|
||||
regulator-name = "vreg_bob";
|
||||
regulator-min-microvolt = <3008000>;
|
||||
regulator-max-microvolt = <3960000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l1c_1p8: ldo1 {
|
||||
regulator-name = "vreg_l1c_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l3c_3p0: ldo3 {
|
||||
regulator-name = "vreg_l3c_3p0";
|
||||
regulator-min-microvolt = <3296000>;
|
||||
regulator-max-microvolt = <3304000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l4c_1p8: ldo4 {
|
||||
regulator-name = "vreg_l4c_1p8";
|
||||
regulator-min-microvolt = <1704000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l5c_1p8: ldo5 {
|
||||
regulator-name = "vreg_l5c_1p8";
|
||||
regulator-min-microvolt = <1704000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l6c_1p8: ldo6 {
|
||||
regulator-name = "vreg_l6c_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3008000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l7c_3p0: ldo7 {
|
||||
regulator-name = "vreg_l7c_3p0";
|
||||
regulator-min-microvolt = <3008000>;
|
||||
regulator-max-microvolt = <3008000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l8c_1p8: ldo8 {
|
||||
regulator-name = "vreg_l8c_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l9c_2p96: ldo9 {
|
||||
regulator-name = "vreg_l9c_2p96";
|
||||
regulator-min-microvolt = <2960000>;
|
||||
regulator-max-microvolt = <3008000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l12c_1p8: ldo12 {
|
||||
regulator-name = "vreg_l12c_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1968000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l13c_3p0: ldo13 {
|
||||
regulator-name = "vreg_l13c_3p0";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
pm8450-rpmh-regulators {
|
||||
compatible = "qcom,pm8450-rpmh-regulators";
|
||||
qcom,pmic-id = "h";
|
||||
|
||||
vdd-s1-supply = <&vph_pwr>;
|
||||
vdd-s2-supply = <&vph_pwr>;
|
||||
vdd-s3-supply = <&vph_pwr>;
|
||||
vdd-s4-supply = <&vph_pwr>;
|
||||
vdd-s5-supply = <&vph_pwr>;
|
||||
vdd-s6-supply = <&vph_pwr>;
|
||||
|
||||
vdd-l2-supply = <&vreg_bob>;
|
||||
vdd-l3-supply = <&vreg_bob>;
|
||||
vdd-l4-supply = <&vreg_bob>;
|
||||
|
||||
vreg_s2h_0p95: smps2 {
|
||||
regulator-name = "vreg_s2h_0p95";
|
||||
regulator-min-microvolt = <848000>;
|
||||
regulator-max-microvolt = <1104000>;
|
||||
};
|
||||
|
||||
vreg_s3h_0p5: smps3 {
|
||||
regulator-name = "vreg_s3h_0p5";
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <500000>;
|
||||
};
|
||||
|
||||
vreg_l2h_0p91: ldo2 {
|
||||
regulator-name = "vreg_l2h_0p91";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <912000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l3h_0p91: ldo3 {
|
||||
regulator-name = "vreg_l3h_0p91";
|
||||
regulator-min-microvolt = <912000>;
|
||||
regulator-max-microvolt = <912000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
pmr735a-rpmh-regulators {
|
||||
compatible = "qcom,pmr735a-rpmh-regulators";
|
||||
qcom,pmic-id = "e";
|
||||
|
||||
vdd-s1-supply = <&vph_pwr>;
|
||||
vdd-s2-supply = <&vph_pwr>;
|
||||
vdd-s3-supply = <&vph_pwr>;
|
||||
|
||||
vdd-l1-l2-supply = <&vreg_s2e_0p85>;
|
||||
vdd-l3-supply = <&vreg_s1e_1p25>;
|
||||
vdd-l4-supply = <&vreg_s1c_1p86>;
|
||||
vdd-l5-l6-supply = <&vreg_s1c_1p86>;
|
||||
vdd-l7-bob-supply = <&vreg_bob>;
|
||||
|
||||
vreg_s1e_1p25: smps1 {
|
||||
regulator-name = "vreg_s1e_1p25";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1296000>;
|
||||
};
|
||||
|
||||
vreg_s2e_0p85: smps2 {
|
||||
regulator-name = "vreg_s2e_0p85";
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1040000>;
|
||||
};
|
||||
|
||||
vreg_l1e_0p8: ldo1 {
|
||||
regulator-name = "vreg_l1e_0p8";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <800000>;
|
||||
};
|
||||
|
||||
vreg_l2e_0p8: ldo2 {
|
||||
regulator-name = "vreg_l2e_0p8";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <800000>;
|
||||
};
|
||||
|
||||
vreg_l3e_1p2: ldo3 {
|
||||
regulator-name = "vreg_l3e_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
};
|
||||
|
||||
vreg_l4e_1p7: ldo4 {
|
||||
regulator-name = "vreg_l4e_1p7";
|
||||
regulator-min-microvolt = <1776000>;
|
||||
regulator-max-microvolt = <1776000>;
|
||||
};
|
||||
|
||||
vreg_l5e_0p88: ldo5 {
|
||||
regulator-name = "vreg_l5e_0p88";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <880000>;
|
||||
};
|
||||
|
||||
vreg_l6e_1p2: ldo6 {
|
||||
regulator-name = "vreg_l6e_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qupv3_id_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
gpio-reserved-ranges = <28 4>, <36 4>;
|
||||
};
|
||||
|
||||
&uart7 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ufs_mem_hc {
|
||||
status = "okay";
|
||||
|
||||
reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
|
||||
|
||||
vcc-supply = <&vreg_l7b_2p5>;
|
||||
vcc-max-microamp = <1100000>;
|
||||
vccq-supply = <&vreg_l9b_1p2>;
|
||||
vccq-max-microamp = <1200000>;
|
||||
};
|
||||
|
||||
&ufs_mem_phy {
|
||||
status = "okay";
|
||||
|
||||
vdda-phy-supply = <&vreg_l5b_0p88>;
|
||||
vdda-pll-supply = <&vreg_l6b_1p2>;
|
||||
vdda-max-microamp = <173000>;
|
||||
vdda-pll-max-microamp = <24900>;
|
||||
};
|
||||
|
||||
&usb_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1_dwc3 {
|
||||
dr_mode = "peripheral";
|
||||
};
|
||||
|
||||
&usb_1_hsphy {
|
||||
status = "okay";
|
||||
|
||||
vdda-pll-supply = <&vreg_l5b_0p88>;
|
||||
vdda18-supply = <&vreg_l1c_1p8>;
|
||||
vdda33-supply = <&vreg_l2b_3p07>;
|
||||
};
|
||||
|
||||
&usb_1_qmpphy {
|
||||
status = "okay";
|
||||
|
||||
vdda-phy-supply = <&vreg_l6b_1p2>;
|
||||
vdda-pll-supply = <&vreg_l1b_0p91>;
|
||||
};
|
||||
1115
arch/arm64/boot/dts/qcom/sm8450.dtsi
Normal file
1115
arch/arm64/boot/dts/qcom/sm8450.dtsi
Normal file
File diff suppressed because it is too large
Load diff
244
include/dt-bindings/clock/qcom,gcc-sm8450.h
Normal file
244
include/dt-bindings/clock/qcom,gcc-sm8450.h
Normal file
|
|
@ -0,0 +1,244 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2021, Linaro Limited
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8450_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_GCC_SM8450_H
|
||||
|
||||
/* GCC HW clocks */
|
||||
#define CORE_BI_PLL_TEST_SE 0
|
||||
#define PCIE_0_PIPE_CLK 1
|
||||
#define PCIE_1_PHY_AUX_CLK 2
|
||||
#define PCIE_1_PIPE_CLK 3
|
||||
#define UFS_PHY_RX_SYMBOL_0_CLK 4
|
||||
#define UFS_PHY_RX_SYMBOL_1_CLK 5
|
||||
#define UFS_PHY_TX_SYMBOL_0_CLK 6
|
||||
#define USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK 7
|
||||
|
||||
/* GCC clocks */
|
||||
#define GCC_AGGRE_NOC_PCIE_0_AXI_CLK 8
|
||||
#define GCC_AGGRE_NOC_PCIE_1_AXI_CLK 9
|
||||
#define GCC_AGGRE_UFS_PHY_AXI_CLK 10
|
||||
#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 11
|
||||
#define GCC_AGGRE_USB3_PRIM_AXI_CLK 12
|
||||
#define GCC_ANOC_PCIE_PWRCTL_CLK 13
|
||||
#define GCC_BOOT_ROM_AHB_CLK 14
|
||||
#define GCC_CAMERA_AHB_CLK 15
|
||||
#define GCC_CAMERA_HF_AXI_CLK 16
|
||||
#define GCC_CAMERA_SF_AXI_CLK 17
|
||||
#define GCC_CAMERA_XO_CLK 18
|
||||
#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 19
|
||||
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 20
|
||||
#define GCC_CPUSS_AHB_CLK 21
|
||||
#define GCC_CPUSS_AHB_CLK_SRC 22
|
||||
#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 23
|
||||
#define GCC_CPUSS_CONFIG_NOC_SF_CLK 24
|
||||
#define GCC_DDRSS_GPU_AXI_CLK 25
|
||||
#define GCC_DDRSS_PCIE_SF_TBU_CLK 26
|
||||
#define GCC_DISP_AHB_CLK 27
|
||||
#define GCC_DISP_HF_AXI_CLK 28
|
||||
#define GCC_DISP_SF_AXI_CLK 29
|
||||
#define GCC_DISP_XO_CLK 30
|
||||
#define GCC_EUSB3_0_CLKREF_EN 31
|
||||
#define GCC_GP1_CLK 32
|
||||
#define GCC_GP1_CLK_SRC 33
|
||||
#define GCC_GP2_CLK 34
|
||||
#define GCC_GP2_CLK_SRC 35
|
||||
#define GCC_GP3_CLK 36
|
||||
#define GCC_GP3_CLK_SRC 37
|
||||
#define GCC_GPLL0 38
|
||||
#define GCC_GPLL0_OUT_EVEN 39
|
||||
#define GCC_GPLL4 40
|
||||
#define GCC_GPLL9 41
|
||||
#define GCC_GPU_CFG_AHB_CLK 42
|
||||
#define GCC_GPU_GPLL0_CLK_SRC 43
|
||||
#define GCC_GPU_GPLL0_DIV_CLK_SRC 44
|
||||
#define GCC_GPU_MEMNOC_GFX_CLK 45
|
||||
#define GCC_GPU_SNOC_DVM_GFX_CLK 46
|
||||
#define GCC_PCIE_0_AUX_CLK 47
|
||||
#define GCC_PCIE_0_AUX_CLK_SRC 48
|
||||
#define GCC_PCIE_0_CFG_AHB_CLK 49
|
||||
#define GCC_PCIE_0_CLKREF_EN 50
|
||||
#define GCC_PCIE_0_MSTR_AXI_CLK 51
|
||||
#define GCC_PCIE_0_PHY_RCHNG_CLK 52
|
||||
#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 53
|
||||
#define GCC_PCIE_0_PIPE_CLK 54
|
||||
#define GCC_PCIE_0_PIPE_CLK_SRC 55
|
||||
#define GCC_PCIE_0_SLV_AXI_CLK 56
|
||||
#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 57
|
||||
#define GCC_PCIE_1_AUX_CLK 58
|
||||
#define GCC_PCIE_1_AUX_CLK_SRC 59
|
||||
#define GCC_PCIE_1_CFG_AHB_CLK 60
|
||||
#define GCC_PCIE_1_CLKREF_EN 61
|
||||
#define GCC_PCIE_1_MSTR_AXI_CLK 62
|
||||
#define GCC_PCIE_1_PHY_AUX_CLK 63
|
||||
#define GCC_PCIE_1_PHY_AUX_CLK_SRC 64
|
||||
#define GCC_PCIE_1_PHY_RCHNG_CLK 65
|
||||
#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 66
|
||||
#define GCC_PCIE_1_PIPE_CLK 67
|
||||
#define GCC_PCIE_1_PIPE_CLK_SRC 68
|
||||
#define GCC_PCIE_1_SLV_AXI_CLK 69
|
||||
#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 70
|
||||
#define GCC_PDM2_CLK 71
|
||||
#define GCC_PDM2_CLK_SRC 72
|
||||
#define GCC_PDM_AHB_CLK 73
|
||||
#define GCC_PDM_XO4_CLK 74
|
||||
#define GCC_QMIP_CAMERA_NRT_AHB_CLK 75
|
||||
#define GCC_QMIP_CAMERA_RT_AHB_CLK 76
|
||||
#define GCC_QMIP_DISP_AHB_CLK 77
|
||||
#define GCC_QMIP_GPU_AHB_CLK 78
|
||||
#define GCC_QMIP_PCIE_AHB_CLK 79
|
||||
#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 80
|
||||
#define GCC_QMIP_VIDEO_CVP_AHB_CLK 81
|
||||
#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 82
|
||||
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 83
|
||||
#define GCC_QUPV3_WRAP0_CORE_2X_CLK 84
|
||||
#define GCC_QUPV3_WRAP0_CORE_CLK 85
|
||||
#define GCC_QUPV3_WRAP0_S0_CLK 86
|
||||
#define GCC_QUPV3_WRAP0_S0_CLK_SRC 87
|
||||
#define GCC_QUPV3_WRAP0_S1_CLK 88
|
||||
#define GCC_QUPV3_WRAP0_S1_CLK_SRC 89
|
||||
#define GCC_QUPV3_WRAP0_S2_CLK 90
|
||||
#define GCC_QUPV3_WRAP0_S2_CLK_SRC 91
|
||||
#define GCC_QUPV3_WRAP0_S3_CLK 92
|
||||
#define GCC_QUPV3_WRAP0_S3_CLK_SRC 93
|
||||
#define GCC_QUPV3_WRAP0_S4_CLK 94
|
||||
#define GCC_QUPV3_WRAP0_S4_CLK_SRC 95
|
||||
#define GCC_QUPV3_WRAP0_S5_CLK 96
|
||||
#define GCC_QUPV3_WRAP0_S5_CLK_SRC 97
|
||||
#define GCC_QUPV3_WRAP0_S6_CLK 98
|
||||
#define GCC_QUPV3_WRAP0_S6_CLK_SRC 99
|
||||
#define GCC_QUPV3_WRAP0_S7_CLK 100
|
||||
#define GCC_QUPV3_WRAP0_S7_CLK_SRC 101
|
||||
#define GCC_QUPV3_WRAP1_CORE_2X_CLK 102
|
||||
#define GCC_QUPV3_WRAP1_CORE_CLK 103
|
||||
#define GCC_QUPV3_WRAP1_S0_CLK 104
|
||||
#define GCC_QUPV3_WRAP1_S0_CLK_SRC 105
|
||||
#define GCC_QUPV3_WRAP1_S1_CLK 106
|
||||
#define GCC_QUPV3_WRAP1_S1_CLK_SRC 107
|
||||
#define GCC_QUPV3_WRAP1_S2_CLK 108
|
||||
#define GCC_QUPV3_WRAP1_S2_CLK_SRC 109
|
||||
#define GCC_QUPV3_WRAP1_S3_CLK 110
|
||||
#define GCC_QUPV3_WRAP1_S3_CLK_SRC 111
|
||||
#define GCC_QUPV3_WRAP1_S4_CLK 112
|
||||
#define GCC_QUPV3_WRAP1_S4_CLK_SRC 113
|
||||
#define GCC_QUPV3_WRAP1_S5_CLK 114
|
||||
#define GCC_QUPV3_WRAP1_S5_CLK_SRC 115
|
||||
#define GCC_QUPV3_WRAP1_S6_CLK 116
|
||||
#define GCC_QUPV3_WRAP1_S6_CLK_SRC 117
|
||||
#define GCC_QUPV3_WRAP2_CORE_2X_CLK 118
|
||||
#define GCC_QUPV3_WRAP2_CORE_CLK 119
|
||||
#define GCC_QUPV3_WRAP2_S0_CLK 120
|
||||
#define GCC_QUPV3_WRAP2_S0_CLK_SRC 121
|
||||
#define GCC_QUPV3_WRAP2_S1_CLK 122
|
||||
#define GCC_QUPV3_WRAP2_S1_CLK_SRC 123
|
||||
#define GCC_QUPV3_WRAP2_S2_CLK 124
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#define GCC_QUPV3_WRAP2_S2_CLK_SRC 125
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||||
#define GCC_QUPV3_WRAP2_S3_CLK 126
|
||||
#define GCC_QUPV3_WRAP2_S3_CLK_SRC 127
|
||||
#define GCC_QUPV3_WRAP2_S4_CLK 128
|
||||
#define GCC_QUPV3_WRAP2_S4_CLK_SRC 129
|
||||
#define GCC_QUPV3_WRAP2_S5_CLK 130
|
||||
#define GCC_QUPV3_WRAP2_S5_CLK_SRC 131
|
||||
#define GCC_QUPV3_WRAP2_S6_CLK 132
|
||||
#define GCC_QUPV3_WRAP2_S6_CLK_SRC 133
|
||||
#define GCC_QUPV3_WRAP_0_M_AHB_CLK 134
|
||||
#define GCC_QUPV3_WRAP_0_S_AHB_CLK 135
|
||||
#define GCC_QUPV3_WRAP_1_M_AHB_CLK 136
|
||||
#define GCC_QUPV3_WRAP_1_S_AHB_CLK 137
|
||||
#define GCC_QUPV3_WRAP_2_M_AHB_CLK 138
|
||||
#define GCC_QUPV3_WRAP_2_S_AHB_CLK 139
|
||||
#define GCC_SDCC2_AHB_CLK 140
|
||||
#define GCC_SDCC2_APPS_CLK 141
|
||||
#define GCC_SDCC2_APPS_CLK_SRC 142
|
||||
#define GCC_SDCC2_AT_CLK 143
|
||||
#define GCC_SDCC4_AHB_CLK 144
|
||||
#define GCC_SDCC4_APPS_CLK 145
|
||||
#define GCC_SDCC4_APPS_CLK_SRC 146
|
||||
#define GCC_SDCC4_AT_CLK 147
|
||||
#define GCC_SYS_NOC_CPUSS_AHB_CLK 148
|
||||
#define GCC_UFS_0_CLKREF_EN 149
|
||||
#define GCC_UFS_PHY_AHB_CLK 150
|
||||
#define GCC_UFS_PHY_AXI_CLK 151
|
||||
#define GCC_UFS_PHY_AXI_CLK_SRC 152
|
||||
#define GCC_UFS_PHY_AXI_HW_CTL_CLK 153
|
||||
#define GCC_UFS_PHY_ICE_CORE_CLK 154
|
||||
#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 155
|
||||
#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 156
|
||||
#define GCC_UFS_PHY_PHY_AUX_CLK 157
|
||||
#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 158
|
||||
#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 159
|
||||
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 160
|
||||
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 161
|
||||
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 162
|
||||
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 163
|
||||
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 164
|
||||
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 165
|
||||
#define GCC_UFS_PHY_UNIPRO_CORE_CLK 166
|
||||
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 167
|
||||
#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 168
|
||||
#define GCC_USB30_PRIM_MASTER_CLK 169
|
||||
#define GCC_USB30_PRIM_MASTER_CLK_SRC 170
|
||||
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 171
|
||||
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 172
|
||||
#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 173
|
||||
#define GCC_USB30_PRIM_SLEEP_CLK 174
|
||||
#define GCC_USB3_0_CLKREF_EN 175
|
||||
#define GCC_USB3_PRIM_PHY_AUX_CLK 176
|
||||
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 177
|
||||
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 178
|
||||
#define GCC_USB3_PRIM_PHY_PIPE_CLK 179
|
||||
#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 180
|
||||
#define GCC_VIDEO_AHB_CLK 181
|
||||
#define GCC_VIDEO_AXI0_CLK 182
|
||||
#define GCC_VIDEO_AXI1_CLK 183
|
||||
#define GCC_VIDEO_XO_CLK 184
|
||||
|
||||
/* GCC resets */
|
||||
#define GCC_CAMERA_BCR 0
|
||||
#define GCC_DISPLAY_BCR 1
|
||||
#define GCC_GPU_BCR 2
|
||||
#define GCC_MMSS_BCR 3
|
||||
#define GCC_PCIE_0_BCR 4
|
||||
#define GCC_PCIE_0_LINK_DOWN_BCR 5
|
||||
#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 6
|
||||
#define GCC_PCIE_0_PHY_BCR 7
|
||||
#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 8
|
||||
#define GCC_PCIE_1_BCR 9
|
||||
#define GCC_PCIE_1_LINK_DOWN_BCR 10
|
||||
#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 11
|
||||
#define GCC_PCIE_1_PHY_BCR 12
|
||||
#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 13
|
||||
#define GCC_PCIE_PHY_BCR 14
|
||||
#define GCC_PCIE_PHY_CFG_AHB_BCR 15
|
||||
#define GCC_PCIE_PHY_COM_BCR 16
|
||||
#define GCC_PDM_BCR 17
|
||||
#define GCC_QUPV3_WRAPPER_0_BCR 18
|
||||
#define GCC_QUPV3_WRAPPER_1_BCR 19
|
||||
#define GCC_QUPV3_WRAPPER_2_BCR 20
|
||||
#define GCC_QUSB2PHY_PRIM_BCR 21
|
||||
#define GCC_QUSB2PHY_SEC_BCR 22
|
||||
#define GCC_SDCC2_BCR 23
|
||||
#define GCC_SDCC4_BCR 24
|
||||
#define GCC_UFS_PHY_BCR 25
|
||||
#define GCC_USB30_PRIM_BCR 26
|
||||
#define GCC_USB3_DP_PHY_PRIM_BCR 27
|
||||
#define GCC_USB3_DP_PHY_SEC_BCR 28
|
||||
#define GCC_USB3_PHY_PRIM_BCR 29
|
||||
#define GCC_USB3_PHY_SEC_BCR 30
|
||||
#define GCC_USB3PHY_PHY_PRIM_BCR 31
|
||||
#define GCC_USB3PHY_PHY_SEC_BCR 32
|
||||
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 33
|
||||
#define GCC_VIDEO_AXI0_CLK_ARES 34
|
||||
#define GCC_VIDEO_AXI1_CLK_ARES 35
|
||||
#define GCC_VIDEO_BCR 36
|
||||
|
||||
/* GCC power domains */
|
||||
#define PCIE_0_GDSC 0
|
||||
#define PCIE_1_GDSC 1
|
||||
#define UFS_PHY_GDSC 2
|
||||
#define USB30_PRIM_GDSC 3
|
||||
|
||||
#endif
|
||||
Loading…
Reference in a new issue