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mmc: sdhci-pci-gli: GL975[50]: Issue 8/16-bit MMIO reads as 32-bit reads.
For some reason, <32-bit reads do not work on Apple ARM64 platforms with these chips (even though they do on other PCIe devices). Issue them as 32-bit reads instead. This is done unconditionally, as it shouldn't hurt even if not necessary. Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Hector Martin <marcan@marcan.st> Link: https://lore.kernel.org/r/20211215161045.38843-3-marcan@marcan.st Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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1 changed files with 23 additions and 0 deletions
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@ -902,7 +902,28 @@ static int gli_probe_slot_gl9763e(struct sdhci_pci_slot *slot)
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return 0;
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return 0;
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}
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}
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#define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
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static u16 sdhci_gli_readw(struct sdhci_host *host, int reg)
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{
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u32 val = readl(host->ioaddr + (reg & ~3));
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u16 word;
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word = (val >> REG_OFFSET_IN_BITS(reg)) & 0xffff;
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return word;
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}
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static u8 sdhci_gli_readb(struct sdhci_host *host, int reg)
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{
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u32 val = readl(host->ioaddr + (reg & ~3));
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u8 byte = (val >> REG_OFFSET_IN_BITS(reg)) & 0xff;
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return byte;
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}
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static const struct sdhci_ops sdhci_gl9755_ops = {
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static const struct sdhci_ops sdhci_gl9755_ops = {
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.read_w = sdhci_gli_readw,
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.read_b = sdhci_gli_readb,
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.set_clock = sdhci_gl9755_set_clock,
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.set_clock = sdhci_gl9755_set_clock,
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.enable_dma = sdhci_pci_enable_dma,
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.enable_dma = sdhci_pci_enable_dma,
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.set_bus_width = sdhci_set_bus_width,
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.set_bus_width = sdhci_set_bus_width,
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@ -922,6 +943,8 @@ const struct sdhci_pci_fixes sdhci_gl9755 = {
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};
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};
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static const struct sdhci_ops sdhci_gl9750_ops = {
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static const struct sdhci_ops sdhci_gl9750_ops = {
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.read_w = sdhci_gli_readw,
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.read_b = sdhci_gli_readb,
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.read_l = sdhci_gl9750_readl,
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.read_l = sdhci_gl9750_readl,
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.set_clock = sdhci_gl9750_set_clock,
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.set_clock = sdhci_gl9750_set_clock,
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.enable_dma = sdhci_pci_enable_dma,
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.enable_dma = sdhci_pci_enable_dma,
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