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drm/amd/display: Make driver backwards-compatible with non-IPS PMFW
[why] Driver needs to be compatible with PM FW that doesn't support IPS [how] Toggle internal control flag Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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c0af8c744e
3 changed files with 19 additions and 12 deletions
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@ -744,16 +744,16 @@ static void dcn35_set_idle_state(struct clk_mgr *clk_mgr_base, bool allow_idle)
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struct dc *dc = clk_mgr_base->ctx->dc;
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uint32_t val = dcn35_smu_read_ips_scratch(clk_mgr);
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if (dc->debug.disable_ips == 0) {
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if (dc->config.disable_ips == 0) {
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val |= DMUB_IPS1_ALLOW_MASK;
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val |= DMUB_IPS2_ALLOW_MASK;
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} else if (dc->debug.disable_ips == DMUB_IPS_DISABLE_IPS1) {
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} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS1) {
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val = val & ~DMUB_IPS1_ALLOW_MASK;
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val = val & ~DMUB_IPS2_ALLOW_MASK;
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} else if (dc->debug.disable_ips == DMUB_IPS_DISABLE_IPS2) {
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} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS2) {
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val |= DMUB_IPS1_ALLOW_MASK;
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val = val & ~DMUB_IPS2_ALLOW_MASK;
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} else if (dc->debug.disable_ips == DMUB_IPS_DISABLE_IPS2_Z10) {
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} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS2_Z10) {
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val |= DMUB_IPS1_ALLOW_MASK;
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val |= DMUB_IPS2_ALLOW_MASK;
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}
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@ -1036,12 +1036,20 @@ void dcn35_clk_mgr_construct(
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dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
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smu_dpm_clks.dpm_clks);
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if (dcn35_smu_get_ips_supported(&clk_mgr->base)) {
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if (ctx->dc->config.disable_ips == 0) {
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bool ips_support = false;
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/*avoid call pmfw at init*/
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ips_support = dcn35_smu_get_ips_supported(&clk_mgr->base);
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if (ips_support) {
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ctx->dc->debug.ignore_pg = false;
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ctx->dc->debug.dmcub_emulation = false;
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ctx->dc->debug.disable_dpp_power_gate = false;
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ctx->dc->debug.disable_hubp_power_gate = false;
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ctx->dc->debug.disable_dsc_power_gate = false;
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} else {
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/*let's reset the config control flag*/
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ctx->dc->config.disable_ips = 1; /*pmfw not support it, disable it all*/
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}
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}
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}
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@ -423,6 +423,7 @@ struct dc_config {
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bool dc_mode_clk_limit_support;
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bool EnableMinDispClkODM;
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bool enable_auto_dpm_test_logs;
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unsigned int disable_ips;
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};
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enum visual_confirm {
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@ -913,7 +914,6 @@ struct dc_debug_options {
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enum det_size crb_alloc_policy;
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int crb_alloc_policy_min_disp_count;
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bool disable_z10;
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unsigned int disable_ips;
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bool enable_z9_disable_interface;
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bool psr_skip_crtc_disable;
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union dpia_debug_options dpia_debug;
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@ -747,7 +747,6 @@ static const struct dc_debug_options debug_defaults_drv = {
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.disable_z10 = false,
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.ignore_pg = true,
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.psp_disabled_wa = true,
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.disable_ips = true,
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.ips2_eval_delay_us = 200,
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.ips2_entry_delay_us = 400
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};
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