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drm/tegra: Changes for v5.12-rc1
Adds support for newer firmware image versions of the Video Image Composer (VIC) and adds a comment clarifying the use of the STREAMID registers. Fixes a couple of issues with display and gr2d on older Tegra SoCs such as Tegra114, as well as a runtime PM reference leak. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmAUY50THHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zoaVREACpqRNRg6iSBciNmMLxoMLCf0scrYTp EH/JvTgCC4FtjDyy7KtexDxnsRc4sTAf6c1mm1lIhjuCgkH5AsM4vUm8hMPglDGf CQ07g4M7uKUZBDMBq4ZdSs4UILWSjLYMCEr6ji9AtqvOC2yY6MaHMboqjlTVjfHr GjbZbj2Zq3pMXaJTPJ6xHyVuXyWzO+immnybE1AvMLxVsHJvde3bqMs1IquoE+fd UBwQ6iaDYD8sIuW8ZvXXfqWq9dVRsJeRq9oSPXbbjcqjuaZxrZlOtjn4V39ftt3R ibWUzgAbjOUdUY/SB0oSBw4ahvznW8H9CZKHoC6z8H2GAVfWQh7lhWlsfGKS1h9N km6w+xCUuqwjcw52OpUOMvodxCbFp2mAmbVkLbltmKAos1Vg9sPBioG3HQAogsqX HOkDz1r8dZTe8tHI/IAGzxjl0u/2Qa3PQ+sPosG5cCT48ZAkXB4RmkrQCbCiNK58 Z/HrY0rWggJbuEir5xUGFmEFsb+3j4NDTkajXw67ydfHBZSa4TvJETGHQB3b8kwe u8qzSHLtdp91yRNho1297hhpRwVk+YmYzzcm1l5JoDuvgHbXWw0TGgqQNWyUtIqP 4YBh5s4QdKMyonXNwS6fQZeMygLtBKhySnZCeRRXnvcFPxWP4f2HU08I5U19qjF5 rJPPEO6xFt+ouw== =3Li8 -----END PGP SIGNATURE----- Merge tag 'drm/tegra/for-5.12-rc1' of ssh://git.freedesktop.org/git/tegra/linux into drm-next drm/tegra: Changes for v5.12-rc1 Adds support for newer firmware image versions of the Video Image Composer (VIC) and adds a comment clarifying the use of the STREAMID registers. Fixes a couple of issues with display and gr2d on older Tegra SoCs such as Tegra114, as well as a runtime PM reference leak. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Thierry Reding <thierry.reding@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210129193807.3653456-1-thierry.reding@gmail.com
This commit is contained in:
commit
c106c5e2fd
9 changed files with 45 additions and 20 deletions
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@ -2186,7 +2186,7 @@ static int tegra_dc_runtime_resume(struct host1x_client *client)
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struct device *dev = client->dev;
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int err;
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err = pm_runtime_get_sync(dev);
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err = pm_runtime_resume_and_get(dev);
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if (err < 0) {
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dev_err(dev, "failed to get runtime PM: %d\n", err);
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return err;
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@ -1301,8 +1301,10 @@ static const struct of_device_id host1x_drm_subdevs[] = {
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{ .compatible = "nvidia,tegra30-hdmi", },
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{ .compatible = "nvidia,tegra30-gr2d", },
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{ .compatible = "nvidia,tegra30-gr3d", },
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{ .compatible = "nvidia,tegra114-dc", },
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{ .compatible = "nvidia,tegra114-dsi", },
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{ .compatible = "nvidia,tegra114-hdmi", },
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{ .compatible = "nvidia,tegra114-gr2d", },
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{ .compatible = "nvidia,tegra114-gr3d", },
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{ .compatible = "nvidia,tegra124-dc", },
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{ .compatible = "nvidia,tegra124-sor", },
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@ -1111,7 +1111,7 @@ static int tegra_dsi_runtime_resume(struct host1x_client *client)
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struct device *dev = client->dev;
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int err;
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err = pm_runtime_get_sync(dev);
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err = pm_runtime_resume_and_get(dev);
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if (err < 0) {
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dev_err(dev, "failed to get runtime PM: %d\n", err);
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return err;
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@ -72,7 +72,7 @@ static int falcon_parse_firmware_image(struct falcon *falcon)
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struct falcon_fw_os_header_v1 *os;
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/* endian problems would show up right here */
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if (bin->magic != PCI_VENDOR_ID_NVIDIA) {
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if (bin->magic != PCI_VENDOR_ID_NVIDIA && bin->magic != 0x10fe) {
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dev_err(falcon->dev, "incorrect firmware magic\n");
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return -EINVAL;
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}
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@ -178,9 +178,10 @@ int falcon_boot(struct falcon *falcon)
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falcon->firmware.data.offset + offset,
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offset, FALCON_MEMORY_DATA);
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/* copy the first code segment into Falcon internal memory */
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falcon_copy_chunk(falcon, falcon->firmware.code.offset,
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0, FALCON_MEMORY_IMEM);
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/* copy the code segment into Falcon internal memory */
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for (offset = 0; offset < falcon->firmware.code.size; offset += 256)
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falcon_copy_chunk(falcon, falcon->firmware.code.offset + offset,
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offset, FALCON_MEMORY_IMEM);
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/* setup falcon interrupts */
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falcon_writel(falcon, FALCON_IRQMSET_EXT(0xff) |
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@ -161,9 +161,14 @@ static const struct gr2d_soc tegra30_gr2d_soc = {
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.version = 0x30,
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};
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static const struct gr2d_soc tegra114_gr2d_soc = {
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.version = 0x35,
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};
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static const struct of_device_id gr2d_match[] = {
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{ .compatible = "nvidia,tegra30-gr2d", .data = &tegra20_gr2d_soc },
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{ .compatible = "nvidia,tegra20-gr2d", .data = &tegra30_gr2d_soc },
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{ .compatible = "nvidia,tegra114-gr2d", .data = &tegra114_gr2d_soc },
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{ .compatible = "nvidia,tegra30-gr2d", .data = &tegra30_gr2d_soc },
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{ .compatible = "nvidia,tegra20-gr2d", .data = &tegra20_gr2d_soc },
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{ },
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};
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MODULE_DEVICE_TABLE(of, gr2d_match);
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@ -1510,7 +1510,7 @@ static int tegra_hdmi_runtime_resume(struct host1x_client *client)
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struct device *dev = client->dev;
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int err;
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err = pm_runtime_get_sync(dev);
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err = pm_runtime_resume_and_get(dev);
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if (err < 0) {
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dev_err(dev, "failed to get runtime PM: %d\n", err);
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return err;
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@ -789,7 +789,7 @@ static int tegra_display_hub_runtime_resume(struct host1x_client *client)
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unsigned int i;
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int err;
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err = pm_runtime_get_sync(dev);
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err = pm_runtime_resume_and_get(dev);
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if (err < 0) {
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dev_err(dev, "failed to get runtime PM: %d\n", err);
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return err;
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@ -3218,7 +3218,7 @@ static int tegra_sor_runtime_resume(struct host1x_client *client)
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struct device *dev = client->dev;
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int err;
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err = pm_runtime_get_sync(dev);
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err = pm_runtime_resume_and_get(dev);
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if (err < 0) {
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dev_err(dev, "failed to get runtime PM: %d\n", err);
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return err;
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@ -117,7 +117,19 @@ static int vic_boot(struct vic *vic)
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if (spec->num_ids > 0) {
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value = spec->ids[0] & 0xffff;
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/*
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* STREAMID0 is used for input/output buffers.
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* Initialize it to SID_VIC in case context isolation
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* is not enabled, and SID_VIC is used for both firmware
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* and data buffers.
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*
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* If context isolation is enabled, it will be
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* overridden by the SETSTREAMID opcode as part of
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* each job.
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*/
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vic_writel(vic, value, VIC_THI_STREAMID0);
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/* STREAMID1 is used for firmware loading. */
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vic_writel(vic, value, VIC_THI_STREAMID1);
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}
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}
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@ -135,16 +147,21 @@ static int vic_boot(struct vic *vic)
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hdr = vic->falcon.firmware.virt;
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fce_bin_data_offset = *(u32 *)(hdr + VIC_UCODE_FCE_DATA_OFFSET);
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hdr = vic->falcon.firmware.virt +
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*(u32 *)(hdr + VIC_UCODE_FCE_HEADER_OFFSET);
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fce_ucode_size = *(u32 *)(hdr + FCE_UCODE_SIZE_OFFSET);
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falcon_execute_method(&vic->falcon, VIC_SET_APPLICATION_ID, 1);
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falcon_execute_method(&vic->falcon, VIC_SET_FCE_UCODE_SIZE,
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fce_ucode_size);
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falcon_execute_method(&vic->falcon, VIC_SET_FCE_UCODE_OFFSET,
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(vic->falcon.firmware.iova + fce_bin_data_offset)
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>> 8);
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/* Old VIC firmware needs kernel help with setting up FCE microcode. */
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if (fce_bin_data_offset != 0x0 && fce_bin_data_offset != 0xa5a5a5a5) {
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hdr = vic->falcon.firmware.virt +
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*(u32 *)(hdr + VIC_UCODE_FCE_HEADER_OFFSET);
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fce_ucode_size = *(u32 *)(hdr + FCE_UCODE_SIZE_OFFSET);
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falcon_execute_method(&vic->falcon, VIC_SET_FCE_UCODE_SIZE,
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fce_ucode_size);
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falcon_execute_method(
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&vic->falcon, VIC_SET_FCE_UCODE_OFFSET,
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(vic->falcon.firmware.iova + fce_bin_data_offset) >> 8);
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}
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err = falcon_wait_idle(&vic->falcon);
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if (err < 0) {
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@ -314,7 +331,7 @@ static int vic_open_channel(struct tegra_drm_client *client,
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struct vic *vic = to_vic(client);
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int err;
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err = pm_runtime_get_sync(vic->dev);
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err = pm_runtime_resume_and_get(vic->dev);
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if (err < 0)
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return err;
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