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microblaze: Fix unaligned value saving to the stack for system with MMU
Several registers weren't saved correctly to the stack. Unaligned expection for system with MMU stores value in ex_tmp_data_loc_X address which is load to registers r3. The next step is to move this value from r3 to a destination register which caused unaligned exception. For several registers this value was directly moved to the register. For example for r28: by "or r28, r0, r3" but register r28 was rewritten when kernel returns from exception handler by value saved on stack. This patch changed r3 saving to the correct address on the stack. For example for r28: by "swi r3, r1, 4 * 28" When kernel returns from the exception handler, correct value is restored. Signed-off-by: Michal Simek <monstr@monstr.eu>
This commit is contained in:
parent
a2f526994e
commit
c11389406f
1 changed files with 28 additions and 28 deletions
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@ -1113,23 +1113,23 @@ lw_r10_vm: R3_TO_LWREG_VM_V (10);
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lw_r11_vm: R3_TO_LWREG_VM_V (11);
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lw_r11_vm: R3_TO_LWREG_VM_V (11);
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lw_r12_vm: R3_TO_LWREG_VM_V (12);
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lw_r12_vm: R3_TO_LWREG_VM_V (12);
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lw_r13_vm: R3_TO_LWREG_VM_V (13);
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lw_r13_vm: R3_TO_LWREG_VM_V (13);
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lw_r14_vm: R3_TO_LWREG_VM (14);
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lw_r14_vm: R3_TO_LWREG_VM_V (14);
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lw_r15_vm: R3_TO_LWREG_VM_V (15);
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lw_r15_vm: R3_TO_LWREG_VM_V (15);
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lw_r16_vm: R3_TO_LWREG_VM (16);
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lw_r16_vm: R3_TO_LWREG_VM_V (16);
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lw_r17_vm: R3_TO_LWREG_VM_V (17);
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lw_r17_vm: R3_TO_LWREG_VM_V (17);
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lw_r18_vm: R3_TO_LWREG_VM_V (18);
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lw_r18_vm: R3_TO_LWREG_VM_V (18);
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lw_r19_vm: R3_TO_LWREG_VM (19);
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lw_r19_vm: R3_TO_LWREG_VM_V (19);
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lw_r20_vm: R3_TO_LWREG_VM (20);
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lw_r20_vm: R3_TO_LWREG_VM_V (20);
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lw_r21_vm: R3_TO_LWREG_VM (21);
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lw_r21_vm: R3_TO_LWREG_VM_V (21);
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lw_r22_vm: R3_TO_LWREG_VM (22);
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lw_r22_vm: R3_TO_LWREG_VM_V (22);
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lw_r23_vm: R3_TO_LWREG_VM (23);
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lw_r23_vm: R3_TO_LWREG_VM_V (23);
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lw_r24_vm: R3_TO_LWREG_VM (24);
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lw_r24_vm: R3_TO_LWREG_VM_V (24);
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lw_r25_vm: R3_TO_LWREG_VM (25);
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lw_r25_vm: R3_TO_LWREG_VM_V (25);
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lw_r26_vm: R3_TO_LWREG_VM (26);
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lw_r26_vm: R3_TO_LWREG_VM_V (26);
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lw_r27_vm: R3_TO_LWREG_VM (27);
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lw_r27_vm: R3_TO_LWREG_VM_V (27);
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lw_r28_vm: R3_TO_LWREG_VM (28);
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lw_r28_vm: R3_TO_LWREG_VM_V (28);
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lw_r29_vm: R3_TO_LWREG_VM (29);
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lw_r29_vm: R3_TO_LWREG_VM_V (29);
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lw_r30_vm: R3_TO_LWREG_VM (30);
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lw_r30_vm: R3_TO_LWREG_VM_V (30);
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lw_r31_vm: R3_TO_LWREG_VM_V (31);
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lw_r31_vm: R3_TO_LWREG_VM_V (31);
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sw_table_vm:
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sw_table_vm:
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@ -1147,23 +1147,23 @@ sw_r10_vm: SWREG_TO_R3_VM_V (10);
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sw_r11_vm: SWREG_TO_R3_VM_V (11);
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sw_r11_vm: SWREG_TO_R3_VM_V (11);
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sw_r12_vm: SWREG_TO_R3_VM_V (12);
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sw_r12_vm: SWREG_TO_R3_VM_V (12);
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sw_r13_vm: SWREG_TO_R3_VM_V (13);
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sw_r13_vm: SWREG_TO_R3_VM_V (13);
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sw_r14_vm: SWREG_TO_R3_VM (14);
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sw_r14_vm: SWREG_TO_R3_VM_V (14);
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sw_r15_vm: SWREG_TO_R3_VM_V (15);
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sw_r15_vm: SWREG_TO_R3_VM_V (15);
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sw_r16_vm: SWREG_TO_R3_VM (16);
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sw_r16_vm: SWREG_TO_R3_VM_V (16);
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sw_r17_vm: SWREG_TO_R3_VM_V (17);
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sw_r17_vm: SWREG_TO_R3_VM_V (17);
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sw_r18_vm: SWREG_TO_R3_VM_V (18);
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sw_r18_vm: SWREG_TO_R3_VM_V (18);
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sw_r19_vm: SWREG_TO_R3_VM (19);
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sw_r19_vm: SWREG_TO_R3_VM_V (19);
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sw_r20_vm: SWREG_TO_R3_VM (20);
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sw_r20_vm: SWREG_TO_R3_VM_V (20);
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sw_r21_vm: SWREG_TO_R3_VM (21);
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sw_r21_vm: SWREG_TO_R3_VM_V (21);
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sw_r22_vm: SWREG_TO_R3_VM (22);
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sw_r22_vm: SWREG_TO_R3_VM_V (22);
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sw_r23_vm: SWREG_TO_R3_VM (23);
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sw_r23_vm: SWREG_TO_R3_VM_V (23);
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sw_r24_vm: SWREG_TO_R3_VM (24);
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sw_r24_vm: SWREG_TO_R3_VM_V (24);
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sw_r25_vm: SWREG_TO_R3_VM (25);
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sw_r25_vm: SWREG_TO_R3_VM_V (25);
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sw_r26_vm: SWREG_TO_R3_VM (26);
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sw_r26_vm: SWREG_TO_R3_VM_V (26);
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sw_r27_vm: SWREG_TO_R3_VM (27);
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sw_r27_vm: SWREG_TO_R3_VM_V (27);
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sw_r28_vm: SWREG_TO_R3_VM (28);
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sw_r28_vm: SWREG_TO_R3_VM_V (28);
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sw_r29_vm: SWREG_TO_R3_VM (29);
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sw_r29_vm: SWREG_TO_R3_VM_V (29);
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sw_r30_vm: SWREG_TO_R3_VM (30);
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sw_r30_vm: SWREG_TO_R3_VM_V (30);
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sw_r31_vm: SWREG_TO_R3_VM_V (31);
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sw_r31_vm: SWREG_TO_R3_VM_V (31);
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#endif /* CONFIG_MMU */
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#endif /* CONFIG_MMU */
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