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KVM: arm64: add active register handling to GICv3 emulation as well
Commit 47a98b15ba
("arm/arm64: KVM: support for un-queuing active
IRQs") introduced handling of the GICD_I[SC]ACTIVER registers,
but only for the GICv2 emulation. For the sake of completeness and
as this is a pre-requisite for save/restore of the GICv3 distributor
state, we should also emulate their handling in the distributor and
redistributor frames of an emulated GICv3.
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
This commit is contained in:
parent
a5f56ba3b4
commit
c11b532910
1 changed files with 50 additions and 4 deletions
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@ -173,6 +173,32 @@ static bool handle_mmio_clear_pending_reg_dist(struct kvm_vcpu *vcpu,
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return false;
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return false;
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}
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}
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static bool handle_mmio_set_active_reg_dist(struct kvm_vcpu *vcpu,
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struct kvm_exit_mmio *mmio,
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phys_addr_t offset)
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{
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if (likely(offset >= VGIC_NR_PRIVATE_IRQS / 8))
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return vgic_handle_set_active_reg(vcpu->kvm, mmio, offset,
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vcpu->vcpu_id);
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vgic_reg_access(mmio, NULL, offset,
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ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED);
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return false;
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}
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static bool handle_mmio_clear_active_reg_dist(struct kvm_vcpu *vcpu,
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struct kvm_exit_mmio *mmio,
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phys_addr_t offset)
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{
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if (likely(offset >= VGIC_NR_PRIVATE_IRQS / 8))
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return vgic_handle_clear_active_reg(vcpu->kvm, mmio, offset,
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vcpu->vcpu_id);
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vgic_reg_access(mmio, NULL, offset,
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ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED);
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return false;
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}
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static bool handle_mmio_priority_reg_dist(struct kvm_vcpu *vcpu,
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static bool handle_mmio_priority_reg_dist(struct kvm_vcpu *vcpu,
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struct kvm_exit_mmio *mmio,
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struct kvm_exit_mmio *mmio,
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phys_addr_t offset)
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phys_addr_t offset)
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@ -428,13 +454,13 @@ static const struct vgic_io_range vgic_v3_dist_ranges[] = {
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.base = GICD_ISACTIVER,
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.base = GICD_ISACTIVER,
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.len = 0x80,
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.len = 0x80,
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.bits_per_irq = 1,
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.bits_per_irq = 1,
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.handle_mmio = handle_mmio_raz_wi,
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.handle_mmio = handle_mmio_set_active_reg_dist,
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},
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},
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{
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{
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.base = GICD_ICACTIVER,
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.base = GICD_ICACTIVER,
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.len = 0x80,
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.len = 0x80,
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.bits_per_irq = 1,
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.bits_per_irq = 1,
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.handle_mmio = handle_mmio_raz_wi,
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.handle_mmio = handle_mmio_clear_active_reg_dist,
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},
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},
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{
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{
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.base = GICD_IPRIORITYR,
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.base = GICD_IPRIORITYR,
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@ -561,6 +587,26 @@ static bool handle_mmio_clear_enable_reg_redist(struct kvm_vcpu *vcpu,
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ACCESS_WRITE_CLEARBIT);
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ACCESS_WRITE_CLEARBIT);
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}
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}
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static bool handle_mmio_set_active_reg_redist(struct kvm_vcpu *vcpu,
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struct kvm_exit_mmio *mmio,
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phys_addr_t offset)
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{
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struct kvm_vcpu *redist_vcpu = mmio->private;
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return vgic_handle_set_active_reg(vcpu->kvm, mmio, offset,
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redist_vcpu->vcpu_id);
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}
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static bool handle_mmio_clear_active_reg_redist(struct kvm_vcpu *vcpu,
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struct kvm_exit_mmio *mmio,
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phys_addr_t offset)
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{
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struct kvm_vcpu *redist_vcpu = mmio->private;
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return vgic_handle_clear_active_reg(vcpu->kvm, mmio, offset,
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redist_vcpu->vcpu_id);
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}
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static bool handle_mmio_set_pending_reg_redist(struct kvm_vcpu *vcpu,
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static bool handle_mmio_set_pending_reg_redist(struct kvm_vcpu *vcpu,
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struct kvm_exit_mmio *mmio,
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struct kvm_exit_mmio *mmio,
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phys_addr_t offset)
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phys_addr_t offset)
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@ -674,13 +720,13 @@ static const struct vgic_io_range vgic_redist_ranges[] = {
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.base = SGI_base(GICR_ISACTIVER0),
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.base = SGI_base(GICR_ISACTIVER0),
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.len = 0x04,
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.len = 0x04,
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.bits_per_irq = 1,
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.bits_per_irq = 1,
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.handle_mmio = handle_mmio_raz_wi,
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.handle_mmio = handle_mmio_set_active_reg_redist,
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},
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},
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{
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{
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.base = SGI_base(GICR_ICACTIVER0),
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.base = SGI_base(GICR_ICACTIVER0),
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.len = 0x04,
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.len = 0x04,
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.bits_per_irq = 1,
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.bits_per_irq = 1,
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.handle_mmio = handle_mmio_raz_wi,
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.handle_mmio = handle_mmio_clear_active_reg_redist,
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},
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},
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{
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{
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.base = SGI_base(GICR_IPRIORITYR0),
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.base = SGI_base(GICR_IPRIORITYR0),
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