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Code Issues Releases Wiki Activity

perf vendor events: Update for Westmere EP-DP

Browse source 
Events are still at version 2:
    https://download.01.org/perfmon/WSM-EP-DP
Json files generated by the latest code at:
    https://github.com/intel/event-converter-for-linux-perf

Tested:

  ...
    6: Parse event definition strings                                  : Ok
    7: Simple expression parser                                        : Ok
  ...
    9: Parse perf pmu format                                           : Ok
   10: PMU events                                                      :
   10.1: PMU event table sanity                                        : Ok
   10.2: PMU event map aliases                                         : Ok
   10.3: Parsing of PMU event table metrics                            : Ok
   10.4: Parsing of PMU event table metrics with fake PMUs             : Ok
  ...
   68: Parse and process metrics                                       : Ok
  ...
   88: perf stat metrics (shadow stat) test                            : Ok
   89: perf all metricgroups test                                      : Ok
   90: perf all metrics test                                           : Ok
   91: perf all PMU test                                               : Ok
  ...

Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.garry@huawei.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Zhengjun Xing <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20220201015858.1226914-8-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Ian Rogers 2022-01-31 17:58:39 -08:00 committed by Arnaldo Carvalho de Melo
parent e0f6eeefe4
commit c11ffe52c9
7 changed files with 2495 additions and 2495 deletions
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2814
tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json
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tools/perf/pmu-events/arch/x86/westmereep-dp/floating-point.json
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@ -1,229 +1,229 @@
[
{
"PEBS": "1",
"EventCode": "0xF7",
"BriefDescription": "X87 Floating point assists (Precise Event)",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0xF7",
"EventName": "FP_ASSIST.ALL",
"PEBS": "1",
"SampleAfterValue": "20000",
"BriefDescription": "X87 Floating point assists (Precise Event)"
"UMask": "0x1"
},
{
"PEBS": "1",
"EventCode": "0xF7",
"BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventCode": "0xF7",
"EventName": "FP_ASSIST.INPUT",
"SampleAfterValue": "20000",
"BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)"
},
{
"PEBS": "1",
"EventCode": "0xF7",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "FP_ASSIST.OUTPUT",
"SampleAfterValue": "20000",
"BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)"
"UMask": "0x4"
},
{
"EventCode": "0x10",
"BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventCode": "0xF7",
"EventName": "FP_ASSIST.OUTPUT",
"PEBS": "1",
"SampleAfterValue": "20000",
"UMask": "0x2"
},
{
"BriefDescription": "MMX Uops",
"Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.MMX",
"SampleAfterValue": "2000000",
"BriefDescription": "MMX Uops"
"UMask": "0x2"
},
{
"EventCode": "0x10",
"BriefDescription": "SSE2 integer Uops",
"Counter": "0,1,2,3",
"UMask": "0x80",
"EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION",
"SampleAfterValue": "2000000",
"BriefDescription": "SSE* FP double precision Uops"
},
{
"EventCode": "0x10",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "FP_COMP_OPS_EXE.SSE_FP",
"SampleAfterValue": "2000000",
"BriefDescription": "SSE and SSE2 FP Uops"
},
{
"EventCode": "0x10",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED",
"SampleAfterValue": "2000000",
"BriefDescription": "SSE FP packed Uops"
},
{
"EventCode": "0x10",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR",
"SampleAfterValue": "2000000",
"BriefDescription": "SSE FP scalar Uops"
},
{
"EventCode": "0x10",
"Counter": "0,1,2,3",
"UMask": "0x40",
"EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION",
"SampleAfterValue": "2000000",
"BriefDescription": "SSE* FP single precision Uops"
},
{
"EventCode": "0x10",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER",
"SampleAfterValue": "2000000",
"BriefDescription": "SSE2 integer Uops"
"UMask": "0x8"
},
{
"EventCode": "0x10",
"BriefDescription": "SSE* FP double precision Uops",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION",
"SampleAfterValue": "2000000",
"UMask": "0x80"
},
{
"BriefDescription": "SSE and SSE2 FP Uops",
"Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_FP",
"SampleAfterValue": "2000000",
"UMask": "0x4"
},
{
"BriefDescription": "SSE FP packed Uops",
"Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED",
"SampleAfterValue": "2000000",
"UMask": "0x10"
},
{
"BriefDescription": "SSE FP scalar Uops",
"Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR",
"SampleAfterValue": "2000000",
"UMask": "0x20"
},
{
"BriefDescription": "SSE* FP single precision Uops",
"Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION",
"SampleAfterValue": "2000000",
"UMask": "0x40"
},
{
"BriefDescription": "Computational floating-point operations executed",
"Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.X87",
"SampleAfterValue": "2000000",
"BriefDescription": "Computational floating-point operations executed"
"UMask": "0x1"
},
{
"EventCode": "0xCC",
"BriefDescription": "All Floating Point to and from MMX transitions",
"Counter": "0,1,2,3",
"UMask": "0x3",
"EventCode": "0xCC",
"EventName": "FP_MMX_TRANS.ANY",
"SampleAfterValue": "2000000",
"BriefDescription": "All Floating Point to and from MMX transitions"
"UMask": "0x3"
},
{
"EventCode": "0xCC",
"BriefDescription": "Transitions from MMX to Floating Point instructions",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0xCC",
"EventName": "FP_MMX_TRANS.TO_FP",
"SampleAfterValue": "2000000",
"BriefDescription": "Transitions from MMX to Floating Point instructions"
"UMask": "0x1"
},
{
"EventCode": "0xCC",
"BriefDescription": "Transitions from Floating Point to MMX instructions",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventCode": "0xCC",
"EventName": "FP_MMX_TRANS.TO_MMX",
"SampleAfterValue": "2000000",
"BriefDescription": "Transitions from Floating Point to MMX instructions"
"UMask": "0x2"
},
{
"EventCode": "0x12",
"BriefDescription": "128 bit SIMD integer pack operations",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACK",
"SampleAfterValue": "200000",
"BriefDescription": "128 bit SIMD integer pack operations"
"UMask": "0x4"
},
{
"EventCode": "0x12",
"BriefDescription": "128 bit SIMD integer arithmetic operations",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACKED_ARITH",
"SampleAfterValue": "200000",
"BriefDescription": "128 bit SIMD integer arithmetic operations"
"UMask": "0x20"
},
{
"EventCode": "0x12",
"BriefDescription": "128 bit SIMD integer logical operations",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACKED_LOGICAL",
"SampleAfterValue": "200000",
"BriefDescription": "128 bit SIMD integer logical operations"
"UMask": "0x10"
},
{
"EventCode": "0x12",
"BriefDescription": "128 bit SIMD integer multiply operations",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACKED_MPY",
"SampleAfterValue": "200000",
"BriefDescription": "128 bit SIMD integer multiply operations"
"UMask": "0x1"
},
{
"EventCode": "0x12",
"BriefDescription": "128 bit SIMD integer shift operations",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACKED_SHIFT",
"SampleAfterValue": "200000",
"BriefDescription": "128 bit SIMD integer shift operations"
"UMask": "0x2"
},
{
"EventCode": "0x12",
"BriefDescription": "128 bit SIMD integer shuffle/move operations",
"Counter": "0,1,2,3",
"UMask": "0x40",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.SHUFFLE_MOVE",
"SampleAfterValue": "200000",
"BriefDescription": "128 bit SIMD integer shuffle/move operations"
"UMask": "0x40"
},
{
"EventCode": "0x12",
"BriefDescription": "128 bit SIMD integer unpack operations",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.UNPACK",
"SampleAfterValue": "200000",
"BriefDescription": "128 bit SIMD integer unpack operations"
"UMask": "0x8"
},
{
"EventCode": "0xFD",
"BriefDescription": "SIMD integer 64 bit pack operations",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACK",
"SampleAfterValue": "200000",
"BriefDescription": "SIMD integer 64 bit pack operations"
"UMask": "0x4"
},
{
"EventCode": "0xFD",
"BriefDescription": "SIMD integer 64 bit arithmetic operations",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACKED_ARITH",
"SampleAfterValue": "200000",
"BriefDescription": "SIMD integer 64 bit arithmetic operations"
"UMask": "0x20"
},
{
"EventCode": "0xFD",
"BriefDescription": "SIMD integer 64 bit logical operations",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACKED_LOGICAL",
"SampleAfterValue": "200000",
"BriefDescription": "SIMD integer 64 bit logical operations"
"UMask": "0x10"
},
{
"EventCode": "0xFD",
"BriefDescription": "SIMD integer 64 bit packed multiply operations",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACKED_MPY",
"SampleAfterValue": "200000",
"BriefDescription": "SIMD integer 64 bit packed multiply operations"
"UMask": "0x1"
},
{
"EventCode": "0xFD",
"BriefDescription": "SIMD integer 64 bit shift operations",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACKED_SHIFT",
"SampleAfterValue": "200000",
"BriefDescription": "SIMD integer 64 bit shift operations"
"UMask": "0x2"
},
{
"EventCode": "0xFD",
"BriefDescription": "SIMD integer 64 bit shuffle/move operations",
"Counter": "0,1,2,3",
"UMask": "0x40",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.SHUFFLE_MOVE",
"SampleAfterValue": "200000",
"BriefDescription": "SIMD integer 64 bit shuffle/move operations"
"UMask": "0x40"
},
{
"EventCode": "0xFD",
"BriefDescription": "SIMD integer 64 bit unpack operations",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.UNPACK",
"SampleAfterValue": "200000",
"BriefDescription": "SIMD integer 64 bit unpack operations"
"UMask": "0x8"
}
]

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tools/perf/pmu-events/arch/x86/westmereep-dp/frontend.json
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[
{
"EventCode": "0xD0",
"BriefDescription": "Instructions decoded",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0xD0",
"EventName": "MACRO_INSTS.DECODED",
"SampleAfterValue": "2000000",
"BriefDescription": "Instructions decoded"
"UMask": "0x1"
},
{
"EventCode": "0xA6",
"BriefDescription": "Macro-fused instructions decoded",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0xA6",
"EventName": "MACRO_INSTS.FUSIONS_DECODED",
"SampleAfterValue": "2000000",
"BriefDescription": "Macro-fused instructions decoded"
"UMask": "0x1"
},
{
"EventCode": "0x19",
"BriefDescription": "Two Uop instructions decoded",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0x19",
"EventName": "TWO_UOP_INSTS_DECODED",
"SampleAfterValue": "2000000",
"BriefDescription": "Two Uop instructions decoded"
"UMask": "0x1"
}
]

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tools/perf/pmu-events/arch/x86/westmereep-dp/memory.json
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tools/perf/pmu-events/arch/x86/westmereep-dp/other.json
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[
{
"EventCode": "0xE8",
"BriefDescription": "Early Branch Prediciton Unit clears",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0xE8",
"EventName": "BPU_CLEARS.EARLY",
"SampleAfterValue": "2000000",
"BriefDescription": "Early Branch Prediciton Unit clears"
"UMask": "0x1"
},
{
"EventCode": "0xE8",
"BriefDescription": "Late Branch Prediction Unit clears",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventCode": "0xE8",
"EventName": "BPU_CLEARS.LATE",
"SampleAfterValue": "2000000",
"BriefDescription": "Late Branch Prediction Unit clears"
"UMask": "0x2"
},
{
"EventCode": "0xE5",
"BriefDescription": "Branch prediction unit missed call or return",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0xE5",
"EventName": "BPU_MISSED_CALL_RET",
"SampleAfterValue": "2000000",
"BriefDescription": "Branch prediction unit missed call or return"
"UMask": "0x1"
},
{
"EventCode": "0xD5",
"BriefDescription": "ES segment renames",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0xD5",
"EventName": "ES_REG_RENAMES",
"SampleAfterValue": "2000000",
"BriefDescription": "ES segment renames"
"UMask": "0x1"
},
{
"EventCode": "0x6C",
"BriefDescription": "I/O transactions",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0x6C",
"EventName": "IO_TRANSACTIONS",
"SampleAfterValue": "2000000",
"BriefDescription": "I/O transactions"
"UMask": "0x1"
},
{
"EventCode": "0x80",
"BriefDescription": "L1I instruction fetch stall cycles",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventCode": "0x80",
"EventName": "L1I.CYCLES_STALLED",
"SampleAfterValue": "2000000",
"BriefDescription": "L1I instruction fetch stall cycles"
"UMask": "0x4"
},
{
"EventCode": "0x80",
"BriefDescription": "L1I instruction fetch hits",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0x80",
"EventName": "L1I.HITS",
"SampleAfterValue": "2000000",
"BriefDescription": "L1I instruction fetch hits"
"UMask": "0x1"
},
{
"EventCode": "0x80",
"BriefDescription": "L1I instruction fetch misses",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventCode": "0x80",
"EventName": "L1I.MISSES",
"SampleAfterValue": "2000000",
"BriefDescription": "L1I instruction fetch misses"
"UMask": "0x2"
},
{
"EventCode": "0x80",
"BriefDescription": "L1I Instruction fetches",
"Counter": "0,1,2,3",
"UMask": "0x3",
"EventCode": "0x80",
"EventName": "L1I.READS",
"SampleAfterValue": "2000000",
"BriefDescription": "L1I Instruction fetches"
"UMask": "0x3"
},
{
"EventCode": "0x82",
"BriefDescription": "Large ITLB hit",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0x82",
"EventName": "LARGE_ITLB.HIT",
"SampleAfterValue": "200000",
"BriefDescription": "Large ITLB hit"
"UMask": "0x1"
},
{
"EventCode": "0x3",
"BriefDescription": "Loads that partially overlap an earlier store",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventCode": "0x3",
"EventName": "LOAD_BLOCK.OVERLAP_STORE",
"SampleAfterValue": "200000",
"BriefDescription": "Loads that partially overlap an earlier store"
"UMask": "0x2"
},
{
"EventCode": "0x13",
"BriefDescription": "All loads dispatched",
"Counter": "0,1,2,3",
"UMask": "0x7",
"EventCode": "0x13",
"EventName": "LOAD_DISPATCH.ANY",
"SampleAfterValue": "2000000",
"BriefDescription": "All loads dispatched"
"UMask": "0x7"
},
{
"EventCode": "0x13",
"BriefDescription": "Loads dispatched from the MOB",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventCode": "0x13",
"EventName": "LOAD_DISPATCH.MOB",
"SampleAfterValue": "2000000",
"BriefDescription": "Loads dispatched from the MOB"
"UMask": "0x4"
},
{
"EventCode": "0x13",
"BriefDescription": "Loads dispatched that bypass the MOB",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0x13",
"EventName": "LOAD_DISPATCH.RS",
"SampleAfterValue": "2000000",
"BriefDescription": "Loads dispatched that bypass the MOB"
"UMask": "0x1"
},
{
"EventCode": "0x13",
"BriefDescription": "Loads dispatched from stage 305",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventCode": "0x13",
"EventName": "LOAD_DISPATCH.RS_DELAYED",
"SampleAfterValue": "2000000",
"BriefDescription": "Loads dispatched from stage 305"
"UMask": "0x2"
},
{
"EventCode": "0x7",
"BriefDescription": "False dependencies due to partial address aliasing",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0x7",
"EventName": "PARTIAL_ADDRESS_ALIAS",
"SampleAfterValue": "200000",
"BriefDescription": "False dependencies due to partial address aliasing"
"UMask": "0x1"
},
{
"EventCode": "0xD2",
"BriefDescription": "All RAT stall cycles",
"Counter": "0,1,2,3",
"UMask": "0xf",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.ANY",
"SampleAfterValue": "2000000",
"BriefDescription": "All RAT stall cycles"
"UMask": "0xf"
},
{
"EventCode": "0xD2",
"BriefDescription": "Flag stall cycles",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.FLAGS",
"SampleAfterValue": "2000000",
"BriefDescription": "Flag stall cycles"
"UMask": "0x1"
},
{
"EventCode": "0xD2",
"BriefDescription": "Partial register stall cycles",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.REGISTERS",
"SampleAfterValue": "2000000",
"BriefDescription": "Partial register stall cycles"
"UMask": "0x2"
},
{
"EventCode": "0xD2",
"BriefDescription": "ROB read port stalls cycles",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.ROB_READ_PORT",
"SampleAfterValue": "2000000",
"BriefDescription": "ROB read port stalls cycles"
"UMask": "0x4"
},
{
"EventCode": "0xD2",
"BriefDescription": "Scoreboard stall cycles",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.SCOREBOARD",
"SampleAfterValue": "2000000",
"BriefDescription": "Scoreboard stall cycles"
"UMask": "0x8"
},
{
"EventCode": "0x4",
"BriefDescription": "All Store buffer stall cycles",
"Counter": "0,1,2,3",
"UMask": "0x7",
"EventCode": "0x4",
"EventName": "SB_DRAIN.ANY",
"SampleAfterValue": "200000",
"BriefDescription": "All Store buffer stall cycles"
"UMask": "0x7"
},
{
"EventCode": "0xD4",
"BriefDescription": "Segment rename stall cycles",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0xD4",
"EventName": "SEG_RENAME_STALLS",
"SampleAfterValue": "2000000",
"BriefDescription": "Segment rename stall cycles"
"UMask": "0x1"
},
{
"EventCode": "0xB8",
"BriefDescription": "Snoop code requests",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "SNOOP_RESPONSE.HIT",
"SampleAfterValue": "100000",
"BriefDescription": "Thread responded HIT to snoop"
},
{
"EventCode": "0xB8",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "SNOOP_RESPONSE.HITE",
"SampleAfterValue": "100000",
"BriefDescription": "Thread responded HITE to snoop"
},
{
"EventCode": "0xB8",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "SNOOP_RESPONSE.HITM",
"SampleAfterValue": "100000",
"BriefDescription": "Thread responded HITM to snoop"
},
{
"EventCode": "0xB4",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "SNOOPQ_REQUESTS.CODE",
"SampleAfterValue": "100000",
"BriefDescription": "Snoop code requests"
"UMask": "0x4"
},
{
"EventCode": "0xB4",
"BriefDescription": "Snoop data requests",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0xB4",
"EventName": "SNOOPQ_REQUESTS.DATA",
"SampleAfterValue": "100000",
"BriefDescription": "Snoop data requests"
"UMask": "0x1"
},
{
"EventCode": "0xB4",
"BriefDescription": "Snoop invalidate requests",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventCode": "0xB4",
"EventName": "SNOOPQ_REQUESTS.INVALIDATE",
"SampleAfterValue": "100000",
"BriefDescription": "Snoop invalidate requests"
"UMask": "0x2"
},
{
"BriefDescription": "Outstanding snoop code requests",
"EventCode": "0xB3",
"UMask": "0x4",
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE",
"SampleAfterValue": "2000000",
"BriefDescription": "Outstanding snoop code requests"
"UMask": "0x4"
},
{
"BriefDescription": "Cycles snoop code requests queued",
"CounterMask": "1",
"EventCode": "0xB3",
"UMask": "0x4",
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE_NOT_EMPTY",
"SampleAfterValue": "2000000",
"BriefDescription": "Cycles snoop code requests queued",
"CounterMask": "1"
"UMask": "0x4"
},
{
"BriefDescription": "Outstanding snoop data requests",
"EventCode": "0xB3",
"UMask": "0x1",
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA",
"SampleAfterValue": "2000000",
"BriefDescription": "Outstanding snoop data requests"
"UMask": "0x1"
},
{
"BriefDescription": "Cycles snoop data requests queued",
"CounterMask": "1",
"EventCode": "0xB3",
"UMask": "0x1",
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA_NOT_EMPTY",
"SampleAfterValue": "2000000",
"BriefDescription": "Cycles snoop data requests queued",
"CounterMask": "1"
"UMask": "0x1"
},
{
"BriefDescription": "Outstanding snoop invalidate requests",
"EventCode": "0xB3",
"UMask": "0x2",
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE",
"SampleAfterValue": "2000000",
"BriefDescription": "Outstanding snoop invalidate requests"
"UMask": "0x2"
},
{
"BriefDescription": "Cycles snoop invalidate requests queued",
"CounterMask": "1",
"EventCode": "0xB3",
"UMask": "0x2",
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE_NOT_EMPTY",
"SampleAfterValue": "2000000",
"BriefDescription": "Cycles snoop invalidate requests queued",
"CounterMask": "1"
"UMask": "0x2"
},
{
"EventCode": "0xF6",
"BriefDescription": "Thread responded HIT to snoop",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0xB8",
"EventName": "SNOOP_RESPONSE.HIT",
"SampleAfterValue": "100000",
"UMask": "0x1"
},
{
"BriefDescription": "Thread responded HITE to snoop",
"Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "SNOOP_RESPONSE.HITE",
"SampleAfterValue": "100000",
"UMask": "0x2"
},
{
"BriefDescription": "Thread responded HITM to snoop",
"Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "SNOOP_RESPONSE.HITM",
"SampleAfterValue": "100000",
"UMask": "0x4"
},
{
"BriefDescription": "Super Queue full stall cycles",
"Counter": "0,1,2,3",
"EventCode": "0xF6",
"EventName": "SQ_FULL_STALL_CYCLES",
"SampleAfterValue": "2000000",
"BriefDescription": "Super Queue full stall cycles"
"UMask": "0x1"
}
]

866
tools/perf/pmu-events/arch/x86/westmereep-dp/pipeline.json
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138
tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json
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@ -1,173 +1,173 @@
[
{
"EventCode": "0x8",
"BriefDescription": "DTLB load misses",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.ANY",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB load misses"
"UMask": "0x1"
},
{
"EventCode": "0x8",
"BriefDescription": "DTLB load miss large page walks",
"Counter": "0,1,2,3",
"UMask": "0x80",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB load miss large page walks"
"UMask": "0x80"
},
{
"EventCode": "0x8",
"BriefDescription": "DTLB load miss caused by low part of address",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.PDE_MISS",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB load miss caused by low part of address"
"UMask": "0x20"
},
{
"EventCode": "0x8",
"BriefDescription": "DTLB second level hit",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"SampleAfterValue": "2000000",
"BriefDescription": "DTLB second level hit"
"UMask": "0x10"
},
{
"EventCode": "0x8",
"BriefDescription": "DTLB load miss page walks complete",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB load miss page walks complete"
"UMask": "0x2"
},
{
"EventCode": "0x8",
"BriefDescription": "DTLB load miss page walk cycles",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.WALK_CYCLES",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB load miss page walk cycles"
"UMask": "0x4"
},
{
"EventCode": "0x49",
"BriefDescription": "DTLB misses",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.ANY",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB misses"
"UMask": "0x1"
},
{
"EventCode": "0x49",
"BriefDescription": "DTLB miss large page walks",
"Counter": "0,1,2,3",
"UMask": "0x80",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB miss large page walks"
"UMask": "0x80"
},
{
"EventCode": "0x49",
"BriefDescription": "DTLB misses casued by low part of address",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.PDE_MISS",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB misses casued by low part of address"
"UMask": "0x20"
},
{
"EventCode": "0x49",
"BriefDescription": "DTLB first level misses but second level hit",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.STLB_HIT",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB first level misses but second level hit"
"UMask": "0x10"
},
{
"EventCode": "0x49",
"BriefDescription": "DTLB miss page walks",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.WALK_COMPLETED",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB miss page walks"
"UMask": "0x2"
},
{
"EventCode": "0x49",
"BriefDescription": "DTLB miss page walk cycles",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.WALK_CYCLES",
"SampleAfterValue": "2000000",
"BriefDescription": "DTLB miss page walk cycles"
"UMask": "0x4"
},
{
"EventCode": "0x4F",
"BriefDescription": "Extended Page Table walk cycles",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventCode": "0x4F",
"EventName": "EPT.WALK_CYCLES",
"SampleAfterValue": "2000000",
"BriefDescription": "Extended Page Table walk cycles"
"UMask": "0x10"
},
{
"EventCode": "0xAE",
"BriefDescription": "ITLB flushes",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0xAE",
"EventName": "ITLB_FLUSH",
"SampleAfterValue": "2000000",
"BriefDescription": "ITLB flushes"
"UMask": "0x1"
},
{
"PEBS": "1",
"EventCode": "0xC8",
"BriefDescription": "ITLB miss",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "ITLB_MISS_RETIRED",
"SampleAfterValue": "200000",
"BriefDescription": "Retired instructions that missed the ITLB (Precise Event)"
},
{
"EventCode": "0x85",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "ITLB_MISSES.ANY",
"SampleAfterValue": "200000",
"BriefDescription": "ITLB miss"
"UMask": "0x1"
},
{
"EventCode": "0x85",
"BriefDescription": "ITLB miss large page walks",
"Counter": "0,1,2,3",
"UMask": "0x80",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.LARGE_WALK_COMPLETED",
"SampleAfterValue": "200000",
"BriefDescription": "ITLB miss large page walks"
"UMask": "0x80"
},
{
"EventCode": "0x85",
"BriefDescription": "ITLB miss page walks",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"SampleAfterValue": "200000",
"BriefDescription": "ITLB miss page walks"
"UMask": "0x2"
},
{
"EventCode": "0x85",
"BriefDescription": "ITLB miss page walk cycles",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_CYCLES",
"SampleAfterValue": "2000000",
"BriefDescription": "ITLB miss page walk cycles"
"UMask": "0x4"
},
{
"BriefDescription": "Retired instructions that missed the ITLB (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xC8",
"EventName": "ITLB_MISS_RETIRED",
"PEBS": "1",
"SampleAfterValue": "200000",
"UMask": "0x20"
},
{
"BriefDescription": "Retired loads that miss the DTLB (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xCB",
"Counter": "0,1,2,3",
"UMask": "0x80",
"EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
"PEBS": "1",
"SampleAfterValue": "200000",
"BriefDescription": "Retired loads that miss the DTLB (Precise Event)"
"UMask": "0x80"
},
{
"PEBS": "1",
"EventCode": "0xC",
"BriefDescription": "Retired stores that miss the DTLB (Precise Event)",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0xC",
"EventName": "MEM_STORE_RETIRED.DTLB_MISS",
"PEBS": "1",
"SampleAfterValue": "200000",
"BriefDescription": "Retired stores that miss the DTLB (Precise Event)"
"UMask": "0x1"
}
]