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drm/i915: Introduce .{enable,disable}_clock() encoder vfuncs
The current code dealing with the clock routing for DDI encoders is a maintenance nightmare. Let's start cleaning it up by allowing the encoder to provide vfuncs for enablign/disabling the clock. We leave them initially unimplemented, falling back to the old if-else approach. v2: Convert the FDI enable sequence Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> #v2 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210205214634.19341-3-ville.syrjala@linux.intel.com
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ad9529824c
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c133df6994
4 changed files with 32 additions and 9 deletions
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@ -1929,6 +1929,23 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
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}
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}
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}
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}
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void intel_ddi_enable_clock(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state)
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{
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if (encoder->enable_clock)
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encoder->enable_clock(encoder, crtc_state);
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else
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intel_ddi_clk_select(encoder, crtc_state);
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}
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static void intel_ddi_disable_clock(struct intel_encoder *encoder)
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{
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if (encoder->disable_clock)
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encoder->disable_clock(encoder);
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else
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intel_ddi_clk_disable(encoder);
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}
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static void
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static void
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icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
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icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
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const struct intel_crtc_state *crtc_state)
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const struct intel_crtc_state *crtc_state)
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@ -2173,7 +2190,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
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* hsw_crtc_enable()->intel_enable_shared_dpll(). We need only
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* hsw_crtc_enable()->intel_enable_shared_dpll(). We need only
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* configure the PLL to port mapping here.
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* configure the PLL to port mapping here.
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*/
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*/
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intel_ddi_clk_select(encoder, crtc_state);
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intel_ddi_enable_clock(encoder, crtc_state);
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/* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */
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/* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */
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if (!intel_phy_is_tc(dev_priv, phy) ||
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if (!intel_phy_is_tc(dev_priv, phy) ||
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@ -2294,7 +2311,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
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intel_pps_on(intel_dp);
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intel_pps_on(intel_dp);
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intel_ddi_clk_select(encoder, crtc_state);
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intel_ddi_enable_clock(encoder, crtc_state);
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if (!intel_phy_is_tc(dev_priv, phy) ||
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if (!intel_phy_is_tc(dev_priv, phy) ||
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dig_port->tc_mode != TC_PORT_TBT_ALT) {
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dig_port->tc_mode != TC_PORT_TBT_ALT) {
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@ -2369,7 +2386,7 @@ static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
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intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
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intel_ddi_clk_select(encoder, crtc_state);
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intel_ddi_enable_clock(encoder, crtc_state);
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drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
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drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
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dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
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dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
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@ -2521,7 +2538,7 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
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dig_port->ddi_io_power_domain,
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dig_port->ddi_io_power_domain,
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fetch_and_zero(&dig_port->ddi_io_wakeref));
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fetch_and_zero(&dig_port->ddi_io_wakeref));
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intel_ddi_clk_disable(encoder);
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intel_ddi_disable_clock(encoder);
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}
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}
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static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
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static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
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@ -2544,7 +2561,7 @@ static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
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dig_port->ddi_io_power_domain,
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dig_port->ddi_io_power_domain,
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fetch_and_zero(&dig_port->ddi_io_wakeref));
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fetch_and_zero(&dig_port->ddi_io_wakeref));
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intel_ddi_clk_disable(encoder);
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intel_ddi_disable_clock(encoder);
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intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
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intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
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}
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}
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@ -2644,7 +2661,7 @@ void intel_ddi_fdi_post_disable(struct intel_atomic_state *state,
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intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
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intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
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intel_disable_ddi_buf(encoder, old_crtc_state);
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intel_disable_ddi_buf(encoder, old_crtc_state);
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intel_ddi_clk_disable(encoder);
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intel_ddi_disable_clock(encoder);
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val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
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val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
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val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
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val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
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@ -28,8 +28,8 @@ void intel_ddi_fdi_post_disable(struct intel_atomic_state *state,
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struct intel_encoder *intel_encoder,
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struct intel_encoder *intel_encoder,
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const struct intel_crtc_state *old_crtc_state,
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const struct intel_crtc_state *old_crtc_state,
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const struct drm_connector_state *old_conn_state);
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const struct drm_connector_state *old_conn_state);
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void intel_ddi_clk_select(struct intel_encoder *encoder,
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void intel_ddi_enable_clock(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state);
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const struct intel_crtc_state *crtc_state);
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void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
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void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state);
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const struct intel_crtc_state *crtc_state);
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void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
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void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
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@ -220,6 +220,12 @@ struct intel_encoder {
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* encoders have been disabled and suspended.
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* encoders have been disabled and suspended.
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*/
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*/
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void (*shutdown)(struct intel_encoder *encoder);
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void (*shutdown)(struct intel_encoder *encoder);
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/*
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* Enable/disable the clock to the port.
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*/
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void (*enable_clock)(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state);
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void (*disable_clock)(struct intel_encoder *encoder);
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enum hpd_pin hpd_pin;
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enum hpd_pin hpd_pin;
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enum intel_display_power_domain power_domain;
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enum intel_display_power_domain power_domain;
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/* for communication with audio component; protected by av_mutex */
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/* for communication with audio component; protected by av_mutex */
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@ -596,7 +596,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
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/* Configure Port Clock Select */
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/* Configure Port Clock Select */
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drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll->info->id != DPLL_ID_SPLL);
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drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll->info->id != DPLL_ID_SPLL);
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intel_ddi_clk_select(encoder, crtc_state);
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intel_ddi_enable_clock(encoder, crtc_state);
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/* Start the training iterating through available voltages and emphasis,
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/* Start the training iterating through available voltages and emphasis,
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* testing each value twice. */
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* testing each value twice. */
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