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V4L/DVB: staging/lirc: add lirc_it87 driver
Signed-off-by: Jarod Wilson <jarod@redhat.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
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1019
drivers/staging/lirc/lirc_it87.c
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1019
drivers/staging/lirc/lirc_it87.c
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drivers/staging/lirc/lirc_it87.h
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drivers/staging/lirc/lirc_it87.h
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/* lirc_it87.h */
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/* SECTION: Definitions */
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/********************************* ITE IT87xx ************************/
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/* based on the following documentation from ITE:
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a) IT8712F Preliminary CIR Programming Guide V0.1
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b) IT8705F Simple LPC I/O Preliminary Specification V0.3
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c) IT8712F EC-LPC I/O Preliminary Specification V0.5
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*/
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/* IT8712/05 Ports: */
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#define IT87_ADRPORT 0x2e
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#define IT87_DATAPORT 0x2f
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#define IT87_INIT {0x87, 0x01, 0x55, 0x55}
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/* alternate Ports: */
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/*
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#define IT87_ADRPORT 0x4e
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#define IT87_DATAPORT 0x4f
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#define IT87_INIT {0x87, 0x01, 0x55, 0xaa}
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*/
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/* IT8712/05 Registers */
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#define IT87_CFGCTRL 0x2
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#define IT87_LDN 0x7
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#define IT87_CHIP_ID1 0x20
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#define IT87_CHIP_ID2 0x21
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#define IT87_CFG_VERSION 0x22
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#define IT87_SWSUSPEND 0x23
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#define IT8712_CIR_LDN 0xa
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#define IT8705_CIR_LDN 0x7
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/* CIR Configuration Registers: */
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#define IT87_CIR_ACT 0x30
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#define IT87_CIR_BASE_MSB 0x60
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#define IT87_CIR_BASE_LSB 0x61
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#define IT87_CIR_IRQ 0x70
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#define IT87_CIR_CONFIG 0xf0
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/* List of IT87_CIR registers: offset to BaseAddr */
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#define IT87_CIR_DR 0
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#define IT87_CIR_IER 1
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#define IT87_CIR_RCR 2
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#define IT87_CIR_TCR1 3
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#define IT87_CIR_TCR2 4
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#define IT87_CIR_TSR 5
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#define IT87_CIR_RSR 6
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#define IT87_CIR_BDLR 5
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#define IT87_CIR_BDHR 6
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#define IT87_CIR_IIR 7
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/* Bit Definition */
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/* IER: */
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#define IT87_CIR_IER_TM_EN 0x80
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#define IT87_CIR_IER_RESEVED 0x40
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#define IT87_CIR_IER_RESET 0x20
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#define IT87_CIR_IER_BR 0x10
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#define IT87_CIR_IER_IEC 0x8
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#define IT87_CIR_IER_RFOIE 0x4
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#define IT87_CIR_IER_RDAIE 0x2
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#define IT87_CIR_IER_TLDLIE 0x1
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/* RCR: */
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#define IT87_CIR_RCR_RDWOS 0x80
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#define IT87_CIR_RCR_HCFS 0x40
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#define IT87_CIR_RCR_RXEN 0x20
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#define IT87_CIR_RCR_RXEND 0x10
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#define IT87_CIR_RCR_RXACT 0x8
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#define IT87_CIR_RCR_RXDCR 0x7
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/* TCR1: */
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#define IT87_CIR_TCR1_FIFOCLR 0x80
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#define IT87_CIR_TCR1_ILE 0x40
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#define IT87_CIR_TCR1_FIFOTL 0x30
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#define IT87_CIR_TCR1_TXRLE 0x8
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#define IT87_CIR_TCR1_TXENDF 0x4
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#define IT87_CIR_TCR1_TXMPM 0x3
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/* TCR2: */
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#define IT87_CIR_TCR2_CFQ 0xf8
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#define IT87_CIR_TCR2_TXMPW 0x7
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/* TSR: */
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#define IT87_CIR_TSR_RESERVED 0xc0
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#define IT87_CIR_TSR_TXFBC 0x3f
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/* RSR: */
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#define IT87_CIR_RSR_RXFTO 0x80
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#define IT87_CIR_RSR_RESERVED 0x40
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#define IT87_CIR_RSR_RXFBC 0x3f
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/* IIR: */
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#define IT87_CIR_IIR_RESERVED 0xf8
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#define IT87_CIR_IIR_IID 0x6
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#define IT87_CIR_IIR_IIP 0x1
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/* TM: */
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#define IT87_CIR_TM_IL_SEL 0x80
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#define IT87_CIR_TM_RESERVED 0x40
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#define IT87_CIR_TM_TM_REG 0x3f
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#define IT87_CIR_FIFO_SIZE 32
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/* Baudratedivisor for IT87: power of 2: only 1,2,4 or 8) */
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#define IT87_CIR_BAUDRATE_DIVISOR 0x1
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#define IT87_CIR_DEFAULT_IOBASE 0x310
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#define IT87_CIR_DEFAULT_IRQ 0x7
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#define IT87_CIR_SPACE 0x00
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#define IT87_CIR_PULSE 0xff
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#define IT87_CIR_FREQ_MIN 27
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#define IT87_CIR_FREQ_MAX 58
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#define TIME_CONST (IT87_CIR_BAUDRATE_DIVISOR * 8000000ul / 115200ul)
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/********************************* ITE IT87xx ************************/
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