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[SCSI] qla4xxx: Take E-port out of reset before disabling pause frames
Problem Description: Disabling pause frames might cause hardware wedging needing a power cycle. This might happen if the Eport is not initialized and is in reset. Solution: Before disabling pause frames ensure that eport is out of reset. Signed-off-by: Manish Dusane <manish.dusane@qlogic.com> Signed-off-by: Vikas Chaudhary <vikas.chaudhary@qlogic.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
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2 changed files with 38 additions and 0 deletions
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@ -1629,9 +1629,37 @@ static void __qla4_83xx_disable_pause(struct scsi_qla_host *ha)
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ql4_printk(KERN_INFO, ha, "Disabled pause frames successfully.\n");
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}
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/**
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* qla4_83xx_eport_init - Initialize EPort.
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* @ha: Pointer to host adapter structure.
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*
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* If EPort hardware is in reset state before disabling pause, there would be
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* serious hardware wedging issues. To prevent this perform eport init everytime
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* before disabling pause frames.
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**/
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static void qla4_83xx_eport_init(struct scsi_qla_host *ha)
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{
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/* Clear the 8 registers */
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qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_REG, 0x0);
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qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_PORT0, 0x0);
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qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_PORT1, 0x0);
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qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_PORT2, 0x0);
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qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_PORT3, 0x0);
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qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_SRE_SHIM, 0x0);
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qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_EPG_SHIM, 0x0);
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qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_ETHER_PCS, 0x0);
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/* Write any value to Reset Control register */
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qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_CONTROL, 0xFF);
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ql4_printk(KERN_INFO, ha, "EPORT is out of reset.\n");
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}
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void qla4_83xx_disable_pause(struct scsi_qla_host *ha)
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{
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ha->isp_ops->idc_lock(ha);
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/* Before disabling pause frames, ensure that eport is not in reset */
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qla4_83xx_eport_init(ha);
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qla4_83xx_dump_pause_control_regs(ha);
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__qla4_83xx_disable_pause(ha);
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ha->isp_ops->idc_unlock(ha);
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@ -55,6 +55,16 @@
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#define QLA83XX_SET_PAUSE_VAL 0x0
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#define QLA83XX_SET_TC_MAX_CELL_VAL 0x03FF03FF
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#define QLA83XX_RESET_CONTROL 0x28084E50
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#define QLA83XX_RESET_REG 0x28084E60
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#define QLA83XX_RESET_PORT0 0x28084E70
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#define QLA83XX_RESET_PORT1 0x28084E80
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#define QLA83XX_RESET_PORT2 0x28084E90
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#define QLA83XX_RESET_PORT3 0x28084EA0
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#define QLA83XX_RESET_SRE_SHIM 0x28084EB0
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#define QLA83XX_RESET_EPG_SHIM 0x28084EC0
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#define QLA83XX_RESET_ETHER_PCS 0x28084ED0
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/* qla_83xx_reg_tbl registers */
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#define QLA83XX_PEG_HALT_STATUS1 0x34A8
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#define QLA83XX_PEG_HALT_STATUS2 0x34AC
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